Data destruction method and memory applying same

Abstract

The embodiment of the invention provides a data destruction method and a memory applying the method, and the method comprises the steps: employing a CGND, MGND and GNDFx three-order ground wire architecture, and disconnecting different ground wires before destroying high-voltage input; the access of the high-voltage power supply is controlled through IO interfaces of the plurality of MCUs, and the high-voltage power supply is guided into the destruction circuit when a preset condition is met; a detection circuit formed by a voltage-regulator tube and a voltage detection IC performs adaptive detection on various high voltages provided by the high-voltage power supply; and sequentially destroying the specific NAND FLASH of the solid state disk or according to different destroying channels, and controlling the on-off of GNDFx and GND of the corresponding channels in the destroying process. Layered GND isolation enables the damage rate of the main control chip to be reduced from 92% or above to 5% or below, the recovery value is remarkably improved, and the damage condition of the storage chip can be confirmed through the main control; and multi-stage protection control is combined with 3-5s high-voltage stable detection, so that the false triggering risk is reduced to be less than 0.1%.

Description

Technical Field

[0001] This invention relates to the field of data security, and specifically to a data destruction method for solid-state drives and a memory using this method. Background Technology

[0002] With increasingly stringent data security regulations (such as GDPR), the demand for physical destruction of solid-state drives (SSDs) has increased significantly. Existing data destruction technologies suffer from the following problems: Traditional physical destruction technologies have drawbacks: mechanical crushing equipment is bulky and expensive (over $20k per unit), and cannot selectively retain the main control chip, resulting in low chip recycling value; electrostatic destruction technology uses full-area high-voltage injection, resulting in a main control chip damage rate of over 92%, further restricting recycling and making it impossible to confirm the damage status of the storage chip through the main control chip.

[0003] The core problem with existing electrocution destruction technology: The lack of GND layer differentiation, with the controller and flash memory sharing a common ground wire, leads to indiscriminate damage during destruction, making the extent of damage uncontrollable. Low voltage detection accuracy (±5V error) results in a false trigger risk exceeding 1‰. The use of single-channel current injection prevents targeted destruction of specific flash memory chips; for 2TB and larger capacity hard drives, high current injection is required, making destruction difficult. Therefore, a data destruction method and a memory device employing this method are needed that can at least partially solve the above problems. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a data destruction method and a memory using the method to overcome or at least partially solve the above problems.

[0005] To address the aforementioned problems, this invention discloses a data destruction method, which comprises the following steps: Layered GND isolation steps: A three-tiered ground architecture of CGND, MGND, and GND_Fx is adopted. The connection of different ground lines is disconnected before the high-voltage input is destroyed to protect the chips and circuits other than NAND FLASH; where x represents the ground line corresponding to different destruction channels. Multi-level high-voltage protection control steps: The high-voltage power supply is controlled through the IO interfaces of multiple MCUs, and the high-voltage power supply is introduced into the destruction circuit only when preset conditions are met; Hardware adaptive dynamic high voltage threshold detection steps: The detection circuit, composed of a Zener diode and a voltage detection IC, adaptively detects various high voltages provided by the high voltage power supply. Multi-channel physical destruction steps: Destroy specific NAND FLASH of the solid-state drive or in sequence according to different destruction channels, and control the connection and disconnection of GND_Fx and GND of the corresponding channel during the destruction process.

[0006] Furthermore, the three-tier ground architecture of CGND, MGND, and GND_Fx includes: The CGND ground wire is the ground wire used by the main controller or other chips that need to be protected; MGND is the ground wire of the internal MCU controller of the solid-state drive, which is connected to the ground wire of the host and serves as the working ground wire of the solid-state drive. GND_Fx is the ground line used by NAND FLASH, where x represents the ground line corresponding to different destruction channels; the other chips are the chips in the solid-state drive other than the MCU controller and NAND FLASH.

[0007] Furthermore, the step of introducing high-voltage power into the destruction circuit only when preset conditions are met includes: The preset conditions are that the high-voltage power supply is continuously and stably supplied for 3-5 seconds, and the high-voltage detection circuit verifies that it has passed the test. The I / O interfaces of the multiple MCUs adopt a high-low level foolproof design. The first-stage switch is turned on by level control, and the subsequent switches can only be turned on if specific level conditions are met.

[0008] Furthermore, in the hardware adaptive dynamic high voltage threshold detection step, the various high voltages include 12V, 24V, and 28V; The circuit uses a Zener diode to match the corresponding high voltage value, and a voltage detection IC achieves voltage detection accuracy better than ±5V.

[0009] Furthermore, the multi-channel physical destruction step includes: Before destruction, disconnect all GND_Fx from MGND, and disconnect and isolate CGND from GND. Select the target destruction channel, and open the corresponding channel's control IO through the MCU to connect GND_Fx of that channel to GND; After releasing high voltage to the target NAND FLASH to complete the destruction, disconnect the connection between GND_Fx and GND of that channel, and then proceed to the next group of destructions; During the destruction process, the MCU records an indeletable destruction log.

[0010] Furthermore, in the layered GND isolation step, the switching state of the low-pass N MOSFET (Rds(on)=5mΩ) is controlled by the MCU controller to achieve discrete isolation between MGND and CGND, and between GND and GND_Fx.

[0011] Furthermore, it also includes a backup physical destruction trigger step: When the standard interface of a solid-state drive cannot be defined as a high-voltage destruction input pin, high voltage is introduced into the destruction circuit through a pin or stamp hole.

[0012] Furthermore, it also includes a destruction status indication step: when the standard interface of the solid-state drive cannot be defined as a high-voltage destruction input pin, the destruction status is fed back to an external indicator light through a pin or stamp hole to display the destruction process.

[0013] Furthermore, the non-deletable destruction log is stored inside the MCU to record the destruction history of the hard drive, and the log content cannot be tampered with or deleted.

[0014] This invention also discloses a memory that executes the above-described data destruction method when performing data destruction.

[0015] The embodiments of the present invention have the following advantages: This invention employs a three-tiered ground architecture (CGND, MGND, GND_Fx) to disconnect different ground lines before destroying the high-voltage input, thus protecting chips and circuits other than NAND FLASH. It controls the access of the high-voltage power supply through multiple MCU I / O interfaces, only introducing the high-voltage power supply into the destruction circuit when preset conditions are met. A detection circuit composed of a Zener diode and a voltage detection IC adaptively detects various high voltages provided by the high-voltage power supply. It destroys specific NAND FLASH chips of the solid-state drive or sequentially according to different destruction channels, controlling the connection and disconnection of GND_Fx and GND for the corresponding channels during the destruction process. Layered GND isolation reduces the main controller chip damage rate from over 92% to below 5%, significantly improving recycling value and allowing confirmation of memory chip damage status via the main controller; multi-level protection control combined with 3-5s high-voltage stability detection reduces the risk of false triggering to below 0.1‰; adaptive high-voltage threshold detection supports multiple voltages such as 12V, 24V, and 28V; multi-channel design enables the destruction of specified chips, adapting to 2TB and larger capacity hard drives; single-channel destruction power is lower than whole-disk destruction and eliminates the need for mechanical shredding equipment, reducing costs by over 60%; non-deletable destruction logs facilitate later auditing and meet data security regulatory requirements. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the steps of a data destruction method and a memory embodiment of the method according to the present invention. Figure 2 This is a complete flowchart of a data destruction method and a memory embodiment of the method according to the present invention; Figure 3 This invention relates to a data destruction method and a memory embodiment of the method, demonstrating the destruction logic. Detailed Implementation

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0019] like Figures 1 to 3 Some embodiments of this application provide a data destruction method, including: S1. Layered GND isolation steps: A three-tiered ground architecture of CGND, MGND, and GND_Fx is adopted. The connection of different ground lines is disconnected before the high-voltage input is destroyed to protect the chips and circuits other than NAND FLASH; where x represents the ground line corresponding to different destruction channels. S2, Multi-level high-voltage protection control steps: The high-voltage power supply is controlled through the IO interfaces of multiple MCUs, and the high-voltage power supply is introduced into the destruction circuit only when the preset conditions are met. S3. Hardware Adaptive Dynamic High Voltage Threshold Detection Steps: The detection circuit, composed of a Zener diode and a voltage detection IC, adaptively detects various high voltages supplied by the high voltage power supply. S4. Multi-channel physical destruction steps: Destroy specific NAND FLASH of the solid-state drive or in sequence according to different destruction channels, and control the connection and disconnection of GND_Fx and GND of the corresponding channel during the destruction process.

[0020] This invention aims to solve the problems of existing physical destruction technologies, which can only destroy the entire disk, cannot destroy specific particles, require a large current, and easily damage the main control chip. It achieves accurate, safe, and low-cost data destruction, while increasing the recycling value of chips.

[0021] The three-tiered ground architecture (CGND, MGND, GND_Fx) includes: CGND, the ground used by the main controller or other chips to be protected; MGND, the ground of the MCU controller inside the solid-state drive (SSD), connected to the host-side ground, serving as the SSD's working ground; and GND_Fx, the ground used by the NAND flash, where x represents the ground corresponding to different destruction channels. The "other chips" refer to the chips in the SSD other than the MCU controller and NAND flash. Clearly defining the functions of CGND (main controller protection ground), MGND (MCU working ground), and GND_Fx (flash memory destruction ground) ensures that high voltage only applies to the target NAND flash memory, physically isolating the main controller chip from the host-side circuitry, improving chip recovery rate, and allowing the main controller to confirm the damage status of the storage chip.

[0022] This invention employs a layered GND isolation system, pioneering a three-tiered ground architecture (CGND, MGND, GND_Fx). An MCU controls the switching state of a low-pass N-MOSFET (Rds(on) = 5mΩ), disconnecting different GND connections before high-voltage input. CGND protects the main controller and the chips requiring protection, MGND is the hard drive's operating ground, and GND_Fx corresponds to the NAND flash memory's destruction channel ground, achieving ground isolation between the main controller and the flash memory and preventing high-voltage damage to the main controller. Multiple MCU I / O interfaces are used for hierarchical control of the high-voltage power supply: the first stage opens the switch via level control, and subsequent stages employ a high-low level foolproof design, allowing high voltage to be introduced into the destruction circuit only after a sustained and stable high-voltage input for 3-5 seconds and passing detection, reducing the risk of false triggering to below 1‰.

[0023] The high-voltage power supply is directed to the destruction circuit only when preset conditions are met. These conditions include: a continuous and stable high-voltage power supply for 3-5 seconds, verified by a high-voltage detection circuit; and the multiple MCU I / O interfaces employing a high-low level foolproof design, with the first-stage switch opened via level control, and subsequent switches requiring specific level conditions to open. This "high-low level foolproof design" and multi-stage switch linkage mechanism (e.g., specific level conditions required for subsequent stages) prevent malfunctions caused by static electricity or accidental triggering. Simultaneously, the 3-5 second stable power supply requirement mitigates voltage fluctuation risks and enhances system reliability.

[0024] In the hardware adaptive dynamic high voltage threshold detection step, the various high voltages include 12V, 24V, and 28V; the circuit matches the corresponding high voltage value through a Zener diode, and the voltage detection IC achieves a voltage detection accuracy better than ±5V.

[0025] Hardware adaptive dynamic high voltage threshold detection consists of a detection circuit composed of a Zener diode (matching voltages such as 12V, 24V, and 28V) and a voltage detection IC. It enables adaptive identification of different high voltages, improving the detection accuracy to within ±0.5V and solving the problem of low detection accuracy in traditional methods.

[0026] The aforementioned multi-channel physical destruction divides the NAND flash chip into several channels, each corresponding to an independent GND_Fx. During destruction, all connections between GND_Fx and MGND, and between CGND and GND, are first disconnected. Then, the MCU reconnects the GND_Fx to GND of the target channel, thus destroying the specified chip. After destruction, the channel connection is disconnected and an indelible log is recorded before proceeding to the next group of destructions. This reduces the high-voltage power required for a single channel and protects other circuits for normal operation.

[0027] In some embodiments of this application, the multi-channel physical destruction steps include: disconnecting all GND_Fx from MGND before destruction, and simultaneously isolating CGND from GND; selecting a target destruction channel, and opening the control IO of the corresponding channel via the MCU to connect GND_Fx to GND; releasing high voltage to the target NAND FLASH to complete the destruction, then disconnecting the connection between GND_Fx and GND of that channel before proceeding to the next group of destructions; during the destruction process, the MCU records an indelible destruction log. Through dynamic channel switching, disconnecting all GND_Fx from MGND before destruction and connecting the target channel ground wire as needed enables precise destruction of specified particles, supporting scenarios where some data is retained (such as destroying only sensitive partitions). The MCU records and permanently stores the destruction log, meeting the audit requirements of regulations such as GDPR and providing legal compliance evidence of the destruction process.

[0028] In the layered GND isolation step, the switching state of the low-pass N MOSFET (Rds(on)=5mΩ) is controlled by the MCU controller to achieve discrete isolation between MGND and CGND, and between GND and GND_Fx.

[0029] In some embodiments of this application, a backup physical destruction triggering step is also included: when the standard interface of the solid-state drive cannot be defined as a high-voltage destruction input pin, high voltage is introduced into the destruction circuit through a pin or a stamp hole. Providing a backup high-voltage input path through the pin / stamp hole accommodates the destruction needs of non-standard interface SSDs (such as embedded devices), expanding the applicable scenarios for the solution.

[0030] It should be noted that the aforementioned perforations are holes resembling the shape of the stamp's edge. The term "perforation," like the word "rouette," originates from French (the French word for perforated paper refers to a toothed roller used for punching holes). Commonly known as stamp perforations, these are holes punched in stamps to facilitate the separation of stamps from a sheet.

[0031] It also includes a destruction status indication step: when the standard interface of the solid-state drive cannot be defined as a high-voltage destruction input pin, the destruction status is fed back to an external indicator light through a pin or stamp hole to display the destruction process. The external indicator light provides real-time feedback on the destruction progress, solving the problem of status monitoring for devices without interfaces, improving operational visibility, and avoiding human error in judging the destruction results.

[0032] The aforementioned non-deletable destruction log is stored internally within the MCU to record the hard drive's destruction history, and the log content cannot be tampered with or deleted. The MCU's internal storage of this immutable log ensures the authenticity and integrity of the destruction records, complies with the requirements of standards such as ISO 27001 for data tracking, and reduces the risk of legal disputes.

[0033] Furthermore, in the multi-channel physical destruction step, the high-voltage power during single-channel destruction is less than the power required for the destruction of the entire disk, and the circuits corresponding to unselected channels remain in a normal, non-operating state during the destruction process. This reduces heat dissipation and equipment costs by 90% (compared to full-domain high voltage), and the fact that unselected circuits remain inactive during single-channel destruction supports partial data reading during the destruction process (such as verifying undestroyed areas), while also reducing peak power consumption.

[0034] In some embodiments of this application, based on the same concept, a memory is also disclosed that can execute the above-described data destruction method. Under normal circumstances, the memory can be used as a solid-state drive. When data destruction is required, the above-described data destruction method is executed to destroy the data stored in it in an irreversible (catastrophic) manner, so as to protect confidential data and prevent data leakage.

[0035] As an example, a backup module design, such as a backup physical destruction trigger module, introduces high voltage through a pin or stamp hole, adapting to scenarios where the standard interface cannot be defined as a high voltage input pin; Backup physical destruction indicator module: Outputs destruction status via pin or stamp hole for easy external observation.

[0036] Compared with the prior art, the present invention has the following beneficial effects: (1) Precise protection of the main control chip: Layered GND isolation reduces the damage rate of the main control chip from more than 92% to less than 5%, significantly improving its recycling value; (2) Reduce the risk of false triggering: Multi-level protection control combined with 3-5s high voltage stability detection reduces the risk of false triggering to below 0.1‰; (3) Adaptable to multiple scenarios: The adaptive high voltage threshold detection supports multiple voltages such as 12V, 24V, and 28V. The multi-channel design enables the destruction of specified particles and is compatible with large-capacity hard drives of 2T and above. (4) Reduced energy consumption and cost: The power consumption of single-channel destruction is lower than that of whole-disc destruction, and no mechanical crushing equipment is required, reducing costs by more than 60%; (5) Traceability: The non-deletable destruction logs facilitate later auditing and meet the requirements of data security regulations.

[0037] In a specific example, the above data destruction method is used for a solid-state drive (SSD), which includes a high-voltage input module: using a custom pin (non-standard protocol pin) of the SSD as a high-voltage input pin, compatible with normal operating interfaces; GND switching module: It uses an NMOS (model XXX, Rds(on)=5mΩ) with a level conversion circuit to control the on / off state of CGND, MGND, and GND_Fx; High voltage detection circuit: includes a Zener diode (YYY for 12V and ZZZ for 24V) and a voltage detection IC (AAA) to achieve high voltage accuracy detection; MCU control module: Uses STM32F0 series MCU, controls the switching of high voltage switch and GND through multiple IO interfaces, and records destruction log; Backup trigger and indicator module: Two sets of pins (1mm in diameter) are set as backup high voltage input ports, and one set of stamp holes are connected to LED indicator lights (red light indicates destruction in progress, green light indicates completion).

[0038] When destruction is required, the following destruction process will be executed. High voltage input: External high voltage (such as 24V) is input through a custom pin or spare pin, and is continuously and stably supplied for 4 seconds; Threshold detection: The high-voltage detection circuit verifies that the voltage is within the range of 24V±0.5V and feeds the signal back to the MCU; GND isolation: The MCU controls the NMOS to disconnect CGND from MGND and all GND_Fx connections from MGND; Channel selection: The user specifies channel 3 (GND_F3) via command, and the MCU controls the corresponding NMOS to open the connection between GND_F3 and GND; High-voltage destruction: The MCU controls the high-voltage switch to turn on, injecting 24V high voltage into the 3rd channel NAND FLASH for 2 seconds until its VCC resistance to ground drops to 150Ω (meeting the destruction judgment criteria). State Reset: The MCU disconnects GND_F3 from GND and stores the destruction log (containing time and channel information) in the internal FLASH. The log cannot be erased. Update indicator: The backup indicator light changes from red to green, indicating that the channel has been destroyed.

[0039] Through the above destruction process, the third channel NAND FLASH could not be read for data and ID after destruction, which met the destruction standard; the GPIO function of the main control chip (STM32F0) was normal, and the DDR and DCDC chips worked stably; the single channel destruction power was 12W, which was only 20% of the total destruction (60W), thus verifying the above destruction effect.

[0040] In the above three-level grounding architecture, the isolation resistance between CGND and MGND is ≥10MΩ to ensure no leakage under high voltage; the multi-channel design supports up to 16 parallel channels, which can meet the partition destruction needs of 8T large-capacity hard drives; the undeletable log is stored using AES-256 encryption and can only be read by dedicated tools to prevent tampering.

[0041] It should be noted that in any embodiment of the present applicant, high voltage refers to a DC voltage that is 3V or 5V higher than the voltage of the memory, and the voltage that can damage the memory is at least not lower than 12V, such as 12V, 24V, or 28V.

[0042] In some embodiments of this application, in the initial state, all grounds GND (CGND, MGND, GND_Fx) are connected, and the system operates normally. When a destruction command is received, the system receives a high-voltage input signal through a preset high-voltage input pin (such as a custom pin or an unused pin). The MCU monitors the high-voltage input through a high-voltage detection circuit, confirming that the high voltage remains stable for 3-5 seconds to prevent false triggering. The MCU controls the NMOSFET to disconnect CGND from GND, protecting the main control chip and other circuits that need protection, and ensuring GND isolation. The MCU selects the NAND FLASH channel to be destroyed (such as GND_F1) according to a preset program or external command. The MCU controls the corresponding NMOSFET to connect the selected GND_F1 to GND, thus achieving the destruction channel connection. The MCU uses multi-stage PMOSFET control to introduce high-voltage power into the destruction circuit, thereby releasing the high voltage; then, the high-voltage current physically destroys the selected NAND FLASH through the connected GND_F1, thus performing the destruction. The MCU detects the current change in the destruction channel to confirm the destruction is complete, and then performs a destruction completion detection. The MCU then controls the NMOSFET to disconnect the destroyed GND_F1 from GND, thus disconnecting the channel. This process is repeated from selecting the destruction channel to disconnecting it.

[0043] After all destruction operations are completed, the MCU controls all NMOSFETs to restore the connection state of each GND, i.e., restore the initial state. The MCU records a detailed log of the destruction operation in its internal storage, including information such as destruction time and destruction channel, thus realizing operation logging.

[0044] Through this embodiment, the technical solution can achieve precise destruction of specific NAND FLASH while effectively protecting non-target components such as the main control chip, thus solving the problems existing in the prior art.

[0045] Furthermore, the high-voltage input module allows the use of custom pins or unused pins from the SSD to be defined as high-voltage input pins (which must not conflict with pins used in the SSD's standard protocol), ensuring compatibility with the SSD's normal operating interface. The physical interface of the high-voltage input guarantees compatibility between the high-voltage destruction function and the SSD's normal operating interface.

[0046] By utilizing existing unused PINs or custom PINs, a high-voltage input function is implemented without the need for an additional physical interface, allowing the destruction function to be integrated into standard SSDs and improving system compatibility. Secondly, by selecting a PIN that does not conflict with standard protocols, normal operation of the SSD is ensured when no destruction operation is performed, enhancing system usability and guaranteeing normal functionality. Thirdly, the use of dedicated or unused PINs reduces the risk of accidental triggering of the destruction function, improving security.

[0047] For example, in a standard M.2 SSD interface, there are usually some reserved, unused pins. We can choose one of these pins, such as pin 75, and define it as a high-voltage input pin. During normal use, this pin remains floating; when data destruction is required, a dedicated device or adapter can be connected to this pin to provide the necessary high-voltage input. This does not affect the daily use of the SSD while providing a convenient access point for data destruction functionality.

[0048] If the interface on a standard solid-state drive cannot be defined as a high-voltage destruction input pin, high voltage can be introduced into the destruction circuit through pins, stamp holes, or other means to complete the destruction. An alternative high-voltage input method is provided through a backup physical destruction trigger module, increasing the system's flexibility and applicability.

[0049] For SSDs where high-voltage input pins cannot be defined on standard interfaces, this provides an alternative solution, expanding the scope of technology application and increasing system applicability. By using pins or stamp holes, more physical implementation methods for high-voltage input are provided, allowing designers to choose the most suitable solution based on specific needs, thus improving design flexibility. This design enables the destruction function to be implemented without changing the standard SSD interface, improving compatibility with existing systems.

[0050] For example, on a standard 2.5-inch SATA SSD, we can design a small stamp hole on the edge of the PCB. This stamp hole does not affect the SSD's functionality during normal use, but when data destruction is required, a high-voltage signal can be input to the SSD's internal destruction circuitry through this stamp hole using a specialized tool. This design ensures both SSD standard compatibility and provides a discreet and effective triggering method for data destruction.

[0051] If the interface on a standard solid-state drive cannot be defined as a high-voltage destruction input pin, the destruction status can be displayed externally via pins, stamp holes, or other means for easy observation.

[0052] Visual indicators allow users to intuitively understand the status of the destruction process, improving operational convenience and reliability. Clear status indicators reduce the possibility of accidental operations and facilitate confirmation of successful completion, enhancing security. Flexible physical implementations for status indicators, such as pins or stamp holes, adapt to different application scenarios and provide flexible feedback methods.

[0053] For example, we could design a small LED indicator on the SSD's PCB, leading it through a perforated hole to the SSD casing. During normal use, this LED remains off. When the destruction process is initiated, the LED begins to flash, indicating that destruction is in progress. Once destruction is successful, the LED remains lit. If a problem occurs during destruction, the LED may flash at a specific frequency to indicate an error. This design provides users with intuitive visual feedback, making the destruction process more controllable and reliable.

[0054] By designing a circuit using a Zener diode and voltage detection IC, it can adapt to various high voltages, such as 12V, 24V, and 28V, providing a flexible high-voltage detection mechanism and enhancing the system's adaptability and safety. Adaptive design enables the system to adapt to different high-voltage inputs, increasing the device's versatility and applicability. Precise high-voltage detection helps prevent false triggering and misoperation, improving system reliability and safety. Dynamic threshold detection adjusts operating parameters according to the actual input voltage, ensuring optimal destruction results under various conditions.

[0055] For example, suppose we design a destruction system that can adapt to 12V, 24V, and 28V high-voltage inputs. We can use a 30V Zener diode and a programmable voltage sensing IC. The Zener diode is used to limit the input voltage and protect subsequent circuitry. The voltage sensing IC is controlled by an MCU, and different detection thresholds can be dynamically set.

[0056] When the system starts up, the MCU initially sets a low detection threshold (e.g., 10V). Once a voltage input is detected, the MCU gradually increases the threshold until a stable voltage level is found. For example, if the input is 24V, the system may find a stable point around 22V. Then, based on this detection result, the MCU selects appropriate parameters to control the subsequent destruction process. This automatic identification and adaptation to different high-voltage inputs, allowing for correct operation under various voltage conditions without manual intervention, greatly improves the system's flexibility and ease of use.

[0057] In enterprises or organizations with high security requirements, the physical destruction of SSDs containing sensitive data is often necessary. This core technology solution can achieve precise destruction of specific NAND flash memory while protecting non-target components such as the controller chip. However, in practical applications, a specific technical problem may be encountered: electromagnetic interference (EMI) during the destruction process.

[0058] When high-voltage current is used to destroy NAND flash memory, it generates a strong electromagnetic pulse (EMI), which can interfere with surrounding electronic equipment and even affect SSD components that are not destroyed. In dense data centers or highly integrated electronic environments, this EMI can cause other devices to malfunction or data errors. Furthermore, EMI can trigger false alarm systems, causing unnecessary disruption. This problem is primarily caused by the rapid changes in high-voltage current over a short period and the electromagnetic field coupling effects resulting from the complex circuitry within the SSD.

[0059] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0060] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0061] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0062] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0063] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0064] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0065] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0066] The present invention has provided a detailed description of a data destruction method and a memory using the method. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data destruction method, characterized in that, include: A three-tier ground architecture of CGND, MGND, and GND_Fx is adopted to disconnect different ground lines before destroying the high-voltage input, thereby protecting the chips and circuits other than NAND FLASH; where x represents the ground line corresponding to different destruction channels. The high-voltage power supply is controlled by multiple MCU I / O interfaces, and the high-voltage power supply is introduced into the destruction circuit only when preset conditions are met. The detection circuit, composed of a Zener diode and a voltage detection IC, adaptively detects various high voltages supplied by a high-voltage power supply. The system can destroy specific NAND flash memory of a solid-state drive or sequentially according to different destruction channels, and control the connection and disconnection of GND_Fx and GND of the corresponding channel during the destruction process.

2. The method according to claim 1, characterized in that, The three-order ground architecture of CGND, MGND, and GND_Fx includes: The CGND ground wire is the ground wire used by the main controller or other chips that need to be protected; MGND is the ground wire of the internal MCU controller of the solid-state drive, which is connected to the ground wire of the host and serves as the working ground wire of the solid-state drive. GND_Fx is the ground line used by NAND FLASH, where x represents the ground line corresponding to different destruction channels; the other chips are the chips in the solid-state drive other than the MCU controller and NAND FLASH.

3. The method according to claim 1, characterized in that, The step of introducing high-voltage power into the destruction circuit only when preset conditions are met includes: The preset conditions are that the high-voltage power supply is continuously and stably supplied for 3-5 seconds, and the high-voltage detection circuit verifies that it has passed the test. The I / O interfaces of the multiple MCUs adopt a high-low level foolproof design. The first-stage switch is turned on by level control, and the subsequent switches can only be turned on if specific level conditions are met.

4. The method according to claim 1, characterized in that, In the hardware adaptive dynamic high voltage threshold detection step, the various high voltages include 12V, 24V, and 28V. The circuit uses a Zener diode to match the corresponding high voltage value, and a voltage detection IC achieves voltage detection accuracy better than ±5V.

5. The method according to claim 1, characterized in that, The multi-channel physical destruction steps include: Before destruction, disconnect all GND_Fx from MGND, and disconnect and isolate CGND from GND. Select the target destruction channel, and open the corresponding channel's control IO through the MCU to connect GND_Fx of that channel to GND; After releasing high voltage to the target NAND FLASH to complete the destruction, disconnect the connection between GND_Fx and GND of that channel, and then proceed to the next group of destructions; During the destruction process, the MCU records an indeletable destruction log.

6. The method according to claim 1, characterized in that, In the layered GND isolation step, the switching state of the low-pass N MOSFET (Rds (on) = 5mΩ) is controlled by the MCU controller to achieve discrete isolation between MGND and CGND, and between GND and GND_Fx.

7. The method according to claim 1, characterized in that, It also includes a backup physical destruction trigger step: When the standard interface of a solid-state drive cannot be defined as a high-voltage destruction input pin, high voltage is introduced into the destruction circuit through a pin or stamp hole.

8. The method according to claim 1, characterized in that, It also includes a destruction status indication step: when the standard interface of the solid-state drive cannot be defined as a high-voltage destruction input pin, the destruction status is fed back to an external indicator light through a pin or stamp hole to show the destruction process.

9. The method according to claim 1, characterized in that, The non-deletable destruction log is stored inside the MCU to record the destruction history of the hard drive, and the log content cannot be tampered with or deleted.

10. A memory, characterized in that, When the memory performs data destruction, it executes the data destruction method described in any one of claims 1 to 9.

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