A method and system for RTL level partitioning for multiple FPGAs

Abstract

The application relates to an RTL level splitting method and system for multiple FPGAs, which are applied to the technical field of FPGAs, wherein FPGA refers to Field-Programmable Gate Array, and RTL level refers to Register Transfer Level; the method comprises the following steps: receiving and statically and exhaustively analyzing an RTL design file to obtain an RTL design processing file and an RTL tree structure file; splitting the RTL design processing file to obtain a splitting result file comprising a plurality of splitting areas; performing RTL splitting on the RTL tree structure file to obtain a plurality of RTL file lists corresponding to the plurality of splitting areas and boundary interconnection information; performing parallel synthesis according to the plurality of RTL file lists to obtain a plurality of synthesized netlist Verilog files; binding the plurality of synthesized netlist Verilog files according to the boundary interconnection information by using time division multiplexing channels to obtain a plurality of bound netlist Verilog files and constraint files; and performing top constraint and layout wiring according to the plurality of bound netlist Verilog files and the constraint files, and then performing multiple FPGA verification. The application has the technical effect that design codes can be better verified on multiple FPGAs.

Description

Technical Field

[0001] This application relates to the field of FPGA-related technology, and in particular to an RTL-level partitioning method and system for multiple FPGAs. Background Technology

[0002] In recent years, integrated circuits have become increasingly large-scale, and the application of large-scale digital circuits with billions or even tens of billions of gates will become more and more common, and the corresponding demand for auxiliary verification will also become more and more widespread.

[0003] Due to the reconfigurability, high speed, and low cost of FPGAs (Field-Programmable Gate Arrays), using FPGAs as hardware simulation accelerators and prototyping verification has become the mainstream choice in digital circuit design. However, the resource capacity of a single FPGA is limited. When the Design Under Test (DUT) is large, a multi-FPGA verification system formed by interconnecting multiple FPGAs is needed. Using this system as hardware implementation to assist in circuit logic design can achieve speedups of several orders of magnitude compared to software simulation. Automatically and appropriately partitioning the DUT to efficiently distribute it across multiple FPGAs is an important problem that needs to be solved in practical engineering.

[0004] The logic partitioning of large-scale circuits can be modeled as a hypergraph partitioning problem, which is essentially a constrained multi-objective combinatorial optimization problem. Currently, a heuristic algorithm is commonly used, employing a multi-level partitioning framework consisting of three stages: node coarsening (clustering), initial partitioning, and local improvement.

[0005] Currently, most segmentation algorithms are still based on netlist segmentation. Netlist segmentation requires the synthesis of the user's design, which consumes a lot of time and increases the engineering iteration time. At the same time, synthesis will optimize away a lot of the original user signals, causing the user to be unable to track the signals of the original design well. Summary of the Invention

[0006] To better verify design code across multiple FPGAs, this application provides an RTL-level partitioning method and system for multiple FPGAs.

[0007] Firstly, this application provides the following technical solution:

[0008] Receive RTL design files, perform static detailed analysis on the RTL design files to obtain RTL design processing files and RTL tree structure files;

[0009] The RTL design processing file is segmented to obtain a segmentation result file, which includes several segmented regions.

[0010] Based on the segmentation result file, the RTL tree structure file is segmented using RTL to obtain a list of RTL files corresponding to several segmented regions and boundary interconnection information.

[0011] Several synthesized netlists in Verilog are obtained by performing parallel synthesis based on several lists of RTL files;

[0012] Based on the boundary interconnection information, several integrated netlist Verilog files are bound together using a time-division multiplexing channel to obtain several bound netlist Verilog files and constraint files.

[0013] Multi-FPGA verification is performed after top-level constraints and place-and-route based on several bound netlist Verilog files and constraint files.

[0014] Through the above technical solution, the method of this application adopts RTL-level partitioning, which fully preserves the hierarchical structure and signals of the user design. The early stage of verification does not require a synthesis process, saving a lot of synthesis time. Parallel synthesis is adopted after partitioning, which shortens the iterative development time and is more conducive to obtaining an optimized solution.

[0015] In one specific feasible implementation, performing a static detailed analysis of the RTL design file to obtain the RTL design processing file and the RTL tree structure file includes:

[0016] A static detailed analysis is performed on the RTL design file to obtain an RTL design processing file, which includes several design modules and several design instances.

[0017] The RTL design processing file is parsed to obtain several design RTL files corresponding to several design instances;

[0018] The RTL design processing file is analyzed in a tree structure to obtain an RTL tree structure file, which includes several nodes representing several design instances and several design RTL files corresponding to several design instances.

[0019] Through the above technical solution, this application outputs an RTL tree structure file that records the tree structure of the user's design, preserving the hierarchical relationship of the original design, which helps to achieve more accurate segmentation and signal tracking. Simultaneously, mapping each design instance to a node provides finer-grained control, which is beneficial for subsequent resource estimation and allocation.

[0020] In one specific implementation, the netlist partitioning of the RTL design processing file to obtain the partitioned result file includes:

[0021] A detailed analysis of the RTL design processing file yields the first RTL design processing file;

[0022] Resource usage information is obtained by estimating the resource usage of several design modules in the first RTL design processing file;

[0023] Based on the resource usage information, the netlist partitioning algorithm is invoked to partition the first RTL design processing file into a partitioned result file. The partitioned result file includes partition boundaries, several partitioned regions, and partition information. The partition information includes information on several partitioned regions assigned to several nodes on the partition boundaries.

[0024] The above technical solution provides an important basis for decision-making in the segmentation algorithm by estimating the resource consumption of each design module, which helps to achieve a more balanced allocation of FPGA resources.

[0025] In one specific implementation scheme, the detailed analysis of the RTL design processing file to obtain the first RTL design processing file includes:

[0026] A detailed analysis of the RTL design processing files yielded several non-design example code files and several design example code files;

[0027] Combine the aforementioned non-design example code files into a single non-design example code file;

[0028] The first RTL design processing file is obtained by integrating the non-design example code file and several design example code files.

[0029] By combining the non-design instance code files using the above technical solution, the design structure is simplified, and resource estimation and subsequent partitioning are facilitated.

[0030] In a specific implementation, the step of performing RTL segmentation on the RTL tree structure file based on the segmentation result file to obtain a list of RTL files corresponding to a number of segmented regions and boundary interconnection information includes:

[0031] The nodes in the RTL tree structure file are numbered hierarchically from the root to the top of the RTL tree structure file.

[0032] Combine several nodes on the dividing boundary into an array;

[0033] Based on the segmentation result file, the array is used to process several nodes to obtain a list of several RTL files and boundary interconnection information corresponding to several segmented regions.

[0034] In a specific implementation, the step of processing several nodes using the array based on the segmentation result file to obtain a list of several RTL files and boundary interconnection information corresponding to several segmented regions includes:

[0035] Select the processing nodes with the largest numbers from the array;

[0036] Based on the segmentation result file, determine the segmentation information of several processing nodes;

[0037] Construct a list of RTL files corresponding to several of the segmented regions;

[0038] Based on the RTL tree structure file and the segmentation information, add the design RTL files of the processing nodes to the list of RTL files.

[0039] Find several parent nodes of the aforementioned processing nodes;

[0040] The original RTL file of the parent node is called based on the RTL tree structure file;

[0041] The original RTL file is processed and added to a list of several RTL files, and the boundary interconnection information of the several processing nodes is recorded;

[0042] Add the aforementioned parent nodes to the array;

[0043] The array is processed in a loop until all nodes in the array have been processed, resulting in a complete set of RTL files and boundary interconnection information.

[0044] In one specific implementation, processing the original RTL file and adding it to a list of several RTL files, and recording the boundary interconnection information of the several processing nodes, includes:

[0045] Sequentially determine whether several child nodes of several parent nodes are assigned to different segmentation regions;

[0046] If several child nodes of the parent node are assigned to different segmentation regions, then the segmentation region information of the several child nodes is recorded.

[0047] The original RTL file is divided according to the segmentation region to obtain several parent node segmented RTL files;

[0048] Record the boundary interconnection information of several of the child nodes;

[0049] Add the parent node split RTL files to the list of RTL files;

[0050] If several child nodes of the parent node are not assigned to different segmentation regions, then several original RTL files are added to several RTL files.

[0051] The above technical solution maintains the hierarchical structure of the design by numbering nodes by level, facilitating top-down or bottom-up processing. Using arrays to store nodes on the segmentation boundaries provides an efficient data structure, which is convenient for subsequent segmentation operations. This method ensures the orderliness and controllability of the segmentation process, and helps to generate more optimized segmentation results.

[0052] Secondly, this application provides an RTL-level partitioning system for multiple FPGAs, employing the following technical solution: The system includes:

[0053] An RTL design file receiving module is used to receive RTL design files, perform static detailed analysis on the RTL design files to obtain RTL design processing files and RTL tree structure files. Specifically, it is used to perform static detailed analysis on the RTL design files to obtain RTL design processing files, wherein the RTL design processing files include several design modules, and each design module includes several design instances; parse the RTL design processing files to obtain several design RTL files corresponding to the several design instances; and perform tree structure analysis on the RTL design processing files to obtain RTL tree structure files, wherein the RTL tree structure files include several nodes representing the several design instances and several design RTL files corresponding to the several design instances.

[0054] The netlist segmentation module is used to segment the RTL design processing file to obtain a segmentation result file, which includes several segmentation regions.

[0055] The RTL segmentation module is used to perform RTL segmentation on the RTL tree structure file according to the segmentation result file to obtain a list of RTL files and boundary interconnection information corresponding to a number of segmented regions. Specifically, it is used to number the nodes in the RTL tree structure file hierarchically from the root to the apex of the RTL tree structure file; combine the nodes on the segmentation boundary into an array; and process the nodes using the array according to the segmentation result file to obtain a list of RTL files and boundary interconnection information corresponding to a number of segmented regions.

[0056] The netlist synthesis module is used to perform parallel synthesis based on several RTL file lists to obtain several synthesized Verilog file lists.

[0057] The binding module is used to bind several integrated netlist Verilog files using a time-division multiplexing channel according to the boundary interconnection information to obtain several bound netlist Verilog files and constraint files;

[0058] The multi-FPGA verification module is used to perform multi-FPGA verification after top-level constraints and placement and routing based on several bound netlist Verilog files and constraint files.

[0059] Thirdly, this application provides a computer device that adopts the following technical solution: it includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described above for an RTL-level partitioning method for multiple FPGAs.

[0060] Fourthly, this application provides a computer-readable storage medium that stores a computer program capable of being loaded by a processor and executed as described above for an RTL-level partitioning method for multiple FPGAs.

[0061] In summary, this application has the following beneficial technical effects:

[0062] (1) The method of this application adopts RTL-level partitioning, which fully preserves the hierarchical structure and signals of the user design. No synthesis process is required in the early stage of verification, saving a lot of synthesis time. Parallel synthesis is adopted after partitioning, which shortens the iterative development time and is more conducive to obtaining an optimized solution.

[0063] (2) The RTL tree structure file output by this application records the tree structure of the user's design, which preserves the hierarchical relationship of the original design and helps to achieve more accurate segmentation and signal tracking. At the same time, each design instance is mapped to a node, which provides finer-grained control and is beneficial for subsequent resource estimation and allocation.

[0064] (3) By estimating the resource consumption of each design module, an important decision basis is provided for the partitioning algorithm, which helps to achieve a more balanced allocation of FPGA resources. Combining non-design instance code files simplifies the design structure and facilitates resource estimation and subsequent partitioning. Attached Figure Description

[0065] Figure 1 This is a flowchart of an RTL-level partitioning method for multiple FPGAs in an embodiment of this application.

[0066] Figure 2 This is a flowchart of RTL segmentation.

[0067] Figure 3 This is an example diagram of RTL segmentation.

[0068] Figure 4This is a structural block diagram of an RTL-level partitioning method for multiple FPGAs in an embodiment of this application.

[0069] Figure reference numerals: 401, RTL design file receiving module; 402, netlist segmentation module; 403, RTL segmentation module; 404, netlist synthesis module; 405, bonding module; 406, multi-FPGA verification module. Detailed Implementation

[0070] The following is in conjunction with the appendix Figures 1-4 This application will be described in further detail.

[0071] This application discloses an RTL-level partitioning method for multiple FPGAs, which is used to better verify design code on multiple FPGAs.

[0072] In recent years, integrated circuits have become increasingly large-scale, and the application of large-scale digital circuits with billions or even tens of billions of gates will become more and more common, and the corresponding demand for auxiliary verification will also become more and more widespread.

[0073] Due to their reconfigurability, high speed, and low cost, FPGAs have become the mainstream choice for hardware simulation accelerators and prototyping in digital circuit design. However, the resource capacity of a single FPGA is limited. When the Design Under Test (DUT) is large, a multi-FPGA verification system is needed, formed by interconnecting multiple FPGAs. Using this system as hardware implementation to assist in circuit logic design can achieve speedups of several orders of magnitude compared to software simulation. Automatically and appropriately partitioning the DUT to efficiently distribute it across multiple FPGAs is an important problem that needs to be solved in practical engineering.

[0074] The logic partitioning of large-scale circuits can be modeled as a hypergraph partitioning problem, which is essentially a constrained multi-objective combinatorial optimization problem. Currently, a heuristic algorithm is commonly used, employing a multi-level partitioning framework consisting of three stages: node coarsening (clustering), initial partitioning, and local improvement.

[0075] Currently, most segmentation algorithms are still based on netlist segmentation. Netlist segmentation requires the synthesis of the user's design, which consumes a lot of time and increases the engineering iteration time. At the same time, synthesis will optimize away a lot of the original user signals, causing the user to be unable to track the signals of the original design well.

[0076] Therefore, this application proposes an RTL-level partitioning method for multiple FPGAs, which enables better verification of design code across multiple FPGAs. Here, FPGA refers to Field-Programmable Gate Array, and RTL level refers to Register Transfer Level.

[0077] like Figure 1 As shown, the method includes:

[0078] S10: Receive the RTL design file, perform a static detailed analysis on the RTL design file to obtain the RTL design processing file and the RTL tree structure file.

[0079] Specifically, it reads in the user-designed RTL design file, such as... Figure 2 This is an RTL partitioning flowchart. On the left is the static detailed analysis module, in which static detailed analysis and hierarchical structure analysis are performed to obtain the RTL design processing file (_static.v) and the RTL tree structure file (tree.json).

[0080] S20, the RTL design processing file is segmented to obtain a segmentation result file, which includes several segmented regions.

[0081] Specifically, such as Figure 2 The netlist partitioning module in the RTL partitioning flowchart shows that the RTL design processing file is input into the netlist partitioning module, and the RTL design processing file is analyzed in detail, resources are estimated and partitioned to obtain the partitioning result file (cut_notes.json). The partitioning here is used to reasonably distribute the RTL design processing file to multiple FPGAs for verification, so the partitioning result file includes several partitioned regions.

[0082] The netlist split here does not produce a fully synthesized netlist; the output is only a Verilog file and not a netlist file.

[0083] S30, perform RTL segmentation on the RTL tree structure file based on the segmentation result file to obtain a list of RTL files and boundary interconnection information corresponding to several segmented regions.

[0084] Specifically, such as Figure 2 The RTL segmentation module in the RTL segmentation flowchart shows that the RTL design processing file and the segmentation result file are input into the RTL segmentation module. Based on the segmentation result file, the RTL tree structure file is segmented by RTL to obtain a list of RTL files corresponding to several segmented regions and boundary interconnection information (cut_info.json).

[0085] S40, based on a list of RTL files, performs parallel synthesis to obtain several synthesized netlists in Verilog format.

[0086] Specifically, multiple synthesis tasks are launched simultaneously for a list of Verilog files, and the resulting synthesis netlist Verilog files are output.

[0087] S50: Based on the boundary interconnection information, several integrated netlist Verilog files are bound together using a time-division multiplexing channel to obtain several bound netlist Verilog files and constraint files.

[0088] Specifically, based on the boundary interconnection information, a time-division multiplexing channel is allocated to each interconnection signal, and several binding netlist Verilog files and constraint files are output after the binding is completed. Time division multiplexing (TDM) is the core technology that enables multiple signals to share the same physical channel through time division.

[0089] S60 performs multi-FPGA verification after top-level constraints and place-and-route based on several bound netlist Verilog files and constraint files.

[0090] Specifically, based on several bound netlist Verilog files and constraint files, the constraints of the top-level I / O are configured, the placement and routing are performed using the Vivado tool, and the final output bit file can be used for board verification.

[0091] The method used in this application adopts RTL-level partitioning, which fully preserves the hierarchical structure and signals of the user design. No synthesis process is required in the early stage of verification, saving a lot of synthesis time. Parallel synthesis is adopted after partitioning, which shortens the iterative development time and is more conducive to obtaining an optimized solution.

[0092] In one embodiment, to better verify design code across multiple FPGAs, the step of performing a static detailed analysis of the RTL design files to obtain RTL design processing files and RTL tree structure files can be specifically performed as follows:

[0093] First, a static detailed analysis is performed on the RTL design file to obtain the RTL design processing file. The RTL design processing file includes several design modules, and each design module includes several design instances. Specifically, Static Elaboration is performed on the user-designed RTL design file to output the RTL design processing file (_static.v). The RTL design processing file includes several design modules, and each design module is further refined into several design instances.

[0094] Then, the RTL design processing file is parsed to obtain several design RTL files corresponding to several design instances. Specifically, one RTL file is output for each design module. Since the design module is further subdivided into several design instances, the RTL design processing file is parsed to obtain several design RTL files corresponding to several design instances.

[0095] Next, a tree structure analysis is performed on the RTL design processing file to obtain an RTL tree structure file. The RTL tree structure file includes several nodes used to represent several design instances and several design RTL files corresponding to several design instances. Specifically, a tree structure analysis is performed on the RTL design processing file to obtain an RTL tree structure file. One node in the RTL tree structure file corresponds to one design instance, and the node is recorded as the design RTL file corresponding to the design instance.

[0096] This application outputs an RTL tree structure file that records the tree structure of the user's design, preserving the hierarchical relationship of the original design, which helps with more accurate segmentation and signal tracing. Simultaneously, mapping each design instance to a node provides finer-grained control, facilitating subsequent resource estimation and allocation.

[0097] In one embodiment, to better verify design code across multiple FPGAs, the step of performing netlist partitioning on the RTL design processing file to obtain a partitioned result file can be specifically performed as follows:

[0098] First, a detailed analysis of the RTL design processing file is performed to obtain the first RTL design processing file. Resource usage is estimated for several design modules in the first RTL design processing file to obtain resource usage information. Specifically, a detailed analysis of the RTL design processing file is performed to obtain the first RTL design processing file. Resource usage is estimated for several design modules in the first RTL design processing file to obtain resource usage information. The resource usage of each design module is estimated.

[0099] Next, based on the resource usage information, the netlist partitioning algorithm is invoked to partition the first RTL design processing file into a netlist, resulting in a partitioned file. This file includes partition boundaries, several partitioned regions, and partition information. The partition information includes the partitioned region information corresponding to several nodes on the partition boundaries. Specifically, based on the resource usage information, the netlist partitioning algorithm is invoked to partition the first RTL design processing file into a netlist, resulting in a partitioned file. Figure 3 This is an example of a partitioning scenario. The dashed lines in the diagram represent the partitioning boundaries. The first RTL design file is partitioned into netlists, as shown below. Figure 3 The shown partition boundary divides the first RTL design processing file into two partition regions. The partition result file will include the partition boundary, several partition regions, and partition information. The partition information refers to the partition region information corresponding to several nodes on the partition boundary.

[0100] By estimating the resource consumption of each design module, an important basis for decision-making in the partitioning algorithm is provided, which helps to achieve a more balanced allocation of FPGA resources.

[0101] In one embodiment, to better verify design code across multiple FPGAs, the step of performing a detailed analysis of the RTL design processing file to obtain a first RTL design processing file can be specifically performed as follows:

[0102] First, a detailed analysis of the RTL design processing file is performed to obtain several non-design instance code files and several design instance code files. The several non-design instance code files are combined into a total non-design instance code file. Specifically, the RTL design processing file is read in, Elaboration (detailed analysis) is performed, and all non-design instance code files inside the design module are combined to obtain the total non-design instance code file.

[0103] Next, the non-design instance code file and several design instance code files are integrated to obtain the first RTL design processing file. Specifically, the non-design instance code files in the RTL design processing file are combined into the non-design instance code file to obtain the first RTL design processing file.

[0104] Combining non-design instance code files simplifies the design structure and facilitates resource estimation and subsequent partitioning.

[0105] In one embodiment, to better verify design code across multiple FPGAs, the step of performing RTL segmentation on the RTL tree structure file based on the segmentation result file to obtain a list of RTL files corresponding to several segmented regions and boundary interconnection information can be specifically performed as follows:

[0106] First, the nodes in the RTL tree structure file are numbered hierarchically, from the root to the tip, in ascending order. Specifically, each node in the RTL tree structure file is numbered hierarchically (from the root to the tip), with the top-level node having the smallest number. Figure 3 For example, node h is numbered 0, nodes g and d are numbered 1; nodes e and f are numbered 2, and nodes a, b and c are numbered 3;

[0107] Then, the nodes on the dividing boundary are grouped into an array. Specifically, the nodes on the dividing boundary are added to the array leveledNodes[depth][] according to their numbers. Figure 3 For example, the nodes on the dividing boundary are node a, node b, node c, and node d. Nodes a, b, c, and d are combined into an array.

[0108] Next, based on the segmentation result file, several nodes are processed using an array to obtain a list of several RTL files and boundary interconnection information corresponding to several segmented regions. Specifically, based on the segmentation result file, several nodes are processed using an array to obtain a list of several RTL files and boundary interconnection information corresponding to several segmented regions.

[0109] In one embodiment, to better verify design code across multiple FPGAs, the step of processing several nodes using an array based on the segmentation result file to obtain a list of several Verilog files and boundary interconnection information corresponding to several segmented regions can be specifically performed as follows:

[0110] First, select the processing nodes with the highest numbers from the array. Specifically, select the processing nodes with the highest numbers from the array, using... Figure 3 For example, the array includes nodes a, b, c, and d. The nodes with the largest numbers are nodes a, b, and c. Therefore, nodes a, b, and c are determined to be the processing nodes.

[0111] Then, based on the segmentation result file, the segmentation information of several processing nodes is determined. Specifically, based on the segmentation result file, the segmentation information of several processing nodes is determined, in order to... Figure 3 For example, based on the segmentation result file, it can be determined that node a and node b are in the same segmentation region, which is named segmentation region 1. Node c is in another segmentation region, which is named segmentation region 2.

[0112] Next, construct a list of RTL files corresponding to several segmented regions. Specifically, construct RTL file lists for segmented regions 1 and 2 respectively to store the Verilog files of the nodes in the corresponding regions.

[0113] Then, based on the RTL tree structure file and the segmentation information, several design RTL files of several processing nodes are added to several RTL file lists. Specifically, the design RTL files of nodes a, b and c are obtained from the RTL tree structure file, and the design RTL files are stored in the RTL file lists of segmentation regions 1 and 2 according to the segmentation information.

[0114] Next, find several parent nodes of several processing nodes; specifically, find several parent nodes of several processing nodes, in order to... Figure 3 For example, the parent node of node a is node e, and the parent node of nodes b and c is node f;

[0115] Next, the original RTL file of the parent node is called according to the RTL tree structure file. The original RTL file is processed and added to a list of several RTL files. The boundary interconnection information of several processing nodes is recorded. Specifically, the original RTL file of the parent node is called according to the RTL tree structure file. The difference between parent node e and parent node f is that the child node a of parent node e is assigned to the same partition region, while the child nodes b and c of parent node f are assigned to different partition regions. The original Verilog file is processed according to different situations and added to a list of several Verilog files. The boundary interconnection information of several processing nodes is recorded.

[0116] Then, add several parent nodes to the array. Specifically, put the processed parent node e and parent node f into the array to get a new array: node e, node f and node d;

[0117] Finally, the array is processed in a loop until all nodes in the array have been processed, resulting in a number of complete RTL files and boundary interconnection information. Specifically, for a new array, the parent node of the node with the largest number is processed in sequence until all nodes in the array have been processed, resulting in a number of complete RTL files and boundary interconnection information.

[0118] In one embodiment, to better verify design code across multiple FPGAs, the step of processing the original RTL file and adding it to a list of several RTL files, and recording the boundary interconnect information of several processing nodes, can be specifically performed as follows:

[0119] First, determine in turn whether several child nodes of several parent nodes are assigned to different partition regions. Specifically, the difference between parent node e and parent node f is that child node a of parent node e is assigned to the same partition region, while child nodes b and c of parent node f are assigned to different partition regions.

[0120] Next, if several child nodes of the parent node are assigned to different partition regions, the partition region information of the child nodes is recorded. Specifically, if several child nodes of the parent node are assigned to different partition regions, for example, child nodes b and c of parent node f are assigned to different partition regions.

[0121] Then, the original RTL file is split according to the segmentation region to obtain several parent node segmented RTL files. Specifically, the original RTL file is split to obtain several parent node segmented RTL files. For example, the original RTL file of parent node f will be split into two parent node segmented RTL files. One parent node segmented RTL file (f1) represents node b, and the other parent node segmented RTL file 2 (f2) represents node c.

[0122] Next, record the boundary interconnection information of several child nodes; specifically, record the boundary interconnection information between node b and node c.

[0123] Then, add several parent node split RTL files to several RTL file lists. Specifically, add several parent node split RTL files to several RTL file lists. For example, add parent node split RTL file (f1) to the RTL file list of split region 1, and add parent node split RTL file (f2) to the RTL file list of split region 2.

[0124] Next, if several child nodes of the parent node are not assigned to different partition regions, several original RTL files are added to several RTL files. Specifically, if several child nodes of the parent node are not assigned to different partition regions, for example, if child node a of parent node e is assigned to a partition region, the original RTL file corresponding to parent node e is directly added to the RTL file list of partition region 1.

[0125] It should also be noted that, with Figure 3 To illustrate how the new array will be processed, for the new array: nodes e, f, and d, first process the nodes with the largest numbers, e and f; the parent node of nodes e and f is node g, and the child node f of node g is divided into different partition regions; the original RTL file of node g is divided into parent node partition RTL files, one parent node partition file (g1) corresponds to the partition RTL file of child node e and parent node f (f1), and another parent node partition file (g2) corresponds to the partition RTL file of parent node f (f2), and then stored in the RTL file list of different partition regions; record the boundary interconnection relationship; finally, add node g to the new array.

[0126] For the new array: nodes g and d; both have the same number and are processed simultaneously; the design RTL file of node d is placed in the RTL file list of segmentation region 2; the parent node of nodes g and d is node h, while the child node g of node h is segmented into different segmentation regions; the original RTL file of node h is divided into parent node segmentation RTL files, one parent node segmentation file (h1) corresponds to the child node e and the parent node g segmentation RTL file (g1), and another parent node segmentation file (h2) corresponds to the parent node g segmentation RTL file (g2), and then stored in the RTL file list of different segmentation regions accordingly; the boundary interconnection relationship is recorded; after processing, all nodes in the node h array are processed.

[0127] Additionally, it should be noted that merging the RTL file lists of different segmentation regions yields an overall design file list used for simulation verification of the segmentation results.

[0128] Based on the above method, embodiments of this application are also disclosed. For example... Figure 4 The system includes the following modules:

[0129] RTL design file receiving module 401 is used to receive RTL design files and perform static detailed analysis on the RTL design files to obtain RTL design processing files and RTL tree structure files.

[0130] The netlist segmentation module 402 is used to segment the RTL design processing file to obtain a segmentation result file, which includes several segmented regions.

[0131] RTL segmentation module 403 is used to perform RTL segmentation on the RTL tree structure file according to the segmentation result file to obtain a list of RTL files and boundary interconnection information corresponding to several segmentation regions.

[0132] Netlist synthesis module 404 is used to perform parallel synthesis based on a list of RTL files to obtain a list of synthesized netlists in Verilog files.

[0133] The binding module 405 is used to bind several integrated netlist Verilog files using a time-division multiplexing channel based on boundary interconnection information to obtain several bound netlist Verilog files and constraint files;

[0134] The multi-FPGA verification module 406 is used to perform multi-FPGA verification after top-level constraints and placement and routing based on several bound netlist Verilog files and constraint files.

[0135] In one embodiment, the RTL design file receiving module 401 is specifically used to perform static detailed analysis on the RTL design file to obtain an RTL design processing file, the RTL design processing file including several design modules, and the design modules including several design instances; parse the RTL design processing file to obtain several design RTL files corresponding to the several design instances; perform tree structure analysis on the RTL design processing file to obtain an RTL tree structure file, the RTL tree structure file including several nodes for representing several design instances and several design RTL files corresponding to the several design instances.

[0136] In one embodiment, the netlist segmentation module 402 is specifically used to perform a detailed analysis of the RTL design processing file to obtain a first RTL design processing file; to perform resource usage estimation on several design modules in the first RTL design processing file to obtain resource usage information; and to call the netlist segmentation algorithm to perform netlist segmentation on the first RTL design processing file based on the resource usage information to obtain a segmentation result file. The segmentation result file includes segmentation boundaries, several segmentation regions, and segmentation information. The segmentation information includes information on several segmentation regions corresponding to several nodes on the segmentation boundaries.

[0137] In one embodiment, the netlist segmentation module 402 is specifically used to perform a detailed analysis of the RTL design processing file to obtain several non-design instance code files and several design instance code files; combine the several non-design instance code files into a total non-design instance code file; and integrate the total non-design instance code file and several design instance code files to obtain a first RTL design processing file.

[0138] In one embodiment, the RTL segmentation module 403 is specifically used to number several nodes in the RTL tree structure file from the root part of the RTL tree structure file to the twig part of the RTL tree structure file in ascending order of size according to the hierarchy; combine several nodes on the segmentation boundary into an array; and process several nodes using the array according to the segmentation result file to obtain several Verilog file lists and boundary interconnection information corresponding to several segmented regions.

[0139] In one embodiment, the RTL segmentation module 403 is specifically used to: filter out a number of processing nodes with the largest numbers from the array; determine the segmentation information of the processing nodes according to the segmentation result file; construct a list of RTL files corresponding to the segmented regions; add the design RTL files of the processing nodes to the list of RTL files according to the RTL tree structure file and the segmentation information; find the parent nodes of the processing nodes; call the original RTL files of the parent nodes according to the RTL tree structure file; process the original RTL files and add them to the list of RTL files, and record the boundary interconnection information of the processing nodes; add the parent nodes to the array; and process the array in a loop until all nodes in the array have been processed to obtain a complete list of netlist RTL files and boundary interconnection information.

[0140] In one embodiment, the RTL segmentation module 403 is specifically used to sequentially determine whether several child nodes of several parent nodes are assigned to different segmentation regions; if several child nodes of a parent node are assigned to different segmentation regions, then record the segmentation region status of several child nodes; segment the original RTL file according to the segmentation region status to obtain several parent node segmented RTL files; record the boundary interconnection information of several child nodes; add several parent node segmented RTL files to a list of several RTL files; if several child nodes of a parent node are not assigned to different segmentation regions, then add several original RTL files to several RTL files.

[0141] This application also discloses a computer device.

[0142] Specifically, the computer device includes a memory and a processor, the memory storing a computer program that can be loaded by the processor and executed as described above for an RTL-level partitioning method for multiple FPGAs.

[0143] This application also discloses a computer-readable storage medium.

[0144] Specifically, the computer-readable storage medium stores a computer program that can be loaded and executed by a processor, such as the RTL-level partitioning method for multiple FPGAs described above. The computer-readable storage medium includes, for example, various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0145] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A method for RTL-level partitioning of multiple FPGAs, characterized in that, The method includes: Receive RTL design files, perform static detailed analysis on the RTL design files to obtain RTL design processing files and RTL tree structure files; The RTL design processing file is segmented to obtain a segmentation result file, which includes several segmentation regions and segmentation boundaries. Based on the segmentation result file, the RTL tree structure file is segmented using RTL to obtain a list of RTL files and boundary interconnection information corresponding to several segmented regions. Several synthesized netlists in Verilog are obtained by performing parallel synthesis based on several lists of RTL files; Based on the boundary interconnection information, several integrated netlist Verilog files are bound together using a time-division multiplexing channel to obtain several bound netlist Verilog files and constraint files. After performing top-level constraints and place-and-route based on several bound netlist Verilog files and constraint files, multi-FPGA verification is performed. The static detailed analysis of the RTL design file to obtain the RTL design processing file and the RTL tree structure file includes: A static detailed analysis is performed on the RTL design file to obtain an RTL design processing file, which includes several design modules and several design instances. The RTL design processing file is parsed to obtain several design RTL files corresponding to several design instances; The RTL design processing file is analyzed in a tree structure to obtain an RTL tree structure file, which includes several nodes for representing several design instances and several design RTL files corresponding to several design instances; The segmentation result file includes segmentation boundaries. The step of performing RTL segmentation on the RTL tree structure file based on the segmentation result file to obtain a list of several RTL files corresponding to several segmented regions and boundary interconnection information includes: The nodes in the RTL tree structure file are numbered hierarchically from the root to the top of the RTL tree structure file. Combine several nodes on the dividing boundary into an array; Based on the segmentation result file, the array is used to process several nodes to obtain a list of several RTL files and boundary interconnection information corresponding to several segmented regions.

2. The method according to claim 1, characterized in that, The segmentation of the RTL design processing file to obtain the segmentation result file includes: A detailed analysis of the RTL design processing file yields the first RTL design processing file; Resource usage information is obtained by estimating the resource usage of several design modules in the first RTL design processing file; The first RTL design processing file is segmented based on the resource occupancy information using a netlist segmentation algorithm to obtain a segmentation result file. The segmentation result file includes a segmentation boundary, several segmentation regions, and segmentation information. The segmentation information includes information on several segmentation regions assigned to several nodes on the segmentation boundary.

3. The method according to claim 2, characterized in that, The detailed analysis of the RTL design processing file to obtain the first RTL design processing file includes: A detailed analysis of the RTL design processing files yielded several non-design example code files and several design example code files; Combine the aforementioned non-design example code files into a single non-design example code file; The first RTL design processing file is obtained by integrating the non-design example code file and several design example code files.

4. The method according to claim 3, characterized in that, The step of processing several nodes using the array based on the segmentation result file to obtain a list of several RTL files and boundary interconnection information corresponding to several segmented regions includes: Select the processing nodes with the largest numbers from the array; Based on the segmentation result file, determine the segmentation information of several processing nodes; Construct a list of RTL files corresponding to several of the segmented regions; Based on the RTL tree structure file and the segmentation information, add the design RTL files of the processing nodes to the list of RTL files. Find several parent nodes of the aforementioned processing nodes; The original RTL file of the parent node is called based on the RTL tree structure file; The original RTL file is processed and added to a list of several RTL files, and the boundary interconnection information of the several processing nodes is recorded; Add the aforementioned parent nodes to the array; The array is processed in a loop until all nodes in the array have been processed, resulting in a complete list of several RTL files and the boundary interconnection information.

5. The method according to claim 4, characterized in that, The process of processing the original RTL file and adding it to a list of several RTL files, and recording the boundary interconnection information of the several processing nodes, includes: Sequentially determine whether several child nodes of several parent nodes are assigned to different segmentation regions; If several child nodes of the parent node are assigned to different segmentation regions, then the segmentation region information of the several child nodes is recorded. The original RTL file is divided according to the segmentation region to obtain several parent node segmented RTL files; Record the boundary interconnection information of several of the child nodes; Add the parent node split RTL files to the list of RTL files; If several child nodes of the parent node are not assigned to different segmentation regions, then several original RTL files are added to several RTL file lists.

6. An RTL-level partitioning system for multiple FPGAs, characterized in that, The system includes: The RTL design file receiving module (401) is used to receive RTL design files, perform static detailed analysis on the RTL design files to obtain RTL design processing files and RTL tree structure files. Specifically, it is used to perform static detailed analysis on the RTL design files to obtain RTL design processing files, wherein the RTL design processing files include several design modules, and each design module includes several design instances; parse the RTL design processing files to obtain several design RTL files corresponding to the several design instances; and perform tree structure analysis on the RTL design processing files to obtain RTL tree structure files, wherein the RTL tree structure files include several nodes representing the several design instances and several design RTL files corresponding to the several design instances. The netlist segmentation module (402) is used to segment the RTL design processing file to obtain a segmentation result file, wherein the segmentation result file includes several segmentation regions and segmentation boundaries; The RTL segmentation module (403) is used to perform RTL segmentation on the RTL tree structure file according to the segmentation result file to obtain a list of RTL files and boundary interconnection information corresponding to a number of segmented regions. Specifically, it is used to number the nodes in the RTL tree structure file from the root part to the tip part of the RTL tree structure file in ascending order of size according to the hierarchy; combine the nodes on the segmentation boundary into an array; and process the nodes using the array according to the segmentation result file to obtain a list of RTL files and boundary interconnection information corresponding to a number of segmented regions. The netlist synthesis module (404) is used to perform parallel synthesis based on several RTL file lists to obtain several synthesized netlist Verilog files; The binding module (405) is used to bind several of the integrated netlist Verilog files according to the boundary interconnection information using a time-division multiplexing channel to obtain several bound netlist Verilog files and constraint files; The multi-FPGA verification module (406) is used to perform multi-FPGA verification after top-level constraints and placement and routing based on several bound netlist Verilog files and constraint files.

7. A computer device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed according to any one of claims 1 to 5.

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