Method for generating standard cell physical layout and related device

Abstract

The application belongs to the technical field of semiconductor design automation, and provides a standard cell physical layout generation method and related equipment. The method comprises: obtaining design data of a to-be-designed standard cell and multi-patterning process constraint parameters under a target process; performing layout on transistors in the to-be-designed standard cell according to the design data and the multi-patterning process constraint parameters, wherein, in the layout process, the transistors in the to-be-designed standard cell are dynamically folded and / or source-drain shared, and the feasibility of a gate cutting process and a contact via cutting process is synchronously detected; after the layout on the transistors in the to-be-designed standard cell is completed, a multi-network synchronous optimization strategy is used to perform wiring on the to-be-designed standard cell to generate a standard cell physical layout, wherein, in the wiring process, signature data is integrated to optimize the wiring. The technical scheme provided by the application can improve the generation efficiency of the standard cell physical layout.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design automation, and particularly relates to a standard cell physical layout generation method and related equipment. BACKGROUND

[0002] A standard cell is a core component unit of an integrated circuit, and the quality (such as area, performance, and process compatibility) of the physical layout of the standard cell directly determines the power consumption, timing characteristics, and production yield of the entire chip. With the continuous evolution of the semiconductor process node to 7nm and below advanced processes, the transistor structure has been transformed from a planar transistor to a fin field effect transistor (FinFET), and the layout constraints of the fin (Fin) and gate (Gate) are more stringent, and the coverage rules (such as the cross-gate width and the gate spacing) of the contact via (Contact / Via) have a more significant impact on process feasibility. However, the traditional standard cell physical layout generation method is based on mature processes (≥28nm) and planar transistor design, which is not fully adapted to the technical characteristics of advanced processes, resulting in obvious process adaptation limitations in 7nm and below process scenarios, which seriously affects the generation efficiency of the standard cell layout.

[0003] Therefore, how to improve the generation efficiency of the standard cell physical layout becomes a technical problem to be solved. SUMMARY

[0004] Embodiments of the present application provide a standard cell physical layout generation method, device, computer program product, computer readable storage medium, and electronic equipment, which can improve the generation efficiency of the standard cell physical layout to a certain extent.

[0005] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0006] According to a first aspect of the embodiments of the present application, a method for generating a standard cell physical layout is provided. The method comprises: obtaining design data of a standard cell to be designed, the design data being used to define transistor connection relationships of the standard cell to be designed, and size requirements and performance requirements of the standard cell to be designed, the transistor connection relationships being used to define functional requirements of the standard cell to be designed; obtaining multi-patterning process constraint parameters under a target process, the multi-patterning process constraint parameters being used to define process rules of a self-aligned double pattern, process rules of a self-aligned quadruple pattern, and process rules of contact via coverage; performing layout on transistors in the standard cell to be designed according to the design data and the multi-patterning process constraint parameters, wherein, during the layout process, the transistors in the standard cell to be designed are dynamically folded and / or source-drain shared, and the feasibility of a gate cutting process and a contact via cutting process is synchronously detected; after the layout on the transistors in the standard cell to be designed is completed, a multi-network synchronous optimization strategy is used to perform wiring on the standard cell to be designed, so as to generate a standard cell physical layout, wherein, during the wiring process, sign-off data is integrated to optimize the wiring.

[0007] In some embodiments of the present application, based on the foregoing scheme, the obtaining of the multi-patterning process constraint parameters under the target process comprises: integrating the gate cutting rules of the self-aligned double pattern, the fin splitting rules of the self-aligned quadruple pattern, and the constraint rules of the contact via position into a standardized parameter set based on a pre-established unified process model; obtaining process data of a target wafer factory, and assigning values to the standardized parameter set based on the process data, to obtain the multi-patterning process constraint parameters.

[0008] In some embodiments of the present application, based on the foregoing scheme, the dynamic folding and source-drain sharing of the transistors in the standard cell to be designed comprises: dynamically splitting a target transistor in the standard cell to be designed into a plurality of equivalent sub-units in a gate extension direction according to the design data and the multi-patterning process constraint parameters, and overlapping the plurality of equivalent sub-units in the gate extension direction, to realize dynamic folding of the target transistor, wherein the number of fins of the equivalent sub-unit is a divisor of the number of fins of the target transistor, and the number of gates of the equivalent sub-unit is the same as the number of gates of the target transistor; according to wiring requirements, performing polarity interchanging on the source and the drain of the equivalent sub-unit, to realize source-drain sharing of the target transistor.

[0009] In some embodiments of the present application, based on the foregoing scheme, dynamically folding the transistors in the standard cell to be designed comprises: dynamically splitting a target transistor in the standard cell to be designed into a plurality of equivalent sub-cells in the fin extension direction according to the design data and the multi-patterning process constraint parameters, and overlapping the plurality of equivalent sub-cells in the fin extension direction to achieve dynamic folding of the target transistor, wherein the number of fins of the equivalent sub-cells is the same as the number of fins of the target transistor, and the number of gates of the equivalent sub-cells is a divisor of the number of gates of the target transistor; and performing polarity exchange of the source and drain of the equivalent sub-cells according to the wiring requirement.

[0010] In some embodiments of the present application, based on the foregoing scheme, during the layout process, the method further comprises: determining candidate positions of the contact via according to the fin distribution characteristics, the candidate positions maintaining a preset alignment relationship with the fin positions; screening the candidate positions based on the maximum gate-crossing width and the minimum gate spacing requirements in the process rules of the contact via coverage; and retaining the candidate positions satisfying the process rules of the contact via coverage to form a candidate position set of the contact via.

[0011] In some embodiments of the present application, based on the foregoing scheme, the synchronization detection of the feasibility of the gate cutting process and the contact via cutting process comprises: extracting the layout-to-be-designed parameters of the transistor, the layout-to-be-designed parameters including the position, height, width of the gate cutting region, and the gate spacing, and the candidate position, size, gate-crossing width, and distance from the gate of the contact via; detecting whether the height of the gate cutting region is not less than the minimum cutting height specified by the process, the distance between the edge of the gate cutting region and the edge of the adjacent gate is not less than the minimum safety distance specified by the process, and the gate cutting region is continuous based on the process rules of the self-aligned double pattern; detecting whether the gate-crossing width of the contact via is not greater than the maximum gate-crossing width specified by the process, the distance between the edge of the contact via and the edge of the gate is not less than the minimum gate-hole spacing specified by the process, and the size of the contact via is within the process allowable range based on the process rules of the contact via coverage; detecting whether there is an overlap between the projection of the candidate position of the contact via and the gate cutting region, and the distance between the edge of the gate cutting region and the edge of the contact via is not less than the minimum cooperative spacing specified by the process; and if any of the detection items fails, adjusting the layout-to-be-designed parameters and returning to perform the detection step until all the detection items pass.

[0012] In some embodiments of the present application, based on the foregoing scheme, the multi-network synchronization optimization strategy is used to wire the standard cell to be designed, including: integrating power supply networks, ground networks and signal networks into a unified optimization space, and constructing a three-dimensional variable pitch wiring grid; allocating wiring resources of each network based on a flow conservation model, and considering signal transmission characteristics and mutual interference constraints of different networks in the process of allocating wiring resources of each network; and using a parallel optimization algorithm to cooperatively search for wiring paths of multiple networks to avoid global wiring conflicts caused by single network optimization.

[0013] In some embodiments of the present application, based on the foregoing scheme, the three-dimensional variable pitch wiring grid is constructed, including: setting differentiated grid pitches for wiring directions and minimum line width requirements of different metal layers, wherein the grid pitches of transverse metal layers and longitudinal metal layers are in a complementary relationship; reducing the grid pitch in a signal dense area and expanding the grid pitch in a power supply network area to form a three-dimensional grid structure with adaptive density; and labeling compatibility information of contact vias at grid nodes of the three-dimensional grid structure to guide connection path selection between different metal layers.

[0014] In some embodiments of the present application, based on the foregoing scheme, the signature data is integrated to optimize wiring, including: converting timing delay, current density, voltage drop and signal integrity parameters in the signature data into wiring weight factors; prioritizing wiring tracks of different metal layers based on the wiring weight factors, wherein the weight factor of a high-level metal track is dynamically adjusted according to its delay characteristics; and preferentially selecting a track path with the optimal weight factor in the wiring process to achieve pre-matching of the wiring result with the signature requirement.

[0015] In some embodiments of the present application, based on the foregoing scheme, after generating the standard cell physical layout, the method further includes: performing process rule verification on the standard cell physical layout; and saving the standard cell physical layout that meets the target requirements in a standard cell library after the standard cell physical layout passes the verification.

[0016] In some embodiments of the present application, based on the foregoing scheme, the process rule verification on the standard cell physical layout includes: calling a process rule checking engine to verify whether transistor layouts in the standard cell physical layout meet the multi-patterning process constraint parameters, and to verify whether transistor wiring in the standard cell physical layout meets physical rules including metal line width, pitch, via size, and signature indicators including timing and power consumption; and if there is a violation, reversely adjusting transistor layout parameters or wiring paths of the standard cell to be designed according to the violation type until all verification items pass.

[0017] According to a second aspect of the embodiments of the present application, a device for generating a standard cell physical layout is provided. The device includes: a first obtaining unit configured to obtain design data of a standard cell to be designed, the design data being used to define transistor connection relationships of the standard cell to be designed, and size requirements and performance requirements of the standard cell to be designed, the transistor connection relationships being used to define functional requirements of the standard cell to be designed; a second obtaining unit configured to obtain multi-patterning process constraint parameters under a target process, the multi-patterning process constraint parameters being used to define process rules of a self-aligned double pattern, process rules of a self-aligned quadruple pattern, and process rules of contact via coverage; a layout unit configured to perform layout on transistors in the standard cell to be designed according to the design data and the multi-patterning process constraint parameters, wherein, during the layout, the transistors in the standard cell to be designed are dynamically folded and / or source-drain shared, and the feasibility of a gate cut process and a contact via cut process is synchronously detected; and a routing unit configured to perform routing on the standard cell to be designed by using a multi-network synchronous optimization strategy after the layout on the transistors in the standard cell to be designed is completed, to generate a standard cell physical layout, wherein, during the routing, review data is integrated to optimize the routing.

[0018] According to a third aspect of the embodiments of the present application, a computer program product is provided. The computer program product includes computer instructions stored in a computer readable storage medium, and adapted to be read and executed by a processor, so that a computer device having the processor performs operations performed by the method according to the first aspect.

[0019] According to a fourth aspect of the embodiments of the present application, a computer readable storage medium is provided. The computer readable storage medium stores at least one computer program instruction. The at least one computer program instruction is loaded and executed by a processor to implement operations performed by the method according to the first aspect.

[0020] According to a fifth aspect of the embodiments of the present application, an electronic device is provided. The electronic device includes one or more processors and one or more memories. The one or more memories store at least one computer program instruction. The at least one computer program instruction is loaded and executed by the one or more processors to implement operations performed by the method according to the first aspect.

[0021] Based on the technical scheme provided in the present application, by obtaining the design data and multi-patterning process constraint parameters in advance, clear basis is provided for subsequent processes, repeated trial and error caused by parameter missing is avoided, and invalid operations are reduced from the source. In the transistor layout stage, by dynamically performing transistor folding and source-drain sharing, the area utilization can be optimized under the premise of meeting the functional requirements, and layout redundancy is reduced, and the feasibility of gate cutting and contact via cutting is detected synchronously, process compliance verification is embedded into the transistor layout process, potential violation problems can be found and solved in advance, and the situation of large-scale adjustment due to process conflict after layout completion is avoided, and rework time is saved. In the wiring stage, by using the multi-network synchronous optimization strategy, the traditional single-network step-by-step wiring fragmentation mode can be broken, the power supply, ground and signal networks can be planned uniformly, the disconnection and redistribution caused by network conflict can be reduced, and the wiring optimization can be integrated into the signing data, so that the wiring result can be adapted to the timing, power consumption and other signing requirements in advance, and the probability of failing the verification in the later stage is reduced. In this way, through data input, layout optimization, wiring adaptation, and process compliance closed loop, each link is closely connected, the cross-stage adjustment cost can be reduced, the period from design to generation of compliant standard cell layout can be greatly shortened, and the generation efficiency of the standard cell physical layout is improved to a certain extent.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0023] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0024] Figure 1 A flowchart of a method for generating a standard cell physical layout in an embodiment of the present application is shown;

[0025] Figure 2 A schematic diagram of folding and source-drain sharing of transistors in a to-be-designed standard cell according to an embodiment of the present application is shown;

[0026] Figure 3 A block diagram of a standard cell physical layout generation device in an embodiment of the present application is shown;

[0027] Figure 4 A structural schematic diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.

[0029] In addition, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a sufficient understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring the aspects of the present application.

[0030] The block diagrams shown in the accompanying drawings are only functional entities, which do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices. It should be noted that in the accompanying drawings, in order to ensure the simplicity of the drawings, some components in the drawings are omitted, which do not affect the explanation of the technical solutions of the present application.

[0031] The flowcharts shown in the accompanying drawings are only exemplary illustrations, which do not necessarily include all contents and operations / steps, and are not necessarily executed in the described order. For example, some operations / steps can be further divided, and some operations / steps can be combined or partially combined, so that the actual execution order can be changed according to the actual situation.

[0032] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0033] The implementation details of the technical solutions of the embodiments of the present application are described below:

[0034] Referring to Figure 1 , a flowchart of a standard cell physical layout generation method in the embodiments of the present application is shown, which can be executed by a device with computing processing function. Referring to Figure 1As shown, the method for generating the standard cell physical layout includes steps 110-140, which are described in detail as follows:

[0035] In step 110, design data of a standard cell to be designed is obtained, the design data being used to define transistor connection relationships of the standard cell to be designed, and size requirements and performance requirements of the standard cell to be designed, the transistor connection relationships being used to define functional requirements of the standard cell to be designed.

[0036] In the present application, the standard cell to be designed refers to a basic functional unit of an integrated circuit which has not yet been designed in terms of physical layout, but has clear functional, performance, size and process adaptation requirements for a specific advanced process (such as FinFET, GAA, CFET). For example, a connection relationship of two PMOS transistors in parallel and two NMOS transistors in series corresponds to a “2-input NAND gate (NAND2)”, and for example, a connection relationship of four PMOS transistors in parallel and four NMOS transistors in series corresponds to a “4-input NAND gate (NAND4)”.

[0037] In the present application, the design data can include one or more of a transistor-level netlist, a hardware description language (HDL) file, and a circuit schematic diagram. These data can be used to define transistor connection relationships of the standard cell to be designed, wherein the transistor connection relationships are used to define functional requirements of the standard cell to be designed. In other words, the transistor connection relationships can describe the logic function of the standard cell to be designed (i.e., what function can be implemented by the standard cell to be designed, such as NAND4, DFF) by clearly defining the connection logic of the transistors in the standard cell to be designed (such as the number of transistors, the type (P-FET / N-FET), and the connection network of the source (S) / gate (G) / drain (D) (such as VDD, VSS, input pin IN, output pin OUT)).

[0038] In the present application, the design data can include one or more of a physical constraint file, a standard cell library template file, and a chip layout plan. These data can be used to define size requirements of the standard cell to be designed, which can clearly define the physical boundary constraints of the standard cell to be designed, and ensure that the generated layout can adapt to the overall layout plan of the chip, such as height (i.e., height along the gate extension direction), cell width (i.e., width along the fin extension direction)).

[0039] In the present application, the design data can include one or more of a timing constraint file (SDC file, Synopsys Design Constraints), a power consumption constraint file (UPF file, Unified Power Format), and a performance specification document. These data can be used to define the performance requirements of the standard cell to be designed. They can explicitly indicate the electrical performance indicators of the standard cell to be designed, such as signal delay (transmission time of a signal from input to output), driving capability (number of downstream cells that can be driven), and static power consumption (leakage current power consumption when idle) targets, to ensure that the generated layout not only can be manufactured, but also can meet the functional requirements of the chip, such as low delay for high-frequency processors and low power consumption for Internet of Things chips.

[0040] With reference to the foregoing Figure 1 In step 120, multi-patterning process constraint parameters under the target process are obtained, which are used to define the process rules of self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and contact via coverage (COAG).

[0041] In the present application, the multi-patterning process constraint parameters are critical for adapting to 7nm and below processes, and are used to define the manufacturing rules of advanced processes.

[0042] In the present application, the process rules of self-aligned double patterning are mainly for cutting and forming of gates. For example, the minimum size of a gate cut region (CT), the minimum distance between the cut edge and the gate, etc.

[0043] In the present application, the process rules of self-aligned quadruple patterning are mainly for forming of fins. For example, the minimum distance between fins, the minimum length of fins, etc.

[0044] In the present application, the process rules of contact via coverage are mainly for the position and size of contact vias (CA, connecting transistors and metal layers). For example, the maximum gate-crossing width of a contact via (the maximum allowed width of a contact via covering a gate), the minimum distance between a contact via and a gate, etc.

[0045] In the present application, the obtaining of the multi-patterning process constraint parameters under the target process can be performed according to the following steps 121 to 122:

[0046] Step 121, based on the pre-established unified process model, the self-aligned double pattern gate cutting rule, the self-aligned four-fold pattern fin splitting rule and the constraint rule of contact via position are integrated into a standardized parameter set.

[0047] Step 122, the process data of the target wafer factory is obtained, and the standardized parameter set is valued based on the process data, to obtain the multi-pattern process constraint parameter.

[0048] In this application, the unified process model can be understood as a standard rule abstract framework, which does not contain specific numerical values, only by extracting common rule dimension, defining standardized parameter name, and explicitly defining the mapping relationship between parameter and rule, the scattered self-aligned double pattern gate cutting rule, self-aligned four-fold pattern fin splitting rule and contact via position constraint rule are integrated into a structured standardized parameter set, which realizes the description of process rules of different wafer factories on the same parameter.

[0049] Further, by obtaining and importing the process data of the target wafer factory, the standardized parameter set is converted into specific constraint values which can be directly used for layout design, and the multi-pattern process constraint parameter can be obtained.

[0050] In order for those skilled in the art to better understand the present application, a specific embodiment is described below in combination with Table 1.

[0051] Table 1: Standardized parameter set example

[0052]

[0053] Based on Table 1, for example, the process data of wafer factory A is: "CT cutting area height ≥ 18 nm, CT end point and adjacent track deviation ≤ 2 nm, fin center distance ≥ 9.5 nm, Fin width = 8 nm, contact hole across Gate maximum 10 nm, CA and CT distance ≥ 8 nm". Based on the process data, the multi-pattern process constraint parameter is obtained: "CT_min=18nm, CT_s=2nm, Fin_pitch=9.5nm, Fin_width=8nm, Omax=10nm, CA_CT_s_min=8nm".

[0054] In the present application, the fragmentation problem of different wafer factory process rules can be solved by unifying the process model, and the manufacturing feasibility of the parameters is ensured by wafer factory process data assignment. In the present application, the multi-patterning process constraint parameters generated based on the method can simultaneously support SADP, SAQP and COAG three process rules, and can realize dynamic adaptation and scalability of multiple rules, and provide accurate process basis for subsequent transistor dynamic folding and multi-network synchronous routing. At the same time, based on the method, the calculation amount does not increase with the increase of process type through parameterized design, so as to significantly improve the calculation efficiency and the generation efficiency of the standard cell physical layout. Moreover, the standardized parameter set can ensure that the process constraints of different wafer factories are processed in the same dimension, avoid layout deviation caused by rule description difference, and improve process consistency.

[0055] With reference to the foregoing Figure 1 In step 130, transistors in the standard cell to be designed are laid out according to the design data and the multi-patterning process constraint parameters, wherein in the layout process, the transistors in the standard cell to be designed are dynamically folded and / or source-drain shared, and the feasibility of the gate cutting process and the contact via cutting process is synchronously detected.

[0056] In the present application, the layout of the transistors in the standard cell to be designed mainly includes the shape, size, spatial position, source-drain-gate connection association and process adaptation structure of the transistors in the standard cell to be designed. The spatial position needs to determine the arrangement coordinates of the transistors in the standard cell in the width direction (fin extension direction) and the height direction (gate extension direction), so as to ensure that the spacing of the transistors meets the self-aligned quadruple pattern fin spacing rule; the source-drain-gate connection association needs to match the transistor connection relationship in the design data, and clearly define the source-drain sharing mode (such as drain-source multiplexing of series transistors), and the corresponding connection of the gate and the input signal; the process adaptation structure needs to layout the range of the gate cutting area (i.e. the minimum height meeting the self-aligned double pattern regulation), and the candidate position of the contact via (meeting the cross-gate limitation of the contact via coverage), so as to lay a foundation for the subsequent synchronous detection of process feasibility.

[0057] In the present application, the dynamic folding and source-drain sharing of the transistors in the standard cell to be designed can be performed according to the following steps 1311 to 1321:

[0058] Step 1311, according to the design data and the multi-patterning process constraint parameters, dynamically splitting the target transistor in the standard cell to be designed into multiple equivalent sub-cells in the gate extension direction, and overlapping the multiple equivalent sub-cells in the gate extension direction to realize dynamic folding of the target transistor, wherein the number of fins of the equivalent sub-cell is a divisor of the number of fins of the target transistor, and the number of gates of the equivalent sub-cell is the same as the number of gates of the target transistor.

[0059] Step 1321, according to the wiring requirement, performing polarity interchanging of the source and the drain of the equivalent sub-cell to realize source-drain sharing of the target transistor.

[0060] In the present application, the transistor in the standard cell to be designed can be dynamically folded in combination with the design data (such as cell width, height limit) of the standard cell to be designed and the multi-patterning process constraint (such as fin pitch, gate cutting size). It should be noted that the dynamic folding here refers to not presetting a fixed splitting rule, but optimizing the folding multiple, equivalent sub-cell arrangement and polarity in real time to meet the design size requirement, conform to the process constraint, and adapt to subsequent wiring and detection, and finally realize the optimal balance of cell area and wiring efficiency on the premise of keeping the electrical performance of the transistor unchanged.

[0061] Specifically, first, an integer multiple folding multiple (the multiple is the ratio of the original number of fins (w) of the target transistor to the maximum allowed number of fins of a single equivalent sub-cell) can be determined, which needs to ensure that the number of fins (w / n, n is the folding multiple) of the equivalent sub-cell after splitting is a divisor of the original number to maintain the total driving capability unchanged; then the original transistor of w fins and g gates is split into n equivalent sub-cells of w / n fins and g gates, the number of gates of all equivalent sub-cells is consistent with that of the original transistor, and the equivalent sub-cells are connected in parallel through a metal line (such as M0 layer) (such as being connected to the same input signal), to ensure that the switching state is synchronized; finally, the equivalent sub-cells can be overlapped in the gate extension direction to reduce the size of the transistor in the gate extension direction.

[0062] In the present application, the source-drain sharing is based on the structural symmetry of the source and the drain of the transistor, and the electrical performance is unchanged after the polarity interchanging. According to the wiring requirement (such as the series / parallel relationship of the transistor, the distance between the source / drain and the metal track), the polarity of the source / drain of the equivalent sub-cell is interchanged (source→drain, drain→source), so that the source or the drain of adjacent equivalent sub-cells is overlapped in the physical position, and the same diffusion area is reused through metal interconnection, to reduce the redundant diffusion area and parasitic capacitance.

[0063] In order for those skilled in the art to better understand the present application, the following will combine the specific embodiments of the present application with the prior art to make a better comparison. Figure 2With a specific embodiment as an example.

[0064] Referring to Figure 2 , a schematic diagram of folding and source-drain sharing of a transistor in a to-be-designed standard cell is shown according to an embodiment of the present application.

[0065] As shown in Figure 2 , "S" represents the source of the transistor, "G" represents the gate of the transistor, and "D" represents the drain of the transistor. As shown in subgraph (a) in Figure 2 , the target transistor includes 4 fins and 1 gate; as shown in subgraph (b) in Figure 2 , the transistor in subgraph (a) can be split into two equivalent subunits of "2 fins and 1 gate", realizing folding of the transistor; as shown in subgraph (c) in Figure 2 , by performing polarity exchange of the source and the drain on one of the equivalent subunits in subgraph (b), source-drain sharing of the transistor is realized.

[0066] Based on the technical solutions in steps 1311 to 1321, the following effects can be achieved:

[0067] Firstly, dynamic folding can reduce the size of the standard cell by splitting and overlapping, and source-drain sharing can further reduce the number of redundant diffusion regions, electrodes, and contact vias, thereby significantly reducing the area of the to-be-designed standard cell and greatly improving the chip integration; secondly, source-drain sharing can reduce the length of the diffusion region boundary and the parasitic capacitance, and in combination with the operation of "polarity exchange adaptive metal track", it can also reduce the wiring length and the parasitic resistance and capacitance; at the same time, dynamic folding supports adjusting the number of equivalent subunit splitting according to the size requirement, and source-drain sharing can adapt to different connection relationships, thereby improving the electrical characteristics and layout flexibility.

[0068] In the present application, the dynamic folding of the transistor in the to-be-designed standard cell can also be performed according to the following steps 1312 to 1322:

[0069] Step 1312, according to the design data and the multi-patterning process constraint parameters, dynamically splitting a target transistor in the to-be-designed standard cell into a plurality of equivalent subunits in the fin extension direction, and overlapping the plurality of equivalent subunits in the fin extension direction thereof, to realize dynamic folding of the target transistor, wherein the fin number of the equivalent subunit is the same as the fin number of the target transistor, and the gate number of the equivalent subunit is a divisor of the gate number of the target transistor.

[0070] Step 1322, according to the wiring requirement, performing polarity exchange of the source and the drain of the equivalent subunit.

[0071] In the present application, it should be understood that the transistor folding logic and sequence in the above steps 1312 to 1322 are opposite to the transistor folding logic and sequence in the above steps 1311 to 1321, and the present application will not make too much repetition on the technical details.

[0072] Based on the technical solutions in the above steps 1312 to 1323, the advantage is that, after the multiple equivalent sub-units overlap in the fin extension direction, the total number of fins of the overall transistor becomes a multiple of the original target transistor fin number (for example, a target transistor with 4 fins is split into 2 equivalent sub-units, and the total fin number increases to 8 after overlapping). As fins are the core current channels of advanced process transistors (such as fin field effect transistors), their number directly determines the current scale that can be carried when turned on, that is, the more fins, the more parallel channels for current passing, and the stronger the maximum carrying capacity of the on-current, thereby significantly enhancing the driving capability of the transistor and better meeting the high-performance requirements of high-speed signal transmission and large load driving.

[0073] In the present application, the following steps 133 to 135 can also be performed during the layout process:

[0074] Step 133, determining a candidate position of the contact via according to the fin distribution characteristics, the candidate position maintaining a preset alignment relationship with the fin position.

[0075] Step 134, screening the candidate position based on the maximum gate width across and the minimum gate spacing requirement in the process rule of the contact via coverage.

[0076] Step 135, retaining the candidate positions that meet the process rule of the contact via coverage to form a candidate position set of the contact via.

[0077] In the present application, the essence of the contact via is to connect the diffusion region and the M0 layer, and the position and form of the diffusion region are completely determined by the distribution of the fins. Therefore, the candidate position of the contact via must be strongly bound to the fin distribution characteristics, and the preset alignment relationship can ensure that the contact via can effectively cover the diffusion region.

[0078] Further, since the generated candidate position of the contact via only meets the basic requirement of alignment with the fin, the core constraints in the process rule of the contact via coverage, that is, the maximum gate width across and the minimum gate spacing, have not been considered. Based on step 134, the initial candidate position is filtered through the process rule of the contact via coverage, which can eliminate the candidate positions that violate the rule and ensure that the remaining candidate positions meet the manufacturing requirements.

[0079] In the present application, the compliant candidate positions of the contact via after screening by step 134 can be further integrated into a structured candidate position set, which can be understood as a contact via position library for subsequent routing stages, that is, there is no need to calculate or verify the contact via position temporarily during subsequent routing, and the candidate position matching the M0 / M1 track is directly selected from the candidate position set.

[0080] Based on the above steps 133 to 135, the initial candidate positions are generated based on the fin as the physical reference, and then the candidate positions that violate the process rules of the contact via coverage are filtered and integrated into a structured candidate position set. Not only can it ensure that the contact via can effectively connect the diffusion region and the metal layer, but also can avoid the core risk of the contact via coverage process in advance, lay a solid foundation for subsequent multi-network synchronous routing and process rule verification, and is beneficial to generate high-yield and high-efficiency standard cell physical layout in subsequent generation.

[0081] In the present application, the feasibility of the synchronous detection gate cutting process and the contact via cutting process can be performed according to the following steps 136 to 139:

[0082] Step 136, extracting the layout parameters of the transistor, the layout parameters including the position, height, width of the gate cutting area, and the distance between the gates, as well as the candidate position, size, gate crossing width and distance from the gate of the contact via.

[0083] Step 137, based on the process rules of the self-aligned double pattern, detecting whether the height of the gate cutting area is not less than the minimum cutting height specified by the process, whether the distance between the edge of the gate cutting area and the edge of the adjacent gate is not less than the minimum safety distance specified by the process, and whether the gate cutting area is continuous.

[0084] Step 138, based on the process rules of the contact via coverage, detecting whether the gate crossing width of the contact via is not greater than the maximum gate crossing width specified by the process, whether the distance between the edge of the contact via and the edge of the gate is not less than the minimum gate hole distance specified by the process, and whether the size of the contact via is within the process allowed range.

[0085] Step 139, detecting whether the projection of the gate cutting area and the candidate position of the contact via exists overlap, and whether the distance between the edge of the gate cutting area and the edge of the contact via is not less than the minimum cooperative distance specified by the process.

[0086] In step 136, the key physical parameters (i.e. layout parameters) directly related to the feasibility of the gate cutting and contact via cutting process can be extracted from the design scheme of the transistor to be laid out, which are the quantitative basis for subsequent rule detection.

[0087] In this application, on the one hand, the position of the gate cutting region determines whether it conflicts with other structures (such as contact via), the height needs to meet the minimum cutting requirement of the self-aligned double patterning process (to avoid incomplete cutting leading to gate failure), the width affects the effective control range of the gate, and the gate spacing needs to meet the adjacent track safety distance of the self-aligned double patterning process (to prevent adjacent gate short circuit), and the position, height, width and gate spacing of the gate cutting region need to be extracted. On the other hand, the candidate position is the basis for judging whether the contact via conflicts with the gate cutting region, the size needs to meet the minimum via requirement of the contact via covering process (to ensure contact reliability), the cross-gate width needs to meet the maximum cross-gate limit of the contact via covering process (to avoid contact via cross-gate being too wide leading to gate and diffusion region short circuit), and the distance from the gate needs to meet the minimum spacing (to reduce parasitic capacitance). Therefore, for the parameters of the contact via, the candidate position, size, cross-gate width and distance from the gate of the contact via need to be extracted.

[0088] After extracting the parameters to be laid out of the transistor, the feasibility of the gate cutting process and the contact via cutting process can be detected.

[0089] Specifically, in step 137, the core logic is that the constraints of the self-aligned double patterning process on the gate cutting region can be focused on, and the manufacturing feasibility of the gate cutting region is verified through three key dimensions, and the core is to ensure that the gate cutting region can be accurately generated by the self-aligned double patterning process and does not cause abnormal function of the gate.

[0090] Among them, the first key dimension is to detect whether the height of the gate cutting region is not less than the minimum cutting height of the process. In the self-aligned double patterning process, the gate cutting region needs to be formed by mask etching, and if the cutting height is too small, the etching will not be complete, and the residual gate conductor may cause adjacent gate short circuit, so it is necessary to verify whether the height of the gate cutting region reaches the lower limit of the process; the second key dimension is to detect whether the distance between the edge of the gate cutting region and the edge of the adjacent gate is not less than the minimum safety distance of the process. If the distance between the gate cutting regions of adjacent gates is too small, the edge of the gate cutting region and the adjacent gate will overlap due to photolithography deviation, thereby destroying the integrity of the adjacent gate, so it is necessary to verify whether the distance meets the safety requirement; the third key dimension is to detect whether the gate cutting region is continuous. If the gate cutting region is broken (such as cutting is not continuous due to layout deviation), the residual segments of the gate conductor will be caused, which will cause gate signal interference and lead to abnormal function of the transistor switch, so the continuity of the gate cutting region needs to be verified.

[0091] In short, step 137 can ensure that the structure of the gate cutting region meets the physical requirements of gate manufacturing by detecting the core risk points of the self-aligned double patterning process in a targeted manner, and avoid the decline of the yield of the self-aligned double patterning process due to the violation of the gate cutting region.

[0092] In step 138, the core logic is to focus on the constraints of the contact via coverage process on the contact via, and to verify the manufacturability of the contact via through three key dimensions. The core is to ensure that the contact via can safely connect the diffusion region and the metal layer, and does not violate the cross-gate and spacing rules of the contact via coverage process.

[0093] Among them, the first key dimension is to detect whether the contact via cross-gate width is not greater than the process maximum cross-gate width. The contact via coverage process allows the contact via to project on the gate, but if the cross-gate width exceeds the process maximum cross-gate width, it will cause the contact via to contact the gate and the diffusion region at the same time, causing short circuit between the gate and the diffusion region, so it is necessary to verify whether the cross-gate width is within the compliance range; The second key dimension is to detect whether the distance between the edge of the contact via and the edge of the gate is not less than the process minimum gate hole spacing. If the spacing between the contact via and the gate is too small, it will increase the parasitic capacitance between the two, causing the switching speed of the transistor to decrease, and even causing signal integrity problems, so it is necessary to verify whether the spacing meets the requirements; The third key dimension is to detect whether the contact via size is within the process allowed range. If the contact via size is less than the process minimum requirement, it will cause the contact area between the contact via and the diffusion region and the metal layer to be insufficient, the contact resistance will increase, and the circuit performance will be affected; If the size is too large, it will waste layout space, so it is necessary to verify whether the contact via size is within the range of the minimum size and the maximum size.

[0094] In step 138, by detecting the core risk points of the contact via coverage process, it can be ensured that the structure of the contact via meets the physical requirements of the via connection, and the yield of the contact via coverage process is prevented from being reduced due to the violation of the contact via.

[0095] In step 139, the core logic is to focus on the spatial compatibility of the gate cut region and the contact via, that is, even if the gate cut region and the contact via each comply with the self-aligned double patterning process and the contact via coverage process rules, if they overlap or have too small spacing in physical space, it will still cause lithography and etching conflicts (such as the etching pattern of the gate cut region interfering with the pattern of the contact via, causing both to be unable to be accurately generated). Therefore, it is necessary to verify the cooperative compliance through two dimensions.

[0096] The first dimension is to detect whether the projection of the gate cut region and the contact via candidate position overlap. If the gate cut region and the contact via candidate position overlap in the x-axis or y-axis projection, it will cause the same region to form the gate cut region and the contact via pattern during lithography, which exceeds the lithography resolution limit, and causes pattern distortion, so it is necessary to ensure that the projections of the two do not overlap. The second dimension is to detect whether the distance between the edge of the gate cut region and the edge of the contact via is not less than the minimum process cooperative spacing. Even if the two projections do not overlap, if the edge spacing is too small, the pattern of the gate cut region and the contact via will be invaded due to lithography deviation, which will damage the structural integrity of each other, so it is necessary to verify whether the cooperative spacing meets the requirements.

[0097] In step 139, through cross-process cooperation detection, the loopholes of single-process rule detection can be filled, and it is ensured that the gate cut region and the contact via do not conflict in space, and the manufacturing yield loss caused by the superposition of the two is avoided.

[0098] Further, after step 139, the following steps can also be performed: if any detection item fails, the layout parameter is adjusted, and the detection step is returned (i.e., step 137 is returned) until all detection items pass.

[0099] In this application, through the process of "layout parameter extraction, single rule detection, cooperative detection, and re-detection after adjusting the layout parameter", the process compliance of transistor layout can be provided with all-round protection. Compared with the traditional "layout and then detection" process, the following advantages are possessed:

[0100] Firstly, it can avoid process risks and reduce rework in the later stage. It embeds the compliance detection of the gate cut region and the contact via in the layout stage, rather than discovering the problem in the wiring or signing stage. The rework rate caused by the violation of the gate cut region / contact via in the traditional method is high, and this process can significantly reduce the rework rate and greatly shorten the design cycle. Secondly, it can guarantee the process feasibility and yield. It covers the single-process rules of self-aligned double patterning process and contact via covering process and the cooperative rules of the two, to ensure that the gate cut region and the contact via meet the manufacturing requirements of advanced processes, so that the etching yield of the gate cut region, the contact yield of the contact via, and the overall manufacturing yield of the chip are significantly improved. Finally, it can reduce the detection complexity and improve the efficiency. Through the logic of the detection process proposed in this application, redundant detection of irrelevant parameters can be avoided, and scattered process rules can be converted into quantitative judgments of whether the parameters meet the requirements, so as to improve the detection efficiency and adapt to the rapid layout needs of large-scale standard cells.

[0101] Continuing to refer to Figure 1In step 140, after the layout of the transistors in the standard cell to be designed is completed, the standard cell to be designed is routed by using a multi-network synchronous optimization strategy to generate a standard cell physical layout, wherein, in the routing process, the signature data is integrated to optimize the routing.

[0102] In the present application, the routing of the standard cell to be designed by using the multi-network synchronous optimization strategy can be performed according to steps 141 to 143 as follows:

[0103] Step 141, the power network, the ground network and the signal network are integrated into a unified optimization space to construct a three-dimensional variable pitch routing grid.

[0104] Step 142, the routing resources of each network are allocated based on a flow conservation model, and in the process of allocating the routing resources of each network, the signal transmission characteristics and mutual interference constraints of different networks are considered.

[0105] Step 143, a parallel optimization algorithm is used to cooperatively search the routing paths of multiple networks to avoid global routing conflicts caused by single network optimization.

[0106] In the traditional scheme, the power network is planned first, then the ground network is planned, and finally the signal network is planned, which has the defect that the network that occupies resources first is optimal, and the network planned later has no available path. In step 141, by integrating the three types of networks into the same optimization space and constructing a three-dimensional variable pitch routing grid suitable for advanced processes, spatial planning conflicts can be avoided from the source.

[0107] Specifically, the construction of the three-dimensional variable pitch routing grid can be performed according to steps 1411 to 1413 as follows:

[0108] Step 1411, for the routing direction and minimum line width requirements of different metal layers, set different grid pitches, wherein the grid pitches of the horizontal metal layer and the vertical metal layer are in a complementary relationship.

[0109] Step 1412, the grid pitch is reduced in the signal dense area, and the grid pitch is expanded in the power network area to form a three-dimensional grid structure with adaptive density.

[0110] Step 1413, the compatible information of the contact via at the grid node of the three-dimensional grid structure is labeled to guide the connection path selection between different metal layers.

[0111] In this application, first, the differential grid spacing can be set according to the wiring direction (horizontal or vertical) of different metal layers and the minimum line width requirement. That is, the horizontal metal layer needs to match the line width and spacing rules of the horizontal wiring, and the vertical metal layer needs to adapt to the vertical wiring requirements, and the spacing of the two is complementary to each other, ensuring that the interlayer contact via can accurately align the grid nodes of different metal layers, avoiding connection failure due to mismatched spacing; then, the grid density can be dynamically adjusted according to the functional requirements of the wiring area. That is, the signal-intensive area (such as the vicinity of multiple input and output pins) needs to reduce the grid spacing to improve the wiring density and shorten the signal path, and the power network area needs to expand the grid spacing to accommodate wider metal lines to meet the current density requirements, forming a three-dimensional grid structure that adapts to the needs of different areas. Finally, the compatible information of the contact via (such as the via size supported by the node, the type of metal layer that can be connected, and the minimum spacing requirement from adjacent vias) can be marked at the nodes of the three-dimensional grid, providing clear guidance for subsequent multi-network cross-layer wiring and avoiding wiring rework due to via compatibility problems.

[0112] Overall, the three-dimensional variable spacing wiring grid constructed through the above steps 1411 to 1413 can not only solve the problem of resource waste or insufficient density of traditional fixed spacing grid, but also ensure the reliability of interlayer connection through complementary spacing and via labeling, which can greatly improve the utilization of wiring resources and cross-layer wiring efficiency, while adapting to the differentiated needs of signal networks and power networks, laying an efficient and compatible structural foundation for multi-network synchronous optimization of wiring.

[0113] Further, in the above step 142, the flow conservation model can be used to accurately match the wiring resources (such as metal layer tracks and via positions) with the actual needs of each network, while considering network characteristics and interference constraints to avoid resource waste or deficiency.

[0114] Specifically, the core of the flow conservation model is to match the resource demand and allocation of the network. For example, the power network needs to transmit a large current, so it needs to allocate low-resistance high-layer metal layers (such as metal layer two and metal layer three) tracks, and the track width needs to meet the current density requirement (such as avoiding high current density leading to metal electromigration); the ground network needs to balance the current with the power network, and the number and position of the allocated tracks need to be symmetrical with the power network to ensure smooth current loop; the flow of the signal network is represented by the signal transmission demand (such as the delay requirement of the clock signal), and low parasitic capacitance metal layer tracks need to be allocated.

[0115] In the present application, the signal transmission characteristics of different networks are considered in the process of allocating wiring resources of each network, because the performance requirements of different signal networks are significantly different. For example, clock signals are sensitive to timing delay and need to be allocated to high-level metal layers with smaller delay; high-speed data signals require high signal integrity and need to be allocated to tracks far from noise sources; and ordinary input signals have lower performance requirements and can be adapted to the remaining conventional resources. Differentiated allocation ensures that key network performance meets the standards.

[0116] At the same time, the mutual interference constraints of different networks also need to be considered, because electromagnetic interference between networks (such as the influence of power supply noise on sensitive signals) is significant in advanced processes. For example, the current fluctuation of the power supply network will generate noise, which needs to maintain a safe distance from clock, high-speed data and other sensitive signal networks; the ground network needs to be a "noise shield layer" and be reasonably allocated between the power supply and sensitive signals to reduce interference transmission. By constraint, each network is ensured to be efficiently routed without mutual performance impact.

[0117] Further, in the above step 143, a parallel optimization algorithm can be used to search for the routing paths of multiple networks simultaneously, and global routing without conflict and optimal performance can be achieved through collaborative adjustment. Specifically, the parallel optimization algorithm can simultaneously search for paths of the three types of networks. For example, when searching for power supply network tracks, the symmetrical requirements of the ground network and the critical path of the signal network are considered simultaneously. If allocating a track to the power supply network leads to no available path for the signal network, the path of the power supply network is adjusted in real time, and the collaborative adaptation of multiple network paths can be achieved. This avoids the traditional method of first optimizing the power supply network (such as occupying the core track of the high-level metal layer), then optimizing the ground network (which may need to bypass the power supply track, leading to an excessively long path), and finally optimizing the signal network (with fewer remaining tracks, which is prone to path overlap), resulting in high global conflict rate;

[0118] In the present application, it should be noted that collaborative search does not pursue the shortest path of a single network, but the optimal performance and conflict-free of all networks as a whole. For example, if a high-level metal track is allocated to an ordinary signal network, although it can shorten the signal path, it will cause the power supply network to bypass a much longer track (increasing the voltage drop). At this time, the algorithm will preferentially allocate the track to the power supply network, and adjust the signal network to a sub-optimal but conflict-free track, ensuring that global indicators such as voltage drop and delay meet the standards, avoiding local optimization leading to global failure.

[0119] In the present application, based on the technical solutions in steps 141-143, one can greatly reduce the wiring conflict rate. That is, the unified optimization space can avoid spatial fragmentation between networks, and parallel collaborative search can eliminate the problem of single network resource occupation, thereby eliminating the need for repeated disconnection and redistribution in the later stage, shortening the wiring period; secondly, it can guarantee the performance of each network to meet the standard. The flow conservation model ensures that resources and demand are matched, and the consideration of signal transmission characteristics and interference constraints allows the performance of key networks (such as power supply and clock) to be prioritized, thereby reducing power network voltage drop, reducing clock signal delay, reducing noise interference of sensitive signals, and improving the overall electrical performance of standard cells; thirdly, it can improve the wiring efficiency and adaptability. Three-dimensional variable spacing grid can adapt to the physical needs of different networks, and parallel algorithms can reduce repeated calculations, thereby improving overall wiring efficiency, and being compatible with FinFET, fully wrapped gate transistors and other advanced process metal layer structures, and adapting to the wiring needs of large-scale standard cell libraries.

[0120] In the present application, the integration of signature data to optimize wiring can be performed according to the following steps 144-146:

[0121] Step 144, converting timing delay, current density, voltage drop and signal integrity parameters in the signature data into wiring weight factors.

[0122] Step 145, prioritizing the wiring tracks of different metal layers based on the wiring weight factors, wherein the weight factors of high-level metal tracks are dynamically adjusted according to their delay characteristics.

[0123] Step 146, preferentially selecting track paths with optimal weight factors during the wiring process to achieve pre-matching of the wiring results with the signature requirements.

[0124] In the present application, the signature data can at least include timing delay, current density (reflecting the ability of metal lines to carry current, which can avoid electromigration failure), voltage drop and signal integrity parameters.

[0125] Further, in steps 144-146, the core is to convert abstract signature data into concrete wiring decision basis, achieving early adaptation of wiring results to signature standards, and avoiding the problem of traditional wiring only meeting physical rules and later signature failure.

[0126] In step 144, key performance indicators (such as timing delay, current density, voltage drop, signal integrity parameters) in the sign-off data can be converted into quantifiable calculation wiring weight factors, and specific sign-off requirements such as “timing delay needs to be ≤ 50 picoseconds, current density needs to be ≤ 4 milliampere / micron” are converted into numerical weight values that can guide track selection, so that abstract quality standards become specific targets that can be compared and prioritized during wiring.

[0127] In the present application, by quantifying sign-off requirements, prioritizing tracks, and selecting optimal paths, the sign-off constraints are deeply integrated into the entire wiring process. This not only improves the sign-off pass rate and significantly shortens the design cycle due to rework, but also ensures that key networks (such as clock signals and high-speed data signals) meet the sign-off requirements precisely, further optimizing the performance, power consumption, and reliability of standard cells.

[0128] Further, in the present application, after generating the standard cell physical layout, the following steps 150 to 160 can be performed:

[0129] Step 150, verifying the process rules of the standard cell physical layout.

[0130] Step 160, after the standard cell physical layout is verified, the standard cell physical layout that meets the target requirements is saved in the standard cell library.

[0131] Specifically, in step 150, the process rule verification of the standard cell physical layout can be performed according to the following steps 151 to 152:

[0132] Step 151, calling a process rule checking engine to verify whether the transistor layout in the standard cell physical layout meets the multi-patterning process constraint parameters, and to verify whether the transistor wiring in the standard cell physical layout meets the physical rules including metal line width, spacing, via size, and sign-off indicators including timing and power consumption.

[0133] Step 152, if there are violations, then according to the type of violation, the transistor layout parameters or wiring path of the standard cell to be designed are adjusted reversely until all verification items pass.

[0134] In this application, the core logic of step 151 is to call the process rule checking engine, which can carry out comprehensive verification from two aspects. One is to verify whether the transistor layout in the layout meets the multi-patterning process constraint parameters, to ensure that the layout adapts to the manufacturing capability of advanced process, and the other is to verify whether the transistor wiring meets the physical rules (including metal line width, line spacing, via size, etc.) and the signed index (including timing, power consumption, etc.), to avoid physical conflict or performance substandard problem in wiring. In step 152, the core logic is to adjust the transistor layout parameters (such as fin number, sub-cell arrangement) or wiring path (such as metal layer selection, track optimization) of the standard cell to be designed reversely according to the violation type (such as layout violating multi-patterning cutting rule, wiring line width not meeting process requirement, timing delay exceeding rule, etc.), until all verification items pass, to form a completely compliant standard cell physical layout.

[0135] Further, after the standard cell physical layout passes all verifications, the layout that meets the target requirements (such as performance, area, process compatibility, etc.) can be saved in the standard cell library, to provide reliable and reusable resources for subsequent unit calling in chip overall design. In this way, through the closed loop process of comprehensive verification, violation correction and compliance storage, the potential risks of layout in process manufacturing and performance can be excluded in advance, to minimize the probability of chip production failure in later stage, and the efficient reuse of layout resources can be realized through the storage of standard cell library, to significantly improve the efficiency and reliability of subsequent large-scale chip design.

[0136] Based on the technical scheme provided in the present application, by obtaining the design data and multi-patterning process constraint parameters in advance, clear basis is provided for subsequent processes, repeated trial and error caused by missing parameters is avoided, and invalid operations are reduced from the source. In the transistor layout stage, by dynamically performing transistor folding and source-drain sharing, the area utilization can be optimized under the premise of meeting the functional requirements, and layout redundancy is reduced. Simultaneously detecting the feasibility of gate cutting and contact via cutting, embedding process compliance verification into the transistor layout process can discover and solve potential violation problems in advance, avoid the need for large-scale adjustment due to process conflicts after layout is completed, and save rework time. In the wiring stage, by using a multi-network synchronous optimization strategy, the traditional single-network step-by-step wiring fragmentation mode can be broken, the power, ground and signal networks can be unified planned, and the disconnection and redistribution caused by network conflicts can be reduced. By integrating the sign-off data to optimize the wiring, the wiring result can be adapted to timing, power consumption and other sign-off requirements in advance, and the probability of failing the verification in the later stage can be reduced. In this way, through data input, layout optimization, wiring adaptation, and process compliance closed loop, each link is closely connected, the cross-stage adjustment cost can be reduced, the period from design to generation of compliant standard cell layout can be greatly shortened, and the generation efficiency of the standard cell physical layout is improved to a certain extent.

[0137] The device embodiment of the present application is introduced below, which can be used to execute the generation method of the standard cell physical layout in the above-mentioned embodiments of the present application. For details not disclosed in the device embodiment of the present application, please refer to the above-mentioned embodiments of the generation method of the standard cell physical layout.

[0138] Referring to Figure 3 , a block diagram of the standard cell physical layout generation device in the embodiment of the present application is shown.

[0139] As shown in Figure 3 , the standard cell physical layout generation device 300 according to the embodiment of the present application comprises a first obtaining unit 301, a second obtaining unit 302, a layout unit 303 and a wiring unit 304.

[0140] The first obtaining unit 301 is configured to obtain design data of a standard cell to be designed, the design data being used to define transistor connection relationship of the standard cell to be designed, and size requirement and performance requirement of the standard cell to be designed, and the transistor connection relationship being used to define function requirement of the standard cell to be designed; the second obtaining unit 302 is configured to obtain multi-patterning process constraint parameters under a target process, the multi-patterning process constraint parameters being used to define process rules of a self-aligned double pattern, process rules of a self-aligned quadruple pattern, and process rules of contact via coverage; the layout unit 303 is configured to perform layout on transistors in the standard cell to be designed according to the design data and the multi-patterning process constraint parameters, wherein, in the layout process, the transistors in the standard cell to be designed are dynamically folded and / or source-drain shared, and the feasibility of gate cutting process and contact via cutting process is synchronously detected; and the routing unit 304 is configured to perform routing on the standard cell to be designed by using a multi-network synchronous optimization strategy after the layout on the transistors in the standard cell to be designed is completed, to generate a standard cell physical layout, wherein, in the routing process, review data is integrated to optimize the routing.

[0141] In some embodiments of the present application, based on the foregoing scheme, the second obtaining unit 302 is configured to integrate the gate cutting rule of the self-aligned double pattern, the fin splitting rule of the self-aligned quadruple pattern, and the constraint rule of contact via position into a standardized parameter set based on a pre-established unified process model; obtain process data of a target wafer factory, and assign values to the standardized parameter set based on the process data, to obtain the multi-patterning process constraint parameters.

[0142] In some embodiments of the present application, based on the foregoing scheme, the layout unit 303 is configured to dynamically split a target transistor in the standard cell to be designed into a plurality of equivalent sub-units in a gate extension direction according to the design data and the multi-patterning process constraint parameters, and overlap the plurality of equivalent sub-units in the gate extension direction thereof, to realize dynamic folding of the target transistor, wherein the fin number of the equivalent sub-unit is a divisor of the fin number of the target transistor, and the gate number of the equivalent sub-unit is the same as the gate number of the target transistor; and perform polarity interchanging on the source and the drain of the equivalent sub-unit according to routing requirement, to realize source-drain sharing of the target transistor.

[0143] In some embodiments of the present application, based on the foregoing scheme, the layout unit 303 is configured to: according to the design data and the multi-patterning process constraint parameters, dynamically split a target transistor in the standard cell to be designed into a plurality of equivalent sub-cells in the fin extension direction, and overlap the plurality of equivalent sub-cells in the fin extension direction to achieve dynamic folding of the target transistor, wherein the number of fins of the equivalent sub-cell is the same as the number of fins of the target transistor, and the number of gates of the equivalent sub-cell is a divisor of the number of gates of the target transistor; and according to the wiring requirement, perform polarity exchange on the source and drain of the equivalent sub-cell.

[0144] In some embodiments of the present application, based on the foregoing scheme, the layout unit 303 is configured to: during the layout process, determine a candidate position of a contact via according to the fin distribution characteristics, the candidate position maintaining a preset alignment relationship with the fin position; perform screening on the candidate position based on the maximum gate-crossing width and minimum gate spacing requirements in the process rule of the contact via coverage; and retain the candidate positions satisfying the process rule of the contact via coverage to form a candidate position set of the contact via.

[0145] In some embodiments of the present application, based on the foregoing scheme, the layout unit 303 is configured to: extract a parameter to be laid out of a transistor, the parameter to be laid out including the position, height, width of a gate cut region, and gate spacing, and the candidate position, size, gate-crossing width, and distance from the gate of a contact via; detect whether the height of the gate cut region is not less than the minimum cut height specified by the process, the distance between the edge of the gate cut region and the edge of the adjacent gate is not less than the minimum safety distance specified by the process, and the gate cut region is continuous based on the process rule of the self-aligned double pattern; detect whether the gate-crossing width of the contact via is not greater than the maximum gate-crossing width specified by the process, the distance between the edge of the contact via and the edge of the gate is not less than the minimum gate-hole spacing specified by the process, and the size of the contact via is within the process allowable range based on the process rule of the contact via coverage; detect whether the projection of the candidate position of the contact via exists overlap with the gate cut region, and the distance between the edge of the gate cut region and the edge of the contact via is not less than the minimum cooperative spacing specified by the process; and if any of the detection items fails, adjust the parameter to be laid out, and return to perform the detection step until all detection items pass.

[0146] In some embodiments of the present application, based on the foregoing scheme, the wiring unit 304 is configured to: integrate the power supply network, the ground network and the signal network into a unified optimization space, and construct a three-dimensional variable pitch wiring grid; allocate wiring resources of each network based on a flow conservation model, and in the process of allocating the wiring resources of each network, consider the signal transmission characteristics and mutual interference constraints of different networks; and use a parallel optimization algorithm to cooperatively search for wiring paths of multiple networks, so as to avoid global wiring conflicts caused by single network optimization.

[0147] In some embodiments of the present application, based on the foregoing scheme, the wiring unit 304 is configured to: set differentiated grid pitches for wiring directions and minimum line width requirements of different metal layers, wherein the grid pitches of the transverse metal layer and the longitudinal metal layer are in a complementary relationship; reduce the grid pitch in a signal dense area and expand the grid pitch in a power supply network area, so as to form a three-dimensional grid structure with adaptive density; and label compatibility information of contact vias at grid nodes of the three-dimensional grid structure, so as to guide connection path selection between different metal layers.

[0148] In some embodiments of the present application, based on the foregoing scheme, the wiring unit 304 is configured to: convert timing delay, current density, voltage drop and signal integrity parameters in the signature data into wiring weight factors; prioritize wiring tracks of different metal layers based on the wiring weight factors, wherein the weight factor of a high-level metal track is dynamically adjusted according to its delay characteristics; and preferentially select a track path with the optimal weight factor in the wiring process, so as to realize pre-matching of the wiring result and the signature requirement.

[0149] In some embodiments of the present application, based on the foregoing scheme, the device further includes a verification unit configured to: after generating the standard cell physical layout, perform process rule verification on the standard cell physical layout; and after the standard cell physical layout passes the verification, save the standard cell physical layout that meets the target requirement in a standard cell library.

[0150] In some embodiments of the present application, based on the foregoing scheme, the verification unit is configured to: call a process rule checking engine to verify whether a transistor layout in the standard cell physical layout meets the multi-patterning process constraint parameters, and whether a transistor wiring in the standard cell physical layout meets physical rules including metal line width, pitch and via size, and signature indexes including timing and power consumption; and if there is a violation, reversely adjust the transistor layout parameters or wiring path of the standard cell to be designed according to the type of the violation until all verification items pass.

[0151] Based on the same inventive concept, the embodiment of the present application provides a computer program product, which comprises computer instructions stored in a computer readable storage medium and adapted to be read and executed by a processor to enable a computer device having the processor to perform the operations performed by the method for generating a standard cell physical layout as described above.

[0152] Based on the same inventive concept, the embodiment of the present application provides a computer readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to enable the processor to perform the operations performed by the method for generating a standard cell physical layout as described above.

[0153] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which refers to Figure 4 , a structural schematic diagram of the electronic device in the embodiment of the present application is shown, the electronic device comprises one or more memories 404, one or more processors 402, and at least one computer program (computer program instructions) stored in the memory 404 and executable on the processor 402, and the processor 402 implements the method for generating a standard cell physical layout as described above when executing the computer program.

[0154] In the above method for generating a standard cell physical layout, Figure 4 , a bus architecture (represented by a bus 400), the bus 400 can comprise any number of interconnected buses and bridges, and the bus 400 links various circuits together, including one or more processors represented by the processor 402 and the memory represented by the memory 404. The bus 400 can also link various other circuits such as peripheral devices, voltage stabilizers and power management circuits, which are well known in the art, and thus, they will not be further described herein. The bus interface 405 provides an interface between the bus 400 and the receiver 401 and the transmitter 403. The receiver 401 and the transmitter 403 can be the same element, i.e., a transceiver, which provides a unit for communicating with various other devices on a transmission medium. The processor 402 is responsible for managing the bus 400 and general processing, while the memory 404 can be used to store data used by the processor 402 in performing operations.

[0155] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items prefaced by "comprising" to indicate a disjunctive list means each single item in the list has been recited before "or" one or more items also can be recited before "or." Further, as used herein, "each of two or more items" or "at least one of two or more items" means each single item in the list of items can be recited before "each of" or "at least one of." Further, as used herein, "wherein" means "wherein each of the two or more items recited before "wherein" can be recited individually or in any combination of one or more items. Further, as used herein, including in the claims "program" means one or more computer programs, software, or applications.

[0156] In several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and other division manners can be used in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or modules shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, and can be electrical or other forms.

[0157] The units described as separate components can or can not be physically separated, and the components of the control device can or can not be physical units, i.e. can be located in one place or can be distributed on multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0158] The integrated units, if implemented in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, and various computer program instruction storage media.

[0159] The above merely provides an example of the present application, and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall fall into the scope of claims of the present application.

Claims

1. A method for generating a standard cell physical layout, characterized in that, The method includes: Obtain the design data of the standard unit to be designed. The design data is used to define the transistor connection relationship of the standard unit to be designed, as well as the size and performance requirements of the standard unit to be designed. The transistor connection relationship is used to limit the functional requirements of the standard unit to be designed. Obtain the multi-patterning process constraint parameters under the target process. The multi-patterning process constraint parameters are used to define the process rules for self-aligned double patterns, the process rules for self-aligned quadruple patterns, and the process rules for contact via coverage. Based on the design data and the multi-patterning process constraint parameters, the transistors in the standard cell to be designed are laid out. During the layout process, the transistors in the standard cell to be designed are dynamically folded and / or source-drain shared, and the feasibility of gate cutting process and contact via cutting process is detected simultaneously. After the transistors in the standard cell to be designed are placed, a multi-network synchronous optimization strategy is used to route the standard cell to generate a physical layout of the standard cell. During the routing process, signature data is incorporated to optimize the routing. The simultaneous detection of the feasibility of the gate dicing process and the contact via dicing process includes: extracting the layout parameters of the transistor, including the position, height, width, and gate pitch of the gate dicing region, as well as the candidate position, size, gate width, and distance from the gate of the contact via; detecting whether the height of the gate dicing region is not less than the minimum dicing height specified by the process, whether the distance between the edge of the gate dicing region and the edge of the adjacent gate is not less than the minimum safety distance specified by the process, and whether the gate dicing region is continuous; based on the process rules for contact via coverage, detecting whether the gate width of the contact via is not greater than the maximum gate width specified by the process, whether the distance between the edge of the contact via and the edge of the gate is not less than the minimum gate via pitch specified by the process, and whether the size of the contact via is within the allowable range of the process; detecting whether the projections of the gate dicing region and the candidate positions of the contact via overlap, and whether the distance between the edge of the gate dicing region and the edge of the contact via is not less than the minimum cooperative spacing specified by the process; if any detection item fails, the layout parameters are adjusted, and the detection steps are returned until all detection items pass.

2. The method of claim 1, wherein, The acquisition of multi-patterning process constraint parameters under the target process includes: Based on a pre-established unified process model, the gate cutting rules of the self-aligned double pattern, the fin segmentation rules of the self-aligned quadruple pattern, and the constraint rules of the contact via position are integrated into a standardized parameter set. The process data of the target wafer fab is obtained, and the standardized parameter set is assigned values ​​based on the process data to obtain the multi-patterned process constraint parameters.

3. The method of claim 1, wherein, Dynamically folding and sharing source and drain parameters for transistors in the standard cell to be designed includes: Based on the design data and the multi-patterning process constraint parameters, the target transistor in the standard cell to be designed is dynamically divided into multiple equivalent sub-units in the gate extension direction, and the multiple equivalent sub-units are overlapped in their gate extension direction to achieve dynamic folding of the target transistor. The number of fins in the equivalent sub-unit is an approximation of the number of fins in the target transistor, and the number of gates in the equivalent sub-unit is the same as the number of gates in the target transistor. According to the wiring requirements, the source and drain of the equivalent sub-unit are interchanged to achieve source-drain sharing of the target transistor.

4. The method of claim 1, wherein, Dynamically folding the transistors in the standard cell to be designed includes: Based on the design data and the multi-patterning process constraint parameters, the target transistor in the standard cell to be designed is dynamically divided into multiple equivalent sub-units in the fin extension direction, and the multiple equivalent sub-units are overlapped in their fin extension direction to achieve dynamic folding of the target transistor. The number of fins in the equivalent sub-units is the same as the number of fins in the target transistor, and the number of gates in the equivalent sub-units is an approximation of the number of gates in the target transistor. According to the wiring requirements, the source and drain of the equivalent sub-unit are interchanged.

5. The method of claim 1, wherein, During the layout process, the method further includes: Candidate positions for contact holes are determined based on the fin distribution characteristics, and the candidate positions maintain a preset alignment relationship with the fin positions; The candidate locations are screened based on the maximum gate width and minimum gate pitch requirements in the process rules for contact via coverage; Candidate positions that satisfy the process rules for contact via coverage are retained to form the candidate position set of the contact via.

6. The method of claim 1, wherein, The method of using a multi-network synchronous optimization strategy to route the standard unit to be designed includes: By incorporating power networks, grounding networks, and signal networks into a unified optimization space, a three-dimensional variable-pitch wiring mesh is constructed. The cabling resources of each network are allocated based on the flow conservation model. In the process of allocating the cabling resources of each network, the signal transmission characteristics of different networks and mutual interference constraints are considered. Parallel optimization algorithms are used to collaboratively search for cabling paths in multiple networks to avoid global cabling conflicts caused by optimizing a single network.

7. The method of claim 6, wherein, The construction of the three-dimensional variable-spacing wiring mesh includes: Different grid spacings are set for different wiring directions and minimum line width requirements of different metal layers, with the grid spacings of the horizontal and vertical metal layers being complementary. In signal-dense regions, the grid spacing is reduced, while in power network regions, the grid spacing is increased to form an adaptive density three-dimensional grid structure. The compatibility information of the contact vias is marked at the grid nodes of the three-dimensional mesh structure to guide the selection of connection paths between different metal layers.

8. The method of claim 1, wherein, The integration of approval data to optimize cabling includes: Convert timing delay, current density, voltage drop, and signal integrity parameters in the approval data into routing weighting factors; The routing tracks of different metal layers are prioritized based on the routing weight factor, wherein the weight factor of the high-layer metal track is dynamically adjusted according to its delay characteristics. During the cabling process, the track path with the optimal weight factor is selected first to achieve a pre-match between the cabling results and the approval requirements.

9. The method of claim 1, wherein, After generating the standard cell physical layout, the method further includes: The process rules of the physical layout of the standard unit are verified. After the standard cell physical layout is verified, the standard cell physical layout that meets the target requirements is saved in the standard cell library.

10. The method according to claim 9, characterized in that, The process rule verification of the standard cell physical layout includes: The process rule inspection engine is invoked to verify whether the transistor layout in the standard cell physical layout meets the multi-patterning process constraint parameters, and to verify whether the transistor wiring in the standard cell physical layout conforms to physical rules including metal line width, spacing, and via size, as well as approval indicators including timing and power consumption. If a violation is found, the transistor layout parameters or wiring path of the standard cell to be designed are adjusted in reverse according to the type of violation until all verification items pass.

11. A device for generating a standard unit physical layout, characterized in that, The device includes: The first acquisition unit is used to acquire the design data of the standard unit to be designed. The design data is used to define the transistor connection relationship of the standard unit to be designed, as well as the size requirements and performance requirements of the standard unit to be designed. The transistor connection relationship is used to limit the functional requirements of the standard unit to be designed. The second acquisition unit is used to acquire the multi-patterning process constraint parameters under the target process. The multi-patterning process constraint parameters are used to define the process rules for self-aligned double patterns, the process rules for self-aligned quadruple patterns, and the process rules for contact via coverage. The layout unit is used to lay out the transistors in the standard cell to be designed according to the design data and the multi-patterning process constraint parameters. During the layout process, the transistors in the standard cell to be designed are dynamically folded and / or source-drain shared, and the feasibility of gate cutting process and contact via cutting process is detected simultaneously. The routing unit is used to route the standard cell to be designed after the transistors in the standard cell to be designed are laid out, using a multi-network synchronous optimization strategy to generate a physical layout of the standard cell. During the routing process, signature data is incorporated to optimize the routing. The simultaneous detection of the feasibility of the gate dicing process and the contact via dicing process includes: extracting the layout parameters of the transistor, including the position, height, width, and gate pitch of the gate dicing region, as well as the candidate position, size, gate width, and distance from the gate of the contact via; detecting whether the height of the gate dicing region is not less than the minimum dicing height specified by the process, whether the distance between the edge of the gate dicing region and the edge of the adjacent gate is not less than the minimum safety distance specified by the process, and whether the gate dicing region is continuous; based on the process rules for contact via coverage, detecting whether the gate width of the contact via is not greater than the maximum gate width specified by the process, whether the distance between the edge of the contact via and the edge of the gate is not less than the minimum gate via pitch specified by the process, and whether the size of the contact via is within the allowable range of the process; detecting whether the projections of the gate dicing region and the candidate positions of the contact via overlap, and whether the distance between the edge of the gate dicing region and the edge of the contact via is not less than the minimum cooperative spacing specified by the process; if any detection item fails, the layout parameters are adjusted, and the detection steps are returned until all detection items pass.

12. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the method as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to perform the operations performed by the method as described in any one of claims 1 to 10.

14. An electronic device, characterized in that, The electronic device includes one or more processors and one or more memories, wherein at least one piece of program code is stored in the one or more memories, and the at least one piece of program code is loaded and executed by the one or more processors to implement the method as described in any one of claims 1 to 10.

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