Control method and device of neural network processing unit, and electronic equipment

Abstract

The invention provides a control method and device of a neural network processing unit and electronic equipment, and relates to the technical field of machine learning. The method is applied to a multi-core neural network processing unit with the same topological structure. The method comprises the following steps: dividing the topological structure of each processing core in the neural network processing unit into a plurality of same stages; each stage comprises at least one branch, and each branch comprises at least one node; determining an execution sequence of each branch included in each stage of each processing core; and executing each branch included in each stage of each processing core according to the execution sequence. According to the method and the device, the technical problems that a factor of sharing weight data among task nodes is not considered in the execution process of multiple cores of the multi-core NPU, and the task nodes are not executed according to a similar execution sequence, so that the weight data are repeatedly loaded in the execution process, more bandwidth is occupied, and the performance of a processor is influenced are solved.

Description

Technical Field

[0001] This disclosure relates to the field of machine learning technology, and more specifically, to a control method and apparatus for a neural network processing unit, and an electronic device. Background Technology

[0002] During the execution of a multi-core neural network processing unit (NPU), if the NPU has a weight cache, the weight data will be stored in the cache. When multiple cores read the same weight data at the same time, they only need to read it from the cache space, which saves bandwidth and improves performance.

[0003] Figure 1 This is a schematic diagram of the structure of a multi-core NPU provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, nodes A0 and A1 share the same weight data, as do B0 and B1. Ideally, if core0 executes A0->A1, core1 should execute B0->B1. However, in actual execution, core1 might execute A1->B1. Since A1 and B1 do not share weight data, core1 repeatedly loads A1 during execution, consuming more bandwidth and impacting processor performance. Summary of the Invention

[0004] This disclosure provides a control method, apparatus, and electronic device for a neural network processing unit, which addresses the technical problem that multiple cores in a multi-core NPU do not consider the shared weight data between task nodes during execution, and do not execute task nodes in a similar execution order, resulting in repeated loading of weight data during execution, occupying more bandwidth, and affecting processor performance.

[0005] According to one aspect of the present disclosure, a control method for a neural network processing unit is provided. The method is applied to a multi-core neural network processing unit with the same topology, comprising: dividing the topology of each processing core in the neural network processing unit into multiple identical stages; each stage includes at least one branch, and each branch includes at least one node; determining the execution order of each branch included in each stage of each processing core; and executing each branch included in each stage of each processing core according to the execution order.

[0006] Optionally, determining the execution order of each branch included in each stage of each processing core includes: determining the weight cache data of each branch included in each stage of each processing core; and determining the execution order of each branch included in each stage of each processing core based on the weight cache data.

[0007] Optionally, the execution order of each branch in each stage of each processing core is determined based on the weight cache data, including: determining the identifier of each processing core; when executing the branch included in the processing core with the larger identifier, first executing the branch with the same weight cache data as the processing core with the smaller identifier, and then executing the branch with different weight cache data as the processing core with the smaller identifier; the execution time of branches with the same weight cache data is the same.

[0008] Optionally, the above method further includes: if the nodes included in the first branch share weights with the nodes included in the second branch, determining that the weight cache data of the first branch and the second branch are the same; the first branch and the second branch are any branches in two different neural network processing units.

[0009] Optionally, the topology type includes at least one of the following: pyramid structure, inverted pyramid structure, and multi-branch structure; the nodes of the multi-core neural network processing unit of the pyramid structure type diffuse from top to bottom; the nodes of the multi-core neural network processing unit of the inverted pyramid structure type converge from top to bottom; and the nodes of the multi-branch structure type multi-core neural network processing unit are arranged in branches.

[0010] Optionally, the topology of each processing core in the neural network processing unit is divided into multiple identical stages, including: dividing the topology of each processing core into multiple identical stages based on the characteristics of the topology of each processing core.

[0011] According to another aspect of the present disclosure, a control device for a neural network processing unit is provided. The device includes: a partitioning module for partitioning the topology of each processing core in the neural network processing unit into multiple identical stages; each stage includes at least one branch, and each branch includes at least one node; a determination module for determining the execution order of each branch included in each stage of each processing core; and a processing module for executing each branch included in each stage of each processing core according to the execution order.

[0012] According to another aspect of the present disclosure, an electronic device is provided, comprising: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the above-described method.

[0013] According to another aspect of the present disclosure, a computer-readable storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the above-described method.

[0014] According to another aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method.

[0015] The beneficial effects of the technical solution provided in this disclosure are: by reordering the branch structure of the NPU, it is ensured that task nodes that read the same weight cache are executed simultaneously in each core of the NPU, thereby achieving the technical effects of improving cache hit rate, saving bandwidth, and improving processor performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments of this disclosure will be briefly introduced below.

[0017] Figure 1 This is a schematic diagram of the structure of a multi-core NPU provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of a multi-core NPU execution process according to an embodiment of the present disclosure; Figure 3 This is a flowchart of a control method for a neural network processing unit according to an embodiment of the present disclosure; Figure 4a This is a schematic diagram of a pyramid-structured multi-core NPU provided in an embodiment of this disclosure; Figure 4b It is Figure 4a A schematic diagram illustrating the phase division of a pyramid-type topological structure; Figure 4c It is Figure 4a A schematic diagram illustrating the phase division of a pyramid-type topological structure; Figure 4d It is Figure 4a A schematic diagram illustrating the phase division of a pyramid-type topological structure; Figure 5 This is a schematic diagram of a multi-branch structure multi-core NPU provided in an embodiment of this disclosure; Figure 6a This is a schematic diagram of the structure of a multi-core NPU with an inverted pyramid structure provided in an embodiment of this disclosure; Figure 6b It is Figure 6a A schematic diagram illustrating the phase division of an inverted pyramid-type topology; Figure 7 This is a schematic diagram of the structure of a control device for a neural network processing unit provided in an embodiment of the present disclosure; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0018] The embodiments of this disclosure are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this disclosure, and do not constitute a limitation on the technical solutions of the embodiments of this disclosure.

[0019] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this disclosure mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element are connected through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term, for example, “A and / or B” or “A, B” indicates implementation as “A,” or implementation as “B,” or implementation as “A and B.”

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] First, the technical terms used in this disclosure will be introduced and explained: A multi-core NPU is a processor specifically designed to accelerate artificial intelligence and machine learning tasks. Its "multi-core" design means that multiple independent processing cores are integrated on a single chip, and each core can perform neural network computing tasks in parallel.

[0022] Weight caching is a mechanism designed to accelerate neural network computation, particularly during the inference and training processes of deep learning models, by improving processing speed and efficiency. In neural networks, weights refer to the parameters connecting neurons in different layers.

[0023] In the context of multi-core NPUs, branch reordering refers to reordering or scheduling optimization of the execution path in a neural network that contains control flow branches (such as conditional statements, loops, dynamic routing, etc.) to improve hardware resource utilization, reduce latency, and increase cache hits.

[0024] A cache hit occurs when a processor or other component attempts to access a piece of data that happens to be in the cache, allowing the data to be read directly from the cache instead of main memory or slower storage media.

[0025] If a multi-core NPU has a weight cache, the weight data will be stored in the cache. When repeatedly reading the weight data, it is not necessary to read it from memory or storage media again, but only from the cache, thereby saving bandwidth and improving processor performance.

[0026] Figure 2 This is a schematic diagram of a multi-core NPU execution process according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, multiple cores (core0, core1, core2, and core3) of a multi-core NPU directly read weight data from the cache, without needing to read from Double Data Rate SDRAM (DDR SDRAM). However, in existing technologies, the multiple cores of a multi-core NPU do not consider the sharing of weight data between task nodes during execution, and do not execute task nodes in a similar execution order. This fails to ensure that task nodes reading the same weight cache are executed simultaneously on each core of the NPU. Consequently, this leads to the repeated loading of weight data during execution, consuming significant bandwidth and thus impacting processor performance.

[0027] The control method, apparatus, and electronic device for the neural network processing unit disclosed herein are intended to solve at least one of the above-mentioned technical problems in the prior art.

[0028] The following description of several exemplary embodiments illustrates the technical solutions of this disclosure and the technical effects produced by these solutions. It should be noted that the following embodiments can be referenced, learned from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0029] This disclosure provides a control method for a neural network processing unit, which is applied to a multi-core NPU with the same topology.

[0030] As some optional embodiments of this disclosure, the types of the above-described topology include at least one of the following: pyramid structure, inverted pyramid structure, and multi-branch structure; the nodes of the multi-core neural network processing unit of the pyramid structure type diffuse from top to bottom; the nodes of the multi-core neural network processing unit of the inverted pyramid structure type converge from top to bottom; and the nodes of the multi-branch structure type multi-core neural network processing unit are arranged in branches.

[0031] The technical solution proposed in this disclosure addresses the situation where each core of a multi-core NPU has nodes that share weight data and have similar topologies (to achieve the purpose of sharing weights, each core of a multi-core NPU must have the same topology). By rearranging the branches, the nodes that share weight data can be executed simultaneously, thereby achieving the purpose of directly reading weight data from the cache.

[0032] The technical solution proposed in this disclosure is not applicable to all topologies, but is only applicable to the following topologies: 1) Pyramid structure; 2) Multiple branches; 3) Inverted pyramid structure.

[0033] The above three structural types will be explained in detail below with specific diagrams.

[0034] Figure 3 This is a flowchart of a control method for a neural network processing unit according to an embodiment of the present disclosure, such as... Figure 3 As shown, the method includes the following steps: Step S301: Divide the topology of each processing core in the neural network processing unit into multiple identical stages; each stage includes at least one branch, and each branch includes at least one node.

[0035] In the embodiments of this disclosure, the number of branches remains constant within a stage. When the branches diverge or converge, a stage needs to be switched.

[0036] A series of nodes executed in sequence is called a branch. There are no dependencies between branches, so the execution order of branches can be changed.

[0037] Figure 4a This is a schematic diagram of a pyramid-structured multi-core NPU provided in an embodiment of this disclosure, as shown below. Figure 4a As shown, although core0 and core1 have the same topology, the node order is not guaranteed. Therefore, when branches exist, core0 and core1 may not execute branches with shared weights simultaneously. For example, the 8th node executed in core0 and the 5th node executed in core1 may share weight data. However, due to the large difference in execution time, when core0 reaches this node, the cache has already been refreshed, and the weight data cannot be read from the cache. It must be moved again, consuming DDR bandwidth.

[0038] To address the aforementioned issues, the technical solution proposed in this disclosure divides the pyramid-type topology into multiple stages, each stage having multiple branches, and the branches allow for changes in their order.

[0039] Figure 4b It is Figure 4a The diagram illustrates the phase division of a pyramid-type topological structure, as shown below. Figure 4b As shown, core0 can be divided into 3 stages (stage0, stage1, stage2). Since core1 has a similar topology to core0, core1 can also be divided into 3 stages.

[0040] As some optional embodiments of this disclosure, step S301 divides the topology of each processing core in the neural network processing unit into multiple identical stages, which is achieved by the following method: dividing the topology of each processing core into multiple identical stages based on the characteristics of the topology of each processing core.

[0041] In the embodiments of this disclosure, when the topology of each processing core is divided into multiple identical stages, the division is based on the characteristics of the topology, such as... Figure 4b In the middle, from top to bottom, node 2 branches into two branches, and node 7 also branches into two branches. Therefore, in Figure 4b This is equivalent to dividing the entire topology into three stages by using nodes 2 and 7 as "boundaries".

[0042] The topology of each NPU core is different, and the way it is divided into multiple stages is also different.

[0043] Step S302: Determine the execution order of each branch included in each stage of each processing core.

[0044] According to some optional embodiments of this disclosure, step S302, which determines the execution order of each branch included in each stage of each processing core, includes the following steps: determining the weight cache data of each branch included in each stage of each processing core; and determining the execution order of each branch included in each stage of each processing core based on the weight cache data.

[0045] like Figure 4b As shown, starting from the bottom of the graph structure, stage 0 of core0 has two branches (left branch and right branch). Core0 executes the left branch first, and then executes the right branch. At this time, the weight data of the left branch of core0, including wt0-8 and wt0-9, and the weight data of the right branch, including wt0-10 and wt0-11, are obtained.

[0046] For core1, the weight data of each branch is also obtained. The weight data of the left branch of stage0 of core1 includes wt0-5 and wt0-6; and the weight data of the right branch of stage0 of core1 includes wt0-7 and wt0-8.

[0047] According to some other optional embodiments of this disclosure, the execution order of each branch included in each stage of each processing core is determined based on weight cache data, which is achieved by the following method: determining the identifier of each processing core; when executing the branch included in the processing core with a large identifier, first executing the branch with the same weight cache data as the processing core with a small identifier, and then executing the branch with different weight cache data as the processing core with a small identifier; the execution time of branches with the same weight cache data is the same.

[0048] As some optional embodiments of this disclosure, if the nodes included in the first branch share weights with the nodes included in the second branch, it is determined that the weight cache data of the first branch and the second branch are the same; the first branch and the second branch are either branches in two different neural network processing units.

[0049] In the embodiments of this disclosure, by comparing core0 and core1, it is found that the weight data of the right branch of stage0 in core1 is the same as the weight data of the left branch of stage0 in core0. That is, node 8 of core0 and node 7 of core1 share weight data, and node 9 of core0 and node 8 of core1 share weight data.

[0050] Nodes sharing weight data should execute at the same time to make full use of cache bandwidth.

[0051] by Figure 4b For example, node 8 of core0 and node 7 of core1 are executed simultaneously, and node 9 of core0 and node 8 of core1 are executed simultaneously. That is, core1 executes the right branch of stage0 first, and then executes the left branch of stage0, so as to achieve the purpose of executing the corresponding nodes of core0 simultaneously.

[0052] Once stage 0 has finished executing, the entire stage 0 can be considered as a single node. Then, the comparison of stage 1 begins, such as... Figure 4c As shown.

[0053] Similarly, stage 1 also includes two branches, using the same... Figure 4b In the same manner as the illustrated embodiment, it is ensured that the nodes sharing weight data in the stage1 branch of core1 and the stage1 branch of core0 execute simultaneously. After execution, stage1 can be treated as a node, and then the comparison of stage2 can begin, as follows... Figure 4d As shown.

[0054] Stage 2 has only one branch left, so there's no need to consider the order of arrangement. As the last stage of this model, the branch rearrangement is now complete.

[0055] Figure 5 This is a schematic diagram of a multi-branch structure multi-core NPU provided in an embodiment of this disclosure. The multi-branch structure is equivalent to a pyramid structure including a stage, so it is only necessary to rearrange all branches in order of equal weight.

[0056] like Figure 5 As shown, for example, by comparing core0 and core1, it is found that node 1 of core0 and node 4 of core1 share weight data, node 2 of core0 and node 5 of core1 share weight data, and node 3 of core0 and node 6 of core1 share weight data. In this case, node 1 of core0 and node 4 of core1 need to be executed simultaneously, node 2 of core0 and node 5 of core1 need to be executed simultaneously, and node 3 of core0 and node 6 of core1 need to be executed simultaneously.

[0057] Figure 6a This is a schematic diagram of an inverted pyramid structure multi-core NPU provided in this disclosure embodiment. The topology of the inverted pyramid is similar to that of a pyramid, except that the stage division is reversed, starting from the top. Figure 6b As shown.

[0058] Similarly, starting from stage0, core0 is used as the reference order. Subsequent cores are executed in the same order as core0, with the same weight data. After stage0 is completed, stage0 is treated as a node, and stage1 is executed again, until all stages are completed. Ultimately, the execution order of all nodes is consistent with core0 based on the weight data.

[0059] Step S303: Execute each branch of each stage of each processing core in the execution order.

[0060] The technical solution proposed in this disclosure, by reordering the topology of the NPU, ensures that task nodes reading the same weighted cache are executed simultaneously in each core of the NPU, thereby achieving the technical effects of improving cache hit rate, saving bandwidth, and improving processor performance.

[0061] This disclosure provides a control device for a neural network processing unit, such as... Figure 7 As shown, the device 70 may include: a division module 701, a determination module 702, and a processing module 703, wherein, The partitioning module 701 is used to divide the topology of each processing core in the neural network processing unit into multiple identical stages; each stage includes at least one branch, and each branch includes at least one node.

[0062] like Figure 4a As shown, although core0 and core1 have the same topology, the node order is not guaranteed. Therefore, when branches exist, core0 and core1 may not execute branches with shared weights simultaneously. For example, the 8th node executed in core0 and the 5th node executed in core1 may share weight data. However, due to the large difference in execution time, when core0 reaches this node, the cache has already been refreshed, and the weight data cannot be read from the cache. It must be moved again, consuming DDR bandwidth.

[0063] To address the aforementioned issues, the technical solution proposed in this disclosure divides the pyramid-type topology into multiple stages, each stage having multiple branches, and the branches allow for changes in their order.

[0064] Figure 4b It is Figure 4a The diagram illustrates the phase division of a pyramid-type topological structure, as shown below. Figure 4b As shown, core0 can be divided into 3 stages (stage0, stage1, stage2). Since core1 has a similar topology to core0, core1 can also be divided into 3 stages.

[0065] According to some optional embodiments of this disclosure, the partitioning module 701 is further configured to partition the topology of each processing core into multiple identical stages based on the characteristics of the topology of each processing core.

[0066] In the embodiments of this disclosure, when the topology of each processing core is divided into multiple identical stages, the division is based on the characteristics of the topology, such as... Figure 4b In the middle, from top to bottom, node 2 branches into two branches, and node 7 also branches into two branches. Therefore, in Figure 4b This is equivalent to dividing the entire topology into three stages by using nodes 2 and 7 as "boundaries".

[0067] The topology of each NPU core is different, and the way it is divided into multiple stages is also different.

[0068] The determination module 702 is used to determine the execution order of each branch included in each stage of each processing core.

[0069] According to some optional embodiments of this disclosure, the determining module 702 includes: a first determining unit, configured to determine the weight cache data of each branch included in each stage of each processing core; and a second determining unit, configured to determine the execution order of each branch included in each stage of each processing core based on the weight cache data.

[0070] like Figure 4b As shown, starting from the bottom of the graph structure, stage 0 of core0 has two branches (left branch and right branch). Core0 executes the left branch first, and then executes the right branch. At this time, the weight data of the left branch of core0, including wt0-8 and wt0-9, and the weight data of the right branch, including wt0-10 and wt0-11, are obtained.

[0071] For core1, the weight data of each branch is also obtained. The weight data of the left branch of stage0 of core1 includes wt0-5 and wt0-6; and the weight data of the right branch of stage0 of core1 includes wt0-7 and wt0-8.

[0072] According to some optional embodiments of this disclosure, the second determining unit is used to determine the identifier of each processing core; when executing the branch included in the processing core with the larger identifier, the branch with the same weight cache data as the processing core with the smaller identifier is executed first, and then the branch with different weight cache data as the processing core with the smaller identifier is executed; the execution time of the branches with the same weight cache data is the same.

[0073] According to some optional embodiments of this disclosure, the above-described apparatus is further configured to determine that the weight cache data of the first branch and the second branch are the same when the nodes included in the first branch and the nodes included in the second branch share weights; the first branch and the second branch are either branches of two different neural network processing units.

[0074] In the embodiments of this disclosure, by comparing core0 and core1, it is found that the weight data of the right branch of stage0 in core1 is the same as the weight data of the left branch of stage0 in core0. That is, node 8 of core0 and node 7 of core1 share weight data, and node 9 of core0 and node 8 of core1 share weight data.

[0075] Nodes sharing weight data should execute at the same time to make full use of cache bandwidth.

[0076] by Figure 4b For example, node 8 of core0 and node 7 of core1 are executed simultaneously, and node 9 of core0 and node 8 of core1 are executed simultaneously. That is, core1 executes the right branch of stage0 first, and then executes the left branch of stage0, so as to achieve the purpose of executing the corresponding nodes of core0 simultaneously.

[0077] Once stage 0 has finished executing, the entire stage 0 can be considered as a single node. Then, the comparison of stage 1 begins, such as... Figure 4c As shown.

[0078] Similarly, stage 1 also includes two branches, using the same... Figure 4b In the same manner as the illustrated embodiment, it is ensured that the nodes sharing weight data in the stage1 branch of core1 and the stage1 branch of core0 execute simultaneously. After execution, stage1 can be treated as a node, and then the comparison of stage2 can begin, as follows... Figure 4d As shown.

[0079] Stage 2 has only one branch left, so there's no need to consider the order of arrangement. As the last stage of this model, the branch rearrangement is now complete.

[0080] Processing module 703 is used to execute each branch of each stage of each processing core in the order of execution.

[0081] According to some optional embodiments of this disclosure, the types of the above-mentioned topology include at least one of the following: pyramid structure, inverted pyramid structure, and multi-branch structure; the nodes of the multi-core neural network processing unit of the pyramid structure type diffuse from top to bottom; the nodes of the multi-core neural network processing unit of the inverted pyramid structure type converge from top to bottom; and the nodes of the multi-branch structure type multi-core neural network processing unit are arranged in branches.

[0082] The technical solution proposed in this disclosure addresses the situation where each core of a multi-core NPU has nodes that share weight data and have similar topologies (to achieve the purpose of sharing weights, each core of a multi-core NPU must have the same topology). By rearranging the branches, the nodes that share weight data can be executed simultaneously, thereby achieving the purpose of directly reading weight data from the cache.

[0083] The technical solution proposed in this disclosure is not applicable to all topologies, but is only applicable to the following topologies: 1) Pyramid structure; 2) Multiple branches; 3) Inverted pyramid structure.

[0084] The apparatus of this disclosure embodiment can execute the method provided in this disclosure embodiment, and its implementation principle is similar, and it has corresponding technical effects. The actions performed by each module in the apparatus of each embodiment of this disclosure correspond to the steps in the method of each embodiment of this disclosure. For a detailed functional description of each module of the apparatus, please refer to the description in the corresponding method shown above, and it will not be repeated here.

[0085] This disclosure provides an electronic device including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of the method provided in any optional embodiment of this disclosure. Compared with the prior art, this achieves the following: ensuring that task nodes reading the same weight cache are executed simultaneously in each core of the NPU, thereby improving cache hit rate, saving bandwidth, and improving processor performance. In one alternative embodiment, an electronic device is provided, such as Figure 8 As shown, Figure 8 The illustrated electronic device 8000 includes a processor 8001 and a memory 8003. The processor 8001 and the memory 8003 are connected, for example, via a bus 8002. Optionally, the electronic device 8000 may further include a transceiver 8008. The transceiver 8008 can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 8004 is not limited to one type, and the structure of the electronic device 8000 does not constitute a limitation on the embodiments of this disclosure.

[0086] Processor 8001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with this disclosure. Processor 8001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0087] Bus 8002 may include a pathway for transmitting information between the aforementioned components. Bus 8002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 8002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0088] The memory 8003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.

[0089] The memory 8003 is used to store computer programs that execute embodiments of the present disclosure, and is controlled by the processor 8001 to execute them. The processor 8001 is used to execute the computer programs stored in the memory 8003 to implement the steps shown in the foregoing method embodiments.

[0090] Electronic devices include, but are not limited to, mobile phones, tablets, etc.

[0091] This disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.

[0092] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.

[0093] It should be understood that although arrows indicate various operation steps in the flowcharts of the embodiments of this disclosure, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of the embodiments of this disclosure, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured as required, and the embodiments of this disclosure do not limit this.

[0094] The above description is only an optional implementation method for some implementation scenarios of this disclosure. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this disclosure without departing from the technical concept of this disclosure also fall within the protection scope of the embodiments of this disclosure.

Claims

1. A control method for a neural network processing unit, the method being applied to multi-core neural network processing units with the same topology, characterized in that, include: The topology of each processing core in the neural network processing unit is divided into multiple identical stages; Each stage includes at least one branch, and each branch includes at least one node; Determine the execution order of each branch included in each stage of each processing core; Each branch of each stage of each processing core is executed in the order described.

2. The method according to claim 1, characterized in that, Determining the execution order of each branch within each stage of each processing core includes: Determine the weight cache data for each branch included in each stage of each processing core; The execution order of each branch in each stage of each processing core is determined based on the weighted cache data.

3. The method according to claim 2, characterized in that, The step of determining the execution order of each branch in each stage of each processing core based on the weighted cache data includes: Determine the identifier of each processing core; When executing the branches of the processing core with the larger identifier, the branches with the same weight cache data as the processing core with the smaller identifier are executed first, and then the branches with different weight cache data are executed; the execution time of the branches with the same weight cache data is the same.

4. The method according to claim 3, characterized in that, The method further includes: If the nodes included in the first branch share weights with the nodes included in the second branch, it is determined that the weight cache data of the first branch and the second branch are the same; the first branch and the second branch are any branches in two different neural network processing units.

5. The method according to any one of claims 2 to 4, characterized in that, The types of topologies include at least one of the following: pyramid structure, inverted pyramid structure, and multi-branch structure; The multi-core neural network processing unit of the pyramid structure type includes nodes that diffuse from top to bottom; The nodes of the inverted pyramid structure type multi-core neural network processing unit converge from top to bottom; The nodes of the multi-core neural network processing unit of the multi-branch structure type are arranged in a branched manner.

6. The method according to claim 1, characterized in that, The method of dividing the topology of each processing core in the neural network processing unit into multiple identical stages includes: Based on the characteristics of the topology of each processing core, the topology of each processing core is divided into multiple identical stages.

7. A control device for a neural network processing unit, characterized in that, include: The partitioning module is used to divide the topology of each processing core in the neural network processing unit into multiple identical stages; Each stage includes at least one branch, and each branch includes at least one node; The determination module is used to determine the execution order of each branch included in each stage of each processing core; A processing module is used to execute each branch of each stage of each processing core in the order of execution.

8. An electronic device, comprising: A memory, a processor, and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the method of any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

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