Preparation parameter optimization method and device of power semiconductor device, equipment and medium

Abstract

The invention relates to the technical field of power semiconductor device preparation, and discloses a preparation parameter optimization method, device and equipment of a power semiconductor device and a medium, the method comprises the following steps: obtaining various characterization data and current preparation parameters of the power semiconductor device, the current preparation parameters being process parameters adopted by the current preparation of the power semiconductor device; cue words are obtained, the cue words are used for indicating the direction in which the target model analyzes the representation data and used for indicating the optimization direction of the current preparation parameters, and the target model is a large language model in which a reinforcement learning algorithm is introduced; the various representation data, the current preparation parameters and the cue words are input into a target model to be analyzed and optimized, target preparation parameters of the power semiconductor device are obtained, and the target preparation parameters are predicted technological parameters enabling the performance of the power semiconductor device to be optimal in the optimization direction. Preparation parameters can be optimized in real time, and the method adapts to changes of new device structures and processes.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device fabrication technology, and specifically to a method, apparatus, equipment, and medium for optimizing the fabrication parameters of power semiconductor devices. Background Technology

[0002] Power semiconductor devices are used for power conversion and circuit control, and are core components for power processing. Typical functions include frequency conversion, voltage conversion, current conversion, power amplification, and power management. They are widely used in energy conversion, motor control, and communication equipment. With the rapid development of emerging technologies such as new energy vehicles, smart grids, and 5G communications, the performance requirements for power semiconductors are becoming increasingly stringent, especially in terms of energy conversion efficiency, system stability, and reliability.

[0003] Currently, designers primarily rely on characterization data analysis of power semiconductor devices to understand their stability and reliability, and then optimize fabrication parameters based on experience to improve device performance. However, manual optimization is not only time-consuming and labor-intensive, but also difficult to adapt to changes in new device structures and processes. Summary of the Invention

[0004] In view of this, the present invention provides a method, apparatus, equipment and medium for optimizing the fabrication parameters of power semiconductor devices, so as to improve the problem that manual optimization is not only time-consuming and labor-intensive, but also difficult to adapt to changes in the structure and process of new devices.

[0005] In a first aspect, the present invention provides a method for optimizing the fabrication parameters of a power semiconductor device. The method includes: acquiring various characterization data and current fabrication parameters of the power semiconductor device, wherein the characterization data refers to data reflecting various characteristics and performance of the power semiconductor device, and the current fabrication parameters are the process parameters used to fabricate the power semiconductor device; acquiring prompt words, wherein the prompt words are used to indicate the direction of the target model's analysis of the characterization data and to indicate the optimization direction of the current fabrication parameters, and the target model is a large language model incorporating reinforcement learning algorithms; inputting the various characterization data, the current fabrication parameters, and the prompt words into the target model for analysis and optimization to obtain the target fabrication parameters of the power semiconductor device, wherein the target fabrication parameters are predicted process parameters that optimize the performance of the power semiconductor device in the optimization direction.

[0006] The method for optimizing the fabrication parameters of power semiconductor devices provided in this embodiment, after acquiring various characterization data, current fabrication parameters, and prompts, inputs these data into a target model for analysis, thereby obtaining the target fabrication parameters for the power semiconductor device. The target model in this embodiment, through a reinforcement learning algorithm, can automatically construct a feedback loop from the analysis results of the characterization data to the device fabrication parameters, achieving real-time data analysis and fabrication parameter optimization. This adapts to changes in new device structures and processes, accelerates the research and development and manufacturing process of power semiconductor devices, and improves research and development and manufacturing efficiency.

[0007] In one optional implementation, multiple characterization data, current fabrication parameters, and prompt words are input into the target model for analysis and optimization to obtain the target fabrication parameters for the power semiconductor device. This includes: determining the analysis results based on the multiple characterization data and prompt words, wherein the analysis results are the results generated by the target model after analyzing the multiple characterization data based on the prompt words; and optimizing the current fabrication parameters using reinforcement learning based on the analysis results to obtain the target fabrication parameters.

[0008] In one optional implementation, the analysis results are determined based on multiple representation data and prompt words, including: generating preliminary analysis results and annotation information based on multiple representation data and prompt words; extracting features from the preliminary analysis results and the representation data with annotation information to obtain multiple feature vectors; and integrating the multiple feature vectors to obtain the analysis results.

[0009] In one alternative implementation, the target model is a large language model that incorporates reinforcement learning algorithms and is enhanced with domain knowledge related to power semiconductor devices. The prompt words are also used to indicate whether the target model needs to interpret the analysis results by combining multidisciplinary theoretical knowledge, integrating multiple feature vectors to obtain the analysis results, including: when the prompt words indicate that multidisciplinary theoretical knowledge is needed for interpretation, interpreting and deriving the analysis results based on multidisciplinary theoretical knowledge to generate interpretable analysis results for power semiconductor devices.

[0010] In one optional implementation, before generating preliminary analysis results and annotation information based on multiple representation data and prompt words, the method further includes: preprocessing the multiple representation data to obtain multiple preprocessed representation data, wherein the preprocessing includes at least one of denoising and dimensionality reduction; generating preliminary analysis results and annotation information based on multiple representation data and prompt words, including: generating preliminary analysis results and annotation information based on multiple preprocessed representation data and prompt words.

[0011] In this embodiment, preprocessing various characterization data can remove noise interference, retain key information, improve the quality of characterization data, and provide a better foundation for subsequent analysis.

[0012] In one alternative implementation, after obtaining the target fabrication parameters of the power semiconductor device, the method further includes: analyzing the output power semiconductor device.

[0013] In one alternative implementation, before inputting various characterization data, current fabrication parameters, and prompt words into the target model for analysis and optimization to obtain the target fabrication parameters for the power semiconductor device, the method further includes: creating a target model based on a large language model.

[0014] In one optional implementation, creating a target model based on a large language model includes: quantizing, pruning, and distilling the large language model to obtain a simplified large language model; introducing a reinforcement learning algorithm into the simplified large language model to obtain an initial model; constructing a concept knowledge graph based on a database, wherein the concepts in the concept knowledge graph are concepts related to the power semiconductor device domain; acquiring a domain dataset, wherein the domain dataset is a dataset related to the power semiconductor device domain; training the initial model based on the domain dataset and the concept knowledge graph, and determining the trained initial model as the target model.

[0015] In this embodiment, quantization, pruning, and knowledge distillation of the large language model can significantly reduce its size without significantly reducing its original performance, thereby improving the reasoning speed and resource utilization efficiency of the large language model and enhancing its performance, thus achieving self-improvement of the large language model.

[0016] In one alternative implementation, the various characterization data include at least two of the following: voltage, current, capacitance, current-voltage characteristic curve, capacitance-voltage characteristic curve, infrared thermal imaging data, power semiconductor device data acquired by an X-ray diffractometer, power semiconductor device data acquired by a scanning electron microscope, power semiconductor device data acquired by X-ray photoelectron spectroscopy, and power semiconductor device data acquired by a transmission electron microscope.

[0017] Secondly, the present invention provides a device for optimizing the fabrication parameters of a power semiconductor device, comprising: a first acquisition module for acquiring various characterization data and current fabrication parameters of the power semiconductor device, wherein the characterization data refers to data reflecting various characteristics and performance of the power semiconductor device, and the current fabrication parameters are the process parameters used to fabricate the power semiconductor device; a second acquisition module for acquiring prompt words, wherein the prompt words are used to indicate the direction of the target model's analysis of the characterization data and to indicate the optimization direction of the current fabrication parameters, and the target model is a large language model incorporating reinforcement learning algorithms; and an analysis and optimization module for inputting the various characterization data, the current fabrication parameters, and the prompt words into the target model for analysis and optimization to obtain the target fabrication parameters of the power semiconductor device, wherein the target fabrication parameters are predicted process parameters that optimize the performance of the power semiconductor device in the optimization direction.

[0018] In one optional implementation, the analysis and optimization module includes: an analysis unit, used to determine the analysis result based on multiple representation data and prompt words, wherein the analysis result is the result generated by the target model after analyzing multiple representation data based on prompt words; and an optimization unit, used to optimize the current preparation parameters in a reinforcement learning manner based on the analysis result to obtain the target preparation parameters.

[0019] In one optional implementation, the analysis unit includes: a generation subunit for generating preliminary analysis results and annotation information based on multiple representation data and prompt words; an extraction subunit for extracting features from the preliminary analysis results and the representation data with annotation information to obtain multiple feature vectors; and an integration subunit for integrating the multiple feature vectors to obtain the analysis results.

[0020] In one alternative implementation, the target model is a large language model enhanced with reinforcement learning algorithms and domain knowledge related to power semiconductor devices. The prompt words are also used to indicate whether the target model needs to interpret the analysis results by combining multidisciplinary theoretical knowledge. The integration subunit includes an interpretation subunit, which is used to interpret and derive the analysis results based on multidisciplinary theoretical knowledge when the prompt words indicate that interpretation by combining multidisciplinary theoretical knowledge is required, thereby generating interpretable analysis results for power semiconductor devices.

[0021] In one optional implementation, the analysis unit further includes: a preprocessing subunit for preprocessing multiple representation data to obtain multiple preprocessed representation data, wherein the preprocessing includes at least one of denoising and dimensionality reduction; and a generation subunit for generating preliminary analysis results and annotation information based on the multiple preprocessed representation data and prompt words.

[0022] In one alternative implementation, after obtaining the target fabrication parameters of the power semiconductor device, the method further includes: analyzing the output power semiconductor device.

[0023] In one alternative implementation, the apparatus further includes a creation module for creating a target model based on a large language model.

[0024] In one optional implementation, the creation module includes: a processing unit for quantizing, pruning, and knowledge distilling the large language model to obtain a simplified large language model; an introduction unit for introducing a reinforcement learning algorithm into the simplified large language model to obtain an initial model; a construction unit for constructing a concept knowledge graph based on a database, wherein the concepts in the concept knowledge graph are concepts related to the power semiconductor device domain; an acquisition unit for acquiring a domain dataset, wherein the domain dataset is a dataset related to the power semiconductor device domain; and a training unit for training the initial model based on the domain dataset and the concept knowledge graph, and determining the trained initial model as the target model.

[0025] In one alternative implementation, the various characterization data include at least two of the following: voltage, current, capacitance, current-voltage characteristic curve, capacitance-voltage characteristic curve, infrared thermal imaging data, power semiconductor device data acquired by an X-ray diffractometer, power semiconductor device data acquired by a scanning electron microscope, power semiconductor device data acquired by X-ray photoelectron spectroscopy, and power semiconductor device data acquired by a transmission electron microscope.

[0026] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method for optimizing the fabrication parameters of the power semiconductor device described in the first aspect or any corresponding embodiment.

[0027] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the method for optimizing the fabrication parameters of a power semiconductor device according to the first aspect or any corresponding embodiment thereof.

[0028] Fifthly, the present invention provides a computer program product, including computer instructions, which are used to cause a computer to execute the method for optimizing the fabrication parameters of a power semiconductor device according to the first aspect or any corresponding embodiment described above. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a schematic flowchart of a method for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram illustrating the specific process of optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention;

[0032] Figure 3 This is a flowchart illustrating another method for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention;

[0033] Figure 4 This is a schematic flowchart of another method for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram illustrating the specific process of optimizing the fabrication parameters of another power semiconductor device according to an embodiment of the present invention;

[0035] Figure 6 This is a structural block diagram of a device for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0038] This invention provides a method for optimizing the fabrication parameters of power semiconductor devices. By introducing a target model of reinforcement learning for data analysis and optimization, a feedback loop can be constructed from the analysis results of characterizing data to the device fabrication parameters. This allows for real-time optimization of fabrication parameters, saving manpower and adapting to changes in new device structures and processes. As a result, the research and development and manufacturing process of power semiconductor devices can be accelerated, and the research and development and manufacturing efficiency can be improved.

[0039] To facilitate understanding of this invention, the relevant technologies will first be explained:

[0040] (1) Power semiconductor devices

[0041] Power semiconductor devices are semiconductor devices used to process high-power electrical energy, primarily for power conversion, control, and protection. They enable efficient conversion between DC and AC, AC and DC, and DC and DC, and can also perform switching control, voltage and current regulation, and provide overcurrent and overvoltage protection. Furthermore, power semiconductors play a crucial role in energy management, including energy-saving control and renewable energy integration, and are widely used in industry, energy, and transportation, making them indispensable core components in modern power systems and electronic equipment.

[0042] According to their operating voltage and frequency, power semiconductors can be divided into thyristors, diodes, insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs), among which MOSFETs are abbreviated as MOS tubes.

[0043] (2) Large Language Model (LLM)

[0044] Large language models are a deep learning-based natural language processing technique that learns language patterns from large-scale text data through self-supervised learning. Large language models have shown great potential in image understanding and data analysis, efficiently processing multimodal data and combining it with physical knowledge for analysis.

[0045] Deep learning is a branch of machine learning that can automatically learn features and patterns from large amounts of data by building multi-layered neural network models. Deep learning can be used for tasks such as image segmentation, object detection, and feature extraction, and can help identify defects and structural features in power semiconductor devices.

[0046] (3) Reinforce learning

[0047] Reinforcement learning is a machine learning method that learns optimal policies through the interaction of an agent with its environment to maximize cumulative rewards. The core idea of ​​reinforcement learning is that an agent learns optimal policies through interaction with its environment, that is, choosing the best action in a given state to maximize long-term rewards.

[0048] The method for optimizing the fabrication parameters of the power semiconductor device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0049] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0050] This embodiment provides a method for optimizing the fabrication parameters of a power semiconductor device, which can be used in a device for optimizing the fabrication parameters of a power semiconductor device. For example, the device for optimizing the fabrication parameters of a power semiconductor device can be a terminal device such as a server, computer, tablet computer, or mobile phone. Figure 1 This is a schematic flowchart of a method for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes the following steps:

[0051] Step S101: Obtain various characterization data and current fabrication parameters of the power semiconductor device.

[0052] Characterization data refers to data reflecting various characteristics and performance of power semiconductor devices, while current fabrication parameters are the process parameters currently used to fabricate power semiconductor devices.

[0053] Specifically, there are various methods for characterizing power semiconductor devices, and the characterization data can be electrical characteristic characterization data, thermal characteristic characterization data, or structural characteristic characterization data, etc.

[0054] For example, various characterization data may include at least two of the following: voltage, current, capacitance, current-voltage characteristic curve, capacitance-voltage characteristic curve, infrared thermography data, power semiconductor device data acquired by X-ray diffraction (XRD), power semiconductor device data acquired by scanning electron microscopy (SEM), power semiconductor device data acquired by X-ray photoelectron spectroscopy (XPS), and power semiconductor device data acquired by transmission electron microscopy (TEM).

[0055] Specifically, voltage, current, capacitance, current-voltage characteristic curves, and capacitance-voltage characteristic curves reflect the electrical characteristics of power semiconductor devices, while infrared thermal imaging data reflects their thermal characteristics. Data acquired by X-ray diffraction (XRD) includes information such as the position, intensity, and shape of diffraction peaks, which can be used to analyze the crystal structure, lattice parameters, and epitaxial layer thickness of power semiconductor devices. Data acquired by scanning electron microscopy (SEM) includes morphological information about power semiconductor devices, which can be used to analyze their surface morphology, for example, to detect defects such as cracks and dislocations on the surface.

[0056] Data acquired through X-ray photoelectron spectroscopy (XPS) of power semiconductor devices includes information such as the energy and intensity of photoelectrons, which can be used to analyze the elemental composition (e.g., element types and their relative abundance), chemical state, and interface state of power semiconductor devices. Data acquired through transmission electron microscopy (TEM) of power semiconductor devices includes microstructural information, which can be used to analyze the lattice structure and defects, quantum well structure, etc.

[0057] The present invention does not limit the form of the characterization data. For example, the characterization data can be in the form of tables, text, graphs or pictures, etc., and covers information on the structure, composition and performance of optoelectronic materials and power semiconductor devices.

[0058] The fabrication parameter optimization device for power semiconductor devices can directly acquire various characterization data from voltage sensors, current sensors, infrared thermal imagers, X-ray diffractometers, scanning electron microscopes, X-ray photoelectron spectroscopy, and transmission electron microscopes. These characterization data can also be input by the user through human-computer interaction devices (such as mice, keyboards, and touch screens) to enable the device to acquire various characterization data.

[0059] For example, the fabrication parameters of power semiconductor devices include, but are not limited to, material parameters, epitaxial growth parameters, photolithography parameters, etching parameters, doping parameters, annealing parameters, and packaging parameters.

[0060] Material parameters refer to the materials selected for fabricating power semiconductor devices, such as material type, crystal purity, and doping concentration. Epitaxial growth parameters refer to the parameters of the epitaxial growth process used in fabricating power semiconductor devices, such as epitaxial layer thickness, growth rate, and growth temperature. Photolithography parameters refer to the parameters of the photolithography process used in fabricating power semiconductor devices, such as photolithographic resolution, photoresist thickness, exposure dose, and development time. Etching parameters refer to the parameters of the etching process used in fabricating power semiconductor devices, such as etching depth and etching rate. Doping parameters refer to the parameters of the doping process used in fabricating power semiconductor devices, such as dopant type, doping concentration, doping depth, and doping method. Annealing parameters refer to the parameters of the annealing process used in fabricating power semiconductor devices, such as annealing temperature and annealing time. Packaging parameters refer to the parameters of the packaging process used in fabricating power semiconductor devices, such as package size, packaging material, and package thickness.

[0061] Specifically, fabrication parameters are crucial to the performance, reliability, and cost control of power semiconductor devices. Material parameters directly affect the device's conductivity, breakdown voltage, and thermal stability. Doping parameters, particularly doping concentration and depth, determine the conductivity and breakdown voltage of the power semiconductor device. Annealing parameters influence dopant activation and crystal defect repair, while packaging parameters affect heat dissipation and mechanical stability. Precise control of process parameters can reduce process defects, ensuring the long-term stability and reliability of power semiconductor devices. Optimizing material and process parameters can reduce manufacturing costs, and selecting appropriate packaging materials and sizes can reduce packaging costs. The optimization of new materials and advanced process technologies drives technological innovation, enabling smaller, higher-performance devices.

[0062] For example, the current fabrication parameters can be determined by the designer based on experience and actual needs. In this embodiment, the power semiconductor device refers to a power semiconductor device obtained by performing the corresponding process flow using the current fabrication parameters. The process flow can refer to epitaxial growth, photolithography, etching, and doping, etc. The current fabrication parameters can be input by the user into the power semiconductor device fabrication parameter optimization device through a human-computer interaction device, so that the power semiconductor device fabrication parameter optimization device can obtain the current fabrication parameters.

[0063] Step S102: Obtain the prompt word.

[0064] The prompt words are used to indicate the direction of the target model's analysis of the representation data and to indicate the direction of optimization of the current preparation parameters. The target model is a large language model that incorporates reinforcement learning algorithms.

[0065] Specifically, prompts can guide the target model to output specific analysis results and guide the target model to optimize the current fabrication parameters in a specific direction. The direction of analysis can refer to the optical performance, electrical performance, structural performance, or thermal performance of the power semiconductor device, etc. The direction of optimization can refer to optimizing the power semiconductor device from the perspective of electrical performance, optical performance, structural performance, or thermal performance, etc.

[0066] The large language model can be the Source Han Sans model, or other lightweight pre-trained models such as the GPT series or Google's T5 model. Reinforcement learning algorithms can include REINFORCE++ and Proximal Policy Optimization (PPO). Reinforcement learning can utilize cloud computing resources, improving the training efficiency of reinforcement learning algorithms through distributed computing.

[0067] By introducing the REINFORCE++ algorithm and the PPO algorithm, the target model can learn a better preparation parameter optimization strategy, thereby improving the accuracy and reliability of the optimization results.

[0068] For example, the prompt words can be text data. For instance, the prompt words could be "Analyze the optical performance of power semiconductor devices based on multiple characterization data, and optimize the optical performance of power semiconductor devices based on the analysis results", or "Analyze the structural defects of power semiconductor devices based on multiple characterization data, and optimize the structural performance of power semiconductor devices based on the analysis results".

[0069] Specifically, the prompt words can be input by the user through a human-computer interaction device into the power semiconductor device fabrication parameter optimization device, enabling the power semiconductor device fabrication parameter optimization device to obtain the prompt words; the prompt words can also be generated by the power semiconductor device fabrication parameter optimization device based on a pre-configured combination of keywords.

[0070] Step S103: Input various characterization data, current fabrication parameters and prompt words into the target model for analysis and optimization to obtain the target fabrication parameters for the power semiconductor device.

[0071] The target fabrication parameters are the predicted process parameters that will optimize the performance of the power semiconductor device in the optimization direction. These target fabrication parameters are also the current fabrication parameters after optimization using the target model.

[0072] Specifically, a sufficient number of representative representation datasets and preparation parameter datasets can be collected in the laboratory. Based on the representation datasets and preparation parameter datasets, the large language model with reinforcement learning algorithm can be debugged and tested. Then, the large language model with reinforcement learning algorithm that has been debugged and tested can be used as the target model and deployed in the terminal device.

[0073] like Figure 2 As shown, a power semiconductor device is first fabricated based on the determined current fabrication parameters. Then, the fabricated power semiconductor device is tested to determine various characterization data. After acquiring these characterization data, prompts, and current fabrication parameters, these data can be input into a target model. The output of the target model is then used as the target fabrication parameters for the power semiconductor device. After obtaining the target fabrication parameters, the power semiconductor device can be re-fabricated based on these parameters, and the performance of the fabricated power semiconductor device can be verified.

[0074] The method for optimizing the fabrication parameters of power semiconductor devices provided in this embodiment, after acquiring various characterization data, current fabrication parameters, and prompts, inputs these data into a target model for analysis, thereby obtaining the target fabrication parameters for the power semiconductor device. The target model in this embodiment, through a reinforcement learning algorithm, can automatically construct a feedback loop from the analysis results of the characterization data to the device fabrication parameters, achieving real-time data analysis and fabrication parameter optimization. This adapts to changes in new device structures and processes, accelerates the research and development and manufacturing process of power semiconductor devices, and improves research and development and manufacturing efficiency.

[0075] This embodiment also provides another method for optimizing the fabrication parameters of power semiconductor devices, which can be used in the aforementioned terminal devices, etc. Figure 3 This is a schematic flowchart of another method for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention, as shown below. Figure 3 As shown, the method includes the following steps:

[0076] Step S301: Obtain various characterization data and current fabrication parameters of the power semiconductor device.

[0077] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0078] Step S302: Obtain the prompt word.

[0079] Please see details Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0080] Step S303: Input various characterization data, current fabrication parameters and prompt words into the target model for analysis and optimization to obtain the target fabrication parameters for the power semiconductor device.

[0081] Specifically, step S303 includes steps S3031 and S3032:

[0082] Step S3031: Determine the analysis results based on various characterization data and prompt words.

[0083] The analysis results are generated by the target model after analyzing various characterization data based on prompt words. For example, the analysis results may include the morphology, composition, or crystal structure of power semiconductor devices.

[0084] For example, after step S3031 above, the method for optimizing the fabrication parameters of the power semiconductor device may further include: the analysis results of the output power semiconductor device.

[0085] Specifically, the fabrication parameter optimization device can output analysis results of power semiconductor devices to a display device. The output format of the analysis results includes, but is not limited to, at least one of the following: image annotation, data analysis report, physical mechanism derivation process, and charts. Users can set prompts according to actual needs, and the target model can adjust the output format of the analysis results through the input prompts, improving the user's understanding and utilization efficiency of the data.

[0086] In some implementations, step S3031 may include steps a1 to a3:

[0087] Step a1: Based on various representation data and prompt words, generate preliminary analysis results and annotation information.

[0088] Specifically, the target model includes a multi-layer neural network, which can be divided into multiple parts. After receiving various representation data and prompt words, the first part of the neural network can identify the feature regions in the representation data based on the prompt words and provide corresponding annotations, such as defect type, structural features and component distribution. The output of the first part of the neural network is the preliminary analysis result and annotation information.

[0089] Step a2 involves extracting features from the preliminary analysis results and the labeled representation data to obtain multiple feature vectors.

[0090] Specifically, the input of the second part of the neural network is connected to the output of the first part of the neural network. After receiving the preliminary analysis results and the representation data with labeled information, the second part of the neural network adjusts the segmentation and feature extraction parameters according to the characteristics of the representation task and representation data obtained from different prompt words, accurately extracts the key features of the representation data with labeled information, and obtains multiple feature vectors, providing more accurate data support for further analysis and extraction.

[0091] Step a3: Integrate multiple feature vectors to obtain the analysis results of power semiconductor devices.

[0092] Specifically, the input of the third part of the neural network is connected to the output of the second part of the neural network, and the output of the third part of the neural network constitutes the output of the target model. After receiving multiple feature vectors, the third part of the neural network integrates the multiple feature vectors to form a comprehensive analysis report.

[0093] Specifically, the neural network in the third part can refer to reinforcement learning algorithms, which guide the model to learn better reasoning strategies through reward mechanisms and policy optimization.

[0094] Alternatively, the reinforcement learning algorithm can be the Advantage Actor-Critic (A2C) algorithm or the Deep Deterministic Policy Gradient (DDPG) algorithm, etc.

[0095] In some embodiments, the target model can be a large language model that incorporates reinforcement learning algorithms and is enhanced with domain knowledge related to power semiconductor devices. The cue words are also used to indicate whether the target model needs to incorporate multidisciplinary theoretical knowledge to interpret the analysis results.

[0096] The fields related to power semiconductor devices include semiconductor physics, device physics, optics, electricity, materials science, and chemistry. Suggested keywords could include "analyzing structural defects in power semiconductor devices based on various characterization data and explaining the causes of these defects," etc.

[0097] When the prompt indicates that analysis requires the integration of multidisciplinary theoretical knowledge, step a3 above can be: based on multidisciplinary theoretical knowledge, interpret and derive the data obtained by integrating multiple feature vectors to generate interpretable analysis results for power semiconductor devices.

[0098] Specifically, the third part of the neural network can also utilize theoretical knowledge from fields such as semiconductor physics, device physics, optics, and electricity to interpret and deduce the integrated data, ensuring that the analysis results conform to scientific principles. Through logical reasoning methods, the data is combined with theoretical knowledge to deduce the underlying physical mechanisms and device performance.

[0099] For example, based on multidisciplinary theoretical knowledge, reinforcement learning can be used to interpret and deduce data obtained by integrating multiple feature vectors, generating interpretable analysis results for power semiconductor devices.

[0100] Introducing reinforcement learning into large language models allows for self-guidance and learning through reward signals in the environment. This reduces reliance on labeled data and enables adaptive trial-and-error analysis, yielding reasonable output results. The adaptability of reinforcement learning allows the target model to continuously adjust its strategies based on environmental changes, adapting to new data analysis needs. Through trial-and-error learning, the target model finds the optimal reasoning path, improving its reasoning ability in complex logical reasoning and multi-step tasks, ensuring that the target model generates more accurate and reliable analysis results.

[0101] Step S3032: Based on the analysis results, optimize the current preparation parameters using reinforcement learning to obtain the target preparation parameters.

[0102] Specifically, after the neural network in the third part obtains the analysis results, the agent in reinforcement learning (such as the optimization module using the PPO algorithm) can select an action based on the current state (i.e., the analysis results and the current preparation parameters) to determine a new combination of preparation parameters (such as specific doping concentration, annealing temperature, etc.). After determining the new combination of preparation parameters, the test performance of the new power semiconductor device is determined, and the reward is calculated based on the comparison between the test performance and the expected target performance. The agent updates its policy based on the received reward signal and the new state (new analysis results and new combination of preparation parameters). For example, in the REINFORCE++ algorithm, the probability of selecting a high-reward action in a similar state is increased by adjusting the parameters of the policy network. This process is repeated continuously, and each iteration optimizes the agent's policy, gradually converging to the optimal preparation parameters (i.e., the target preparation parameters).

[0103] The new fabrication parameters can be applied to the fabrication of actual power semiconductor devices. After fabrication, performance data (such as energy conversion efficiency and on-resistance) can be obtained through testing. The new fabrication parameters can also be applied to the fabrication of simulated power semiconductor devices, and the aforementioned test performance can be determined through simulation. The new fabrication parameters and corresponding test performance can be stored as samples in a fabrication parameter dataset, which is also pre-configured on the terminal device.

[0104] The reinforcement learning algorithm constructs a closed-loop feedback loop from model prediction to actual fabrication, and then optimizes the model based on the results. This enables real-time optimization of the fabrication parameters of power semiconductor devices and solves the problem in related technologies that it is difficult to dynamically adjust the fabrication parameters to adapt to new requirements.

[0105] Meanwhile, data continuously accumulates in the feedback loop, used to further fine-tune the target model, making its predictions more accurate and the reinforcement learning strategy more effective. Specifically, the agent in reinforcement learning selects actions based on its current state. After the environment (the parameter optimization device) executes the action, new device performance data is returned to the agent as a reward signal. The agent adjusts its parameters based on the reward signal, enhancing its ability to output high-quality optimization solutions. This process is repeated continuously, and the model learns better parameter adjustment strategies through trial and error, improving its ability to predict and optimize device performance. Simultaneously, the accumulated data is also used for supervised learning to fine-tune the model, expanding its knowledge base and improving its understanding of power semiconductor devices. Through the combination of reinforcement learning and supervised learning, the model continuously optimizes in the feedback loop, improving its performance.

[0106] In this embodiment, leveraging the multimodal data analysis and processing capabilities and multimodal output capabilities of the target model, potential relationships between characterization data can be uncovered, providing a new approach for the characterization analysis of power semiconductor devices. Introducing reinforcement learning into the target model effectively reduces reliance on large amounts of labeled data, lowers data acquisition and labeling costs, saves manpower and time, and improves detection efficiency. Simultaneously, it enhances the model's generalization ability and adaptability, enabling it to better handle different types of power semiconductor device characterization tasks and new device structures, reducing human error and subjective judgment, and improving detection accuracy. Furthermore, by constructing a closed-loop feedback loop from model prediction to device fabrication and employing reinforcement learning strategies, real-time and accurate optimization of fabrication parameters is achieved. This significantly shortens the R&D and manufacturing cycle of power semiconductors and improves overall production efficiency.

[0107] Furthermore, the adaptability of reinforcement learning enables the target model to find the optimal reasoning path, improving its reasoning ability in complex logical reasoning and multi-step tasks, and ensuring that the target model can generate more accurate and reliable analysis results.

[0108] In some optional implementations, prior to step a1, the process of determining the analysis results based on multiple characterization data and prompt words further includes: preprocessing the multiple characterization data to obtain multiple preprocessed characterization data. The preprocessing includes at least one of denoising and dimensionality reduction.

[0109] Specifically, the output of the fourth part of the neural network is connected to the input of the first part of the neural network, and the input of the fourth part of the neural network constitutes the input of the target model. After receiving various representation data, the fourth part of the neural network performs preprocessing operations such as denoising and dimensionality reduction on the representation data to remove noise interference in the representation data, retain key information, improve the quality of the representation data, and provide a better foundation for subsequent analysis.

[0110] At this point, step a1 above specifically involves generating preliminary analysis results and annotation information based on various preprocessed characterization data and prompt words.

[0111] This embodiment also provides another method for optimizing the fabrication parameters of power semiconductor devices, which can be used in the aforementioned terminal devices. Figure 4 This is a schematic flowchart of another method for optimizing the fabrication parameters of a power semiconductor device according to an embodiment of the present invention, as shown below. Figure 4 As shown, the method includes the following steps:

[0112] Step S401: Obtain various characterization data and current fabrication parameters of the power semiconductor device.

[0113] Please see details Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0114] Step S402: Obtain the prompt word.

[0115] Please see details Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0116] Step S403: Create the target model based on the large language model.

[0117] Specifically, step S403 includes:

[0118] Step S4031 involves quantizing, pruning, and knowledge distilling the large language model to obtain a simplified large language model.

[0119] Specifically, after obtaining the large language model, quantization and pruning can be used to remove unimportant connections and neurons, thereby reducing the number of parameters and computational complexity. Following quantization and pruning, the quantized and pruned large language model is fine-tuned using a power semiconductor device characterization dataset to restore its performance. The performance of the pruned large language model is then evaluated to ensure that the accuracy loss is within a preset range. This quantization pruning method significantly reduces the model size and computational complexity while maintaining its performance.

[0120] Quantization refers to the process of converting the data type of parameters in a large language model from a high-precision representation (such as 32-bit floating-point numbers) to a low-precision representation (such as 16-bit floating-point numbers, 8-bit integers, or even lower precision). Quantization reduces the storage space and computational cost of large language models. Quantization can be uniform quantization, non-uniform quantization, or cluster-based quantization, among others.

[0121] Uniform quantization divides the range of model parameters into several equally spaced intervals, each interval corresponding to a quantized value. For example, the range of a 32-bit floating-point number can be evenly divided into 256 intervals, with each parameter represented by an 8-bit integer, and each integer corresponding to the center value of an interval. Non-uniform quantization can use non-equal interval division based on the distribution of parameters. For regions with more concentrated distribution, finer intervals are used, while for sparser distribution, coarser intervals are used. Cluster-based quantization clusters model parameters according to their numerical characteristics, with each cluster center serving as a quantized value.

[0122] Alternatively, the pruning strategy can be weight-based pruning, gradient-based pruning, or sensitivity analysis-based pruning.

[0123] Pruning based on weight size refers to determining which weight parameters to remove based on the absolute value of the weight parameters in a large language model. For example, by setting a weight threshold, iterating through all weight parameters in the large language model, and setting weight parameters whose absolute value is less than the weight threshold to zero, pruning is achieved.

[0124] Gradient-based pruning determines whether to prune based on the magnitude of the gradient of each weight parameter in a large language model. For example, a gradient threshold can be set, and connections corresponding to weights whose absolute gradient value is less than the threshold can be removed. Compared to pruning based on weight magnitude, this method more dynamically considers the importance of weight parameters during training because the gradient reflects the immediate impact of weight parameters on the loss function. This can, to some extent, avoid pruning weight parameters that are critical to model performance, helping to maintain good model accuracy after pruning.

[0125] Sensitivity analysis is used to evaluate how sensitive each parameter or connection in a large language model is to the output of the large language model. Sensitivity analysis-based pruning refers to determining whether to prune based on the sensitivity of parameters in the large language model. For example, parameters with sensitivity less than a sensitivity threshold are pruned.

[0126] After quantizing and pruning the large language model, knowledge distillation is used to compress and optimize it. Specifically, a high-performance teacher model is trained on a power semiconductor device representation dataset to ensure it learns rich knowledge and features. Then, using the same power semiconductor device representation dataset and the labels generated from the teacher model's output, a student model is trained. By mimicking the output distribution of the teacher model, the student model learns deeper knowledge and generalization ability. Finally, the trained student model is selected as the simplified large language model.

[0127] Among them, the teacher model is a large language model after quantization and pruning (such as the Siyuan large model), and the student model can be designed according to the specific needs of power semiconductor device characterization analysis. It can be a Siyuan large model with further reduction of the number of layers, neurons or dimensions based on the teacher model.

[0128] In this embodiment, quantization, pruning, and knowledge distillation of the large language model can significantly reduce its size without significantly reducing its original performance, thereby improving the reasoning speed and resource utilization efficiency of the large language model and enhancing its performance, thus achieving self-improvement of the large language model.

[0129] Specifically, large language models emphasize lightweight architecture design, which can reduce the number of model parameters and computational complexity, enabling the final target model to be deployed and run on resource-constrained devices.

[0130] Step S4032: Introduce reinforcement learning algorithm into the simplified large language model to obtain the initial model.

[0131] Specifically, after obtaining the simplified large language model, a reinforcement learning algorithm is added to the simplified large language model. Then, the simplified large language model with the reinforcement learning algorithm is trained based on the representation dataset and the preparation parameter set. The trained simplified large language model with the reinforcement learning algorithm is the initial model.

[0132] Step S4033: Construct a conceptual knowledge graph based on the database.

[0133] The concepts in the concept knowledge graph are domain-related to power semiconductor devices. The concept knowledge graph is extracted and abstracted from a knowledge graph, focusing on the representation of knowledge at the conceptual level. It provides a simpler and more universal framework for understanding and processing domain knowledge, facilitating the organization, transfer, and reasoning of knowledge.

[0134] For example, the database can be a public database or a self-built database. A public database can refer to a database that users can access and use for free or for a fee, while a self-built database can refer to a database that users create and maintain themselves based on the characteristics of the field related to power semiconductor devices.

[0135] Specifically, tools such as WikiData can be used to integrate knowledge related to power semiconductor devices from databases and construct a knowledge graph. A knowledge graph is a graph-based data structure composed of nodes (entities) and edges (relationships) used to represent various types of knowledge and the relationships between them. A knowledge graph can contain a large amount of information such as specific entities, concepts, events, and attributes, used to comprehensively and accurately describe the knowledge system of one or more fields (in this invention, the field of power semiconductor devices).

[0136] After determining the knowledge graph, to improve performance, key concepts are extracted based on the frequency of concept occurrences in the power semiconductor device characterization dataset. The knowledge graph containing these key concepts is then defined as the concept knowledge graph. Key concepts are those in the knowledge graph with a frequency greater than a preset frequency, which can be set by the designers according to the application requirements of the large language model.

[0137] Step S4034: Obtain the domain dataset.

[0138] Among them, the domain dataset is a dataset related to power semiconductor devices, which can be the power semiconductor device characterization dataset mentioned above.

[0139] Step S4035: Train the initial model based on the domain dataset and concept knowledge graph, and determine the trained initial model as the target model.

[0140] Specifically, the initial model is enhanced with domain knowledge related to power semiconductor devices, including knowledge alignment, knowledge retrieval, knowledge injection, knowledge simplification and cleansing, as well as model training and validation.

[0141] Knowledge alignment refers to matching technical terms in the text input to the initial model with entities in the concept knowledge graph. Through knowledge alignment, a connection can be established between the input text and the concept knowledge graph, enabling the initial model to understand the precise meaning and contextual information of the technical terms in the input text.

[0142] Knowledge retrieval refers to retrieving knowledge tuples related to the input text from a conceptual knowledge graph based on knowledge alignment results, and then representing these knowledge tuples in a structured manner. Structured knowledge is easier to inject into the initial model and allows the initial model to better understand and utilize the knowledge.

[0143] Knowledge injection refers to injecting retrieved and structured knowledge into the input of an initial model using methods such as text enhancement or embedding fusion. For example, relevant knowledge descriptions can be added to the original input text, or the embedding vectors of knowledge can be fused with the embedding vectors of the text, enabling the initial model to utilize domain knowledge when processing the input.

[0144] Knowledge simplification and purification refers to using conceptual knowledge graphs to simplify the representation of knowledge, remove unnecessary complex information and noise, and retain the core knowledge that is useful to the initial model, making it easier for the initial model to learn and utilize knowledge in the field of power semiconductor devices.

[0145] Model training refers to training an initial model (baseline model) using a domain dataset. During training, processed knowledge is injected into the initial model, allowing it to learn the relationship between domain knowledge and the input text, and adjusting the initial model's parameters to adapt to the requirements of the domain task.

[0146] Model validation refers to verifying the effectiveness of knowledge injection through ablation experiments, i.e., comparing the performance of the initial model with and without knowledge injection. Simultaneously, it evaluates the performance and accuracy of the initial model in power semiconductor device characterization data analysis tasks, such as whether the initial model accurately analyzes relevant data and whether its answers to questions conform to domain knowledge. Based on the validation results, the initial model and the knowledge injection process are further optimized.

[0147] For example, prompt word engineering can guide the initial model to make reasonable inferences in the field of power semiconductor devices. Prompt word engineering includes the design, testing, and iteration of prompt words to optimize the specific instructions or questions the initial model responds to. First, when designing prompt words, the initial model is required to incorporate knowledge of the field related to power semiconductor devices; for example, it may be required to analyze XRD data and explain the impact of lattice parameters on device performance. Then, testing is conducted to observe whether the output of the initial model meets expectations, evaluating its accuracy and completeness. Based on the test results, the prompt words are iteratively optimized; for example, by refining the task description, adding background knowledge, or adjusting the expression of instructions, to improve the professionalism and accuracy of the initial model's output. Finally, the validated initial model is determined as the target model.

[0148] Furthermore, role-playing and step-by-step guidance methods can be used to allow the target model to analyze data from the perspective of a specific expert, or to break down complex tasks into sequential steps to gradually guide the model's reasoning. Cue words combine multimodal data (such as spectral images, electrical measurement curves, and chart data) with textual data for joint analysis.

[0149] For example, when inputting prompts, if the requirement is to analyze device performance, the prompts can guide the initial model to first analyze the overall morphology of the device, then analyze the grain size, then analyze the surface flatness of the thin film, the uniformity of the grains, etc., thus breaking down a complex task into multiple tasks through prompts.

[0150] Step S404: Input various characterization data, current fabrication parameters and prompt words into the target model for analysis and optimization to obtain the target fabrication parameters for the power semiconductor device.

[0151] Please see details Figure 3 Step S303 of the illustrated embodiment will not be described again here.

[0152] In this embodiment, the target model can deeply interpret the features in the characterization data based on information in the knowledge base, uncover the intrinsic connections, make accurate analyses, deduce possible physical mechanisms, and generate interpretable analysis reports. This helps researchers better understand the performance and state of power semiconductor devices and provides guidance for subsequent optimization schemes for power semiconductor devices. This embodiment simplifies the large language model to determine the target model, which can reduce the amount of data and achieve efficient and real-time analysis of power semiconductor device characterization data.

[0153] The following detailed description, with reference to the accompanying drawings, outlines the process for optimizing the fabrication parameters of the power semiconductor device provided by this invention.

[0154] For example, it can be as follows Figure 5 As shown, the first step is to fabricate a power semiconductor device. Specifically, the corresponding process flow can be executed according to the current fabrication parameters, such as wafer cutting, doping, and deposition, to obtain the power semiconductor device.

[0155] After the power semiconductor device is fabricated, it is characterized and analyzed, and various characterization data are collected. These data may include characterization images, electrical performance parameters (such as breakdown voltage and on-resistance), etc.

[0156] Then, the multimodal data is input into the target model for optimization analysis. Specifically, the multimodal data includes various characterization data, prompts, and current preparation parameters. The target model supports data input from various power semiconductor characterization techniques, such as voltage, current, and capacitance values ​​in electrical characteristic tests, such as current-voltage characteristic curves, capacitance (C)-voltage (V) characteristic curves, infrared thermal imaging images, XRD diffraction patterns, SEM and TEM microscope images, etc., covering information on the structure, composition, performance, and other aspects of power semiconductor materials and devices.

[0157] After multimodal data is input into the target model, the target model first preprocesses the representation data. Specifically, the target model performs preprocessing operations such as denoising and dimensionality reduction on various representation data to remove noise interference in the image, retain key information, improve image quality, and provide a better foundation for subsequent analysis.

[0158] Then, the target model undergoes deep learning-assisted analysis. Based on the characterization tasks and image characteristics of different power semiconductor devices, the parameters of the deep learning model for segmentation and feature extraction are adjusted to accurately extract key features from the image, providing more accurate data support for further analysis.

[0159] Next, the target model performs multimodal data fusion. Specifically, the target model integrates representational data from different modalities (such as images, text, and tables). Features are first extracted from each modality separately, and then these feature vectors are concatenated or fused using methods such as weighted averaging. This effectively reduces data dimensionality, improves processing efficiency, and yields more comprehensive and accurate information. Multimodal data fusion can fully leverage the advantages of various data sources, improving the understanding and prediction capabilities of power semiconductor device performance and status.

[0160] Subsequently, the target model performs data processing and analysis. Specifically, the target model processes and integrates power semiconductor characterization data to generate a comprehensive analysis report and optimization results for fabrication parameters.

[0161] Finally, the target model outputs multimodal results, including analysis results and target preparation parameters. This invention supports various output formats, including but not limited to image annotation, data analysis reports, physical mechanism derivation, and chart generation. Users can choose the appropriate output format according to their actual needs to improve the efficiency of data understanding and utilization.

[0162] After determining the target fabrication parameters, the fabrication parameters of the power semiconductor device can be adjusted according to the target fabrication parameters, which can accelerate the research and development and manufacturing process of power semiconductors. The mechanism from output feedback to fabrication ensures that the analysis results can be immediately applied to the optimization of the fabrication process.

[0163] The advantages of the power semiconductor device fabrication parameter optimization method provided by this invention are mainly reflected in several aspects. Regarding efficient deployment and cost reduction, by leveraging quantization pruning and knowledge distillation techniques, large models are successfully deployed efficiently on local GPUs, significantly reducing hardware investment costs and deployment time. In terms of real-time optimization and improved R&D efficiency, this invention constructs a closed-loop feedback loop from model prediction to device fabrication and employs reinforcement learning strategies to achieve real-time and accurate optimization of fabrication parameters, significantly shortening the R&D and manufacturing cycle of power semiconductors and improving overall production efficiency.

[0164] Furthermore, this invention demonstrates a deep understanding of physics, integrating knowledge from semiconductor physics, device physics, and electrical principles to enhance the model's ability to comprehend the physical characteristics of power semiconductor devices. Simultaneously, it introduces a user input prompt function, using prompt engineering to guide the model in customized analysis and optimization, fully meeting the personalized needs of different users and significantly enhancing the model's flexibility and practicality in real-world applications. Moreover, this invention incorporates reinforcement learning, employing REINFORCE++ and PPO algorithms to effectively improve the model's overall performance in complex optimization tasks. By designing a reward mechanism and policy optimization process, and integrating large language models with reinforcement learning techniques, a closed-loop feedback loop is constructed from model prediction to device fabrication. This enables real-time guidance of fabrication parameter optimization based on representation results, achieving real-time data analysis and fabrication parameter optimization prediction, accelerating the R&D and manufacturing process of power semiconductors, and improving R&D and manufacturing efficiency. Furthermore, the model exhibits strong generalization capabilities, easily adapting to continuous changes in device structures and processes, thereby reducing potential additional costs due to process changes.

[0165] This embodiment also provides a device for optimizing the fabrication parameters of a power semiconductor device. This device is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0166] This embodiment provides a device for optimizing the fabrication parameters of power semiconductor devices, such as... Figure 6 As shown, it includes:

[0167] The first acquisition module 601 is used to acquire various characterization data and current fabrication parameters of the power semiconductor device. The characterization data refers to data reflecting various characteristics and performance of the power semiconductor device, and the current fabrication parameters are the process parameters used to fabricate the power semiconductor device.

[0168] The second acquisition module 602 is used to acquire prompt words, wherein the prompt words are used to indicate the direction of the target model's analysis of the representation data and to indicate the direction of optimization of the current preparation parameters. The target model is a large language model that incorporates reinforcement learning algorithms.

[0169] The analysis and optimization module 603 is used to input various characterization data, current fabrication parameters and prompt words into the target model for analysis and optimization to obtain the target fabrication parameters of the power semiconductor device. The target fabrication parameters are the predicted process parameters that enable the power semiconductor device to achieve optimal performance in the optimization direction.

[0170] In some optional implementations, the analysis and optimization module 603 includes:

[0171] The analysis unit is used to determine the analysis results based on multiple representation data and prompt words. The analysis results are the results generated by the target model after analyzing multiple representation data based on prompt words.

[0172] The optimization unit is used to optimize the current preparation parameters using reinforcement learning based on the analysis results, so as to obtain the target preparation parameters.

[0173] In some optional implementations, the analysis unit includes:

[0174] The generation sub-unit is used to generate preliminary analysis results and annotation information based on various representation data and prompt words;

[0175] Extracting sub-units is used to extract features from preliminary analysis results and characterization data with labeled information, resulting in multiple feature vectors;

[0176] The integration subunit is used to integrate multiple feature vectors to obtain the analysis results.

[0177] In some alternative implementations, the target model is a large language model enhanced with reinforcement learning algorithms and domain knowledge related to power semiconductor devices. Cue words are also used to indicate whether the target model needs to incorporate multidisciplinary theoretical knowledge to interpret the analysis results. The integration sub-units include:

[0178] The interpretation subunit is used to interpret and derive the analysis results based on multidisciplinary theoretical knowledge when the prompt indicates that interpretation is required, thereby generating interpretable analysis results for power semiconductor devices.

[0179] In some optional implementations, the analysis unit further includes:

[0180] The preprocessing subunit is used to preprocess various types of characterization data to obtain various types of preprocessed characterization data, wherein the preprocessing includes at least one of denoising and dimensionality reduction;

[0181] The generated subunits include:

[0182] The processing subunit is used to generate preliminary analysis results and annotation information based on various preprocessed characterization data and prompt words.

[0183] In some alternative implementations, after obtaining the target fabrication parameters for the power semiconductor device, the method further includes:

[0184] Analysis results of output power semiconductor devices.

[0185] In some alternative embodiments, the apparatus further includes:

[0186] Create a module to generate a target model based on the large language model.

[0187] In some alternative implementations, the creation module includes:

[0188] The processing unit is used to quantize, prune, and distill knowledge from the large language model to obtain a simplified large language model.

[0189] An introduction unit is used to introduce reinforcement learning algorithms into a simplified large language model to obtain an initial model;

[0190] The building unit is used to construct a concept knowledge graph based on a database, wherein the concepts in the concept knowledge graph are concepts related to the field of power semiconductor devices;

[0191] The acquisition unit is used to acquire the domain dataset, wherein the domain dataset is a dataset related to the domain of power semiconductor devices;

[0192] The training unit is used to train the initial model based on the domain dataset and concept knowledge graph, and the trained initial model is determined as the target model.

[0193] In some alternative implementations, the various characterization data include at least two of the following: voltage, current, capacitance, current-voltage characteristic curve, capacitance-voltage characteristic curve, infrared thermal imaging data, power semiconductor device data acquired by X-ray diffraction, power semiconductor device data acquired by scanning electron microscopy, power semiconductor device data acquired by X-ray photoelectron spectroscopy, and power semiconductor device data acquired by transmission electron microscopy.

[0194] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0195] In this embodiment, the device for optimizing the fabrication parameters of the power semiconductor device is presented in the form of a functional unit. Here, a unit refers to an application-specific integrated circuit (ASIC) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0196] This invention also provides a computer device having the above-described features. Figure 6 The device shown is a parameter optimization apparatus for the fabrication of power semiconductor devices.

[0197] Please see Figure 7 , Figure 7This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7 As shown, the computer device includes one or more processors 710, memory 720, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take the 710 processor as an example.

[0198] The processor 710 may be a central processing unit, a network processor, or a combination thereof. The processor 710 may further include a hardware chip. This hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0199] The memory 720 stores instructions executable by at least one processor 710 to cause the at least one processor 710 to perform the method shown in the above embodiments.

[0200] The memory 720 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 720 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 720 may optionally include memory remotely located relative to the processor 710, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0201] The memory 720 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 720 may also include a combination of the above types of memory.

[0202] The computer device also includes an input device 730 and an output device 740. The processor 710, memory 720, input device 730, and output device 740 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0203] Input device 730 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 740 may include display devices, auxiliary lighting devices (e.g., power semiconductor devices), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, power semiconductor devices, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0204] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0205] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0206] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0207] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0208] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A method for optimizing the fabrication parameters of a power semiconductor device, characterized in that, The method includes: The process involves acquiring various characterization data and current fabrication parameters for a power semiconductor device. The characterization data refers to data reflecting various characteristics and performance of the power semiconductor device, and the current fabrication parameters are the process parameters used to fabricate the power semiconductor device. Obtain prompt words, wherein the prompt words are used to indicate the direction of the target model's analysis of the representation data and to indicate the direction of optimization of the current preparation parameters, and the target model is a large language model incorporating reinforcement learning algorithms; The various characterization data, the current fabrication parameters, and the prompt words are input into the target model for analysis and optimization to obtain the target fabrication parameters of the power semiconductor device. The target fabrication parameters are predicted process parameters that will optimize the performance of the power semiconductor device in the optimization direction.

2. The method according to claim 1, characterized in that, The step of inputting the various characterization data, the current fabrication parameters, and the prompt words into the target model for analysis and optimization to obtain the target fabrication parameters of the power semiconductor device includes: Based on the various representation data and the prompt words, the analysis results are determined, wherein the analysis results are the results generated by the target model after analyzing the various representation data based on the prompt words; Based on the analysis results, the current preparation parameters are optimized using reinforcement learning to obtain the target preparation parameters.

3. The method according to claim 2, characterized in that, The step of determining the analysis results based on the various characterization data and the prompt words includes: Based on the various characterization data and the prompt words, preliminary analysis results and annotation information are generated; Feature extraction is performed on the preliminary analysis results and the characterization data with the labeled information to obtain multiple feature vectors; The analysis results are obtained by integrating the multiple feature vectors.

4. The method according to claim 3, characterized in that, The target model is a large language model enhanced with reinforcement learning algorithms and domain knowledge related to the power semiconductor device. The prompt words also indicate whether the target model needs to incorporate multidisciplinary theoretical knowledge to interpret the analysis results. The integration of the multiple feature vectors to obtain the analysis results includes: When the prompt indicates that an explanation requires the application of multidisciplinary theoretical knowledge, the analysis results are explained and deduced based on multidisciplinary theoretical knowledge to generate interpretable analysis results for the power semiconductor device.

5. The method according to claim 3, characterized in that, Before generating preliminary analysis results and annotation information based on the various characterization data and the prompt words, the method further includes: The various characterization data are preprocessed to obtain various preprocessed characterization data, wherein the preprocessing includes at least one of denoising and dimensionality reduction; Based on the various characterization data and the prompt words, preliminary analysis results and annotation information are generated, including: Based on various preprocessed characterization data and the prompt words, the preliminary analysis results and the annotation information are generated.

6. The method according to any one of claims 2 to 5, characterized in that, After obtaining the target fabrication parameters of the power semiconductor device, the method further includes: Output the analysis results of the power semiconductor device.

7. The method according to any one of claims 1 to 5, characterized in that, Before analyzing and optimizing the various characterization data, the current fabrication parameters, and the prompt words into the target model to obtain the target fabrication parameters of the power semiconductor device, the method further includes: Based on the large language model, the target model is created.

8. The method according to claim 7, characterized in that, The step of creating the target model based on the large language model includes: The large language model is quantized, pruned, and knowledge distilled to obtain a simplified large language model. A reinforcement learning algorithm is introduced into the simplified large language model to obtain an initial model; Based on the database, a concept knowledge graph is constructed, wherein the concepts in the concept knowledge graph are concepts related to the power semiconductor device. Obtain a domain dataset, wherein the domain dataset is a dataset of the domain related to the power semiconductor device; The initial model is trained based on the domain dataset and the concept knowledge graph, and the trained initial model is determined as the target model.

9. The method according to any one of claims 1 to 5, characterized in that, The various characterization data include at least two of the following: voltage, current, capacitance, current-voltage characteristic curve, capacitance-voltage characteristic curve, infrared thermal imaging data, data of the power semiconductor device acquired by an X-ray diffractometer, data of the power semiconductor device acquired by a scanning electron microscope, data of the power semiconductor device acquired by X-ray photoelectron spectroscopy, and data of the power semiconductor device acquired by a transmission electron microscope.

10. A device for optimizing the fabrication parameters of a power semiconductor device, characterized in that, The device includes: The first acquisition module is used to acquire various characterization data and current fabrication parameters of the power semiconductor device. The characterization data refers to data reflecting various characteristics and performance of the power semiconductor device, and the current fabrication parameters are the process parameters used to fabricate the power semiconductor device. The second acquisition module is used to acquire prompt words, wherein the prompt words are used to indicate the direction of the target model's analysis of the representation data and to indicate the optimization direction of the current preparation parameters, and the target model is a large language model that incorporates reinforcement learning algorithms; The analysis and optimization module is used to analyze and optimize the various characterization data, the current fabrication parameters, and the prompt words into the target model to obtain the target fabrication parameters of the power semiconductor device. The target fabrication parameters are predicted process parameters that will enable the power semiconductor device to achieve optimal performance in the optimization direction.

11. A computer device, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the computer instructions to perform the method for optimizing the fabrication parameters of the power semiconductor device according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the method for optimizing the fabrication parameters of the power semiconductor device according to any one of claims 1 to 9.

13. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute the method for optimizing the fabrication parameters of the power semiconductor device according to any one of claims 1 to 9.

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