Preparation method of power semiconductor module

Abstract

According to the preparation method of the power semiconductor module provided by the invention, compared with a traditional ceramic substrate, remarkable thinning and heat dissipation performance improvement of the module are realized. The preparation method of the power semiconductor module comprises the following steps: obtaining a metal substrate, and carrying out pretreatment on the surface of the metal substrate; specific sputtering parameters are set, and a thin film dielectric layer is formed on the surface of the pretreated metal substrate through sputtering based on the specific sputtering parameters; wherein the specific sputtering parameters comprise the substrate temperature of 500-580 DEG C, the nitrogen flow of 25-35 sccm, and the flow ratio of nitrogen to air of 1: 3-1: 5; the thickness of the thin film dielectric layer is 3-6 [mu] m; a metal material of a preformed circuit is brazed to the upper surface of the thin film dielectric layer to form a circuit; and packaging after installing crystal grains on the formed circuit.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device fabrication, and more particularly to a method for fabricating a power semiconductor module. Background Technology

[0002] Power semiconductor modules are widely used in new energy, rail transportation, and industrial frequency conversion, among other fields. One of their core components is the insulating circuit substrate (such as DCB and AMB ceramic substrates) that carries and interconnects the chips. Traditional AMB substrates use silicon nitride (Si3N4) or alumina (Al2O3) ceramic as the insulating layer. While this provides high reliability, the ceramic layer thickness is typically 0.2-0.6 mm, limiting further miniaturization and reduction of thermal resistance. Furthermore, the bonding between the ceramic and copper layers relies on active metal brazing, a process involving high temperature and pressure, resulting in high manufacturing costs and susceptibility to ceramic cracking.

[0003] In pursuit of thinner dielectric layers, some researchers have attempted to deposit aluminum nitride (AlN) or aluminum oxide thin films on metal substrates using physical vapor deposition (PVD). However, these methods generally result in AlN films that are mostly amorphous or randomly oriented with poor crystallinity, leading to thermal conductivity far below theoretical values ​​(typically <100 W / m·K), which fails to meet the heat dissipation requirements of high-power devices.

[0004] Therefore, there is an urgent need to develop a novel dielectric layer structure and its manufacturing method that combines ultra-thin thickness, ultra-high thermal conductivity, excellent insulation strength and high reliable bonding strength, in order to break through the performance bottleneck of traditional ceramic substrates. Summary of the Invention

[0005] This invention provides a method for fabricating a power semiconductor module. Compared with traditional ceramic substrates, this method achieves significant thinning of the module and improved heat dissipation performance.

[0006] In a first aspect, the present invention provides a method for fabricating a power semiconductor module, comprising:

[0007] Obtain a metal substrate and perform pretreatment on the surface of the metal substrate;

[0008] Specific sputtering parameters are set, and a thin film dielectric layer is sputtered onto the surface of the pretreated metal substrate based on the specific sputtering parameters; wherein, the specific sputtering parameters include: substrate temperature of 500-580℃, nitrogen flow rate of 25-35 sccm, and nitrogen to air flow ratio of 1:3-1:5; the thickness of the thin film dielectric layer is 3-6 μm;

[0009] The metal material of the pre-formed circuit is brazed to the upper surface of the thin film dielectric layer to form a circuit;

[0010] After the die is mounted on the formed circuit, it is packaged.

[0011] Optionally, the thin film dielectric layer is an aluminum nitride thin film; and / or, the thermal conductivity of the thin film dielectric layer is 170-190 W / m·K.

[0012] Optionally, in the process of sputtering a thin film dielectric layer on the surface of the pretreated metal substrate based on the specific sputtering parameters, the method further includes: monitoring the orientation growth of the thin film dielectric layer in real time by X-ray diffraction.

[0013] Optionally, the orientation ratio of the X-ray diffraction of the thin film dielectric layer is I(002) / I(100) ≥ 2.5, and the oxygen content is ≤ 2 at.%.

[0014] Optionally, the step of brazing the metal material of the preformed circuit to the upper surface of the thin film dielectric layer includes: brazing the thick copper foil of the preformed circuit to the upper surface of the thin film dielectric layer using a Ti-Cu-Ag active solder alloy.

[0015] Optionally, the brazing temperature is set to 920-940℃ and held at that temperature for 50-60 minutes under a nitrogen protective atmosphere.

[0016] Optionally, after brazing, a TiN / TiAlxNy reaction layer with a thickness of 50-200 nm is formed at the contact surface between the Ti-Cu-Ag active solder alloy layer and the thin film dielectric layer.

[0017] Optionally, the Ti content of the Ti-Cu-Ag active solder alloy is 8-12 at.%; the total composition of Cu and Ag is 100 at.%.

[0018] Optionally, the pretreatment of the metal substrate surface includes roughening treatment and cleaning and deoxidation treatment.

[0019] Optionally, the roughening treatment makes the surface roughness of the metal substrate reach 0.8-1.5 μm.

[0020] In a second aspect, the present invention provides a power semiconductor module, which is prepared by the above-described preparation method, the power semiconductor module comprising:

[0021] metal substrate;

[0022] A thin-film dielectric layer is disposed on the surface of the metal substrate; the thickness of the thin-film dielectric layer is 3–6 μm.

[0023] The circuit is disposed on the upper surface of the thin-film dielectric layer.

[0024] The die is mounted on the circuit.

[0025] An encapsulation layer surrounds the metal substrate, the thin-film dielectric layer, the circuit, and the die.

[0026] As can be seen from the above technical solutions, the present invention has the following advantages:

[0027] This invention provides a method for fabricating a power semiconductor module. The method involves obtaining a metal substrate and pre-treating its surface; setting specific sputtering parameters and sputtering a thin-film dielectric layer onto the pre-treated metal substrate surface based on these parameters; wherein the specific sputtering parameters include: a substrate temperature of 500–580°C, a nitrogen flow rate of 25–35 sccm, and a nitrogen-to-air flow ratio of 1:3–1:5; the thickness of the thin-film dielectric layer is 3–6 μm; the metal material of a pre-formed circuit is brazed to the upper surface of the thin-film dielectric layer; and after mounting a die on the formed circuit, it is packaged. This method achieves a reduction in the thickness of the power semiconductor module, significantly reducing interface thermal resistance, improving heat dissipation path efficiency compared to traditional ceramic solutions, and reducing weight and production costs. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic flowchart illustrating a method for fabricating a power semiconductor module according to an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of the structure of a power semiconductor module prepared by a method for preparing a power semiconductor module according to an embodiment of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of this disclosure, and to fully understand and implement the process of how this disclosure applies technical means to solve technical problems and achieve corresponding technical effects, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. The embodiments of this disclosure and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort should fall within the protection scope of this disclosure.

[0032] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0033] Example 1:

[0034] This embodiment provides a method for fabricating a power semiconductor module. The method employs a specific sputtering process to deposit a highly crystalline, oriented AlN thin film with a thickness of approximately 3-6 μm on a copper substrate. This film possesses high thermal conductivity (approximately 170-190 W / m·K, depending on deposition conditions), low oxygen content (≤2 at.%), and excellent dielectric strength (>400 V / μm), and directly serves as the bonding interface for thick copper lines in the AMB (Ampere Block). Compared to traditional ceramic substrates, this approach achieves significant module thinning and improved heat dissipation performance. Specific implementation details are as follows.

[0035] AMB (Active Metal Brazing) is an advanced ceramic-to-metal bonding technology. Compared to traditional direct copper bonding (DBC) technology, AMB has significant advantages, especially suitable for high-power, high-reliability applications. The method provided in this invention inherits the core advantages of traditional AMB technology: it uses Ti-Cu-Ag active solder (Ti is an active metal) to form a TiN / TiAlxNy reaction layer through a chemical reaction at high temperatures (920-940℃), thereby achieving a strong and reliable bond between thick copper circuitry and the aluminum nitride (AlN) thin-film dielectric layer. However, it also represents a revolution in traditional AMB technology: traditional AMB targets relatively thick (a few tenths of a millimeter) sintered ceramic sheets, while this invention targets extremely thin (a few micrometers) sputtered aluminum nitride films. This allows power semiconductor modules fabricated using this method to be thinner, with shorter heat dissipation paths and superior performance.

[0036] Figure 1 This is a schematic flowchart illustrating a method for fabricating a power semiconductor module according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a power semiconductor module prepared by a method for preparing a power semiconductor module according to an embodiment of the present invention.

[0037] refer to Figure 1 and Figure 2 As shown, the method for fabricating the power semiconductor module includes:

[0038] Step 01: Obtain a metal substrate 100 and perform pretreatment on the surface of the metal substrate 100.

[0039] In one optional embodiment, the metal substrate 100 is a copper-based thermally conductive carrier plate; the specific material of the metal substrate 100 can be selected according to the needs of the product, and the present invention does not limit it.

[0040] In one alternative embodiment, the thickness of the metal substrate 100 is 0.3-1.2 mm.

[0041] It is understood that the pretreatment of the surface of the metal substrate 100 includes roughening treatment and cleaning and deoxidation treatment. Optionally, the roughening treatment can make the surface roughness of the metal substrate 100 reach 0.8–1.5 μm.

[0042] Step 02: Set specific sputtering parameters, and based on the specific sputtering parameters, sputter a thin film dielectric layer 200 on the surface of the pretreated metal substrate 100 to form a thin film dielectric layer 200; wherein, the specific sputtering parameters include: substrate temperature of 500–580℃, nitrogen flow rate of 25–35 sccm, nitrogen to air flow ratio of 1:3–1:5; and the thickness of the thin film dielectric layer 200 is 3–6 μm.

[0043] In an optional embodiment, the thin film dielectric layer 200 is an aluminum nitride thin film.

[0044] In an alternative embodiment, the thermal conductivity of the thin-film dielectric layer 200 is 170–190 W / m·K.

[0045] Specifically, this can be understood as meaning that only under the specific sputtering parameters provided by this invention can a relatively thin thin-film dielectric layer 200 be formed, that is, the thickness of the thin-film dielectric layer 200 can be controlled between 3 and 6 μm. These specific sputtering parameters are: substrate temperature of 500–580°C, nitrogen flow rate of 25–35 sccm, and nitrogen to air flow ratio of 1:3–1:5. These specific sputtering parameters were obtained by the inventors of this application through extensive experimental research.

[0046] Under these specific sputtering parameters, the thermal conductivity of the resulting thin-film dielectric layer 200 is 170–190 W / m·K. Optionally, the thin-film dielectric layer 200 is an aluminum nitride thin film.

[0047] Furthermore, in the process of sputtering a thin film dielectric layer 200 on the surface of the pretreated metal substrate 100 based on the specific sputtering parameters, the method further includes: monitoring the orientation growth of the thin film dielectric layer 200 in real time by X-ray diffraction, thereby ensuring that the orientation ratio I(002) / I(100) of the X-ray diffraction of the thin film dielectric layer 200 is ≥2.5 and the oxygen content is ≤2 at.%.

[0048] X-ray diffraction (XRD) is a powerful experimental technique used to interpret the internal structure of materials by analyzing the "diffraction pattern" produced when X-rays interact with regularly arranged atoms within a crystal. XRD allows for real-time monitoring of the deposition process, thereby monitoring the growth of the thin film and ensuring it is growing with a strong (002) orientation. After preparation, XRD patterns demonstrate the acquisition of highly oriented, high-quality AlN films, and these patterns are linked to the film's high thermal conductivity, a key advantage.

[0049] (002) and (100) are Miller indices, used to identify atomic planes in different directions within a crystal. They refer to the "coordinates" of the atomic arrangement direction inside the crystal. In materials like aluminum nitride (AlN), the atoms (Al and N atoms) inside are not randomly stacked, but arranged periodically in three-dimensional space according to a very strict and regular geometric pattern, forming a "space lattice". This structure is called a crystal. We can imagine cutting this lattice with a series of parallel, equally spaced planes, which will pass through a series of atoms. These planes are called crystal planes. Due to the symmetry of the atomic arrangement, there are many crystal planes in different directions. To distinguish these crystal planes in different directions, scientists use a set of integers (h, k, l) to name them, which are called Miller indices. (100) crystal plane: usually represents the family of planes perpendicular to the a-axis. (002) crystal plane: usually represents the family of planes perpendicular to the c-axis. This is particularly important for aluminum nitride (AlN), a hexagonal wurtzite structure. AlN is anisotropic, which means that its physical properties (such as thermal conductivity and electrical conductivity) are different in different directions. Its c-axis direction (i.e., the

[001] direction, corresponding to the normal direction of the (002) crystal plane) is the direction with the highest thermal conductivity.

[0050] In X-ray diffraction (XRD) experiments, crystal planes with different orientations produce diffraction peaks at different angles. The intensity (I) of a peak reflects how many crystal grains have that crystal plane that exactly satisfies the diffraction condition. I(002) represents the contribution intensity of the (002) crystal plane (i.e., the c-axis direction) to the diffraction signal among all crystal grains. I(100) represents the contribution intensity of the (100) crystal plane (i.e., the a-axis direction) to the diffraction signal among all crystal grains. The ratio I(002) / I(100)≥2.5 means: strong orientation growth (preferred orientation): This means that in AlN thin films grown by sputtering, the vast majority of small crystals (grains) are like "neatly arranged soldiers," with their c-axis highly consistent and perpendicular to the copper substrate surface. High crystallinity: This ratio will be close to 1 for randomly oriented polycrystalline thin films (i.e., grains with random orientations). A ratio much greater than 1 indicates that the thin film not only has consistent orientation but also very good crystallinity and few defects. Direct evidence of high thermal conductivity: As mentioned earlier, heat conducts fastest along the c-axis in AlN crystals. In your thin film, almost all of the c-axis is perpendicular to the substrate, meaning that the direction of heat flow from the upper grains down to the copper substrate for heat dissipation is precisely the direction of highest thermal conductivity for each AlN grain. This is the fundamental guarantee for achieving a near-theoretical thermal conductivity of 170-190 W / m·K. Therefore, in this patent, the characteristic of "XRD orientation ratio I(002) / I(100) ≥ 2.5" is a quantitative and measurable key indicator.

[0051] Step 03: Brazing the metal material of the pre-formed circuit to the upper surface of the thin film dielectric layer 200 to form a circuit.

[0052] Specifically, this can be understood as brazing the thick copper foil of the pre-formed circuit to the upper surface of the thin-film dielectric layer 200 using a Ti-Cu-Ag active solder alloy. Optionally, during brazing, the brazing temperature is set to 920–940℃, and the temperature is maintained for 50–60 minutes under a nitrogen protective atmosphere. The Ti content of the Ti-Cu-Ag active solder alloy is 8–12 at.%; the Cu to Ag ratio must ensure a total composition of 100 at.%.

[0053] In addition to the above process, a TiN / TiAlxNy reaction layer is formed at the contact surface between the Ti–Cu–Ag active solder alloy layer and the thin film dielectric layer 200 after brazing. Optionally, the thickness of the TiN / TiAlxNy reaction layer is 50–200 nm.

[0054] The metal material of the preformed circuit is brazed to the upper surface of the thin film dielectric layer 200 using AMB (Active Metal Brazing) technology. Specifically, the process steps are as follows: after cleaning and degreasing the thin film dielectric layer 200, the upper surface is roughened to enhance adhesion; an active solder is prepared by mixing active metal powder (such as Ti, Zr, Cr, etc.) with a silver-copper alloy and adding an organic binder to form a printable paste; the paste of active solder is coated onto the upper surface of the thin film dielectric layer 200 to form a circuit pattern using screen printing or stencil printing techniques, and then dried to remove excess solvent; metal materials are stacked on the upper surface of the active solder layer and placed in a hydrogen or vacuum environment and heated to 850-950℃ for brazing, at which time the active solder and the thin film dielectric layer 200 react to form a compound interface layer (such as a TiN / TiAlxNy reaction layer), and the silver-copper alloy forms a conductive circuit; nickel or gold is electroplated on the surface of the brazed device to improve solderability; laser trimming and other process steps can also be performed as needed, but this invention does not limit these steps. The above AMB technology steps can be used to obtain metallized circuits with good conductivity and strong adhesion on the thin film dielectric layer.

[0055] In one alternative embodiment, the brazed metal material is patterned using laser cutting or wet etching processes to form circuit 300, and the line accuracy of the formed circuit 300 is to be ±10μm.

[0056] Step 04: After mounting the die 400 on the formed circuit 300, perform encapsulation. (The encapsulation layer is...) Figure 2 (not shown in the image)

[0057] Specifically, after mounting the die 400 on the formed circuit 300, encapsulation includes processes such as die 400 mounting, wire bonding, and protective coating deposition. Encasing the metal substrate 100, thin-film dielectric layer 200, circuit 300, and die 400 within a packaging layer protects the power semiconductor module. This packaging layer isolates the module from dust, moisture, and oxidation, preventing performance degradation or failure due to mechanical damage or chemical corrosion. The packaged power semiconductor module is then connected to an external cable via soldered terminals to transmit signals.

[0058] The power semiconductor module fabrication method provided in the above embodiments can be applied to the fabrication of multi-chip module (MCM) products.

[0059] The method for fabricating power semiconductor modules provided by this invention has absolute advantages and benefits, as detailed below:

[0060] 1. Structural advantages: The thickness of the thin film dielectric layer 200 can be controlled to only 3–6 μm, so that the overall package thickness is reduced by more than 40% compared with traditional power semiconductor devices; the interface thermal resistance is significantly reduced, and the heat dissipation path efficiency is improved compared with traditional ceramic solutions; the weight is reduced by about 30–40%.

[0061] 2. Performance advantages: The thermal conductivity of the power semiconductor module reaches 170–190 W / m·K, which is 10–20% higher than that of ceramic substrates; the dielectric strength is >400V / μm, and the withstand voltage of 6μm film is about 2.4–3.0kV; the thick copper conductor can carry a current of 300–500A (depending on the line width and heat dissipation conditions); the thermal cycle life is >5000 cycles (-40℃ to +125℃) without obvious delamination.

[0062] 3. Manufacturing advantages: The process flow is simplified by about 60%, enabling automated production; material costs are reduced by about 40-60%; the film thickness, orientation and performance uniformity are high, making it suitable for large-area production.

[0063] The power semiconductor module prepared by the method provided in this invention is suitable for electric vehicle power modules (main drive inverters, DC-DC converters), industrial power conversion (frequency converters, UPS), new energy power generation (photovoltaic, wind power inverters), rail transit traction converters, and aerospace power management systems, and has broad market application prospects.

[0064] Example 2

[0065] This embodiment provides a power semiconductor module, which is prepared using the power semiconductor module preparation method described in Embodiment 1.

[0066] Figure 2 This is a schematic diagram of the structure of a power semiconductor module fabricated using a method for fabricating a power semiconductor module according to an embodiment of the present invention. Figure 2 As shown, the power semiconductor module includes: a metal substrate 100, a thin-film dielectric layer 200, a circuit 300, a die 400, and an encapsulation layer (not shown in the figure). The specific structure is described below.

[0067] Metal substrate 100; optionally, metal substrate 100 is a copper-based thermally conductive carrier plate; wherein the specific material of metal substrate 100 can be selected according to the needs of the product, and the present invention does not limit it.

[0068] A thin-film dielectric layer 200 is disposed on the surface of the metal substrate 100; the thickness of the thin-film dielectric layer 200 is 3–6 μm; optionally, the thin-film dielectric layer 200 is an aluminum nitride thin film; the thermal conductivity of the thin-film dielectric layer 200 is 170–190 W / m·K; the dielectric strength of the thin-film dielectric layer 200 is >400 V / μm. Optionally, the X-ray diffraction orientation ratio I(002) / I(100) of the thin-film dielectric layer 200 is ≥2.5, and the oxygen content is ≤2 at.%.

[0069] Circuit 300 is disposed on the upper surface of the thin-film dielectric layer 200. Optionally, the material of circuit 300 is copper. Optionally, the line accuracy of circuit 300 is ±10μm.

[0070] Die 400 is mounted on the circuit 300;

[0071] An encapsulation layer is wrapped around the metal substrate 100, the thin film dielectric layer 200, the circuit 300 and the die 400.

[0072] In one embodiment, an active solder layer is further included between the thin-film dielectric layer 200 and the circuit 300. Optionally, the active solder layer is a Ti-Cu-Ag active solder. The active solder layer serves as a solder layer to connect the thin-film dielectric layer 200 and the circuit 300.

[0073] In one embodiment, optionally, the Ti content in the Ti–Cu–Ag active solder is 8–12 at.%; the total composition of Cu and Ag is 100 at.%.

[0074] In one embodiment, a reactive bonding layer is formed at the interface between the Ti–Cu–Ag active solder layer and the thin-film dielectric layer 200. Optionally, the reactive bonding layer is a TiN / TiAlxNy reactive layer. Optionally, the thickness of the TiN / TiAlxNy reactive layer is 50–200 nm. The reactive bonding layer enhances the adhesion between the thin-film dielectric layer 200 and the circuit 300.

[0075] In one embodiment, the thickness of the reactive layer bonding is optionally 50–200 nm.

[0076] In one embodiment, the thickness of the metal substrate 100 is optionally 0.3–1.2 mm.

[0077] In one embodiment, the thickness of the circuit 300 is optionally 0.3–0.6 mm.

[0078] In one embodiment, a solder terminal area is also included outside the encapsulation layer. The packaged power semiconductor module is connected to an external cable via the solder terminals to enable signal transmission.

[0079] In one embodiment, the power semiconductor module is a multi-chip module (MCM) product.

[0080] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element limited by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0081] While the embodiments disclosed herein are as described above, the foregoing content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope of this disclosure; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A method for fabricating a power semiconductor module, characterized in that, include: Obtain a metal substrate and perform pretreatment on the surface of the metal substrate; A specific sputtering parameter is set, and a thin film dielectric layer is sputtered on the surface of the pretreated metal substrate based on the specific sputtering parameter; wherein, the specific sputtering parameter includes: substrate temperature of 500–580℃, nitrogen flow rate of 25–35 sccm, nitrogen to air flow ratio of 1:3–1:5; and the thickness of the thin film dielectric layer is 3–6 μm. The metal material of the pre-formed circuit is brazed to the upper surface of the thin film dielectric layer to form a circuit; After the die is mounted on the formed circuit, it is packaged.

2. The method for fabricating a power semiconductor module according to claim 1, characterized in that, The thin-film dielectric layer is an aluminum nitride thin film; and / or, the thermal conductivity of the thin-film dielectric layer is 170–190 W / m·K.

3. The method for fabricating a power semiconductor module according to claim 1, characterized in that, The process of sputtering a thin film dielectric layer on the surface of the pretreated metal substrate based on the specific sputtering parameters also includes: monitoring the orientation growth of the thin film dielectric layer in real time by X-ray diffraction.

4. The method for fabricating a power semiconductor module according to claim 3, characterized in that, The orientation ratio of the X-ray diffraction of the thin film dielectric layer is I(002) / I(100)≥2.5, and the oxygen content is ≤2 at.%.

5. The method for fabricating a power semiconductor module according to claim 1, characterized in that, The step of brazing the metal material of the pre-formed circuit to the upper surface of the thin film dielectric layer includes: brazing the thick copper foil of the pre-formed circuit to the upper surface of the thin film dielectric layer using a Ti–Cu–Ag active solder alloy.

6. The method for fabricating a power semiconductor module according to claim 5, characterized in that, During brazing, set the brazing temperature to 920–940℃ and hold it at that temperature for 50–60 minutes under a nitrogen protective atmosphere.

7. The method for fabricating a power semiconductor module according to claim 5, characterized in that, After brazing, a TiN / TiAlxNy reaction layer with a thickness of 50–200 nm is formed at the contact surface between the Ti–Cu–Ag active solder alloy layer and the thin film dielectric layer.

8. The method for fabricating a power semiconductor module according to claim 5, characterized in that, The Ti-Cu-Ag active solder alloy has a Ti content of 8–12 at.% and a total Cu and Ag composition of 100 at.%.

9. The method for fabricating a power semiconductor module according to claim 1, characterized in that, The pretreatment of the metal substrate surface includes roughening treatment and cleaning and deoxidation treatment.

10. The method for fabricating a power semiconductor module according to claim 9, characterized in that, The roughening treatment brings the surface roughness of the metal substrate to 0.8–1.5 μm.

11. A power semiconductor module, manufactured using the preparation method described in any one of claims 1-10, characterized in that, The power semiconductor module includes: metal substrate; A thin-film dielectric layer is disposed on the surface of the metal substrate; the thickness of the thin-film dielectric layer is 3–6 μm. The circuit is disposed on the upper surface of the thin-film dielectric layer. The die is mounted on the circuit. An encapsulation layer surrounds the metal substrate, the thin-film dielectric layer, the circuit, and the die.

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