Error calibration method and device for analog-to-digital conversion ADC circuit, equipment and storage medium

Abstract

The invention relates to the technical field of computers, in particular to an error calibration method and device for an analog-to-digital conversion ADC circuit, equipment and a storage medium. The method comprises the following steps: acquiring an actual binary bit weight value of each target sampling capacitor in a single-channel analog-to-digital conversion ADC circuit; according to the actual binary bit weight value and the ideal binary bit weight value, determining a weight deviation value of each target sampling capacitor; and storing the weight deviation value so as to calibrate the digital signal output by the single-channel analog-to-digital conversion ADC circuit according to the weight deviation value to obtain a calibrated digital signal. By adopting the scheme, error calibration can be carried out on the ADC circuit, so that the linearity of the ADC circuit is further improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an error calibration method, apparatus, device, and storage medium for an analog-to-digital converter (ADC) circuit. Background Technology

[0002] In the design of analog-to-digital converter (ADC) circuits, analog circuits are highly sensitive to changes in the Physical Verification Test (PVT). Therefore, even with meticulous design during the circuit preparation process, the performance of the ADC circuit may not be ideal in actual testing. To address this issue, digital calibration methods are needed to calibrate the ADC circuit for errors, thereby further improving its linearity. Summary of the Invention

[0003] This disclosure aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, the first objective of this disclosure is to propose an error calibration method for analog-to-digital converter (ADC) circuits to calibrate the ADC circuits and further improve their linearity.

[0005] The second objective of this disclosure is to provide an error calibration device for an analog-to-digital converter (ADC) circuit.

[0006] The third objective of this disclosure is to propose an electronic device.

[0007] The fourth objective of this disclosure is to provide a computer-readable storage medium.

[0008] The fifth objective of this disclosure is to provide a computer program product.

[0009] To achieve the above objectives, a first aspect of this disclosure provides an error calibration method for an analog-to-digital converter (ADC) circuit, comprising:

[0010] Obtain the actual binary bit weight value of each target sampling capacitor in a single-channel analog-to-digital converter (ADC) circuit;

[0011] The weight deviation value of each target sampling capacitor is determined based on the actual binary bit weight value and the ideal binary bit weight value.

[0012] The weight deviation value is stored to calibrate the digital signal output by the single-channel analog-to-digital converter circuit based on the weight deviation value, so as to obtain the calibrated digital signal.

[0013] Optionally, the single-channel analog-to-digital converter (ADC) circuit is a pipelined ADC circuit, which includes multiple cascaded pipeline modules. The step of obtaining the actual binary bit weight value of each target sampling capacitor in the single-channel ADC circuit includes:

[0014] Determine the target pipeline module among the plurality of cascaded pipeline modules, wherein the target pipeline module is not the last stage pipeline module among the plurality of cascaded pipeline modules;

[0015] Based on all pipeline modules following the target pipeline module, determine the actual binary bit weight value of each sampling capacitor in the target pipeline module;

[0016] Based on the target pipeline module and the actual binary bit weight value of each sampling capacitor in the target pipeline module, the actual binary bit weight value of each sampling capacitor in all pipeline modules preceding the target pipeline module is determined step by step from high to low, so as to obtain the actual binary bit weight value of each target sampling capacitor in the single-channel analog-to-digital converter (ADC) circuit. The target sampling capacitor is the sampling capacitor in the target pipeline module and the pipeline modules preceding the target pipeline module.

[0017] Optionally, determining the actual binary bit weight value of each sampling capacitor in the target pipeline module based on all pipeline modules following the target pipeline module includes:

[0018] Based on all pipeline modules following the target pipeline module, quantize the first and second output voltages before and after the transition point corresponding to the highest bit sampling capacitor in the target pipeline module to obtain the first quantized value and the second quantized value.

[0019] Based on the first quantization value and the second quantization value, determine the actual binary bit weight value of the highest-order sampling capacitor in the target pipeline module;

[0020] Based on the actual binary bit weight value of the highest-ranking sampling capacitor in the target pipeline module, the actual binary bit weight value of each capacitor in the target pipeline module is obtained bit by bit from high to low.

[0021] Optionally, the step of determining the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module in descending order of binary bit weight value based on the target pipeline module and the actual binary bit weight value of each sampling capacitor in the target pipeline module includes:

[0022] Based on the target pipeline module, quantize the first and second output voltages before and after the transition point corresponding to the highest bit sampling capacitor in the pipeline module preceding the target pipeline module;

[0023] Based on the actual binary bit weight value of each sampling capacitor in the target pipeline module, the first output voltage and the second output voltage are calibrated to obtain the calibrated first output voltage and the calibrated second output voltage.

[0024] Based on the calibrated first output voltage and the calibrated second output voltage, the actual binary bit weight value of each sampling capacitor in the preceding stage pipeline module of the target pipeline module is determined, so as to determine the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module in descending order.

[0025] Optionally, calibrating the digital signal output by the single-channel analog-to-digital converter circuit according to the weighted deviation value to obtain the calibrated digital signal includes:

[0026] A random disturbance signal is superimposed on the input signal to obtain the superimposed disturbance input signal;

[0027] The superimposed perturbation input signal is input to the single-channel analog-to-digital converter (ADC) circuit to obtain the first digital signal;

[0028] The first digital signal is calibrated according to the weight deviation value to obtain the second digital signal;

[0029] Determine the digital quantity corresponding to the random disturbance signal, and subtract the digital quantity from the second digital signal to obtain the calibrated digital signal.

[0030] Optionally, the step of superimposing a random perturbation signal onto the input signal to obtain a superimposed perturbation input signal includes:

[0031] When the random disturbance signal is a large-amplitude random disturbance signal, the amplitude range corresponding to the large-amplitude random disturbance signal is determined according to the minimum discrimination range of the single-channel analog-to-digital converter circuit.

[0032] Optionally, after obtaining the calibrated digital signal, the method further includes:

[0033] Using a reference channel as a benchmark, determine the offset error and gain error of the single-channel analog-to-digital converter (ADC) circuit relative to the reference channel;

[0034] The calibrated digital signal is calibrated based on the offset error and the gain error.

[0035] To achieve the above objectives, a second aspect of this disclosure provides an error calibration device for an analog-to-digital converter (ADC) circuit, comprising:

[0036] The weight acquisition unit is used to acquire the actual binary bit weight value of each target sampling capacitor in the single-channel analog-to-digital converter (ADC) circuit.

[0037] The deviation acquisition unit is used to determine the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value.

[0038] An error calibration unit is used to store the weight deviation value, and to calibrate the digital signal output by the single-channel analog-to-digital converter circuit according to the weight deviation value to obtain a calibrated digital signal.

[0039] To achieve the above objectives, a third aspect of this disclosure provides an electronic device, including: a processor and a memory communicatively connected to the processor;

[0040] The memory stores instructions that the computer executes;

[0041] The processor executes computer execution instructions stored in memory to implement the method shown in any of the first aspects above.

[0042] To achieve the above objectives, a fourth aspect of this disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method shown in any of the first aspects above.

[0043] To achieve the above objectives, a fifth aspect of this disclosure provides a computer program product including a computer program that, when executed by a processor, implements the method shown in any of the first aspects above.

[0044] In summary, the method, apparatus, device, and storage medium provided in this disclosure acquire the actual binary bit weight value of each target sampling capacitor in a single-channel analog-to-digital converter (ADC) circuit; determine the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value; and store the weight deviation value. Therefore, the digital signal output by the single-channel ADC circuit can be calibrated based on the weight deviation value to obtain a calibrated digital signal, which can improve the linearity of the ADC circuit, and the error itself is relatively small. Secondly, storing only the weight deviation value of the target sampling capacitor occupies less storage space and has lower hardware costs.

[0045] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0046] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0047] Figure 1 A schematic flowchart illustrating an error calibration method for an analog-to-digital converter (ADC) circuit provided in this embodiment of the present disclosure;

[0048] Figure 2 A schematic diagram of a transmission curve with capacitance mismatch provided in an embodiment of this disclosure;

[0049] Figure 3 This is a schematic diagram of a digital output with capacitor mismatch provided in an embodiment of the present disclosure;

[0050] Figure 4 This is a schematic diagram of the structure of a sub-digital-to-analog converter circuit provided in an embodiment of the present disclosure;

[0051] Figure 5 An enlarged schematic diagram of a transmission curve with capacitance mismatch provided in an embodiment of this disclosure;

[0052] Figure 6 This is a schematic diagram of a capacitance calibration process provided in an embodiment of the present disclosure;

[0053] Figure 7 This is a schematic diagram illustrating the injection of a random disturbance signal according to an embodiment of the present disclosure.

[0054] Figure 8 This is a schematic diagram of the structure of an MDAC Dither DAC provided in an embodiment of the present disclosure;

[0055] Figure 9 This is a schematic diagram of the structure of an error calibration device for an analog-to-digital converter (ADC) circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0056] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0057] The present disclosure will now be described in detail with reference to specific embodiments.

[0058] In the first embodiment, such as Figure 1 As shown, Figure 1This is a flowchart illustrating an error calibration method for an analog-to-digital converter (ADC) circuit provided in an embodiment of this disclosure. The method can be implemented using a computer program and can run on a device for error calibration of the ADC circuit. This computer program can be integrated into an application or run as a standalone utility application.

[0059] The error calibration device for the analog-to-digital converter (ADC) circuit can be an electronic device with error calibration function for the ADC circuit.

[0060] For example, the error calibration method for this analog-to-digital converter (ADC) circuit includes the following steps:

[0061] S101, obtain the actual binary bit weight value of each target sampling capacitor in the single-channel analog-to-digital converter circuit;

[0062] It should be noted that the working principle of a single-channel ADC circuit is to convert analog signals into digital signals. This process involves sampling, holding, quantizing, and encoding the input signal. Capacitor mismatch can cause errors in the sampling and quantization processes, thus affecting the output of the single-channel ADC circuit.

[0063] According to some embodiments, Figure 2 This is a schematic diagram of a transmission curve with capacitance mismatch provided in an embodiment of this disclosure. Figure 2 As shown, Vres is the margin output, Vref is the reference voltage, and Vin is the input signal. This single-channel analog-to-digital converter (ADC) circuit has three sampling capacitors, and the output signal has three binary bits, with each sampling capacitor corresponding to one binary bit. At the comparator threshold, capacitor mismatch will cause a deviation in the binary bit weight, and each comparator threshold voltage point corresponds to a different capacitor mismatch. In other words, the error at each transition point is caused by the sampling capacitor corresponding to that transition point. Therefore, if the actual binary bit weights can be obtained and substituted into the digital domain for calculation, a linear digital output can be obtained.

[0064] In some embodiments, the mismatch of some sampling capacitors in a single-channel ADC circuit has a significant impact on the output, while the impact of mismatch of other sampling capacitors can be ignored. Therefore, it is only necessary to measure the actual binary bit weight value corresponding to the sampling capacitor that has a significant impact on the output and substitute it into the digital domain for calculation to obtain a linear digital output. It is not necessary to calculate the actual binary bit weight value of all sampling capacitors, which can reduce the amount of computation.

[0065] S102, determine the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value;

[0066] According to some embodiments, the weight deviation value refers to the deviation of the actual binary bit weight value from the ideal binary bit weight value.

[0067] S103 stores the weight deviation value, and uses the weight deviation value to calibrate the digital signal output by the single-channel analog-to-digital converter circuit to obtain the calibrated digital signal.

[0068] According to some embodiments, Figure 3 This is a schematic diagram of a digital output with capacitor mismatch provided in an embodiment of this disclosure. Figure 3 As shown, by extracting and storing the weight deviation value, it can be substituted into the actual output digital signal to obtain a linear digital output.

[0069] In summary, the method provided in this embodiment obtains the actual binary bit weight value of each target sampling capacitor in a single-channel analog-to-digital converter (ADC) circuit; determines the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value; and stores the weight deviation value. Therefore, the digital signal output by the single-channel ADC circuit can be calibrated based on the weight deviation value to obtain a calibrated digital signal, which can improve the linearity of the ADC circuit and the error itself is small; secondly, storing only the weight deviation value of the target sampling capacitor occupies less storage space and has lower hardware costs.

[0070] This embodiment also provides another error calibration method for analog-to-digital converter (ADC) circuits. This method can be performed by an electronic device.

[0071] For example, the error calibration method for this analog-to-digital converter (ADC) circuit may include the following steps:

[0072] S201, Identify the target pipeline module among multiple cascaded pipeline modules;

[0073] According to some embodiments, a single-channel analog-to-digital converter (ADC) circuit can be, for example, a pipelined single-channel ADC circuit, which includes multiple cascaded pipeline modules.

[0074] It should be noted that in multiple cascaded pipeline modules, the higher the cascade bit depth, the less impact the mismatch of the internal sampling capacitors has on the output. Therefore, only the sampling capacitors in the multiple preceding pipeline modules need to be calibrated.

[0075] In some embodiments, the target pipeline module is the last pipeline module among a plurality of preceding pipeline modules that needs to be calibrated. This target pipeline module is not the last pipeline module among a plurality of cascaded pipeline modules. For example, the target pipeline module could be the second-stage pipeline module in a plurality of 11 cascaded pipeline modules.

[0076] S202, based on all pipeline modules following the target pipeline module, determine the actual binary bit weight value of each sampling capacitor in the target pipeline module;

[0077] According to some embodiments, in multiple cascaded pipeline modules, each pipeline module includes a sub-analog-to-digital converter circuit and a sub-digital-to-analog converter circuit. The sub-analog-to-digital converter circuit can sample the input signal and quantize it into a quantized signal. The sub-digital-to-analog converter circuit can subtract the quantized signal from the input signal to obtain a margin signal, and amplify the margin signal to obtain a margin output signal. The margin output signal can be used as an input signal to the next stage pipeline module.

[0078] To give an example from a scenario, Figure 4 This is a schematic diagram of the structure of a sub-digital-to-analog converter circuit provided in an embodiment of this disclosure. Figure 4 As shown, the sub-digital-to-analog converter circuit includes a first capacitor-flipping switched capacitor module, a second capacitor-flipping switched capacitor module, and an operational amplifier. Both the first and second capacitor-flipping switched capacitor modules include a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, three fifth switches S5, a sixth switch S6, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

[0079] In the first capacitor flip-type switched capacitor module, the first terminal of the first switch S1, the first terminal of the second switch S2, the first terminal of the third switch S3, and the first terminal of the fourth switch S4 are used to receive the positive input signal VIP. In the second capacitor flip-type switched capacitor module, the first terminal of the first switch S1, the first terminal of the second switch S2, the first terminal of the third switch S3, and the first terminal of the fourth switch S4 are used to receive the negative input signal VIM.

[0080] The first terminal of the fifth switch S5 is used to receive three selectable reference signals: Vrefn, Vrefp, and Vcm. The second terminal of the first fifth switch S5 is connected to the second terminal of the second switch S2 and the first terminal of the second capacitor C2. The second terminal of the second fifth switch S5 is connected to the second terminal of the third switch S3 and the first terminal of the third capacitor C3. The second terminal of the third fifth switch S5 is connected to the second terminal of the fourth switch S4 and the first terminal of the fourth capacitor C4.

[0081] The second terminal of the first switch S1 is connected to the first terminal of the first capacitor C1 and the first terminal of the sixth switch S6, respectively.

[0082] In the first capacitor flip-type switched capacitor module, the second terminals of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are connected to the positive input terminal of the operational amplifier AMP. In the second capacitor flip-type switched capacitor module, the second terminals of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are connected to the negative input terminal of the operational amplifier AMP.

[0083] In the first capacitor-flipping switched capacitor module, the connection point between the second terminal of the sixth switch S6 and the negative output terminal of the operational amplifier AMP is the positive output terminal of the sub-digital-to-analog converter circuit. In the second capacitor-flipping switched capacitor module, the connection point between the second terminal of the sixth switch S6 and the positive output terminal of the operational amplifier AMP is the negative output terminal of the sub-digital-to-analog converter circuit.

[0084] According to some embodiments, the following relationship is obtained from the transfer function curve:

[0085]

[0086] in,

[0087] These are the 8 discrimination intervals of this single-channel ADC circuit.

[0088] In some embodiments, the residual amplification function can be achieved simply by connecting the capacitor plates of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 to different reference voltages in the discrimination intervals of different sub-analog-to-digital converter circuits. The decoding logic table is shown in Table (I).

[0089]

[0090]

[0091] Table (1)

[0092] Where D1D2D3 refers to the quantized signals input to the sub-analog-to-digital converter circuit, V 2p V represents the voltage corresponding to the second capacitor C2 in the first capacitor flip-type switched capacitor module. 3p V represents the voltage corresponding to the third capacitor C3 in the first capacitor flip-type switched capacitor module. 4p V represents the voltage corresponding to the fourth capacitor C4 in the first capacitor flip-type switched capacitor module. 2n V is the voltage corresponding to the second capacitor C2. 3nV represents the voltage corresponding to the third capacitor C3 in the second capacitor flip-type switched capacitor module. 4n This is the voltage corresponding to the fourth capacitor C4 in the second capacitor flip-type switched capacitor module.

[0093] In some embodiments, the first capacitor C1 is a feedback capacitor, and the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are sampling capacitors. Capacitor mismatch mainly refers to the mismatch between the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 and the first capacitor C1. Therefore, the mismatch of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can be characterized using the first capacitor C1 as a reference according to the following formula:

[0094] ΔC i =C i -C1, i = 2, 3, 4

[0095] Where C1 is the capacitance value of the first capacitor C1, C i Let ΔC be the capacitance value of the i-th capacitor Ci. i Let be the capacitance mismatch value of the i-th capacitor Ci.

[0096] According to the principle of charge conservation, the positive output voltage Vres,p is:

[0097]

[0098] Among them, C tot The expression is C1+C2+C3+C4.

[0099] Repeating the derivation process described above, we can obtain:

[0100]

[0101] The above equation can be simplified by designing intermediate parameters m1 and m2:

[0102]

[0103]

[0104] Vres = m1 * (VIP - VIM) - m2

[0105] In this equation, m1 is independent of the input signal and will cause a gain error in the output. m2, on the other hand, is related to the input signal; different input values ​​will result in different error values, which will introduce a nonlinear error into the output.

[0106] It should be noted that the transmission curve after mismatch is as follows: Figure 2 As shown, to analyze in detail how capacitor mismatch affects the output, the 000-001 portion of the sub-analog-to-digital converter output can be amplified, such as... Figure 5As shown, it can be observed that when the input equals (-5 / 8)Vref and the quantization signal changes from 000 to 001, only the base plate voltage of the fourth capacitor C4 in the circuit changes. Ideally, the output of the sub-digital-to-analog converter changes from (1 / 2)Vref to (-1 / 2)Vref, and the weight W4 of the fourth capacitor C4 corresponds to a value of 1. When the fourth capacitor C4 is mismatched, when the quantization signal output changes from 000 to 001, the output of the sub-analog-to-digital converter jumps from point a to point b, and the output jump value is W4. That is to say, the error of each jump point is caused by the capacitor corresponding to that jump point.

[0107] In some embodiments, Figure 6 This is a schematic diagram of a capacitance calibration process provided in an embodiment of this disclosure. Figure 6 As shown, when measuring the actual binary bit weight value of the fourth capacitor C4, firstly, as... Figure 6 As shown in (a), the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed, while the three fifth switches S5 and the sixth switch S6 are opened. During the sampling phase, the input is set to (-5 / 8)Vref. Then, as... Figure 6 As shown in (b), during the amplification stage, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are opened, while the three fifth switches S5 and the sixth switch S6 are closed, forcing the quantization signal to "000". At this time, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in the first capacitor flip-type switched capacitor module are connected to Vrefn, and the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in the second capacitor flip-type switched capacitor module are connected to Vrefp. Therefore, we can obtain... Figure 5 The value V of point a in the interval 000 shown res,000 :

[0108]

[0109] Secondly, such as Figure 6 As shown in (c), the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed, while the three fifth switches S5 and the sixth switch S6 are opened. During the sampling phase, the input is set to (-5 / 8)Vref. Finally, as... Figure 6As shown in (d), during the amplification stage, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are opened, while the three fifth switches S5 and the sixth switch S6 are closed, forcing the quantization signal to "001". At this time, the second capacitor C2 and the third capacitor C3 in the first capacitor flip-type switched capacitor module are connected to Vrefn, and the fourth capacitor C4 is connected to Vcm. Thus, we can obtain... Figure 5 The value V of point b in the interval 001 shown res,001 :

[0110]

[0111] Therefore, the mismatch value of the fourth capacitor C4 can be obtained as follows:

[0112]

[0113] Finally, using the capacitance value C1 of the first capacitor C1 as the standard, the actual binary bit weight value W4 corresponding to the fourth capacitor C4 can be obtained as follows:

[0114]

[0115] In other words, we only need to obtain the value V of point a in the interval 000. res,000 And the value V of point b in the interval 001 res,001 Then, the actual binary bit weight value W4 corresponding to the fourth capacitor C4 can be calculated. These two values ​​can be obtained by quantization through the subsequent pipeline module. Therefore, the mismatch in the subsequent pipeline module will affect the quantization result, which requires a specific calibration order. Because it affects the calibration accuracy, the subsequent pipeline module needs to be calibrated first, and then calibrated step by step from the end to the beginning.

[0116] Secondly, when measuring the actual binary bit weight values ​​of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, the measurements can be taken in the order of the fourth capacitor C4, the third capacitor C3, and the second capacitor C2. The true weights of the third capacitor C3 and the second capacitor C2 can be obtained at different jump points (-3 / 8)Vref and (-1 / 8)Vref, respectively.

[0117] In summary, when determining the actual binary bit weight value of each sampling capacitor in the target pipeline module based on all pipeline modules following the target pipeline module, firstly, the first and second output voltages before and after the transition point corresponding to the highest-order sampling capacitor in the target pipeline module can be quantized based on all pipeline modules following the target pipeline module, yielding the first and second quantized values. Next, the actual binary bit weight value of the highest-order sampling capacitor in the target pipeline module can be determined based on the first and second quantized values. Finally, the actual binary bit weight value of each capacitor in the target pipeline module can be obtained bit by bit from high to low based on the actual binary bit weight value of the highest-order sampling capacitor.

[0118] S203, based on the target pipeline module and the actual binary bit weight value of each sampling capacitor in the target pipeline module, determine the actual binary bit weight value of each sampling capacitor in all pipeline modules preceding the target pipeline module in descending order, so as to obtain the actual binary bit weight value of each target sampling capacitor in the single-channel ADC circuit.

[0119] According to some embodiments, the target sampling capacitor is the sampling capacitor in the target pipeline module and the pipeline module preceding the target pipeline module.

[0120] In some embodiments, firstly, based on the target pipeline module, the first and second output voltages before and after the transition point corresponding to the highest-order sampling capacitor in the preceding pipeline module can be quantized. Next, based on the actual binary bit weight value of each sampling capacitor in the target pipeline module, the first and second output voltages can be calibrated to obtain calibrated first and second output voltages. Finally, based on the calibrated first and second output voltages, the actual binary bit weight value of each sampling capacitor in the preceding pipeline module can be determined, thus determining the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module from high to low.

[0121] Taking a scenario as an example, the target pipeline module is a second-stage pipeline module. Each pipeline module includes three sampling capacitors: a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. During capacitor calibration, firstly, the output of the second-stage pipeline module can be quantized using the pipeline modules from the third stage to the last stage, and the actual binary bit weights of the fourth capacitor C4, the third capacitor C3, and the second capacitor C2 in the second-stage pipeline module are obtained bit by bit. Then, based on the second-stage pipeline module and the actual binary bit weights of the fourth capacitor C4, the third capacitor C3, and the second capacitor C2 in the second-stage pipeline module, the actual binary bit weights of the fourth capacitor C4, the third capacitor C3, and the second capacitor C2 in the first-stage pipeline module are obtained.

[0122] S204: Determine the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value, and store the weight deviation value.

[0123] S205, a random disturbance signal is superimposed on the input signal to obtain the input signal after superimposed disturbance;

[0124] It's important to note that dithering can be understood as "tricking" the converter by adding random perturbations, thereby addressing some nonlinear issues. Nonlinearity errors in the transfer function are particularly noticeable in pipelined single-channel ADC circuits. System errors in these circuits lead to nonlinearity in the transfer function, resulting in nonlinear errors in the output. The periodicity of both the quantized output waveform and the error waveform is closely related to the periodicity of the input signal, coherent sampling, and the periodicity of the transfer function. While the non-uniformity of this quantization error noise cannot be improved, its periodicity can be mitigated by adding random perturbation signals.

[0125] According to some embodiments, the random disturbance signal includes small-amplitude random disturbance signals and large-amplitude random disturbance signals.

[0126] In some embodiments, a small-amplitude random perturbation signal can improve the accuracy of a single-channel ADC circuit to some extent. For example, if the input signal 'a' is less than half the least significant bit (LSB) of the single-channel ADC circuit, the single-channel ADC circuit cannot output the correct digital signal corresponding to the input signal 'a'. However, after adding a small-amplitude random perturbation signal, the input signal 'a' will exceed half the LSB. At this time, the single-channel ADC circuit can output a valid digital signal. Furthermore, since the small-amplitude random perturbation signal is approximately white noise and is unrelated to the actual input signal, from a spectral perspective, the added small-amplitude random perturbation signal is simply submerged in the background noise. With the help of some digital filters, the valid digital signal can be extracted.

[0127] Furthermore, for pipelined single-channel ADC circuits, when a small signal is input, the preceding pipeline modules may not reach the quantization threshold, thus only having the function of amplification. The error introduced during the amplification process will be transmitted to the final output, causing nonlinear error. If a Dither signal is added to the input, it will force the sub-analog-to-digital conversion circuits of the preceding pipeline modules to start quantization, that is, the input will randomly enter different discrimination intervals. This randomness will break the fixed error introduced by the original discrimination interval.

[0128] In some embodiments, the effect of large-amplitude random perturbation signals differs from that of small-amplitude random perturbation signals. Small-amplitude random perturbation signals are generally used in low-speed, low-precision single-channel ADC circuits because their LSB is relatively large. In high-precision single-channel ADC circuits, the LSB is smaller, and some internal noise is equivalent to small-amplitude random perturbation signals. The effect of large-amplitude random perturbation signals is to allow the input signal to continuously and randomly cross different discrimination intervals of the transfer function, thereby weakening some errors in the transfer function and improving linearity.

[0129] According to some embodiments, the amplitude range corresponding to a large-amplitude random disturbance signal can be determined based on the minimum discrimination range of a single-channel ADC circuit.

[0130] In some embodiments, the amplitude of the large-amplitude random disturbance signal should be comparable to the size of the minimum discrimination interval of the transfer function. This allows the input signal, after being combined with the large-amplitude random disturbance signal, to randomly cross different intervals of the transfer function, thereby reducing the influence of periodic errors in the transfer function.

[0131] In other words, for a pipelined single-channel ADC circuit, when a large signal is input, the input signal already spans multiple discrimination intervals. However, these interval crossings are not random but closely related to the input signal. Therefore, the nonlinear error between different discrimination intervals will appear periodically with the input signal, generating some fixed harmonics in the frequency spectrum. If the amplitude range of the injected random disturbance signal is only the size of one discrimination interval, its effect will be less significant.

[0132] S206, the input signal after superimposed perturbation is input to the single-channel ADC circuit to obtain the first digital signal;

[0133] S207, calibrate the first digital signal according to the weight deviation value to obtain the second digital signal;

[0134] According to some embodiments, the first digital signal can be added to the corresponding weight deviation value to obtain the second digital signal, thereby eliminating the effects of capacitor mismatch.

[0135] S208, determine the digital quantity corresponding to the random disturbance signal, subtract the digital quantity from the second digital signal to obtain the calibrated digital signal;

[0136] According to some embodiments, the digital quantities corresponding to different random disturbance signals can be iterated in the initial stage, so that the Dither component can be subtracted from the output digital code when using Dither calibration.

[0137] In some embodiments, Figure 7 This is a schematic diagram illustrating the injection of a random disturbance signal according to an embodiment of this disclosure. Figure 7 As shown, in the initial stage, the input of a single-channel ADC circuit can be connected to a common-mode voltage, and the output code of the sub-analog-to-digital converter circuit in the first-stage pipeline module can be controlled to always be the quantized signal in the middle (e.g., Figure 2 011 in Figure 7 The 8th quantization signal in the process indicates that the range of the superimposed random disturbance signal does not exceed the minimum discrimination interval of the sub-analog-to-digital converter circuit in the first-stage pipeline module, and the first-stage sub-pipeline is operating in the middle of the transfer curve.

[0138] When injecting a random perturbation signal into the sub-analog-to-digital converter circuit, a flash perturbation digital-to-analog converter (Flash Dither DAC) with one bit higher than the quantization signal can be used to generate the random perturbation signal. The highest bit of the random perturbation signal is the sign bit. For example, when the quantization signal is 5 bits, the random perturbation signal is 6 bits.

[0139] Since the random disturbance signal injected into the sub-analog-to-digital converter circuit is not directly superimposed on the input signal, the sub-analog-to-digital converter circuit cannot work properly. Therefore, it is necessary to use a sub-analog-to-digital converter circuit with added disturbance amplification function to replace the primary sub-analog-to-digital converter circuit, so as to inject the random disturbance signal into the sub-analog-to-digital converter circuit in a specific way.

[0140] For example, an MDAC Dither DAC can be used to replace the original MDAC. This MDAC Dither DAC can be, for example, a capacitive DAC.

[0141] To give an example from a scenario, Figure 8 This is a schematic diagram of the structure of an MDAC Dither DAC provided in an embodiment of this disclosure. Figure 8 As shown, the quantized signal is 9 bits, and the random perturbation signal is 10 bits, relative to... Figure 4The sub-digital-to-analog converter circuit shown includes a first capacitor-flipping switched capacitor module comprising nine fifth switches S5, nine three-channel switches S7, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, and an eighth switch S8; wherein,

[0142] The first terminals of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, and the thirteenth capacitor C13 are respectively connected to the first terminal of a fifth switch S5. The control terminal of each fifth switch S5 is connected to a 3-channel switch S7. The input terminal of the 3-channel switch S7 is used to receive the first clock signal clk1, the second clock signal clk2, the quantization signal Bits1<9:0>, and the random disturbance signal Bits0<9:0>.

[0143] The first terminal of the fifteenth capacitor C15 is connected to the second terminal of the fifth capacitor C5 and the second terminal of the sixth capacitor C6. The second terminal of the fifteenth capacitor C15 is connected to the second terminal of the seventh capacitor C7, the second terminal of the eighth capacitor C8, the second terminal of the ninth capacitor C9, the second terminal of the tenth capacitor C10, and the first terminal of the sixteenth capacitor C16. The second terminal of the sixteenth capacitor C16 is connected to the second terminal of the eleventh capacitor C11, the second terminal of the twelfth capacitor C12, the second terminal of the thirteenth capacitor C13, the second terminal of the fourteenth capacitor C14, the first terminal of the seventeenth capacitor C17, the positive input terminal of the operational amplifier AMP, and the first terminal of the eighth switch S8. The second terminal of the eighth switch S8 is connected to the first terminal of the eighteenth capacitor C18. The second terminal of the eighteenth capacitor C18 is connected to the negative output terminal of the operational amplifier AMP.

[0144] Among them, the capacitance values ​​of the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eleventh capacitor C11, the fifteenth capacitor C15, and the sixteenth capacitor C16 are Cu; the capacitance values ​​of the eighth capacitor C8 and the twelfth capacitor C12 are 2Cu; the capacitance values ​​of the ninth capacitor C9 and the thirteenth capacitor C13 are 4Cu; and the capacitance values ​​of the tenth capacitor C10 and the fourteenth capacitor C14 are 8Cu.

[0145] Among them, Cu can be, for example, 25fF. The capacitance value of the seventeenth capacitor C17 can be, for example, 6.4pF. The capacitance value of the eighteenth capacitor C18 can be, for example, 0.8pF.

[0146] During the active phase of the second clock signal clk2, the eighth switch S8 is closed.

[0147] It should be noted that, Figure 8 The diagram only shows the circuit structure related to the sub-digital-to-analog converter circuit in the first capacitor flip-type switched capacitor module. For the structure connected to the input signal, please refer to [reference needed]. Figure 4 The circuit shown is for Figure 8 The structure of the first capacitor flip-type switched capacitor module is the same as that of the first capacitor flip-type switched capacitor module.

[0148] In some embodiments, during the initial stage, the MDAC Dither DAC alternately outputs analog values ​​corresponding to 0 and the Flash Dither DAC. When the Flash Dither DAC outputs an analog voltage of 0, each output can continue for multiple cycles, allowing for accumulation and averaging at the end to reduce errors. The entire single-channel ADC circuit outputs only the first-stage quantization value, that is, the quantized signal in the middle, which is output by the single-channel ADC after data alignment. Then, by subtracting the preceding fixed value from the digital code of different random disturbance signals, the digital quantity corresponding to each random disturbance signal can be obtained. Storing these digital quantities allows for the subtraction of the random disturbance signal component during Dither calibration.

[0149] S209, using the reference channel as a reference, determines the offset error and gain error of the single-channel ADC circuit relative to the reference channel;

[0150] It should be noted that the charge injection from the sampling switch in the sampling protection circuit, the offset voltage of the comparator, and the offset voltage of the operational amplifier in the digital-to-analog converter circuit will all introduce offset voltage into the ADC output, causing the common-mode level of the output signal to deviate from the ideal value. Therefore, offset calibration of the ADC circuit is necessary. For a single-channel ADC circuit, the offset error manifests as a fixed deviation of all output values ​​from the ideal value, appearing as a fixed DC component in the frequency domain, and will not affect the harmonic components of the single-channel ADC circuit.

[0151] However, analog-to-digital converter (ADC) circuits are multi-channel ADC circuits, which include multiple single-channel ADC circuits. The single-channel ADC circuits of different channels need to work together. Therefore, the mismatch between channels will limit the accuracy of system-level applications, and the mismatch between multiple channels needs to be calibrated.

[0152] According to some embodiments, the optimal square approximation algorithm can be used for multi-channel offset calibration in the digital domain. Using a reference channel as a benchmark, the offset error and gain error of a single-channel ADC circuit relative to the reference channel are determined. Then, the outputs of each channel are processed to eliminate relative offset and gain mismatches.

[0153] In some embodiments, the calibration model of the single-channel ADC circuit relative to the reference channel is shown in the following equation:

[0154] D i =a i +b i *D ref

[0155] D ic =D ref =(D i -a i ) / b i

[0156] Among them, D i D is the raw digital output of the i-th single-channel ADC circuit. ic D represents the calibrated digital output of the i-th single-channel ADC circuit, where i is a positive integer; ref Digital output for the reference channel; a i b is the offset error of the i-th single-channel ADC circuit relative to the reference channel; i Let be the gain error of the i-th single-channel ADC circuit relative to the reference channel.

[0157] In some embodiments, adjusting the offset and gain errors of the i single-channel ADC circuits to be the same as the reference channel can eliminate the mismatch between the i single-channel ADC circuits. That is, if all single-channel ADC circuits have the same input signal, after eliminating the mismatch between channels, the outputs of all single-channel ADC circuits will be the same as the reference channel. In other words, it is only necessary to calculate the 'a' of the i-th single-channel ADC circuit. i and b i This allows for the calibration of the i-th single-channel ADC circuit.

[0158] According to some embodiments, when calculating a of the i-th single-channel ADC circuit i and b i When the reference channel and the i-th single-channel ADC circuit can be given the same clock signal and input signal, the reference channel and the i-th single-channel ADC circuit will output the converted sequence D respectively. ref <1:N> and D i <1:N>, where N is the number of transformation points, and satisfies D i <n>=a i +b i *D ref <n>.

[0159] In some embodiments, according to the principle of least squares, we can obtain:

[0160]

[0161]

[0162]

[0163] Therefore, we can solve for:

[0164]

[0165]

[0166] S210 calibrates the obtained calibrated digital signal based on the offset error and gain error.

[0167] In summary, the method provided in this embodiment occupies less storage space and has lower hardware costs by storing only the weighted deviation values ​​of the sampling capacitors in the target pipeline module and its preceding pipeline modules, and the error itself is also smaller. Secondly, by determining the weighted deviation values ​​of the sampling capacitors in the target pipeline module and its preceding pipeline modules step by step from high to low, and by obtaining the actual binary bit weight value of each capacitor in the target pipeline module bit by bit from high to low, the accuracy of the weighted deviation value determination can be improved. Furthermore, adding perturbation techniques and multi-channel calibration to perform error calibration on the ADC circuit can further improve the linearity of the ADC circuit.

[0168] To achieve the above embodiments, this disclosure also proposes an error calibration device for an analog-to-digital converter (ADC) circuit.

[0169] like Figure 9 As shown, the error calibration device 900 of the analog-to-digital converter (ADC) circuit includes:

[0170] The weight acquisition unit 901 is used to acquire the actual binary bit weight value of each target sampling capacitor in the single-channel analog-to-digital converter circuit.

[0171] The deviation acquisition unit 902 is used to determine the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value.

[0172] Error calibration unit 903 is used to store weight deviation values, so as to calibrate the digital signal output by the single-channel analog-to-digital converter circuit according to the weight deviation values, and obtain the calibrated digital signal.

[0173] Optionally, the single-channel analog-to-digital converter (ADC) circuit is a pipelined ADC circuit, which includes multiple cascaded pipeline modules. When the weight acquisition unit 901 acquires the actual binary bit weight value of each target sampling capacitor in the single-channel ADC circuit, it is specifically used for:

[0174] Identify the target pipeline module among multiple cascaded pipeline modules, wherein the target pipeline module is not the last stage pipeline module among the multiple cascaded pipeline modules;

[0175] Based on all pipeline modules following the target pipeline module, determine the actual binary bit weight value of each sampling capacitor in the target pipeline module;

[0176] Based on the actual binary bit weight values ​​of the target pipeline module and each sampling capacitor in the target pipeline module, the actual binary bit weight values ​​of each sampling capacitor in all pipeline modules preceding the target pipeline module are determined step by step from high to low, so as to obtain the actual binary bit weight values ​​of each target sampling capacitor in the single-channel analog-to-digital converter ADC circuit. Here, the target sampling capacitor refers to the sampling capacitor in the target pipeline module and the pipeline modules preceding the target pipeline module.

[0177] Optionally, the weight acquisition unit 901 is used to determine the actual binary bit weight value of each sampling capacitor in the target pipeline module based on all pipeline modules following the target pipeline module, specifically for:

[0178] Based on all pipeline modules following the target pipeline module, quantize the first and second output voltages before and after the transition point corresponding to the highest bit sampling capacitor in the target pipeline module to obtain the first quantized value and the second quantized value.

[0179] Based on the first quantization value and the second quantization value, determine the actual binary bit weight value of the highest-order sampling capacitor in the target pipeline module;

[0180] Based on the actual binary bit weight value of the highest-ranking sampling capacitor in the target pipeline module, the actual binary bit weight value of each capacitor in the target pipeline module is obtained bit by bit from high to low.

[0181] Optionally, the weight acquisition unit 901 is used to determine the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module in descending order of binary bit weight value based on the target pipeline module and the actual binary bit weight value of each sampling capacitor in the target pipeline module. Specifically, it is used for:

[0182] Based on the target pipeline module, quantize the first and second output voltages before and after the transition point corresponding to the highest bit sampling capacitor in the pipeline module preceding the target pipeline module;

[0183] Based on the actual binary bit weight value of each sampling capacitor in the target pipeline module, the first output voltage and the second output voltage are calibrated to obtain the calibrated first output voltage and the calibrated second output voltage.

[0184] Based on the calibrated first output voltage and the calibrated second output voltage, the actual binary bit weight value of each sampling capacitor in the preceding stage pipeline module of the target pipeline module is determined, so as to determine the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module in descending order.

[0185] Optionally, the error calibration unit 903 is used to calibrate the digital signal output by the single-channel analog-to-digital converter circuit according to the weighted deviation value. When obtaining the calibrated digital signal, it is specifically used for:

[0186] A random disturbance signal is superimposed on the input signal to obtain the superimposed disturbance input signal;

[0187] The input signal with superimposed perturbation is input to a single-channel analog-to-digital converter (ADC) circuit to obtain the first digital signal.

[0188] The first digital signal is calibrated based on the weight deviation value to obtain the second digital signal;

[0189] Determine the digital quantity corresponding to the random disturbance signal, and subtract the digital quantity from the second digital signal to obtain the calibrated digital signal.

[0190] Optionally, the error calibration unit 903 is used to superimpose a random disturbance signal onto the input signal to obtain the input signal after superimposed disturbance, specifically for:

[0191] When the random disturbance signal is a large-amplitude random disturbance signal, the amplitude range corresponding to the large-amplitude random disturbance signal is determined according to the minimum discrimination range of the single-channel analog-to-digital converter circuit.

[0192] Optionally, after obtaining the calibrated digital signal, the error calibration unit 903 is further used to:

[0193] Using the reference channel as a benchmark, determine the offset error and gain error of the single-channel analog-to-digital converter circuit relative to the reference channel;

[0194] The calibrated digital signal is then calibrated based on the offset error and gain error.

[0195] It should be noted that the explanation of the aforementioned error calibration method embodiment for analog-to-digital converter (ADC) circuit also applies to the error calibration device for the ADC circuit of this embodiment, and will not be repeated here.

[0196] In summary, the apparatus provided in this disclosure acquires the actual binary bit weight value of each target sampling capacitor in a single-channel analog-to-digital converter (ADC) circuit; determines the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value; and stores the weight deviation value. Therefore, the digital signal output by the single-channel ADC circuit can be calibrated based on the weight deviation value to obtain a calibrated digital signal, which can improve the linearity of the ADC circuit and reduce the error itself. Furthermore, storing only the weight deviation value of the target sampling capacitors requires less storage space and has lower hardware costs.

[0197] To implement the above embodiments, this disclosure also proposes an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0198] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided in the foregoing embodiments.

[0199] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program that, when executed by a processor, implements the methods provided in the foregoing embodiments.

[0200] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in this disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0201] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0202] This disclosure is intended to provide implementation schemes for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0203] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0204] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0205] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0206] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0207] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0208] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. When executed, the program includes one or a combination of the steps of the method embodiments.

[0209] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0210] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.< / n> < / n>

Claims

1. An error calibration method for an analog-to-digital converter (ADC) circuit, characterized in that, include: Obtain the actual binary bit weight value of each target sampling capacitor in a single-channel analog-to-digital converter (ADC) circuit; The weight deviation value of each target sampling capacitor is determined based on the actual binary bit weight value and the ideal binary bit weight value. The weight deviation value is stored to calibrate the digital signal output by the single-channel analog-to-digital converter circuit based on the weight deviation value, so as to obtain the calibrated digital signal.

2. The method according to claim 1, characterized in that, The single-channel analog-to-digital converter (ADC) circuit is a pipelined ADC circuit, which includes multiple cascaded pipeline modules. Obtaining the actual binary bit weight value of each target sampling capacitor in the single-channel ADC circuit includes: Determine the target pipeline module among the plurality of cascaded pipeline modules, wherein the target pipeline module is not the last stage pipeline module among the plurality of cascaded pipeline modules; Based on all pipeline modules following the target pipeline module, determine the actual binary bit weight value of each sampling capacitor in the target pipeline module; Based on the target pipeline module and the actual binary bit weight value of each sampling capacitor in the target pipeline module, the actual binary bit weight value of each sampling capacitor in all pipeline modules preceding the target pipeline module is determined step by step from high to low, so as to obtain the actual binary bit weight value of each target sampling capacitor in the single-channel analog-to-digital converter (ADC) circuit. The target sampling capacitor is the sampling capacitor in the target pipeline module and the pipeline modules preceding the target pipeline module.

3. The method according to claim 2, characterized in that, The step of determining the actual binary bit weight value of each sampling capacitor in the target pipeline module based on all pipeline modules following the target pipeline module includes: Based on all pipeline modules following the target pipeline module, quantize the first and second output voltages before and after the transition point corresponding to the highest bit sampling capacitor in the target pipeline module to obtain the first quantized value and the second quantized value. Based on the first quantization value and the second quantization value, determine the actual binary bit weight value of the highest-order sampling capacitor in the target pipeline module; Based on the actual binary bit weight value of the highest-ranking sampling capacitor in the target pipeline module, the actual binary bit weight value of each capacitor in the target pipeline module is obtained bit by bit from high to low.

4. The method according to claim 2, characterized in that, The step of determining the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module in descending order of binary bit weight value based on the target pipeline module and the actual binary bit weight value of each sampling capacitor in the target pipeline module includes: Based on the target pipeline module, quantize the first and second output voltages before and after the transition point corresponding to the highest bit sampling capacitor in the pipeline module preceding the target pipeline module; Based on the actual binary bit weight value of each sampling capacitor in the target pipeline module, the first output voltage and the second output voltage are calibrated to obtain the calibrated first output voltage and the calibrated second output voltage. Based on the calibrated first output voltage and the calibrated second output voltage, the actual binary bit weight value of each sampling capacitor in the preceding stage pipeline module of the target pipeline module is determined, so as to determine the actual binary bit weight value of each sampling capacitor in all preceding pipeline modules of the target pipeline module in descending order.

5. The method according to claim 1, characterized in that, The step of calibrating the digital signal output by the single-channel analog-to-digital converter circuit according to the weighted deviation value to obtain the calibrated digital signal includes: A random disturbance signal is superimposed on the input signal to obtain the superimposed disturbance input signal; The superimposed perturbation input signal is input to the single-channel analog-to-digital converter (ADC) circuit to obtain the first digital signal; The first digital signal is calibrated according to the weight deviation value to obtain the second digital signal; Determine the digital quantity corresponding to the random disturbance signal, and subtract the digital quantity from the second digital signal to obtain the calibrated digital signal.

6. The method according to claim 5, characterized in that, The step of superimposing a random perturbation signal onto the input signal to obtain the superimposed perturbation input signal includes: When the random disturbance signal is a large-amplitude random disturbance signal, the amplitude range corresponding to the large-amplitude random disturbance signal is determined according to the minimum discrimination range of the single-channel analog-to-digital converter circuit.

7. The method according to claim 1, characterized in that, After obtaining the calibrated digital signal, the method further includes: Using a reference channel as a benchmark, determine the offset error and gain error of the single-channel analog-to-digital converter (ADC) circuit relative to the reference channel; The calibrated digital signal is calibrated based on the offset error and the gain error.

8. An error calibration device for an analog-to-digital converter (ADC) circuit, characterized in that, include: The weight acquisition unit is used to acquire the actual binary bit weight value of each target sampling capacitor in the single-channel analog-to-digital converter (ADC) circuit. The deviation acquisition unit is used to determine the weight deviation value of each target sampling capacitor based on the actual binary bit weight value and the ideal binary bit weight value. An error calibration unit is used to store the weight deviation value, and to calibrate the digital signal output by the single-channel analog-to-digital converter circuit according to the weight deviation value to obtain a calibrated digital signal.

9. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 7.

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