Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device including a highly integrated memory cell and a method of manufacturing the semiconductor device are provided. The semiconductor device may include a horizontally arranged switching element including a nanosheet and a horizontal wire surrounding the nanosheet; a pyramid-shaped first contact node formed on a first edge of the horizontally arranged nanosheets; a horizontally arranged vertical wire including a pyramid portion surrounding the pyramid-shaped first contact node and coupled to the horizontally arranged nanosheets; a data storage element coupled to a second edge of the horizontally arranged nanosheets; and a support surrounding the horizontally arranged vertical wire.

Description

[0001] Cross-reference with related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063353, filed on May 14, 2024, and Korean Patent Application No. 10-2025-0059692, filed on May 8, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to semiconductor devices, and more specifically, to semiconductor devices including three-dimensional (3D) memory cells and methods of manufacturing the semiconductor device. Background Technology

[0004] Recently, in order to address the trend of large capacity and miniaturization of storage devices, a three-dimensional (3D) storage device has been proposed, in which multiple storage cells are stacked. Summary of the Invention

[0005] Embodiments of this disclosure relate to a semiconductor device including highly integrated memory cells and a method of manufacturing the semiconductor device.

[0006] According to one embodiment of this disclosure, a semiconductor device may include: a horizontally arranged switching element comprising a nanosheet and a horizontal wire surrounding the nanosheet; a pyramid-shaped first contact node formed on a first edge of the horizontally arranged nanosheet; a horizontally arranged vertical wire including a pyramid portion surrounding the pyramid-shaped first contact node and coupled to the horizontally arranged nanosheet; a data storage element coupled to a second edge of the horizontally arranged nanosheet; and a support member surrounding the horizontally arranged vertical wire.

[0007] According to one embodiment of the present invention, a method of manufacturing a semiconductor device may include: forming a stop layer on a substrate; forming horizontally and vertically arranged slats on the stop layer; forming an enclosure structure surrounding portions of the horizontally and vertically arranged slats and exposing protruding shape edges of the slats; forming a support member including a support recess that simultaneously exposes the protruding shape edges of the vertically arranged slats and separately exposes the protruding shape edges of the horizontally arranged slats; forming flat shape edges of the slats by cutting the protruding shape edges of the slats; forming horizontally and vertically arranged first contact nodes on the flat shape edges of the horizontally and vertically arranged slats; and forming vertical conductors that are commonly coupled to the vertically arranged first contact nodes, separately coupled to the horizontally arranged first contact nodes, and formed in the support recess. Attached Figure Description

[0008] Figure 1AThis is a schematic perspective view showing a storage unit according to an embodiment of the present disclosure.

[0009] Figure 1B It is along Figure 1A The diagram shows a schematic cross-sectional view of the memory cell intercepted by line X1-X1'.

[0010] Figure 2A This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2B It is shown Figure 2A The second layer partial perspective view shown.

[0012] Figure 2C It is shown Figure 2B A partial perspective view of the second conductor shown.

[0013] Figure 2D It is shown Figure 2B A partial perspective view of the first spacer shown.

[0014] Figure 2E It is shown Figure 2B A partial perspective view of the second spacer shown.

[0015] Figure 3A This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 3B This is a schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4A It is along Figure 3B The diagram shows a schematic cross-sectional view of a semiconductor device taken by line A-A'.

[0018] Figure 4B It is along Figure 3B The diagram shows a schematic cross-sectional view of a semiconductor device taken by line B-B'.

[0019] Figure 4C It is along Figure 3B The diagram shows a schematic cross-sectional view of a semiconductor device taken by line A1-A1'.

[0020] Figures 5A to 28B Various views of a semiconductor device formed using a semiconductor device manufacturing method according to embodiments of the present disclosure are shown. Detailed Implementation

[0021] This document describes various embodiments of the present disclosure with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices. It should be noted that the structures in the drawings can be modified by manufacturing techniques and / or tolerances. Embodiments of this disclosure are not limited to the described embodiments and the specific structures shown in the drawings, but may include other embodiments or modifications of the described embodiments, including any structural changes that may occur due to manufacturing process requirements. Therefore, the areas shown in the drawings are schematic in nature, and the shapes of the various areas shown in the drawings are intended to illustrate the specific structure of each area of ​​each element, and are not intended to limit the scope of the embodiments of this disclosure.

[0022] The following embodiments relate to three-dimensional (3D) memory cells with vertically stacked memory cells for increasing memory cell density and reducing parasitic capacitance.

[0023] Figure 1A This is a schematic perspective view showing a storage unit MC according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The diagram shows a schematic cross-sectional view of the memory cell MC intercepted by line X1-X1'.

[0024] Reference Figure 1A and 1B The storage cell MC may include a switching element (or switch) TR and a data storage element (or data storage device) CAP. A first side of the switching element TR may be coupled to a first wire BL, and a second side of the switching element TR may be coupled to the data storage element CAP.

[0025] The first conductor BL may be oriented perpendicularly to a first direction D1. The first conductor BL may include a bit line. The first conductor BL may be referred to as a "vertical conductor," "vertically oriented bit line," "vertically extended bit line," or "cylindrical bit line." The first conductor BL may include a conductive material. The first conductor BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductor BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductor BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductor BL may include a titanium nitride / tungsten (TiN / W) stack, wherein titanium nitride and tungsten are stacked sequentially.

[0026] A switching element TR has the function of controlling the voltage or current supply to a data storage element CAP during data write and read operations. The switching element TR may include a nanosheet HL, a nanosheet dielectric layer GD, and a second conductor WL. The second conductor WL may include a horizontal conductor or a horizontal word line, and the nanosheet HL may include an active layer. The switching element TR may include a transistor, in which case the second conductor WL can serve as a gate electrode. The switching element TR may also be referred to as a "nanosheet transistor," an "access element," or a "select element." The second conductor WL may be referred to as a "horizontal gate electrode" or a "horizontal word line."

[0027] The nanosheet HL can extend along a second direction D2 intersecting the first direction D1. The second wire WL can extend along a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction, i.e., the second direction D2, and the second wire WL can extend along the second horizontal direction, i.e., the third direction D3. The nanosheet HL can be referred to as a "horizontal layer".

[0028] The nanosheet HL may include a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. The first doped region SR may be electrically coupled to the first conductive line BL, and the second doped region DR may be electrically coupled to the data storage element CAP. The height of the second doped region DR in the first direction D1 may be greater than the height of the channel CH in the first direction D1. The length of the second doped region DR in the second direction D2 may be less than the length of the channel CH in the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR in the third direction D3 may be equal to each other.

[0029] The nanosheet HL may include a first region NS and a second region WS horizontally disposed along a second direction D2. The second region WS may extend from the first region NS. The second region WS may have a thickness that gradually increases from the first region NS toward the data storage element CAP along the second direction D2 between the first region NS and the data storage element CAP. The average vertical height or thickness of the second region WS in the first direction D1 may be greater than the average vertical height or thickness of the first region NS. In the following, the first region NS is referred to as a "narrow sheet" and the second region WS is referred to as a "wide sheet".

[0030] The narrow sheet NS can have a flat plate shape. The wide sheet WS can have a fan-shaped shape. The wide sheet WS can have a thickness that gradually increases in the second direction D2. The narrow sheet NS can be referred to as a "flat sheet", and the wide sheet WS can be referred to as a "fan-shaped sheet". The boundary between the narrow sheet NS and the wide sheet WS can have curvature.

[0031] The first doped region SR and the channel CH can be disposed in a narrow wafer NS, and the second doped region DR can be disposed in a wide wafer WS. The channel CH formed in the narrow wafer NS can be referred to as a "narrow channel" or a "flat channel". A portion of the second doped region DR can extend to be disposed in the narrow wafer NS. The second doped region DR can include a thick portion disposed in the wide wafer WS and a thin portion disposed in the narrow wafer NS. The sides of the wide wafer WS and the second doped region DR that contact the data storage element CAP can each have a flat side surface shape.

[0032] The horizontal length of the wide slice WS in the second direction D2 can be less than the horizontal length of the narrow slice NS. The narrow slice NS can be called a "long slice", and the wide slice WS can be called a "short slice".

[0033] Nanosheets HL can include semiconductor materials. For example, nanosheets HL can include polycrystalline silicon, monocrystalline silicon, germanium, or silicon-germanium. In some embodiments, nanosheets HL can include oxide semiconductor materials. For example, oxide semiconductor materials can include indium gallium zinc oxide (IGZO), InSnZnO, ZnSnO, or combinations thereof. In some embodiments, nanosheets HL can include conductive metal oxides. In some embodiments, nanosheets HL can include two-dimensional materials such as MoS2, WS2, or MoSe2.

[0034] When the nanosheet HL is formed from an oxide semiconductor material, the channel CH can also be formed from an oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The nanosheet HL can also be referred to as an "active layer" or "thin body".

[0035] The first doped region SR and the second doped region DR can be doped with impurities of the same conductivity type. Each of the first doped region SR and the second doped region DR can be doped with either an N-type or a P-type conductive impurity. The first doped region SR and the second doped region DR can include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR can be coupled to the first conductive line BL, and the second doped region DR can be coupled to the data storage element CAP. The first doped region SR and the second doped region DR can be referred to as the "first source / drain region" and the "second source / drain region".

[0036] The nanosheet HL can be horizontally oriented from the first wire BL along the second direction D2.

[0037] The second conductor WL can have a gate-around (GAA) structure. For example, the second conductor WL can surround the nanosheet HL and extend in the third direction D3. A nanosheet dielectric layer GD can be formed between the nanosheet HL and the second conductor WL. The nanosheet dielectric layer GD can surround the nanosheet HL. The second conductor WL can surround the nanosheet HL on the nanosheet dielectric layer GD.

[0038] The second conductor WL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductor WL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof. For example, the second conductor WL may include a TiN / W stack, wherein titanium nitride and tungsten are stacked sequentially. The second conductor WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, and the P-type work function material may have a high work function of approximately 4.5 eV or greater. The second conductor WL may include a stack of low work function materials and high work function materials.

[0039] A nanosheet dielectric layer (GD) can be disposed between the nanosheet HL and the second conductive line WL. The nanosheet dielectric layer (GD) can be referred to as a "gate dielectric layer" or a "channel-side dielectric layer." The nanosheet dielectric layer (GD) can include silicon oxide, silicon nitride, metal oxides, metal oxide nitrides, metal silicates, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The nanosheet dielectric layer (GD) can also include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiNO, HfZrO, or combinations thereof. The nanosheet dielectric layer (GD) can be formed through the thermal oxidation of semiconductor materials.

[0040] The data storage element CAP can include a storage element such as a capacitor. The data storage element CAP can be horizontally positioned along the second direction D2 from the switching element TR. The data storage element CAP can include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN can extend horizontally along the second direction D2 from the nanosheet HL. The first electrode SN, the dielectric layer DE, and the second electrode PN can be horizontally positioned along the second direction D2. The first electrode SN can be a storage node, and the second electrode PN can be a plate node.

[0041] The first electrode SN may include an internal space and multiple outer surfaces. The internal space of the first electrode SN may include multiple inner surfaces. The outer surfaces of the first electrode SN may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in a first direction D1, and the horizontal outer surfaces of the first electrode SN may extend horizontally in a second direction D2 or a third direction D3. The internal space of the first electrode SN may be three-dimensional. The dielectric layer DE may conformally cover the inner surface of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically coupled to the second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0042] The data storage element CAP can have a three-dimensional structure. The first electrode SN can also have a three-dimensional structure, which may be horizontally oriented in a second direction D2. In an example of a three-dimensional structure, the first electrode SN can have a cylindrical shape. The cylindrical shape of the first electrode SN may include an inner cylindrical surface and an outer cylindrical surface. Some of the outer cylindrical surfaces of the first electrode SN can be electrically coupled to the second doped region DR of the nanosheet HL. The dielectric layer DE and the second electrode PN can be disposed on the inner cylindrical surface of the first electrode SN.

[0043] In some embodiments, the first electrode SN may be columnar or cylindrical. Cylindrical may refer to a structure combining columnar and cylindrical shapes.

[0044] The first electrode SN and the second electrode PN can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium nitride silicon / titanium nitride stacks (TiSiN / TiN), titanium nitride / titanium nitride silicon (TiN / TiSiN) stacks, or combinations thereof. The second electrode PN can also include a combination of metal-based materials and silicon-based materials. For example, the second electrode PN can be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the interstitial filling material that fills the interior of the first electrode SN, titanium nitride (TiN) can be used as the second electrode PN of the data storage element CAP, and tungsten nitride can be a low-resistance material.

[0045] The dielectric layer DE can be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer DE may include silicon oxide, silicon nitride, high-k materials, perovskite materials, or combinations thereof. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In some embodiments, the dielectric layer DE may be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0046] The dielectric layer DE can be formed of zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure comprising zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. A ZA stack can have a structure where alumina (Al2O3) is stacked on top of zirconium oxide (ZrO2). A ZAZ stack can have a structure in which zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. Both the ZA and ZAZ stacks can be referred to as a "zirconia (ZrO2) base layer." In some embodiments, the dielectric layer DE can be formed of hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure comprising hafnium oxide (HfO2). The dielectric layer DE can include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. HA stacks can have a structure where alumina (Al2O3) is stacked on hafnium oxide (HfO2). HAH stacks can have a structure where hafnium oxide (HfO2), alumina (Al2O3), and hafnium oxide (HfO2) are stacked sequentially. Both HA stacks and HAH stacks can be referred to as "hafnium oxide (HfO2) substrates".

[0047] In ZA, ZAZ, HA, and HAH stacks, alumina (Al2O3) can have a larger bandgap energy than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Alumina (Al2O3) can also have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE can comprise a stack of high-k materials and high-bandgap materials, with the high-bandgap material having a larger bandgap energy than the high-k material.

[0048] The dielectric layer DE may include silicon oxide (SiO2) as a high bandgap material other than aluminum oxide (Al2O3). Because the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. In some embodiments, the dielectric layer DE may include a stacked structure in which high-k materials and high-bandgap materials are stacked alternately. For example, the dielectric layer DE may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack, HZAZH (H The stacked structures can be of various types, including (ZrO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stacks, (ZHZAZHZ / ZrO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2) stacks, (HZHZ / ZrO2 / HfO2 / ZrO2) stacks, or (AHZAZHA / Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3) stacks. In these stacked structures, alumina (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0049] In some embodiments, the dielectric layer DE may include a high-k material and a high-bandgap material. Specifically, the dielectric layer DE may have a laminated structure or a hybrid structure. According to the laminated structure, multiple layers of high-k material and multiple layers of high-bandgap material are stacked. According to the hybrid structure, the high-k material and the high-bandgap material are mixed.

[0050] In some embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0051] In some embodiments, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0052] In some embodiments, an interface control layer may be further formed between the first electrode SN and the dielectric layer DE to mitigate leakage current. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or combinations thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0053] Data storage element CAP can include a three-dimensional capacitor. Data storage element CAP can include a metal-insulator-metal (MIM) capacitor. Data storage element CAP can be replaced with another data storage material. For example, the data storage material can be a thyristor, phase change material, magnetic tunnel junction (MTJ), or variable resistance material.

[0054] The memory cell MC may also include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first conductor BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may include doped polycrystalline silicon, and the first doped region SR may include impurities diffused from the first contact node BLC.

[0055] The second contact node SNC can be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC can include a metal-based material or a semiconductor material. For example, the second contact node SNC can include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC can include doped silicon, and the second doped region DR can include impurities diffused from the second contact node SNC.

[0056] The height of the first contact node BLC in the first direction D1 can be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 can be greater than the height of the channel CH in the first direction D1. The first contact node BLC and the second contact node SNC can each contain phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0057] The first contact node BLC can be selectively grown from the narrow NS of the nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth (SEG). For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The first contact node BLC can be a doped silicon epitaxial layer. The second contact node SNC can be selectively grown from the wide WS of the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The second contact node SNC can be a doped silicon epitaxial layer. The first contact node BLC can be a phosphorus-doped silicon epitaxial layer.

[0058] The first contact node BLC can be a narrow-side contact node, and the second contact node SNC can be a wide-side contact node.

[0059] The nanosheet HL may include a first edge and a second edge. The first edge may refer to a portion of the first doped region SR electrically coupled to the first wire BL, and the second edge may refer to a portion of the second doped region DR electrically coupled to the first electrode SN of the data storage element CAP.

[0060] The memory cell MC may also include an ohmic contact layer BLO located between the first contact node BLC and the first conductor BL. The ohmic contact layer BLO may include a metal silicide, such as titanium silicide or molybdenum silicide.

[0061] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductor WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductor BL and the second conductor WL. The first spacer SP1 and the second spacer SP2 may each comprise a dielectric material. The first spacer SP1 and the second spacer SP2 may each comprise silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 and the second spacer SP2 may each comprise silicon nitride.

[0062] A first spacer SP1 may surround a first portion of the nanosheet HL, a second wire WL may surround a second portion of the nanosheet HL, and a second spacer SP2 may surround a third portion of the nanosheet HL. The first, second, and third portions of the nanosheet HL may be defined within a narrow strip NS.

[0063] The first contact node BLC can have a pyramid shape, and the ohmic contact layer BLO and the first conductor BL can each have a pyramid shape covering the first contact node BLC. For example, the first contact node BLC, the ohmic contact layer BLO, and the first conductor BL can each be a quadrangular pyramid shape. The first contact node BLC can be a phosphorus-doped silicon epitaxial layer, which can be grown into a pyramid shape. The contact resistance can be improved by controlling the size of the first contact node BLC.

[0064] Figure 2A This is a schematic perspective view showing a semiconductor device 100V according to an embodiment of the present disclosure. Figure 2B It is shown Figure 2A The partial perspective view of the second layer L2 shown. Figure 2C It is shown Figure 2B A partial perspective view of the second conductor WL shown. Figure 2D It is shown Figure 2B A partial perspective view of the first spacer SP1 shown. Figure 2E It is shown Figure 2B A partial perspective view of the second spacer SP2 shown.

[0065] refer to Figures 2A to 2EA 100V semiconductor device may include a three-dimensional array of memory cells (MCs). (See above reference.) Figure 1A and Figure 1B A detailed description of the storage unit MC is provided.

[0066] Semiconductor device 100V may include memory cells MC arranged horizontally as HA and vertically as VA. The memory cells MC in each horizontally arranged HA may be horizontally spaced apart in a third direction D3. The memory cells MC in each vertically arranged VA may be vertically stacked in a first direction D1. The stacking of the horizontally arranged HA may include the stacking of the vertically arranged VA. The memory cells MC in each horizontally arranged HA may be coupled to different first conductors BL and share a second conductor WL. The memory cells MC in each vertically arranged VA may share different second conductors WL and be coupled to a first conductor BL. The first conductor BL may include a body portion MBL and multiple pyramid portions PBL. The body portion MBL may refer to the portion where the pyramid portions PBL are interconnected.

[0067] Each vertical arrangement VA can consist of multiple layers L1, L2, and L3. For example, a vertical arrangement VA for a 100V semiconductor device can have a first layer L1, a second layer L2, and a third layer L3 stacked vertically in sequence.

[0068] Each memory cell MC may include a first conductive line BL, a nanosheet HL, and a data storage element CAP, all in a pyramid shape. The nanosheet HL may include a first doped region SR, a channel CH, and a second doped region DR. A first contact node BLC and an ohmic contact layer BLO may be formed between the first doped region SR and the first conductive line BL of the nanosheet HL. A second contact node SNC may be formed between the second doped region DR of the nanosheet HL and the data storage element CAP. The nanosheet HL may be surrounded by a nanosheet dielectric layer GD. A second conductive line WL may extend in a third direction D3, while surrounding the channel CH of the nanosheet HL on the nanosheet dielectric layer GD. The memory cell MC may also include a first spacer SP1 and a second spacer SP2.

[0069] The first spacer SP1 can surround the first part of the nanosheet HL in the horizontal arrangement HA, the second conductor WL can surround the second part of the nanosheet HL in the horizontal arrangement HA, and the second spacer SP2 can surround the third part of the nanosheet HL in the horizontal arrangement HA.

[0070] More specifically, the first spacer SP1 and the second spacer SP2 can extend in the third direction D3, while surrounding the nanosheet HL arranged horizontally in HA. More specifically, the first spacer SP1 can extend in the third direction D3, while surrounding the second doped region DR in HA. The second spacer SP2 can extend in the third direction D3, while surrounding the first doped region SR in HA. The second conductive line WL can extend in the third direction D3, while surrounding the channel CH of the nanosheet HL in HA. Thus, the second conductive line WL, the first spacer SP1, and the second spacer SP2 can surround the nanosheet HL disposed on the same horizontal plane.

[0071] The semiconductor device 100V may further include a support member BLS, which may include a support recess for a horizontally arranged first conductor BL. The first conductor BL may be disposed in the support recess. The first conductor BL may be supported by the support member BLS. The support member BLS may extend vertically in a first direction D1. The support member BLS may include a dielectric material. The first conductor BL may be formed to be self-aligned with the support recess of the support member BLS. The support member BLS may include a low-k material, silicon carbide, silicon nitride, an air gap, or a combination thereof.

[0072] Figure 3A This is a schematic perspective view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3B This is a schematic plan view illustrating a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4A It is along Figure 3B The diagram shows a schematic cross-sectional view of the semiconductor device 100 taken by line A-A'. Figure 4B It is along Figure 3B The diagram shows a schematic cross-sectional view of the semiconductor device 100 taken by line B-B'. Figure 4C It is along Figure 3B The diagram shows a schematic cross-sectional view of the semiconductor device 100 taken along line A1-A1'. (Refer to the above.) Figures 1A to 2E The following detailed description of the overlapping components is provided.

[0073] Reference Figures 3A to 4C The semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a three-dimensional array of memory cells MC. Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP. The switching element TR may include a second wire WL, a nanosheet dielectric layer GD, and a nanosheet HL.

[0074] The memory cell array (MCA) may include a first sub-cell array (MCA1) and a second sub-cell array (MCA2). Each of the first and second sub-cell arrays may comprise a three-dimensional array of memory cells (MCs). The memory cells (MCs) in the first sub-cell array (MCA1) may share a first vertical conductor (BLA), and the memory cells (MCs) in the second sub-cell array (MCA2) may share a second vertical conductor (BLB). The first vertical conductor (BLA) and the second vertical conductor (BLB) may each have a pyramid shape. The bottom of the first vertical conductor (BLA) and the bottom of the second vertical conductor (BLB) may be electrically isolated from each other.

[0075] The first sub-cell array MCA1 may include horizontally and vertically arranged memory cells MC. Each memory cell MC of the first sub-cell array MCA1 may include a first vertical conductor BLA, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductor WL and a nanosheet HL. The switching element TR of the memory cell MC may be a nanosheet transistor. The first sub-cell array MCA1 may include horizontally and vertically arranged nanosheet transistors. The first sub-cell array MCA1 may include a horizontally arranged first vertical conductor BLA. The first sub-cell array MCA1 may include horizontally and vertically arranged second conductor WL. The first sub-cell array MCA1 may include horizontally and vertically arranged data storage elements CAP.

[0076] The second sub-cell array MCA2 may include horizontally and vertically arranged memory cells MC. Each memory cell MC of the second sub-cell array MCA2 may include a second vertical conductor BLB, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductor WL and a nanosheet HL. The switching element TR of the memory cell MC may be a nanosheet transistor. The second sub-cell array MCA2 may include horizontally and vertically arranged nanosheet transistors. The second sub-cell array MCA2 may include a horizontally arranged second vertical conductor BLB. The second sub-cell array MCA2 may include horizontally and vertically arranged second conductor WL. The second sub-cell array MCA2 may include horizontally and vertically arranged data storage elements CAP.

[0077] The first wire BL can extend vertically in the first direction D1, the nanosheet HL can extend in the second direction D2, and the second wire WL can extend horizontally in the third direction D3.

[0078] The first inter-cell dielectric layer IL1 can be disposed between data storage elements CAP disposed adjacent to each other in the third direction D3. The second inter-cell dielectric layer IL2 can be disposed between second conductors WL stacked vertically in the first direction D1. The third inter-cell dielectric layer IL3 can be disposed between the first electrodes SN of the data storage elements CAP stacked vertically in the first direction D1. The first to third inter-cell dielectric layers IL1, IL2 and IL3 can each include silicon oxide, silicon carbide (SiCO), silicon nitride, or a combination thereof. The first inter-cell dielectric layer IL1 can be referred to as a "device isolation layer".

[0079] Each memory cell (MC) may further include a first contact node (BLC) and a second contact node (SNC). The first contact node (BLC) may be disposed between a first vertical conductor (BLB) and a nanosheet (HL) and between a second vertical conductor (BLB) and a nanosheet (HL). The first contact node (BLC) may include a metal-based material or a semiconductor material. For example, the first contact node (BLC) may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node (BLC) may include doped polysilicon, and the first doped region (SR) may include impurities diffused from the first contact node (BLC). The second contact node (SNC) may be disposed between the nanosheet (HL) and the first electrode (SN). The second contact node (SNC) may include a metal-based material or a semiconductor material. For example, the second contact node (SNC) may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node (SNC) may include doped polysilicon, and the second doped region (DR) may include impurities diffused from the second contact node (SNC). The height of the first contact node (BLC) in the first direction (D1) may be less than the height of the second contact node (SNC) in the first direction (D1). The height of the first contact node (BLC) in the first direction (D1) may be greater than the height of the channel (CH) in the first direction (D1). The first contact node (BLC) and the second contact node (SNC) can each comprise either phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0080] Each memory cell MC may also include an ohmic contact layer BLO located between the first contact node BLC and the first conductor BL. The ohmic contact layer BLO may include a metal silicide, such as titanium silicide or molybdenum silicide.

[0081] The first contact node (BLC) can be selectively grown from the nanosheet (HL). The first contact node (BLC) can be formed by selective epitaxial growth (SEG). For example, the first contact node (BLC) can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The first contact node (BLC) can be a doped silicon epitaxial layer. The second contact node (SNC) can be selectively grown from the nanosheet (HL). The second contact node (SNC) can be formed by selective epitaxial growth (SEG). For example, the second contact node (SNC) can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The second contact node (SNC) can be a doped silicon epitaxial layer. The first contact node (BLC) can be a phosphorus-doped silicon epitaxial layer.

[0082] Each memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductor WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductor BL and the second conductor WL. The first spacer SP1 and the second spacer SP2 may each comprise a dielectric material. The first spacer SP1 and the second spacer SP2 may each comprise silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 and the second spacer SP2 may each comprise silicon nitride.

[0083] A first spacer SP1 may surround a first portion of the nanosheet HL, a second wire WL may surround a second portion of the nanosheet HL, and a second spacer SP2 may surround a third portion of the nanosheet HL. The first, second, and third portions of the nanosheet HL may be defined within a narrow strip NS.

[0084] The first contact node BLC can have a pyramid shape, and the ohmic contact layer BLO and the first conductor BL can each have a pyramid shape covering the first contact node BLC. The first contact node BLC can be a phosphorus-doped silicon epitaxial layer, which can be grown into a pyramid shape. The contact resistance can be improved by controlling the size of the first contact node BLC.

[0085] The memory cell array MCA may include a plurality of second conductors WL stacked vertically along a first direction D1. The memory cell array MCA may include a plurality of nanosheets HL stacked vertically along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP stacked vertically along the first direction D1. The memory cell array MCA may include a plurality of first conductors BLA and BLB spaced apart on a third direction D3. The memory cell array MCA may include dummy second conductors WLU and WLL, respectively positioned at a level higher than the uppermost second conductor WL and a level lower than the lowermost second conductor WL. The dummy second conductors WLU and WLL may each have a horizontally extending linear shape.

[0086] The memory cell array MCA may include a stack of multiple hard mask layers HM1 and HM2 positioned at a level above the topmost second conductor WL.

[0087] The lower structure LS and stop layer LSL can be disposed below the memory cell array MCA. The stop layer LSL prevents electrical contact between the first vertical conductor BLA and the second vertical conductor BLB and the lower structure LS. The stop layer LSL also prevents electrical contact between the data storage element CAP and the lower structure LS. The stop layer LSL may include a dielectric material. The lower structure LS may be made of a material suitable for semiconductor fabrication. The lower structure LS may include one or more of conductive, dielectric, and semiconductor materials. The lower structure LS may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. The lower structure LS may also include another semiconductor material such as germanium. The lower structure LS may also include a III-V group semiconductor substrate, such as a compound semiconductor substrate like GaAs.

[0088] An inter-array dielectric layer (BLF) can be disposed between the first vertical conductor (BLA) and the second vertical conductor (BLB). The inter-array dielectric layer (BLF) may include a dielectric material. For example, the inter-array dielectric layer (BLF) may include silicon oxide with embedded air gaps.

[0089] The first vertical conductor BLA and the second vertical conductor BLB can be formed to be self-aligned with the support member BLS. The first vertical conductor BLA, which is adjacent to each other in the third direction D3, can be isolated from each other by the support member BLS. The second vertical conductor BLB, which is adjacent to each other in the third direction D3, can be isolated from each other by the support member BLS. The first vertical conductor BLA and the second vertical conductor BLB, which are adjacent to each other in the second direction D2, can be isolated from each other by an inter-array dielectric layer BLF.

[0090] Nanosheets HL of switching elements TR arranged horizontally along the third direction D3 can share a second conductor WL. Nanosheets HL of switching elements TR horizontally arranged along the third direction D3 can be coupled to different first conductors BL. Switching elements SR stacked in the first direction D1 can share a first conductor BL, and switching elements TR horizontally arranged along the third direction D3 can share a second conductor WL.

[0091] The second electrode PN of the data storage element CAP can be coupled to the common board PL.

[0092] Return to reference Figure 4BThe memory cell array (MCA) may include vertically arranged second conductors WL and vertically arranged second inter-cell dielectric layers IL2. Each second inter-cell dielectric layer IL2 may be disposed between the second conductors WL. The memory cell array (MCA) may include dummy second conductors WLU and WLL, respectively disposed at a level higher than the uppermost second conductor WL and a level lower than the lowermost second conductor WL. The dummy second conductors WLU and WLL may each have a horizontally extending linear shape.

[0093] The nanosheet dielectric layer GD can surround the nanosheet HL, and the second wire WL can surround the nanosheet HL on the nanosheet dielectric layer GD.

[0094] The semiconductor device 100 may further include a support member BLS, which may include support recesses for a first vertical conductor BLA and a second vertical conductor BLB arranged horizontally. The first vertical conductor BLA and the second vertical conductor BLB may be disposed in the support recesses. The first vertical conductor BLA and the second vertical conductor BLB may be supported by the support member BLS. The support member BLS may extend vertically in a first direction D1. The support member BLS may include a dielectric material. The first vertical conductor BLA and the second vertical conductor BLB may be formed to be self-aligned with the support recesses of the support member BLS. The support member BLS may include a low-k material, silicon carbide, silicon nitride, an air gap, or a combination thereof.

[0095] according to Figures 1A to 4C The semiconductor device 100 may include horizontally arranged switching elements TR, each switching element TR including a nanosheet HL and a second conductor WL surrounding the nanosheet HL, each first vertical conductor BLA having a pyramid shape and coupled to a first edge of the horizontally arranged nanosheet HL, a data storage element CAP coupled to a second edge of the horizontally arranged nanosheet HL, a support member BLS including a support recess filled with the first vertical conductors BLA, a first spacer SP1 disposed between the data storage element CAP and the second conductor WL and surrounding the nanosheet HL, and a second spacer SP2 disposed between the first vertical conductors BLA and the second conductor WL and surrounding the nanosheet HL. The first vertical conductors BLA may be formed to be self-aligned in the support recess of the support member BLS.

[0096] according to Figures 1A to 4CThe semiconductor device 100 may include horizontally arranged switching elements TR, each switching element TR including a nanosheet HL and a second conductive line WL surrounding the nanosheet HL, each second vertical conductive line BLB having a pyramid shape and coupled to a first edge of the horizontally arranged nanosheet HL, a data storage element CAP coupled to a second edge of the horizontally arranged nanosheet HL, a support member BLS including a support recess filled with the second vertical conductive lines BLB, a first spacer SP1 disposed between the data storage element CAP and the second conductive line WL and surrounding the nanosheet HL, and a second spacer SP2 disposed between the second vertical conductive lines BLB and the second conductive line WL and surrounding the nanosheet HL. The second vertical conductive lines BLB may be formed to be self-aligned in the support recess of the support member BLS.

[0097] according to Figures 1A to 4C The semiconductor device 100 may include a first sub-cell array MCA1, a second sub-cell array MCA2, an inter-array dielectric layer BLF, and a support. The first sub-cell array MCA1 includes horizontally arranged first vertical conductors BLA, and the second sub-cell array MCA2 includes horizontally arranged second vertical conductors BLB. The inter-array dielectric layer BLF is located between the first sub-cell arrays MCA1 and MCA2. The support BLS includes a support recess filled with the horizontally arranged first vertical conductors BLA and BLB, wherein each first vertical conductor BLA has a pyramid shape, and each second vertical conductor BLB has a pyramid shape. The first sub-cell arrays MCA1 and MCA2 may each include a three-dimensional array of memory cells MC. Each memory cell MC may include horizontally arranged switching elements TR, and each switching element TR includes a nanosheet HL and a second conductor WL surrounding the nanosheet HL. The nanosheet HL may include a narrow strip NS and a wide strip WS. Each memory cell MC may also include a first contact node BLC, an ohmic contact layer BLO, a second contact node SNC, and a data storage element CAP.

[0098] Figures 5A to 28B Various views of a semiconductor device formed using a semiconductor device manufacturing method according to embodiments of the present disclosure are shown.

[0099] Figure 5A This is a plan view showing the structure of the second module layer at the horizontal plane, to describe the method of forming the module stack SB. Figure 5B It is along Figure 5A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 5C It is along Figure 5A The cross-sectional view of the structure cut by line A1-A1' shown in the figure.

[0100] Reference Figures 5A to 5CA stop layer 11A can be formed on the substrate 11, and a mold stack SB can be formed on the stop layer 11A.

[0101] Substrate 11 may be a material suitable for semiconductor processing. Substrate 11 may include one or more of conductive, dielectric, and semiconductor materials. Substrate 11 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. Substrate 11 may also include another semiconductor material such as germanium. Substrate 11 may also include a III-V group semiconductor substrate, such as a compound semiconductor substrate like GaAs.

[0102] The stop layer 11A may include a dielectric material. The stop layer 11A may include silicon oxide, silicon carbide, or a combination thereof. The mold stack SB may include an alternating stack of a first mold layer 12 and a second mold layer 13.

[0103] The first mold layer 12 can be stacked alternately with the second mold layer 13. The first mold layer 12 and the second mold layer 13 can be epitaxially grown multiple times to form a mold stack SB. The first mold layer 12 can be placed on top of the mold stack SB.

[0104] The first mode layer 12 and the second mode layer 13 can be made of different semiconductor materials. The first mode layer 12 can include silicon germanium or single-crystal silicon germanium. The second mode layer 13 can include single-crystal silicon. The first mode layer 12 and the second mode layer 13 can be formed by an epitaxial growth process. During the epitaxial growth process, the bottommost first mode layer 12 can be used as a seed layer. Each first mode layer 12 can be thinner than each second mode layer 13. The first mode layer 12 can include a first epitaxial growth layer, and the second mode layer 13 can include a second epitaxial growth layer.

[0105] In one embodiment, multiple single-crystal silicon-germanium layers can be alternately stacked with multiple single-crystal silicon layers in the mode stack SB. For example, the first mode layer 12 can be a single-crystal silicon-germanium layer, and the second mode layer 13 can be a single-crystal silicon layer. The stacking of single-crystal silicon-germanium layers and single-crystal silicon layers (SiGe / Si stack) can be performed multiple times. The first mode layer 12 can be referred to as a "sacrificial layer", and the second mode layer 13 can be referred to as a "nanosheet target layer" or a "recessed target layer".

[0106] Modular stacking (SB) can be referred to as "vertical stacking". Modular stacking SB can be formed by alternately stacking multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a single-crystal silicon-germanium layer, and the nanosheet target layer can be a single-crystal silicon layer.

[0107] The thickness ratio of the first module layer 12 and the second module layer 13 in the module stack SB can be modified in various ways. For example, the thickness of each first module layer 12 can be approximately 5 to 20 nm, and the thickness of each second module layer 13 can be approximately 50 to 80 nm. The number of first module layers 12 and the number of second module layers 13 in the module stack SB can be modified in various ways. In some embodiments, a triple stack including a first module layer 12, a second module layer 13, and a first module layer 12 can be defined at the bottom and top of the module stack SB. The thickness of the second module layer 13 in the triple stack can be less than the thickness of the second module layer 13 in the module stack SB.

[0108] A first hard mask layer 14 may be formed on the die stack SB. The first hard mask layer 14 may include a dielectric material such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. For example, the first hard mask layer 14 may include SiO2, Si3N4, amorphous carbon, or a combination thereof.

[0109] Subsequently, a first hard mask layer 14 can be used as a stop to etch portions of the die stack SB, forming a plurality of sacrificial isolation openings 15. The sacrificial isolation openings 15 can be initial openings for cell isolation. From a top view perspective, the cross-section of each sacrificial isolation opening 15 can be rectangular. In some embodiments, the cross-section of each sacrificial isolation opening 15 can be circular or elliptical. In some embodiments, the sacrificial isolation opening 15 can be referred to as a "sacrificial isolation trench". The sacrificial isolation openings 15 can extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation openings 15 can be arranged at predetermined intervals along a third direction D3. The etching process for forming the sacrificial isolation openings 15 can be stopped at a stop layer 11A.

[0110] Figure 6A This is a plan view showing the structure of the second module layer horizontal plane to describe the method used to form the sacrificial linear openings 18 and 19. Figure 6B It is along Figure 6A The cross-sectional view of the structure intercepted by line A-A' is shown. Figure 6C It is along Figure 6A The cross-sectional view of the structure cut by line A1-A1' is shown.

[0111] Reference Figures 6A to 6CA sacrificial isolation layer 16 may be formed to fill the sacrificial isolation opening 15. The sacrificial isolation layer 16 may comprise the same material. The sacrificial isolation layer 16 may be formed of a dielectric material. The sacrificial isolation layer 16 may have etch selectivity relative to the mold stack SB. For example, each sacrificial isolation layer 16 may comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof. Forming the sacrificial isolation layer 16 may include forming a sacrificial isolation material on the mold stack SB to fill the sacrificial isolation opening 15 and planarizing the sacrificial isolation material to expose the surface of the first hard mask layer 14.

[0112] The sacrificial isolation layer 16 may extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation layer 16 may be arranged at predetermined intervals along a third direction D3. Each sacrificial isolation layer 16 may include a stack of a first sacrificial sub-spacer layer and a first sacrificial gap-filling layer. The first sacrificial sub-spacer layer may be silicon nitride, and the first sacrificial gap-filling layer may be silicon oxide. The sacrificial isolation layers 16 may penetrate the mold stack SB along the first direction D1.

[0113] Subsequently, a second hard mask layer 17 can be formed on the die stack SB and the sacrificial isolation layer 16. The second hard mask layer 17 may include silicon nitride. The second hard mask layer 17 can be formed by etching the second hard mask material using a mask layer such as a photoresist. The second hard mask layer 17 may have a plurality of linear openings defined therein.

[0114] A second hard mask layer 17 can be used as an etching barrier to etch portions of the die stack SB. Therefore, a plurality of sacrificial linear openings 18 and 19 can be formed between the sacrificial isolation layers 16. The sacrificial linear openings may include a first sacrificial linear opening 18 and a second sacrificial linear opening 19. From a top view perspective, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may extend vertically in a first direction D1. The sacrificial isolation layer 16 may be disposed between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 along a second direction D2. From a top view perspective, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may each have a rectangular shape. In some embodiments, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may each have a circular or elliptical shape. The width of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 in the second direction D2 may be smaller than its width in the third sacrificial direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 can be referred to as "sacrificial linear trenches". The sacrificial isolation layer 16 may not contact the first sacrificial linear opening 18 and the second sacrificial linear opening 19.

[0115] Figure 7AThis is a plan view showing the structure of the second module layer at the horizontal plane, to describe the method of forming the linear sacrificial layers 18L and 19L. Figure 7B It is along Figure 7A The cross-sectional view of the structure cut by line A-A' shown in the figure.

[0116] Reference Figure 7A and Figure 7B Linear sacrificial layers 18L and 19L can be formed to fill the first linear sacrificial opening 18 and the second linear sacrificial opening 19. The linear sacrificial layers may include the first linear sacrificial layer 18L and the second linear sacrificial layer 19L. From a top view perspective, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may have a linear shape extending along a third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may extend vertically in a first direction D1. A sacrificial isolation layer 16 may be disposed between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L along a second direction D2. From a top view perspective, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may each have a rectangular shape. In some embodiments, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may each have a circular or elliptical shape. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may comprise the same material. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L can be formed of a dielectric material. For example, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L can each comprise silicon oxide, silicon nitride, silicon carbide, silicon carbide, or a combination thereof. The sacrificial isolation layer 16 may not contact the first linear sacrificial layer 18L and the second linear sacrificial layer 19L.

[0117] Figure 8A This is a plan view showing the structure of the horizontal plane of the second mold layer to describe the recess of the second mold layer 12. Figure 8B It is along Figure 8A The cross-sectional view of the structure cut by line A-A' is shown. Figure 8C It is along Figure 8A The cross-sectional view of the structure cut by line A1-A1' is shown.

[0118] Reference Figures 8A to 8C In the first linear sacrificial layer 18L and the second linear sacrificial layer 19L, the first linear sacrificial layer 18L can be selectively removed. The second hard mask layer 17 can be used as an etching stop to remove the first linear sacrificial layer 18L. Therefore, a first linear opening 20 can be formed. From a top view perspective, the first linear opening 20 can be horizontally spaced from the second linear sacrificial layer 19L in the second direction D2.

[0119] The etching process used to form the first linear opening 20 can be stopped at the stop layer 11A.

[0120] Subsequently, the first mold layer 12 and the second mold layer 13 can be selectively recessed through the first linear opening 20.

[0121] The difference in etch selectivity between the first template layer 12 and the second template layer 13 can be used to selectively recess the first template layer 12. The first template layer 12 can be removed using either a wet etching process or a dry etching process. For example, when the first template layer 12 comprises a silicon-germanium layer and the second template layer 13 comprises a monocrystalline silicon layer, the silicon-germanium layer can be etched using an etchant or etching gas that is selective relative to the monocrystalline silicon layer. The first template layers, each with its original thickness, can be retained, as indicated by reference numeral "12A".

[0122] Subsequently, a portion (first portion) of each second mold layer 13 can be recessed to form a narrow strip 13N. A wet etching process or a dry etching process can be used to recess the second mold layer 13. The original body portion 13A and the narrow strip 13N can be formed by the partial recess of each second mold layer 13. The original body portion 13A can maintain its original thickness T1, and the narrow strip 13N can have a thickness T2 less than the original thickness T1. The horizontal length of the original body portion 13A in the second direction D2 can be equal to or different from the horizontal length of the narrow strip 13N in the second direction D2. The combination of the original body portion 13A and the narrow strip 13N can be referred to as a “preliminary active layer.” The narrow strip 13N can be referred to as a “flat strip” or a “protruding narrow strip.”

[0123] The recessed process used to form the narrow wafer 13N can be referred to as a "thinning process" or "trimming process" for the second template layer 13. To form the narrow wafer 13N, the upper surface, lower surface, and side surfaces of the second template layer 13 can be recessed. The narrow wafer 13N can be referred to as a "thin active layer." The narrow wafer 13N may include a monocrystalline silicon layer. The recessed process used to form the narrow wafer 13N can use, for example, thermal SC-1 (HSC1). HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of 1:4:20. Using HSC1, the second template layer 13 can be selectively etched.

[0124] Narrow sheets 13N can be formed by a partial recessing process of the second template layer 13 as described above. Inter-nanosheet recesses 21 can be formed between vertically arranged narrow sheets 13N. The upper and lower surfaces of the narrow sheets 13N can each include a flat surface. The boundary between the original body portion 13A and the narrow sheets 13N can be vertical or have curvature. Each first template layer 12A can be disposed between vertically stacked original body portions 13A. Horizontally and vertically arranged narrow sheets 13N can be formed above the stop layer 11A.

[0125] Figure 9AThis is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the horizontal opening 22 of the sacrificial isolation layer. Figure 9B It is along Figure 9A The cross-sectional view of the structure intercepted by line A-A' is shown.

[0126] Reference Figure 9A and 9B The sacrificial isolation layer 16 can be selectively peeled off through the recesses 21 between the nanosheets. Therefore, each horizontal opening 22 of the sacrificial isolation layer can be formed on the third direction D3 between the original body portions 13A.

[0127] The sides of the first module layer 12A, the sides of the original main body portion 13A, and the sides of the narrow strip 13N can be exposed on the third direction D3 through the horizontal opening 22 of the sacrificial isolation layer.

[0128] Figure 10A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the first inter-unit dielectric layer 23, the first spacer layer 26A, and the second inter-unit dielectric layer 27. Figure 10B It is along Figure 10A The cross-sectional view of the structure intercepted by line A-A' is shown. Figure 10C It is along Figure 10A The cross-sectional view of the structure cut by line A1-A1' is shown. Figure 10D It is along Figure 10A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0129] Reference Figures 10A to 10D The first inter-cell dielectric layer 23 may be formed in the horizontal opening 22 of the sacrificial isolation layer. Each first inter-cell dielectric layer 23 may include a dielectric material. Each first inter-cell dielectric layer 23 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. Forming the first inter-cell dielectric layer 23 may include forming a dielectric material that fills the horizontal opening 22 of the sacrificial isolation layer, and performing an etch-back process on the dielectric material.

[0130] The first inter-unit dielectric layer 23 can fill a portion of the horizontal opening 22 of the sacrificial isolation layer. The sides of the first module layer 12A and the original main body portion 13A can be covered by the first inter-unit dielectric layer 23 in the third direction D3. The first inter-unit dielectric layer 23 can expose the sides of the narrow strip 13N. The remaining portions of the horizontal opening 22 of the sacrificial isolation layer, i.e., the non-gap-filled portions, can expose the sides of the narrow strip 13N.

[0131] Subsequently, a nanosheet dielectric layer 25 can be formed on the exposed portion of the narrow strip 13N. The nanosheet dielectric layer 25 can be referred to as the "gate dielectric layer".

[0132] The nanosheet dielectric layer 25 can be formed by oxidizing the surface of the narrow sheet 13N. In some embodiments, the nanosheet dielectric layer 25 can be formed by a silicon oxide deposition process and an oxidation process. The nanosheet dielectric layer 25 may include silicon oxide, silicon nitride, metal oxide, metal oxide nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer 25 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof. The nanosheet dielectric layer 25 can be formed on all surfaces of the narrow sheet 13N.

[0133] A first spacer layer 26A may be formed on the nanosheet dielectric layer 25. The first spacer layer 26A may include silicon nitride. The first spacer layer 26A may surround and cover the narrow strip 13N on the nanosheet dielectric layer 25. The first spacer layer 26A may be thicker than the nanosheet dielectric layer 25.

[0134] The second inter-unit dielectric layer 27 can be formed on the first spacer layer 26A. The second inter-unit dielectric layer 27 may include silicon oxide. A silicon oxide deposition and etch-back process can be performed to form the second inter-unit dielectric layer 27. The second inter-unit dielectric layer 27 may be disposed in the nanosheet recess 21 on the first spacer layer 26A. The second inter-unit dielectric layer 27 may not be disposed in the first linear opening 20. The non-gap filling space 27R may be defined on the side surface of the second inter-unit dielectric layer 27.

[0135] The nanosheet dielectric layer 25 and the first spacer layer 26A can also be formed on the surface of the stop layer 11A.

[0136] As described above, the first spacer layer 26A can be disposed between the narrow strips 13N along the third direction D3.

[0137] Figure 11A This is a plan view showing the structure of the horizontal plane of the narrow strip to describe the method of forming the first spacer 26. Figure 11B It is along Figure 11A The cross-sectional view of the structure intercepted by line A-A' is shown. Figure 11C It is along Figure 11A The cross-sectional view of the structure cut by line A1-A1' is shown. Figure 11D It is along Figure 11A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0138] Reference Figures 11A to 11D The first spacer layer 26A can be selectively recessed through the first linear opening 20. The remaining first spacer layer can become the first spacer 26.

[0139] When forming the first spacer 26, a first linear surrounding recess 28 can be formed on the nanosheet dielectric layer 25 surrounding the narrow strip 13N. Each second inter-unit dielectric layer 27 can be disposed between the vertically arranged first linear surrounding recesses 28. The first spacer 26 may have a cup shape covering a first side surface of the second inter-unit dielectric layer 27. An upper dummy horizontal recess 28U can be formed above the uppermost second inter-unit dielectric layer 27, and a lower dummy horizontal recess 28L can be formed below the lowermost second inter-unit dielectric layer 27L. The upper dummy horizontal recess 28U and the lower dummy horizontal recess 28L may each have a non-circling shape, i.e., a flat shape.

[0140] The first spacer 26 may surround the first portion of the narrow strip 13N on the nanosheet dielectric layer 25 on the same horizontal plane.

[0141] Figure 12A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the horizontal conductor layer 29A. Figure 12B It is along Figure 12A The cross-sectional view of the structure cut by line A-A' is shown. Figure 12C It is along Figure 12A The cross-sectional view of the structure cut by line A1-A1' is shown. Figure 12D It is along Figure 12A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0142] Reference Figures 12A to 12D This can form a horizontal conductor layer 29A that fills the linear surrounding recess 28.

[0143] Figure 13A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the horizontal guide 29. Figure 13B It is along Figure 17A The cross-sectional view of the structure cut by line A-A' is shown. Figure 13C It is along Figure 13A The cross-sectional view of the structure cut by line A1-A1' is shown. Figure 13D It is along Figure 13A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0144] Reference Figures 13A to 13D This can form a horizontal guide wire 29 that fills the first linear surrounding recess 28. The horizontal guide wire 29 can extend horizontally in the third direction D3.

[0145] Forming the horizontal conductors 29 may include performing a horizontal etch-back process on the horizontal conductor layer 29A. Each horizontal conductor 29 may simultaneously surround the narrow strip 13N on the same horizontal plane. Each horizontal conductor 29 may include a metal substrate material, a semiconductor material, or a combination thereof. Each horizontal conductor 29 may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, each horizontal conductor 29 may include a titanium nitride and tungsten (TiN / W) stack, wherein the titanium nitride and W are stacked sequentially. Each horizontal conductor 29 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, and the P-type work function material may have a high work function of approximately 4.5 eV or greater. Each second inter-cell dielectric layer 27 may be disposed between the plurality of horizontal conductors 29 along a first direction D1. The horizontal conductors 29 surrounding the narrow strip 13N may be referred to as “gate-around (GAA) electrodes.” The narrow strip 13N may be referred to as a “nanopie channel,” “nanowire,” or “nanowire channel.”

[0146] A lower dummy horizontal electrode 29L can be formed on the stop layer 11A. An upper dummy horizontal electrode 29U can be formed above the uppermost horizontal conductor 29. The dummy horizontal electrodes 29L and 29U can each have a non-circular shape.

[0147] The horizontal conductor 29 can be on the same horizontal plane around the second part of the narrow strip 13N on the nanosheet dielectric layer 25.

[0148] After the horizontal conductor 29 is formed, a second linear surrounding recess 29V can be defined to open the third portion of the narrow strip 13N. The second linear surrounding recess 29V can be the space for forming the second spacer and the etch stop spacer.

[0149] The second linear surrounding recess 29V can surround the third part of the narrow strip 13N on the same horizontal plane on the nanosheet dielectric layer 25.

[0150] Figure 14A This is a plan view showing the structure of the horizontal plane of the narrow strip to describe the method of forming the second spacer 30. Figure 14B It is along Figure 14A The cross-sectional view of the structure intercepted by line A-A' is shown. Figure 14C It is along Figure 14A The cross-sectional view of the structure cut by line B1-B1' is shown.

[0151] Reference Figures 14A to 14C Multiple spacer materials can be formed in the second linear surrounding recess 29V.

[0152] A second spacer 30 may be formed on one side of each horizontal conductor 29. The second spacer 30 may comprise silicon oxide, silicon nitride, silicon carbide, an embedded air gap, or a combination thereof. The second spacer 30 may contact one side of each horizontal conductor 29 and cover a second side of the second inter-cell dielectric layer 27. The second spacer 30 may have a cup shape covering the second side of the second inter-cell dielectric layer 27. The second spacer 30 may surround a third portion of the narrow strip 13N on the nanosheet dielectric layer 25.

[0153] After the second spacer 30 is formed, the protruding structure 31 may be exposed. The protruding structure 31 may include a portion of the nanosheet dielectric layer 25 and a fourth portion 13E of the narrow sheet 13N. The fourth portion 13E of the narrow sheet 13N may be a target to be cut. Hereinafter, the fourth portion 13E will be referred to as the protruding edge 13E of the narrow sheet 13N.

[0154] As described above, an enclosure structure can be formed around portions (i.e., the first to the third portions) of the horizontally and vertically arranged narrow strips 13N, exposing the protruding edges 13E of the narrow strips 13N. The enclosure structure may include a first spacer 26, a horizontal guide 29, and a second spacer 30.

[0155] Figure 15A This is a plan view showing the structure of the narrow horizontal plane to describe the method of partially recessing the nanosheet dielectric layer 25. Figure 15B It is along Figure 15A The cross-sectional view of the structure intercepted by line A-A' is shown. Figure 15C It is along Figure 15A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0156] Reference Figures 15A to 15C A portion of the nanosheet dielectric layer 25 exposed by the second spacer 30 can be horizontally recessed. This exposes edge portions of the narrow strip 13N, such as the protruding edge 13E (reference numeral 37) of the narrow strip 13N. The protruding edges 13E of the narrow strip 13N can be perpendicularly spaced apart from each other by gaps G. The outer surface 32, side surfaces 33 and 34, upper surface 35, and lower surface 36 of the protruding edge 13E can be exposed through the partial recesses of the nanosheet dielectric layer 25.

[0157] Figure 16A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the sacrificial growth layer 38. Figure 16B It is along Figure 16A The cross-sectional view of the structure intercepted by line A-A' is shown. Figure 16C It is along Figure 16A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0158] Reference Figures 16A to 16CA sacrificial growth layer 38 can be formed on the protruding edge 13E of the narrow wafer 13N. The sacrificial growth layer 38 can be formed by selective epitaxial growth (SEG). The sacrificial growth layer 38 can cover all surfaces of the protruding edge 13E of the narrow wafer 13N. Each sacrificial growth layer 38 can have a pyramid shape. Each sacrificial growth layer 38 can include a silicon-germanium epitaxial layer. The sacrificial growth layer 38 can include a convex profile 38A, and gaps 38B can be formed between the vertically arranged sacrificial growth layers 38.

[0159] Figure 17A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the support 39. Figure 17B It is along Figure 17A The cross-sectional view of the structure cut by line A-A' is shown. Figure 17C It is along Figure 17A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0160] Reference Figures 17A to 17C The deposition and etching processes of the support material can be performed on the sacrificial growth layer 38. Therefore, a support member 39 supporting the sacrificial growth layer 38 can be formed. The support members 39, disposed adjacent to each other, can be spaced apart from each other in the second direction D2. Each support member 39 may include a dielectric material. Each support member 39 may include silicon nitride. The support member 39 may have an integral structure supporting the sacrificial growth layer 38. The support member 39 may include a void filler 39A filling the voids 38B formed between the sacrificial growth layers 38. The support member 39 may expose the convex profile 38A of the sacrificial growth layer 38.

[0161] Figure 18A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the initial support recess 39R. Figure 18B It is along Figure 18A The cross-sectional view of the structure cut by line A-A' is shown. Figure 18C It is along Figure 18A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0162] Reference Figures 18A to 18C The sacrificial growth layer 38 can be removed to form an initial support recess 39R. The initial support recess 39R can extend vertically in a first direction D1 and be spaced apart from each other in a second direction D2. The initial support recess 39R can expose the protruding edge 13E of the vertically arranged narrow strip 13N. The void filler 39A can be exposed through the initial support recess 39R.

[0163] Figure 19A This is a plan view showing the structure of the narrow horizontal plane to describe a method for removing the void filler 39A. Figure 19B It is along Figure 19AThe cross-sectional view of the structure cut by line A-A' is shown. Figure 19C It is along Figure 19A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0164] Reference Figures 19A to 19C The void filler 39A can be removed through the initial support recess 39R. The volume of the initial support recess 39R can expand while the void filler 39A is removed. The expanded initial support recess can become the support recess 40.

[0165] The support recesses 40 may extend vertically in a first direction D1 and be spaced apart from each other in a second direction D2. The support recesses 40 may expose the protruding edge 13E of the vertically arranged narrow strip 13N.

[0166] Figure 20A This is a plan view showing the structure of the horizontal plane of the narrow strip to describe the method used to cut the edge of the narrow strip 13N. Figure 20B It is along Figure 20A The cross-sectional view of the structure cut by line A-A' is shown. Figure 20C It is along Figure 20A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0167] Reference Figures 20A to 20C The protruding edge 13E of the narrow strip 13N can be cut through the support recess 40. Therefore, the protruding edge 13E of the narrow strip 13N may not be provided in the support recess 40. The flat-shaped edge 13F of the narrow strip 13N may be exposed in the support recess 40.

[0168] The support recess 40 can have a structure with pyramid-shaped recesses joined together.

[0169] Figure 21A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the first contact node 41. Figure 21B It shows along Figure 21A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 21C It is along Figure 21A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0170] Reference Figures 21A to 21CThe first contact node 41 can be formed on the flat-shaped edge 13F of the narrow wafer 13N. Forming the first contact node 41 can include selective epitaxial growth (SEG). For example, semiconductor material can be grown from the flat-shaped edge 13F of the narrow wafer 13N by selective epitaxial growth (SEG). Each first contact node 41 can include SEG Si. Because each narrow wafer 13N comprises single-crystal silicon, a silicon layer can be epitaxially grown along the crystal surface of the flat-shaped edge 13F of the narrow wafer 13N. The first contact node 41 can be formed on the narrow wafer 13N in the support recess 40. Each first contact node 41 can have a pyramid shape. The first contact nodes 41 can be spaced apart from each other.

[0171] Each first contact node 41 may include a dopant. When a silicon layer is grown using selective epitaxial growth (SEG), dopant can be doped in situ. Therefore, each first contact node 41 may be a doped epitaxial layer. Each first contact node 41 may include an N-type dopant as a dopant. The N-type dopant may include phosphorus, arsenic, antimony, or combinations thereof. The first contact node 41 may include a phosphorus-doped silicon epitaxial layer formed by selective epitaxial growth (SEG), i.e., a doped SEG-SiP.

[0172] Each first doped region 42 can be formed on one side of each sliver 13N. A thermal processing step can be performed to form the first doped region 42 so that the dopant can diffuse from the first contact node 41.

[0173] Figure 22A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming vertical conductors 44A and 44B. Figure 22B It shows along Figure 22A The cross-sectional view of the structure cut by line A-A' shown in the figure. Figure 22C It is along Figure 22A The cross-sectional view of the structure intercepted by line B-B' is shown.

[0174] Reference Figures 22A to 22C An ohmic contact layer 43 may be formed on the first contact node 41. Each ohmic contact layer 43 may include a metal silicide. Forming the ohmic contact layer 43 may include depositing a metal substrate on the first contact node 41 and performing a thermal treatment process on the metal substrate and the silicide reaction of the first contact node 41. The ohmic contact layer 43 may have a pyramid shape surrounding the first contact node 41.

[0175] Subsequently, vertical conductors 44A and 44B can be formed on the ohmic contact layer 43. The vertical conductors may include a first vertical conductor 44A and a second vertical conductor 44B horizontally spaced apart from each other. The first vertical conductor 44A and the second vertical conductor 44B can be coupled together to the first contact node 41 through the ohmic contact layer 43. The first vertical conductor 44A and the second vertical conductor 44B can be coupled together to a narrow strip 13N disposed along the first direction D1. The first vertical conductor 44A and the second vertical conductor 44B can extend vertically in the first direction D1. The first vertical conductor 44A and the second vertical conductor 44B may each comprise a metal base material. The first vertical conductor 44A and the second vertical conductor 44B may each comprise titanium nitride, tungsten, or a combination thereof.

[0176] Deposition and blanket etching processes can be performed on the vertical conductor material to form the first vertical conductor 44A and the second vertical conductor 44B.

[0177] The bottoms of the first vertical conductor 44A and the second vertical conductor 44B may contact the stop layer 11A. The stop layer 11A prevents bridging between the substrate 11 and the first vertical conductor 44A and the second vertical conductor 44B. The bottoms of the first vertical conductor 44A and the second vertical conductor 44B may be discontinuous. The first vertical conductor 44A and the second vertical conductor 44B may fill the support recess 40 while covering the ohmic contact layer 43.

[0178] The support 39 can surround the first vertical conductor 44A and the second vertical conductor 44B.

[0179] As described above, the support member 39 may include a support recess 40. A first contact node 41, an ohmic contact layer 43, and a first vertical conductor 44A and a second vertical conductor 44B may fill the support recess 40. The pyramid-shaped first contact node 41 may be electrically coupled to the narrow strip 13N, and the ohmic contact layer 43 may surround the first contact node 41. The first vertical conductor 44A and the second vertical conductor 44B may include a combination of pyramid-shaped protrusions. The pyramid-shaped protrusions of the first vertical conductor 44A and the second vertical conductor 44B may surround the first contact node 41. The ohmic contact layer 43 may be disposed between the pyramid-shaped protrusions of the first vertical conductor 44A and the second vertical conductor 44B and the first contact node 41. The first vertical conductors 44A, which are adjacent to each other in the third direction D3, may be spaced apart by the support member 39. The second vertical conductors 44B, which are adjacent to each other in the third direction D3, may be spaced apart by the support member 39.

[0180] Figure 23A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the second linear opening 46. Figure 23B It is along Figure 23AThe cross-sectional view of the structure cut by line A-A' is shown.

[0181] Reference Figure 23A and Figure 23B An inter-array dielectric layer 45 can be formed to fill the first linear opening 20 on the first vertical conductor 44A and the second vertical conductor 44B. The inter-array dielectric layer 45 can extend vertically in a first direction D1 and horizontally in a third direction D3. The first vertical conductor 44A and the second vertical conductor 44B, which are disposed adjacent to each other in a second direction D2, can be isolated by the inter-array dielectric layer 45. The inter-array dielectric layer 45 may include a dielectric material. The inter-array dielectric layer 45 may include silicon oxide, silicon nitride, an air gap, or a combination thereof.

[0182] Subsequently, the second linear sacrificial layer 19L can be removed. Therefore, the second linear opening 46 can be formed.

[0183] After the second linear opening 46 is formed, the first mold layer 12A can be selectively recessed through the second linear opening 46. The difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be used to selectively recess the first mold layer 12A. The first mold layer 12A can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a monocrystalline silicon layer, the silicon-germanium layer can be etched using an etchant or etching gas that is selective relative to the monocrystalline silicon layer.

[0184] Subsequently, the original body portion 13A can be recessed. A wet etching process or a dry etching process can be used to recess the original body portion 13A. The vertical thickness of the original body portion 13A can be reduced, as indicated by reference numeral "13S". In the following text, the original body portion with the reduced vertical thickness is referred to as "recessed portion 13S".

[0185] Each interbody recess 47 can be formed between vertically arranged recessed portions 13S.

[0186] Figure 24A This is a planar diagram showing the structure of the narrow sheet horizontal plane to describe the method for forming the nanosheet HL. Figure 24B It is along Figure 24A The cross-sectional view of the structure cut by line A-A' is shown.

[0187] Reference Figure 24A and 24B A third inter-unit dielectric layer 48 may be formed to fill the inter-substrate recess 47. Each third inter-unit dielectric layer 48 may include silicon oxide.

[0188] After forming the third inter-unit dielectric layer 48, a storage opening 49 can be formed by a horizontal recess in the recessed portion 13S. The storage opening 49 can be referred to as a "capacitor opening". Nanosheets HL can be formed by the horizontal recess in the recessed portion 13S. Each nanosheet HL can include a narrow sheet 13N and a wide sheet 13W. The wide sheet 13W of the nanosheet HL can refer to the remaining recessed portion 13S after the recess. The average vertical height of the wide sheet 13W of the nanosheet HL in the first direction D1 can be greater than the average vertical height of the narrow sheet 13N. The thickness of the wide sheet 13W of the nanosheet HL can gradually increase in the second direction D2. The horizontal length of the wide sheet 13W in the second direction D2 can be less than the horizontal length of the narrow sheet 13N. The wide sheet 13W of the nanosheet HL can have a fan-shaped shape. The wide sheet 13W can be referred to as a "fan-shaped sheet", and the narrow sheet 13N can be referred to as a "flat sheet".

[0189] To form nanosheets HL, each comprising a wide sheet 13W, the recessed portions 13S can be etched isotropically or anisotropically. One side of the wide sheet 13W, i.e., the side exposed by each storage opening 49, can have a flat shape. One side of the wide sheet 13W can have various shapes.

[0190] Each nanosheet HL may include a first edge and a second edge. The first edge may refer to the portion electrically coupled to the first vertical conductor 44A and the second vertical conductor 44B, the first contact node 41, and the ohmic contact layer 43, and the second edge may refer to the portion exposed by each storage opening 49.

[0191] Each storage opening 49 can be located between the third inter-cell dielectric layers 48.

[0192] In some embodiments, the horizontal recess of the recessed portion 13S for forming the wide sheet 13W can stop at the boundary region between the narrow sheet 13N and the wide sheet 13W.

[0193] Reference Figures 5A to 24B The narrow strip 13N can be formed by recessing a first portion of the second mold layer 13, and the wide strip 13W can be formed by recessing a second portion of the second mold layer 13. The wide strip 13W can be horizontally continuous from the narrow strip 13N.

[0194] Figure 25A This is a plan view showing the structure of the nanosheet horizontal plane to describe the method of forming the second contact node 50. Figure 25B It is along Figure 25A The cross-sectional view of the structure intercepted by line A-A' is shown.

[0195] Reference Figure 25A and Figure 25B Pre-cleaning can be performed on one side of each nanosheet HL, that is, on the surface of each wide sheet 13W.

[0196] Subsequently, a second contact node 50 can be formed on one side of the nanosheet HL, i.e., the wide wafer 13W. Forming the second contact node 50 can include selective epitaxial growth (SEG). For example, semiconductor material can be grown from the side of the wide wafer 13W via selective epitaxial growth (SEG). Each second contact node 50 can include SEG Si. Because each wide wafer 13W comprises single-crystal silicon, a silicon layer can be epitaxially grown along the crystal surface of the side of the wide wafer 13W.

[0197] Each second contact node 50 may include a dopant. When a silicon layer is grown using selective epitaxial growth (SEG), dopant can be doped in situ. Therefore, each second contact node 50 may be a doped epitaxial layer. Each second contact node 50 may include an N-type dopant as a dopant. The N-type dopant may include phosphorus, arsenic, antimony, or combinations thereof. The second contact node 50 may include a phosphorus-doped silicon epitaxial layer formed by selective epitaxial growth (SEG), i.e., a doped SEG SiP.

[0198] Because the second contact node 50 is formed using selective epitaxial growth (SEG), a gapless or seamless second contact node 50 can be formed. Because the second contact node 50 is formed using selective epitaxial growth (SEG), the process for forming the second contact node 50 can be simplified.

[0199] Each second contact node 50 can be disposed between the vertically stacked third inter-unit dielectric layers 48.

[0200] The second doped region 51 can be formed in the wide sheet 13W of the nanosheet HL. A thermal processing step can be performed to form the second doped region 51 so that the dopant can diffuse from the second contact node 50.

[0201] Each nanosheet HL may include a first doped region 42, a second doped region 51, and a channel 52. The channel 52 may be defined between the first doped region 42 and the second doped region 51. The first doped region 42 and the channel 52 may be formed in each narrow wafer 13N, and the second doped region 51 may be formed in each wide wafer 13W. A portion of each second doped region 51 may extend into the narrow wafer 13N. One side of each second doped region 51 of the nanosheet HL may be coupled to the channel 52, and the other side of each second doped region 51 of the nanosheet HL may be coupled to a second contact node 50.

[0202] In some embodiments, an ohmic contact layer comprising metal silicide may be further formed after the formation of the second contact node 50.

[0203] Figure 26A This is a plan view showing the structure of the nanosheet in a horizontal plane to describe the method of forming the first electrode 53. Figure 26B It is along Figure 26A The cross-sectional view of the structure intercepted by line A-A' is shown.

[0204] Reference Figure 26A and Figure 26B The first electrode 53 of the data storage element can be formed on the second contact node 50. Each first electrode 53 can have a horizontally oriented cylindrical shape. Each first electrode 53 can be disposed in a different storage opening 49. First electrodes 53 disposed adjacent to each other in the second direction D2 can be spaced apart from each other by the second linear opening 46. First electrodes 53 disposed adjacent to each other in the third direction D3 can be spaced apart from each other by the first inter-cell dielectric layer 23. First electrodes 53 disposed adjacent to each other in the first direction D1 can be spaced apart from each other by the third inter-cell dielectric layer 48. Forming the first electrode 53 may include depositing a metal material, a gap-filling sacrificial material, and an isolation metal material in the vertical / horizontal direction. The sacrificial material may include oxide or polysilicon.

[0205] Each first electrode 53 may include an internal space and multiple outer surfaces, and the internal space of the first electrode 53 may include multiple inner surfaces. The outer surfaces of the first electrode 53 may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode 53 may extend vertically in a first direction D1, and the horizontal outer surfaces of the first electrode 53 may extend horizontally in a second direction D2 or a third direction D3. The internal space of the first electrode 53 may be three-dimensional. The first electrode 53 may have a cylindrical shape.

[0206] In the outer surface of the first electrode 53, the vertical outer surface can be electrically coupled to the nanosheet HL and the second contact node 50.

[0207] The first electrode 53 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode 53 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or combinations thereof.

[0208] Figure 27A This is a plan view showing the structure of the narrow horizontal plane to describe the method of partially recessing the dielectric layer 48 between the third units. Figure 27B It is along Figure 27AThe cross-sectional view of the structure intercepted by line A-A' is shown.

[0209] Reference Figure 27A and Figure 27B This allows for a partial horizontal recess in the third inter-unit dielectric layer 48 (see reference numeral "54"). Consequently, the outer wall of the first electrode 53 can be partially exposed. Each first electrode 53 can have a semi-cylindrical shape. The depth of the horizontal recess in the third inter-unit dielectric layer 48 can be a depth that does not expose the second contact node 50. The semi-cylindrical shape of each first electrode 53 can include a cylindrical inner surface and a semi-cylindrical outer surface.

[0210] Figure 28A This is a plan view showing the structure of the narrow horizontal plane to describe the method of forming the second electrode 56. Figure 28B It is along Figure 28A The cross-sectional view of the structure intercepted by line A-A' is shown.

[0211] Reference Figure 28A and Figure 28B A dielectric layer 55 and a second electrode 56 may be sequentially formed on each of the first electrodes 53. The first electrode 53, the dielectric layer 55, and the second electrode 56 may be data storage elements (CAPs). The second electrodes 56 of the data storage elements (CAPs) may be merged together to form a common plate (PL).

[0212] The dielectric layer 55 and the second electrode 56 may be disposed on the cylindrical inner surface of the first electrode 53. A portion of the dielectric layer 55 and a portion of the second electrode 56 may extend to be disposed on the semi-cylindrical outer surface of the first electrode 53. The second electrode 56 may extend perpendicularly in the first direction D1.

[0213] The dielectric layer 55 may be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer 55 may include silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 55 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). The dielectric layer 55 may include ZA (ZrO2 / Al2O3) stacks, ZAZ (ZrO2 / Al2O3 / ZrO2) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HA (HfO2 / Al2O3) stacks, HAH (HfO2 / Al2O3 / HfO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, and HAHAH stacks. Stacked structures include (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2), HZAZH(HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2), ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2), HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2), or AHZAHZA(Al2O3 / HfO2 / ZrO2 / Al2O3 / HfO2 / ZrO2 / Al2O3).

[0214] The second electrode 56 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the second electrode 56 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, or combinations thereof. The second electrode 56 may also include a combination of metal-based materials and silicon-based materials. For example, the second electrode 56 may have a structure of titanium nitride, tungsten, and polycrystalline silicon stacked sequentially.

[0215] In some embodiments, a lower interface control layer may be further formed between the first electrode 53 and the dielectric layer 55 to mitigate leakage current. An upper interface control layer may be formed between the second electrode 56 and the dielectric layer 55. The lower and upper interface control layers may each comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium (Nb), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or combinations thereof. The lower and upper interface control layers may each comprise a single-layer or double-layer structure. For example, the upper interface control layer may comprise a stack of titanium oxide (TiO2) and niobium oxide (Nb2O5).

[0216] In some embodiments, this can be omitted. Figure 27B The recesses in the first inter-unit dielectric layer 23 and the third inter-unit dielectric layer 48. Then, refer to... Figure 28B A dielectric layer 55 and a second electrode 56 can be formed thereon. Therefore, a data storage element CAP with a concave shape can be formed.

[0217] According to the above embodiment, the first vertical conductor 44A and the second vertical conductor 44B corresponding to the bit lines can be formed by self-alignment with the support member 36 without the need for high aspect ratio etching. Therefore, a memory cell array comprising memory cells of the same size can be formed.

[0218] Furthermore, according to the above embodiment, since high aspect ratio etching is not performed to form the first vertical conductor 44A and the second vertical conductor 44B, the cost can be reduced.

[0219] According to various embodiments of this disclosure, vertical conductors can be formed by self-alignment with the support without the need for high aspect ratio etching.

[0220] According to various embodiments of this disclosure, a memory cell array comprising memory cells having the same size can be formed.

[0221] According to various embodiments of this disclosure, costs can be reduced because high aspect ratio etching is not performed to form vertical conductors.

[0222] While embodiments of the present disclosure have been described and illustrated with reference to specific examples and accompanying drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that those skilled in the art will recognize, based on this disclosure, that the various embodiments can be implemented in various ways through substitutions, changes, and modifications without departing from the spirit and / or scope of this disclosure and the appended claims. Moreover, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: A horizontally arranged switching element comprising a nanosheet and a horizontal wire surrounding the nanosheet; A pyramid-shaped first contact node is formed on the first edge of the horizontally arranged nanosheet; A horizontally arranged vertical conductor, which includes a pyramidal portion surrounding the first contact node and is coupled to the horizontally arranged nanosheet; A data storage element coupled to the second edge of the horizontally arranged nanosheet; and A support member surrounding the horizontally arranged vertical conductor.

2. The semiconductor device according to claim 1, wherein, The support member includes a plurality of support recesses, and the pyramidal portion of the vertical guide has a structure that fills the support recesses.

3. The semiconductor device according to claim 1, wherein, The support includes low-k materials, silicon carbide, silicon nitride, air gaps, or combinations thereof.

4. The semiconductor device according to claim 1, further comprising: A first spacer is disposed between the data storage element and the horizontal conductor and surrounds the nanosheet; and A second spacer is disposed between the vertical conductor and the horizontal conductor and surrounds the nanosheet.

5. The semiconductor device according to claim 4, wherein, The first edge of each nanosheet comprises a flat-shaped edge, and the first contact node comprises a selectively epitaxial growth layer grown from the flat-shaped edge.

6. The semiconductor device according to claim 1, wherein, Each of the first contact nodes includes a doped silicon epitaxial layer.

7. The semiconductor device of claim 1, further comprising an ohmic contact layer disposed between the vertical conductor and the first contact node and having a pyramid shape covering the first contact node.

8. The semiconductor device according to claim 1, wherein, Each of the nanosheets comprises: The first and second doped regions, which are horizontally spaced apart from each other, and A channel is formed between the first doped region and the second doped region.

9. The semiconductor device according to claim 1, wherein, The nanosheets include single-crystal silicon, oxide semiconductor materials, two-dimensional materials, or combinations thereof.

10. The semiconductor device according to claim 1, further comprising: A second contact node is formed between the second edge of the nanosheet and the data storage element.

11. The semiconductor device according to claim 10, wherein, Each of the second contact nodes includes a doped silicon epitaxial layer.

12. The semiconductor device according to claim 1, wherein, Each of the nanosheets comprises: Narrow strips, coupled to each of the vertical conductors; and A wide strip, coupled to each of the data storage elements, and having a thickness that gradually increases from the narrow strip toward the data storage element.

13. A method for manufacturing a semiconductor device, the method comprising: A stop layer is formed on the substrate; Narrow strips arranged horizontally and vertically are formed on the stop layer; A surrounding structure is formed, which surrounds portions of the horizontally and vertically arranged narrow strips and exposes the protruding shape edges of the narrow strips; A support member is formed including a support recess, the support recess simultaneously exposing the protruding shape edge of the vertically arranged narrow strip and separately exposing the protruding shape edge of the horizontally arranged narrow strip; The narrow strip is formed into a flat shape edge by cutting the protruding shape edge of the narrow strip; First contact nodes are formed on the flat-shaped edges of the horizontally and vertically arranged narrow strips; and A vertical conductor is formed, which is commonly coupled to the vertically arranged first contact node, individually coupled to the horizontally arranged first contact node, and formed in the support recess.

14. The method according to claim 13, wherein, The support member forming the support recess includes: A sacrificial growth layer is formed covering the protruding shape edges of the horizontally and vertically arranged narrow strips; The support member forms a portion that partially covers the sacrificial growth layer and exposes a portion of the sacrificial growth layer; and The support recess is formed by removing the sacrificial growth layer.

15. The method according to claim 14, wherein, The formation of the sacrificial growth layer includes selective epitaxial growth of a silicon-germanium layer.

16. The method according to claim 13, wherein, The support includes low-k materials, silicon carbide, silicon nitride, air gaps, or combinations thereof.

17. The method of claim 13, further comprising: An ohmic contact layer is formed on the first contact node before the vertical conductor is formed.

18. The method according to claim 13, wherein, The surrounding structure that forms the protruding shape edge of the narrow strip includes: A nanosheet dielectric layer is formed on the surface of the horizontally and vertically arranged narrow strips; A first spacer is formed on the nanosheet dielectric layer, the first spacer surrounding a first portion of the horizontally and vertically arranged narrow sheet; A horizontal guide is formed on the first spacer around the second portion of the horizontally arranged narrow strip; and A second spacer is formed on the horizontal guide wire, surrounding the third portion of the narrow strip arranged horizontally; The second spacer exposes the protruding edge of the narrow strip and a portion of the nanosheet dielectric layer on the protruding edge.

19. The method according to claim 13, wherein, Forming the horizontally and vertically arranged narrow strips on the stop layer includes: A horizontally and vertically arranged nanosheet target layer is formed on the stop layer; and The first portion of the nanosheet target layer is selectively recessed to form the horizontally and vertically arranged narrow sheets.

20. The method of claim 19, further comprising: After the vertical conductor is formed The second portion of the nanosheet target layer is selectively recessed to form wide sheets arranged horizontally and vertically. A second contact node is selectively formed from the side of the wide plate; and Data storage elements are formed, and the data storage elements are respectively coupled to the second contact node.

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