Floating gate type flash memory and manufacturing method thereof

Abstract

The invention discloses a floating gate type flash memory and a manufacturing method thereof, and belongs to the technical field of flash memorizers, and the manufacturing method of the floating gate type flash memory comprises the following steps: providing a substrate which is provided with a memory cell area and a peripheral logic circuit area; forming a light resistor on the peripheral logic circuit region, and etching the oxide in the storage unit region; forming a low-temperature oxide with a preset thickness on the storage unit region and the peripheral logic circuit region with the photoresist; and removing the light resistance and the low-temperature oxide on the peripheral logic circuit region after the low-temperature oxide of the storage unit region is subjected to wet etching, and reserving at least part of the low-temperature oxide on the source region of the storage unit device of the storage unit region. The low-temperature oxide is covered on the substrate again, and the low-temperature oxide is etched back, so that the residual low-temperature oxide in the source region and the drain region meets the requirement of subsequent etching.

Description

Technical Field

[0001] This invention relates to the field of flash memory technology, and in particular to a floating-gate flash memory and its manufacturing method. Background Technology

[0002] Flash memory can be classified according to the arrangement of circuits within the semiconductor chip. Vertically arranged flash memory is called NAND flash memory, and horizontally arranged flash memory is called NOR flash memory. NAND flash memory is easier to increase storage capacity and has a faster write speed, while NOR flash memory has a faster read speed. NOR flash memory has horizontally arranged storage cells, giving it a structure with a faster read speed than NAND flash memory and allowing it to determine the location of data more quickly. Split-gate (FG) flash memory technology is widely used in various embedded electronic products such as financial IC cards and automotive electronics. This type of flash memory can increase storage integration density, which helps save chip area and reduce manufacturing costs.

[0003] like Figure 1 As shown, in the 50nm Floating Gate NOR Flash process flow, a pad oxide layer 11, a floating gate dielectric layer 12, an ONO dielectric layer 13, and a control gate dielectric layer 14 are first stacked in the memory cell region 100. Multiple columnar structures are formed by etching. The substrate 10 between the columnar structures contains corresponding source and drain regions (not shown). Then, an oxide layer 30 is formed on the substrate 10. The required structure is formed on the polysilicon gate 16 of the peripheral logic circuit region 200 by etching the oxide layer 30. At this time, the oxide layer 30 in the memory cell region 100 is divided into source oxide 31 and drain oxide 32 with different widths by the columnar structures. In order to form the subsequent structure, the excess oxide layer 30 in the memory cell region 100 also needs to be removed. The process requires that the height of the source oxide 31 be kept above the ONO dielectric layer 13, while the drain oxide 32 needs to be completely removed by etching to avoid subsequent etching of the gate sidewall of the peripheral logic circuit region 200 and damage to the active region.

[0004] The conventional method for removing excess oxide layer 30 is, for example... Figure 2 As shown, photoresist 40 is arranged on top of the peripheral logic circuit region 200 and the source oxide 31. The drain oxide 32 is completely removed by etching. However, when the drain oxide 32 is etched, the source oxide 31 is also etched at the same time. Therefore, the drain oxide 32 is not completely removed, but the source oxide 31 has dropped below the ONO dielectric layer 13, or even been completely removed. This cannot meet the requirements of subsequent processes and is very likely to damage the active region when the gate sidewall of the peripheral logic region is etched again in the future.

[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a method for manufacturing a floating-gate flash memory to solve the problem that the source oxide is also etched when the drain oxide is etched.

[0007] To solve the above technical problems, the present invention provides a method for fabricating the gate dielectric layer of a floating-gate flash memory, comprising the following steps:

[0008] A substrate is provided, wherein the substrate has a memory cell area and a peripheral logic circuit area;

[0009] A memory cell device has been formed on the memory cell area, and a logic device has been formed on the peripheral logic circuit area; the memory cell area is covered with oxide, and the drain area size of the memory cell device is larger than the source area size of the memory cell device;

[0010] Photoresist is formed on the peripheral logic circuit area, and the oxide of the memory cell area is etched.

[0011] A low-temperature oxide layer of a predetermined thickness is formed on the memory cell area and the peripheral logic circuit area with photoresist;

[0012] After wet etching of the low-temperature oxide in the memory cell area, the photoresist and low-temperature oxide on the peripheral logic circuit area are removed, and at least a portion of the low-temperature oxide is retained on the source region of the memory cell device in the memory cell area.

[0013] Preferably, the memory cell device includes, from bottom to top, a pad oxide layer, a floating gate dielectric layer, an ONO dielectric layer, and a control gate dielectric layer.

[0014] Preferably, during wet etching of the low-temperature oxide, the low-temperature oxide on the drain region of the memory cell device is removed, and the top surface of the remaining low-temperature oxide on the source region of the memory cell device is etched above the top surface of the ONO dielectric layer.

[0015] Preferably, a low-temperature oxide of a predetermined thickness is formed on the memory cell area and the peripheral logic circuit area with photoresist to completely fill the openings of the source area between the memory cell devices, while the openings of the drain area between the memory cell devices are not completely filled.

[0016] Preferably, the preset thickness of the low-temperature oxide is greater than half the height of the opening between the memory cell devices that exposes the source region.

[0017] Preferably, the preset thickness of the low-temperature oxide is less than half the height of the opening between the memory cell devices that exposes the drain area.

[0018] Preferably, the step of forming the oxide covering the memory cell region includes: sequentially forming a sidewall layer and an oxide layer on the memory cell device and the polysilicon gate, etching the oxide layer in the peripheral logic circuit region, forming sidewall oxides on both sides of the polysilicon gate, and forming oxides on the memory cell region.

[0019] Preferably, when etching the oxide layer in the peripheral logic circuit area, a portion of the oxide layer on top of the control gate dielectric layer is also removed.

[0020] The present invention also provides a floating-gate flash memory, which is manufactured using the floating-gate flash memory manufacturing method described above.

[0021] In the floating-gate flash memory and its fabrication method provided by this invention, by removing all oxides remaining in the memory cell region, re-covering the substrate with low-temperature oxides, and etching the low-temperature oxides, the morphology of the low-temperature oxides on the source and drain regions differs due to the size differences between the source and drain regions of the memory cell devices. Therefore, etching the low-temperature oxides ensures that the remaining low-temperature oxides meet the requirements of subsequent etching, i.e., the top surface of the low-temperature oxides on the source region can be controlled above the ONO dielectric layer, and the low-temperature oxides in the drain region can be removed. Furthermore, the process segment after the formation of the memory cell region and logic region devices and before the contact holes is optimized, so that an oxide of a predetermined thickness can be retained on the source region of the memory cell device in the memory cell region, improving the process window of this segment, reducing the possibility of leakage current in the memory cell device, and improving the stability of the memory cell device. Attached Figure Description

[0022] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0023] Figure 1 These are schematic diagrams of the structures of oxides in various locations in the prior art;

[0024] Figure 2 A schematic diagram of the structure for treating drain oxide in the prior art;

[0025] Figure 3 This is an electron microscope image of the source oxide in the prior art;

[0026] Figure 4 This is an electron microscope image of the drain oxide in the prior art;

[0027] Figure 5This is a schematic diagram of the oxide layer structure according to an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the structure of oxides in each region according to an embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of the structure for removing oxides according to an embodiment of the present invention;

[0030] Figure 8 This is a schematic diagram of the structure of a low-temperature oxide deposition according to an embodiment of the present invention;

[0031] Figure 9 This is a schematic diagram illustrating the removal of excess low-temperature oxides according to an embodiment of the present invention;

[0032] Figure 10 This is an execution flowchart of an embodiment of the present invention.

[0033] In the attached image:

[0034] 100. Storage cell area; 200. Peripheral logic circuit area.

[0035] 10. Substrate; 11. Pad oxide layer; 12. Floating gate dielectric layer; 13. ONO dielectric layer; 14. Control gate dielectric layer; 15. Gate oxide layer; 16. Polysilicon gate; 20. Sidewall layer; 30. Oxide layer; 31. Source oxide; 32. Drain oxide; 33. Sidewall oxide; 40. Photoresist; 50. STI isolation structure; 60. Low-temperature oxide; 61. Remaining low-temperature oxide. Detailed Implementation

[0036] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0037] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] Studies have found that, for example Figure 1 As shown, after etching the oxide layer 30, the oxide layer 30 in the memory cell region 100 is divided into source oxide 31 and drain oxide 32 with different widths by a columnar structure. In the peripheral logic circuit region 200, the oxide layer 30 forms sidewall oxide 33 attached to the polysilicon gate 16. The oxide layer 30 has a certain thickness. Since the thicknesses of the source oxide 31 and drain oxide 32 in the opening are similar, for example... Figure 3 and Figure 4 As shown, the thickness of the source oxide 31 is 261 nm, and the thickness of the drain oxide 32 is 221 nm. In existing technologies, a photoresist 40 is often used to cover the source oxide 31, and the drain oxide 32 is etched down to below the ONO dielectric layer 13, while the source oxide 31 remains above the ONO dielectric layer 13. However, this etching method also damages the source oxide 31, causing its top surface to drop below the ONO dielectric layer 13.

[0039] Further research found that, for example Figure 2 As shown, after covering the peripheral logic circuit area 200 and the source oxide 31 with photoresist 40, under the condition of BHF (buffered hydrogen fluoride: NH4F+HF+H2O) treatment for 240s, the drain oxide 32 still has about 12 nanometers remaining. However, at this time, the height of the source oxide 31 is already lower than the surface of the ONO dielectric layer 13, which does not meet the process requirements. Under the condition of BHF treatment for 300s, both the source oxide 31 and the drain oxide 32 drop below the ONO dielectric layer 13, which still does not meet the process requirements.

[0040] Based on the above research, it can be seen that prolonged BHF treatment and photoresist 40 stripping during BHF treatment will cause the reagent to continuously etch the source oxide 31, damaging the source oxide 31.

[0041] Based on this, the present invention mainly optimizes the process segment after the formation of the memory cell area and logic area devices and before the contact holes, so that the source area of ​​the memory cell device in the memory cell area can retain an oxide of a preset thickness, improve the process window of this process segment, reduce the possibility of leakage current of the memory cell device, and improve the stability of the memory cell device.

[0042] For details, please refer to Figures 5-10 This is a schematic diagram of an embodiment of the present invention. Figure 10 As shown, a method for manufacturing a floating-gate flash memory includes the following steps:

[0043] S1, a substrate 10 is provided, the substrate 10 having a storage cell area 100 and a peripheral logic circuit area 200.

[0044] S2, a memory cell device has been formed on the memory cell area 100, and a logic device has been formed on the peripheral logic circuit area 200; the memory cell area 100 is covered with oxide, and the drain area size of the memory cell device is larger than the source area size of the memory cell device.

[0045] The memory cell device includes a pad oxide layer 11, a floating gate dielectric layer 12, an ONO dielectric layer 13, and a control gate dielectric layer 14, arranged sequentially from bottom to top. When forming the memory cell device, the pad oxide layer 11, the floating gate dielectric layer 12, the ONO dielectric layer 13, and the control gate dielectric layer 14 are sequentially deposited on the memory cell region 100, and etched to the surface of the substrate 10 to form an opening for exposing the active region. The CD value (critical dimension) of the drain opening is greater than the CD value of the source opening.

[0046] In this process, the control gate dielectric layer 14, the ONO dielectric layer 13, the floating gate dielectric layer 12, and the pad oxide layer 11 are etched up to the substrate 10 to form multiple pillar-shaped structures, exposing the source and drain regions between the pillar-shaped structures. The pad oxide layer 11 is made of silicon oxide, the floating gate dielectric layer 12 and the control gate dielectric layer 14 are both made of polysilicon, and the ONO dielectric layer 13 includes silicon oxide, silicon nitride and silicon oxide arranged sequentially.

[0047] The logic device includes a polysilicon gate 16.

[0048] In one embodiment, before covering the memory cell region 100 and the peripheral logic circuit region 200 with the sidewall layer 20, polysilicon is deposited in the peripheral logic circuit region 200 and etched to the substrate 10 to form a polysilicon gate 16, and a gate oxide layer 15 is also deposited before depositing the polysilicon.

[0049] The steps for forming the oxide covering the memory cell region 100 include: sequentially forming a sidewall layer 20 and an oxide layer 30 on the memory cell device and the polysilicon gate 16; etching the oxide layer 30 in the peripheral logic circuit region 200; forming sidewall oxides 33 on both sides of the polysilicon gate 16; and forming oxide on the memory cell region 100. The peripheral logic circuit region 200 also includes multiple STI isolation structures 50.

[0050] like Figure 5 As shown, a sidewall layer 20 is applied to the memory cell region 100 and the peripheral logic circuit region 200, and an oxide layer 30 is deposited on the memory cell region 100 and the peripheral logic circuit region 200. Furthermore, before forming the sidewall layer 20, a plurality of STI isolation structures 50 are formed in the peripheral logic circuit region 200. Additionally, when etching the oxide layer 30 in the peripheral logic circuit region 200, a portion of the oxide layer 30 on top of the control gate dielectric layer 14 is also removed.

[0051] Understandably, the oxide layer 30 is made of silicon oxide. The sidewall layer 20 can be made of silicon nitride or doped silicon dioxide, silicon nitride, or other known sidewall materials; no specific limitation is made here.

[0052] For example, the oxide layer 30 in the peripheral logic circuit region 200 is etched to form a sidewall oxide 33 on the polysilicon gate 16, such as... Figure 6 As shown, the residual oxide layer 30 in the storage cell area 100 is removed, as follows: Figure 7 As shown.

[0053] It should be noted that after etching the oxide layer 30 in the peripheral logic circuit region 200, forming the sidewall oxide 33 on the polysilicon gate 16, and covering the peripheral logic circuit region 200 with photoresist 40, the remaining oxide layer 30 in the memory cell region 100 is then removed. Figure 7 As shown, photoresist 40 can be first applied to the peripheral logic circuit area 200 to protect it, and then all oxide layers 30 located in the memory cell area 100 can be removed.

[0054] In one embodiment, when etching the oxide layer 30 in the peripheral logic circuit region 200, a portion of the oxide layer 30 on top of the control gate dielectric layer 14 is also removed. After depositing the oxide layer 30, when forming the sidewall oxide 33 of the polysilicon gate 16, photolithography is performed, for example, using a mask similar to that in the prior art, to form a photoresist 40 (not shown) on the top surface of the oxide in the polysilicon gate 16 and the opening, thereby consuming a portion of the oxide layer 30 in the memory cell region 100. Similarly, the source oxide 31 and drain oxide 32 are formed for complete removal in subsequent processes. Alternatively, when etching the oxide layer 30 in the peripheral logic circuit region 200, the oxide layer 30 in the memory cell region 100 is consumed simultaneously, eliminating the need to fabricate a photoresist 40, such as... Figure 6 As shown, this is to thoroughly remove residual source oxide 31 and drain oxide 32 in subsequent processes.

[0055] S3, a photoresist 40 is formed on the peripheral logic circuit area 200, and the oxide of the memory cell area 100 is etched. Specifically, when removing the residual oxide layer 30 in the memory cell area 100, a layer of photoresist 40 is used to protect the peripheral logic circuit area 200. After removing the residual oxide layer 30 in the memory cell area 100, the photoresist 40 damaged by etching is also removed, and a new photoresist 40 is applied to the peripheral logic circuit area 200.

[0056] Specifically, in the fabrication of flash memory, the conventional practice is to fabricate the cell active area (CAA) and the peripheral logic area (PAA) of the flash memory cell separately, using two sets of photomasks, for example... Figure 1 and Figure 2As shown, photoresist 40 is formed on the memory cell area 100 and the peripheral logic circuit area 200, respectively, and the photoresist 40 in the memory cell area 100 is etched to meet the process requirements of the memory cell area 100 and the peripheral logic circuit area 200. In the process disclosed in this invention, photoresist 40 is only set on the peripheral logic circuit area 200, saving one set of photomasks. It is not necessary to control the CD value of the photoresist 40 in the memory cell area 100. The photoresist 40 covers all peripheral logic circuit areas 200, and the photolithography process can be changed from the KrF process (photoresist process) to an in-line process, thereby reducing costs.

[0057] S4, a low-temperature oxide 60 of a predetermined thickness is formed on the storage cell area 100 and the peripheral logic circuit area 200 with photoresist 40.

[0058] In one embodiment, the low-temperature oxide 60 here is an LTO film, which stands for Low Temperature Oxide, primarily composed of silicon dioxide (SiO2). It has important applications in semiconductor manufacturing and lithium-ion batteries. LTO films are typically prepared using processes such as low-temperature chemical vapor deposition (LPCVD), exhibiting good uniformity and electrical insulation properties. During its preparation, doping with phosphorus or boron can improve the film's characteristics, making it suitable for the manufacture of various electronic devices.

[0059] The openings above the source and drain regions are filled differently due to their size differences. A low-temperature oxide 60 of a predetermined thickness is formed on the memory cell region 100 and the peripheral logic circuit region 200 with photoresist 40 to completely fill the openings exposing the source region between the memory cell devices, while the openings exposing the drain region between the memory cell devices are not completely filled. Figure 8 As shown, a low-temperature oxide 60 of a predetermined thickness is formed on the memory cell region 100 to fill the opening above the source region. Due to the size difference between the openings above the source and drain regions, the low-temperature oxide 60 can completely fill the opening in the source region. The low-temperature oxide 60 on the source region is partially recessed along the sidewall. Therefore, during subsequent etching of the low-temperature oxide 60, the height of the oxide in the source and drain regions is simultaneously reduced, achieving the effect of controlling the height of the low-temperature oxide 60 on the source region above the ONO dielectric layer 13, controlling the low-temperature oxide 60 in the drain region below the ONO dielectric layer 13, or even removing the low-temperature oxide 60 in the drain region.

[0060] In one embodiment, the predetermined thickness of the low-temperature oxide 60 is greater than half the height of the opening exposed in the source region between the memory cell devices. This ensures that, after filling, the narrow source region opening can be completely filled by the low-temperature oxide 60.

[0061] In one embodiment, the preset thickness of the low-temperature oxide 60 is less than half the height of the opening exposing the drain region between the memory cell devices. This ensures that even after the larger drain opening is filled, it still has a recess, allowing the low-temperature oxide 60 to shrink along the height direction of the recessed surface during subsequent etching. It is understood that the source and drain sides of the columnar memory cell devices have different morphologies due to different etching processes, which can be referred to... Figure 3 and Figure 4 The morphology of the opening in the middle region shows that the opening height in the source region is slightly smaller than that in the drain region.

[0062] Even better, the thickness of the low-temperature oxide 60 is greater than half the size of the source region opening and less than half the size of the drain region opening. The ratio of the bottom width of the source region opening to the drain region opening is 36.3:107.8.

[0063] In the preceding process, a photoresist 40 is formed to protect the peripheral logic circuit area 200. When a low-temperature oxide 60 of a predetermined thickness is formed on the sidewall layer 20 in the memory cell area 100, the low-temperature oxide 60 is simultaneously covered on the photoresist 40, such as... Figure 8 As shown.

[0064] More preferably, the preset thickness of the low-temperature oxide 60 is 35 nm. After etching, the second preset thickness of the low-temperature oxide 60 above the source region is 261 nm.

[0065] S5, after wet etching of the low-temperature oxide 60 of the memory cell region 100, the photoresist 40 and the low-temperature oxide 60 on the peripheral logic circuit region 200 are removed, and at least a portion of the low-temperature oxide 60 is retained on the source region of the memory cell device in the memory cell region 100.

[0066] During wet etching of the low-temperature oxide 60, the low-temperature oxide 60 on the drain region of the memory cell device is removed, and the top surface of the remaining low-temperature oxide 61 on the source region of the memory cell device is etched above the top surface of the ONO dielectric layer 13. The low-temperature oxide 60 is etched using BHF (buffered hydrogen fluoride: NH4F+HF+H2O) or HF. The low-temperature oxide 60 is etched isotropically to ensure that the remaining low-temperature oxide 61 in both the source and drain regions has the required thickness.

[0067] Due to the size difference between the source and drain regions, the opening above the source region is completely filled by the low-temperature oxide 60. The low-temperature oxide 60 above the source and drain regions has different thicknesses. The thickness of the low-temperature oxide 60 in the memory cell region 100 is reduced simultaneously by isotropic wet etching, ensuring that the low-temperature oxide 60 on the source and drain regions has different thicknesses after etching.

[0068] More preferably, during isotropic etching of the low-temperature oxide 60, the low-temperature oxide 60 on the drain region is removed, and the top surface of the remaining low-temperature oxide 61 on the source region is etched above the top surface of the ONO dielectric layer 13.

[0069] For example, the thickness of the low-temperature oxide 60 is 35 nm. The low-temperature oxide 60 has a height of 221 nm at the drain and a height of 261 nm at the source. After wet isotropic etching of the low-temperature oxide 60 to clean the low-temperature oxide 60 on the drain, there will still be residual low-temperature oxide 61 in the area above the ONO dielectric layer 13 at the source.

[0070] Specifically, during the back etching of the low-temperature oxide 60, the low-temperature oxide 60 on the drain region is completely removed, and the top surface of the low-temperature oxide 60 in the source region is etched above the top surface of the ONO dielectric layer 13. Clearly, if the low-temperature oxide 60 in the source region is higher than the ONO dielectric layer 13, all the low-temperature oxide 60 in the drain region can be removed. Furthermore, during the isotropic etching of the low-temperature oxide 60, the low-temperature oxide 60 on the photoresist 40 is simultaneously etched away. After the isotropic etching of the low-temperature oxide 60, the photoresist 40 is also removed. Figure 9 As shown, the photoresist 40 and low-temperature oxide 60 at the top of the peripheral logic circuit area 200 are also removed.

[0071] In one embodiment, after isotropic etching of the low-temperature oxide 60, the sidewall oxide 33 is etched back, and the remaining low-temperature oxide 61 protects the active region, preventing damage to the active region caused by etching. Before depositing the low-temperature oxide 60 in this invention, the sidewall oxide 33 of the polysilicon gate 16 is formed in the peripheral logic circuit region 200 by depositing the oxide layer 30 and performing dry etching. The low-temperature oxide 60 retains sufficient oxide in the source region to prevent damage to the active region in subsequent steps.

[0072] Based on the same technical concept, the present invention also provides a floating-gate flash memory, manufactured using the floating-gate flash memory manufacturing method described above. By removing all oxide layers 30 remaining in the memory cell region 100, an LTO film 60 is re-covered on the substrate 10. Due to the differences in the openings of the columnar structure, the LTO film 60 forms a recess along the sidewall of the first type of opening in the drain region, while the second type of opening on the source side is completely filled due to the different CD values. The LTO film 60 is etched back isotropically, thereby controlling the top surface of the LTO film 60 on the source region to be above the ONO dielectric layer 13, and removing the LTO film 60 in the drain region.

[0073] In the floating-gate flash memory and its gate dielectric layer sidewall oxide etching method provided by the present invention, by removing all oxide layers 30 remaining in the memory cell region 100, a low-temperature oxide 60 is re-covered on the substrate 10. Since the source and drain regions are exposed through openings between the columnar memory cell devices, and the sizes of the source and drain regions differ, the low-temperature oxide 60 forms a recess along the drain region sidewall, while the source region is completely filled due to the different CD values. The low-temperature oxide 60 is etched isotropically back, thereby controlling the height of the low-temperature oxide 60 on the source region to be above the ONO dielectric layer 13, and removing the low-temperature oxide 60 from the drain region. Furthermore, since there is no need to set photoresist 40 in the memory cell region 100, a photomask is saved, and there is no need to control the CD value of the photoresist 40 in the memory cell region 100, thus reducing the process cost.

[0074] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a floating-gate flash memory, characterized in that, Includes the following steps: A substrate is provided, wherein the substrate has a memory cell area and a peripheral logic circuit area; A memory cell device has been formed on the memory cell area, and a logic device has been formed on the peripheral logic circuit area; the memory cell area is covered with oxide, and the drain area size of the memory cell device is larger than the source area size of the memory cell device; Photoresist is formed on the peripheral logic circuit area, and the oxide of the memory cell area is etched. A low-temperature oxide layer of a predetermined thickness is formed on the memory cell area and the peripheral logic circuit area with photoresist; After wet etching of the low-temperature oxide in the memory cell area, the photoresist and low-temperature oxide on the peripheral logic circuit area are removed, and at least a portion of the low-temperature oxide is retained on the source region of the memory cell device in the memory cell area.

2. The method for manufacturing a floating-gate flash memory according to claim 1, characterized in that, The memory cell device includes, from bottom to top, a pad oxide layer, a floating gate dielectric layer, an ONO dielectric layer, and a control gate dielectric layer.

3. The method for manufacturing a floating-gate flash memory according to claim 2, characterized in that, During wet etching of the low-temperature oxide, the low-temperature oxide on the drain region of the memory cell device is removed, and the top surface of the remaining low-temperature oxide on the source region of the memory cell device is etched above the top surface of the ONO dielectric layer.

4. The method for manufacturing a floating-gate flash memory according to claim 1, characterized in that, A low-temperature oxide of a predetermined thickness is formed on the memory cell area and the peripheral logic circuit area with photoresist to completely fill the openings of the source area between the memory cell devices, while the openings of the drain area between the memory cell devices are not completely filled.

5. In the method for manufacturing a floating-gate flash memory according to claim 4, the preset thickness of the low-temperature oxide is greater than half the height of the opening between the memory cell devices exposing the source region.

6. In the method for manufacturing a floating-gate flash memory according to claim 4, the preset thickness of the low-temperature oxide is less than half the height of the opening exposing the drain area between the memory cell devices.

7. The method for fabricating a floating-gate flash memory according to claim 2, wherein the logic device includes a polysilicon gate, and the step of forming the oxide covering the memory cell region includes: A sidewall layer and an oxide layer are sequentially formed on the memory cell device and the polysilicon gate. The oxide layer in the peripheral logic circuit region is etched. Sidewall oxides are formed on both sides of the polysilicon gate, and oxides are formed on the memory cell region.

8. The method for manufacturing a floating-gate flash memory according to claim 7, characterized in that, When etching the oxide layer in the peripheral logic circuit area, a portion of the oxide layer on top of the control gate dielectric layer is also removed.

9. A floating-gate flash memory, characterized in that, It is manufactured using the method for fabricating a floating-gate flash memory as described in any one of claims 1-8.

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