Shielded gate trench device and method of manufacturing the same

Abstract

The application provides a shield gate trench type device and a manufacturing method thereof. A first gate oxide layer of the shield gate trench structure covers a bottom of a trench and partially extends to a sidewall of the shield gate trench. A second gate oxide layer is connected with the first gate oxide layer and covers a sidewall of the trench near a top area. A first insulating medium layer is arranged on the first gate oxide layer, and a height of the first gate oxide layer on the sidewall of the shield gate trench is higher than that of the first insulating medium layer, so that the first insulating medium layer and the first gate oxide layer form a first step structure. A second insulating medium layer is bridged on a mesa of the first step structure to form a structure wrapping a shield gate with the first insulating medium layer. A third insulating medium layer covers a top of the trench. The application can effectively reduce the temperature sensitivity of a threshold voltage.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a shielded gate trench device and its fabrication method. Background Technology

[0002] Insulated-gate field-effect transistors (MOSFETs) are widely used in various power systems due to their advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance, and good frequency response. In various high-stress systems, power MOSFETs are required to have lower conduction losses and the ability to operate for longer periods under high voltage and high current, meaning they must have high reliability and a large safe operating area. Shielded-gate MOSFETs (SGT MOSFETs) are widely used in low- and medium-voltage ionization systems due to their excellent specific on-resistance and switching figure of merit. However, the thermal instability of SGTs becomes increasingly prominent due to the increase in channel density and transconductance. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention proposes a shielded gate trench device and its manufacturing method, which mainly solves the thermal instability problem of existing SGT devices.

[0004] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0005] This application provides a shielded trench type device, including:

[0006] A semiconductor substrate, a shielding gate trench structure disposed in the semiconductor substrate, and a source structure disposed in the top region of the shielding gate trench structure;

[0007] The shielding trench structure includes: a first gate oxide layer, a second gate oxide layer, a first insulating dielectric layer, a second insulating dielectric layer, a third insulating dielectric layer, a shielding grid, and a control grid disposed within the trench; the first gate oxide layer covers the bottom of the trench and extends partially to the sidewall of the shielding trench; the second gate oxide layer is connected to the first gate oxide layer and covers the area near the top of the sidewall of the trench; the first insulating dielectric layer is disposed on the first gate oxide layer, and the height of the first gate oxide layer on the sidewall of the shielding trench is higher than that of the first insulating dielectric layer, such that the first insulating dielectric layer and the first gate oxide layer form a first step structure; the second insulating dielectric layer spans across the platform of the first step structure to form a structure that wraps around the shielding grid with the first insulating dielectric layer; the third insulating dielectric layer covers the top of the trench; wherein a gap is left between the second insulating dielectric layer and the first gate oxide layer, the control grid fills the gap and the area near the top of the trench, and the thickness of the first gate oxide layer is different from the thickness of the second gate oxide layer.

[0008] In one embodiment of this application, the thickness of the first gate oxide layer is 1-5 times the thickness of the second gate oxide layer, or the thickness of the second gate oxide layer is 1-5 times the thickness of the first gate oxide layer.

[0009] In one embodiment of this application, the thickness of the thicker gate oxide layer in the first gate oxide layer and the second gate oxide layer is determined by the threshold voltage and the doping concentration of the body region in the source structure.

[0010] In one embodiment of this application, the first insulating dielectric layer and the second insulating dielectric layer form a second stepped structure. The side of the first insulating dielectric layer that contacts the control gate serves as the first platform of the second stepped structure, and the side of the second insulating dielectric layer that is away from the shielding gate serves as the second platform of the second stepped structure. Thus, relative to the bottom of the shielding gate trench, the first platform is lower than the second platform.

[0011] In one embodiment of this application, the semiconductor substrate layer includes: a drain metal layer, a heavily doped second conductivity type drain region, and a lightly doped second conductivity type drift region stacked sequentially, wherein the shielding gate trench structure is disposed on the side of the lightly doped second conductivity type drift region away from the drain metal layer.

[0012] In one embodiment of this application, the source structure includes a moderately doped first conductivity type body region, a heavily doped first conductivity type ohmic contact region, a heavily doped second conductivity type source region, and a source metal layer; the moderately doped first conductivity type body region is disposed on the side of the lightly doped second conductivity type drift region away from the heavily doped second conductivity type drain region; the heavily doped first conductivity type ohmic contact region and the heavily doped second conductivity type source region are disposed on the moderately doped first conductivity type body region and located on the side of the shielding gate trench structure, and the heavily doped second conductivity type source region is disposed on the side close to the shielding gate trench; the source metal layer covers the top of the shielding gate structure and is electrically connected to the heavily doped first conductivity type ohmic contact region and the heavily doped second conductivity type source region, and the side of the moderately doped first conductivity type body region close to the lightly doped second conductivity type drift region is located between the first mesa and the second mesa.

[0013] In one embodiment of this application, the material of the shielded trench device includes silicon, silicon carbide, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.

[0014] In one embodiment of this application, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type.

[0015] In one embodiment of this application, the concentration of lightly doped impurities is ≤1e16cm-3, the concentration of moderately doped impurities is ∈(1e16cm-3,1e18cm-3], and the concentration of heavily doped impurities is >1e18cm-3.

[0016] This application also provides a method for fabricating a shielded gate trench structure device, comprising: providing a semiconductor substrate layer and forming a trench in the semiconductor substrate layer; growing a first gate oxide layer in the trench and depositing a first insulating dielectric layer on the first gate oxide layer; depositing a shielded gate polycrystalline material on the first insulating dielectric layer; depositing a mask material and forming a shielded gate and an active region by exposure etching, and then removing the mask; etching a portion of the first gate oxide layer and the first insulating dielectric layer from top to bottom along the inner wall of the trench, and thermally oxidizing and growing a second gate oxide layer inside the trench, the second gate oxide layer being in contact with the first gate oxide layer; growing a second insulating dielectric layer, the second insulating dielectric layer being in contact with the first gate oxide layer. On the mesa of the first stepped structure formed by the gate oxide layer and the first insulating dielectric layer, a structure is formed with the first insulating dielectric layer to enclose the shielding gate; a gate polycrystalline material is deposited in the trench to form a control gate filling the trench; ion implantation and push-junction are performed in the active region to form a moderately doped first conductivity type body region and a heavily doped second conductivity type source region; a third insulating dielectric layer is formed covering the active region and the trench after surface oxidation and passivation; contact holes are photolithographically etched at the position of the third insulating dielectric layer corresponding to the active region, and ohmic doping and annealing are performed to form a heavily doped first conductivity type ohmic contact region; metal is deposited to form a source metal layer, and source pads and gate pads are formed by photolithography.

[0017] As described above, the present invention provides a shielding trench type device and its manufacturing method, which have the following beneficial effects.

[0018] This application increases the proportion of thin gate oxide portion in the trench gate structure by using a first gate oxide layer and a second gate oxide layer with different thicknesses, thereby reducing the temperature sensitivity of the threshold voltage and improving the thermal instability of the device. Attached Figure Description

[0019] Figure 1 This is a cross-sectional structural diagram of a shielding trench structure device in one embodiment of this application.

[0020] Figure 2 This is a cross-sectional structural diagram of a shielding grid trench structure device in another embodiment of this application.

[0021] Figure 3 This is a schematic flowchart illustrating the fabrication method of a shielding trench device according to one embodiment of this application.

[0022] Figures 4-17 This is a schematic diagram of the device structure corresponding to each step in the fabrication method of the shielding trench type device in one embodiment of this application.

[0023] Explanation of icon numbers:

[0024] 1-Drain metal layer, 2-Heavily doped second conductivity type drain region, 3-Lightly doped second conductivity type drift region, 4-First gate oxide layer, 5-First insulating dielectric layer, 6-Shielding gate, 7-Second insulating dielectric layer, 8-Second gate oxide layer, 9-Control gate; 10-Mediumly doped first conductivity type body region, 11-Heavily doped second conductivity type source region, 12-Heavily doped first conductivity type ohmic contact region, 13-Third insulating dielectric layer, 14-Source metal layer. Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0026] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] The inventor discovered through research that:

[0028] Studies on the thermal instability of MOSFETs show that the thermal instability and SOA of the device can be optimized from two aspects: (1) One direction is to reduce the drain current corresponding to the zero temperature point and reduce the width of the interval where thermal instability occurs, which can be achieved by increasing the channel length and decreasing the channel width; (2) The other direction is to reduce the temperature sensitivity of the threshold voltage, which can be achieved mainly by reducing the bulk concentration and reducing the oxide layer thickness.

[0029] This application improves the thermal instability of devices by reducing the temperature sensitivity of the threshold voltage. The technical solution of this application will be described in detail below with reference to specific embodiments.

[0030] Please see Figure 1 , Figure 1 This is a cross-sectional view of a shielded gate trench structure device according to an embodiment of this application. The device includes: a semiconductor substrate layer, a shielded gate trench structure disposed in the semiconductor substrate layer, and a source structure disposed in the top region of the shielded gate trench structure;

[0031] The shielding trench structure includes: a first gate oxide layer, a second gate oxide layer, a first insulating dielectric layer, a second insulating dielectric layer, a third insulating dielectric layer, a shielding grid, and a control grid disposed within the trench; the first gate oxide layer covers the bottom of the trench and extends partially to the sidewall of the shielding trench; the second gate oxide layer is connected to the first gate oxide layer and covers the area near the top of the sidewall of the trench; the first insulating dielectric layer is disposed on the first gate oxide layer, and the height of the first gate oxide layer on the sidewall of the shielding trench is higher than that of the first insulating dielectric layer, such that the first insulating dielectric layer and the first gate oxide layer form a first step structure; the second insulating dielectric layer spans across the platform of the first step structure to form a structure that wraps around the shielding grid with the first insulating dielectric layer; the third insulating dielectric layer covers the top of the trench; wherein a gap is left between the second insulating dielectric layer and the first gate oxide layer, the control grid fills the gap and the area near the top of the trench, and the thickness of the first gate oxide layer is different from the thickness of the second gate oxide layer. Figure 1 This is the case where the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer. Figure 2 This refers to the case where the thickness of the first gate oxide layer is less than the thickness of the second gate oxide layer.

[0032] In one embodiment, the thickness of the first gate oxide layer is 1-5 times the thickness of the second gate oxide layer, or the thickness of the second gate oxide layer is 1-5 times the thickness of the first gate oxide layer.

[0033] In one embodiment of this application, the thickness of the thicker gate oxide layer in the first and second gate oxide layers is determined by the threshold voltage and the doping concentration of the body region in the source structure. Since the device threshold voltage depends on the thicker oxide layer portion, which is more difficult to turn on, the thinner gate oxide portion does not affect the device threshold voltage. The thickness t of the thicker gate oxide layer is... ox From the threshold voltage V TH Doping concentration N in the bulk region A Sure.

[0034] In one embodiment of this application, the first insulating dielectric layer and the second insulating dielectric layer form a second stepped structure. The side of the first insulating dielectric layer that contacts the control gate serves as the first platform of the second stepped structure, and the side of the second insulating dielectric layer that is away from the shielding gate serves as the second platform of the second stepped structure. Thus, relative to the bottom of the shielding gate trench, the first platform is lower than the second platform.

[0035] In one embodiment of this application, the semiconductor substrate layer includes: a drain metal layer, a heavily doped second conductivity type drain region, and a lightly doped second conductivity type drift region stacked sequentially, wherein the shielding gate trench structure is disposed on the side of the lightly doped second conductivity type drift region away from the drain metal layer.

[0036] In one embodiment of this application, the source structure includes a moderately doped first conductivity type body region, a heavily doped first conductivity type ohmic contact region, a heavily doped second conductivity type source region, and a source metal layer; the moderately doped first conductivity type body region is disposed on the side of the lightly doped second conductivity type drift region away from the heavily doped second conductivity type drain region; the heavily doped first conductivity type ohmic contact region and the heavily doped second conductivity type source region are disposed on the moderately doped first conductivity type body region and located on the side of the shielding gate trench structure, and the heavily doped second conductivity type source region is disposed on the side close to the shielding gate trench; the source metal layer covers the top of the shielding gate structure and is electrically connected to the heavily doped first conductivity type ohmic contact region and the heavily doped second conductivity type source region, and the side of the moderately doped first conductivity type body region close to the lightly doped second conductivity type drift region is located between the first mesa and the second mesa.

[0037] In one embodiment of this application, the material of the shielded trench device includes silicon, silicon carbide, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.

[0038] In one embodiment of this application, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N-type and the second conductivity type is P-type. Figure 1 and Figure 2 The schematic diagram provided is merely an example of a structure with the first conductivity type being P-type and the second conductivity type being N-type, and should not be considered as a limitation of this application.

[0039] In one embodiment of this application, the concentration of lightly doped impurities is ≤1e16cm-3, the concentration of moderately doped impurities is ∈(1e16cm-3,1e18cm-3], and the concentration of heavily doped impurities is >1e18cm-3.

[0040] In the forward conduction state, the electrode connection method in this embodiment is as follows: the source metal layer 14 and the shielding gate 6 are connected to a low potential, the control gate 9 is connected to a high potential, and the drain metal layer 1 is connected to a high potential. As the control gate potential gradually increases from zero, since the thickness of the second gate oxide layer 8 is less than the thickness of the first gate oxide layer 4, the inversion layer channel will be formed first in the side portion of the body region 10 near the second gate oxide layer 8, while the side portion near the first gate oxide layer 4 requires a higher voltage to form an inversion layer channel. The conduction of the channel depends on the thick gate oxide portion; the thin gate oxide portion does not affect the device threshold voltage. Therefore, the structure proposed in this application can effectively increase the proportion of the thin gate oxide portion in the device without increasing the body region concentration or adjusting the threshold voltage, thereby reducing the temperature sensitivity of the threshold voltage. The temperature sensitivity simulation results are as follows. Figure 3 As shown, this application can effectively improve the thermal instability performance of the device.

[0041] Please see Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a shielded trench device according to an embodiment of this application. The fabrication method includes:

[0042] Step S300: Provide a semiconductor substrate layer and form trenches in the semiconductor substrate layer; as... Figure 4 As shown in the figure, N-drift is a lightly doped second conductivity type drift region in the semiconductor substrate, and N+ is a heavily doped second conductivity type drain region in the semiconductor substrate. The trench is set on the side of the drift region away from the drain region.

[0043] Step S310: A first gate oxide layer is grown in the trench, and a first insulating dielectric layer is deposited on the basis of the first gate oxide layer; as shown. Figure 5 and Figure 6 As shown, the first gate oxide layer covers the side of the drift region away from the drain region. A first insulating dielectric layer is disposed on the first gate oxide layer.

[0044] Step S320: Deposit a shielding gate polycrystalline material on the first insulating dielectric layer; such as Figure 7 As shown, the shielding grid polycrystalline material fills the trench and covers the side of the first insulating dielectric layer away from the drift region.

[0045] Step S330: Deposit mask material, and form a shielding gate and active region through exposure etching, then remove the mask. Specifically, in Figure 7 Based on the obtained structure, a back-etching process is performed to form a partially filled trench shielding grid, such as... Figure 8 As shown. In Figure 8 Based on the structure, a grinding process is used to expose the drift zone outside the grooves, resulting in... Figure 9 The structure shown.

[0046] Step S340: A portion of the first gate oxide layer and the first insulating dielectric layer are etched from top to bottom along the inner wall of the trench. A second gate oxide layer is then thermally oxidized and grown inside the trench, the second gate oxide layer being in contact with the first gate oxide layer. A second insulating dielectric layer is then grown, spanning the platform of the first stepped structure formed by the first gate oxide layer and the first insulating dielectric layer, to form a structure enclosing the shielding gate. Figure 9 Based on the structure, a portion of the first gate oxide layer is etched to obtain, as shown below. Figure 10 The structure shown. In Figure 10 Based on the structure shown, the first insulating dielectric layer is etched to form a stepped structure between the first insulating dielectric layer and the first gate oxide layer, such as... Figure 11 As shown. Again. Figure 11 Based on the structure, a second insulating dielectric layer is added to obtain, as shown below. Figure 12 The structure shown.

[0047] Step S350: Deposit gate polycrystalline material within the trench to form a control gate filling the trench. Figure 12 Based on the structure shown, a gate polycrystalline material is deposited to form a structure as shown. Figure 13 The structure shown.

[0048] Step S360: Ion implantation and push-junction are performed in the active region to form a moderately doped first conductivity type body region and a heavily doped second conductivity type source region; the resulting structure is as follows Figure 14 As shown.

[0049] Step S370: After surface oxidation and passivation, a third insulating dielectric layer is formed covering the active region and the trench; the resulting structure is as follows. Figure 15 As shown.

[0050] Step S380: Photolithographically etch contact holes at the location corresponding to the active region in the third insulating dielectric layer, and perform ohmic doping and annealing to form a heavily doped first conductivity type ohmic contact region;

[0051] In step S390, metal is deposited to form a source metal layer, and source and gate pads are formed by photolithography. After steps S380 and S390, the resulting structure is as follows: Figure 16 As shown.

[0052] Finally, a drain metal layer can be fabricated on the side of the drain region away from the drift region, forming a structure like... Figure 17 The structure shown.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A shielded trench type device, characterized in that, include: A semiconductor substrate, a shielding gate trench structure disposed in the semiconductor substrate, and a source structure disposed in the top region of the shielding gate trench structure; The shielding trench structure includes: a first gate oxide layer, a second gate oxide layer, a first insulating dielectric layer, a second insulating dielectric layer, a third insulating dielectric layer, a shielding grid, and a control grid disposed within the trench; the first gate oxide layer covers the bottom of the trench and extends partially to the sidewall of the shielding trench; the second gate oxide layer is connected to the first gate oxide layer and covers the area near the top of the sidewall of the trench; the first insulating dielectric layer is disposed on the first gate oxide layer, and the height of the first gate oxide layer on the sidewall of the shielding trench is higher than that of the first insulating dielectric layer, such that the first insulating dielectric layer and the first gate oxide layer form a first step structure; the second insulating dielectric layer spans across the platform of the first step structure to form a structure that wraps around the shielding grid with the first insulating dielectric layer; the third insulating dielectric layer covers the top of the trench; wherein a gap is left between the second insulating dielectric layer and the first gate oxide layer, the control grid fills the gap and the area near the top of the trench, and the thickness of the first gate oxide layer is different from the thickness of the second gate oxide layer.

2. The shielded gate trench type device according to claim 1, characterized in that, The thickness of the first gate oxide layer is 1-5 times the thickness of the second gate oxide layer, or the thickness of the second gate oxide layer is 1-5 times the thickness of the first gate oxide layer.

3. The shielded trench type device according to claim 2, characterized in that, The thickness of the thicker gate oxide layer in the first and second gate oxide layers is determined by the threshold voltage and the doping concentration of the body region in the source structure.

4. The shielded gate trench type device according to claim 1, characterized in that, The first insulating dielectric layer and the second insulating dielectric layer form a second stepped structure. The side of the first insulating dielectric layer that contacts the control gate serves as the first platform of the second stepped structure, and the side of the second insulating dielectric layer that is away from the shielding gate serves as the second platform of the second stepped structure. Therefore, relative to the bottom of the shielding gate trench, the first platform is lower than the second platform.

5. The shielded grid trench type device according to claim 4, characterized in that, The semiconductor substrate includes: a drain metal layer, a heavily doped second conductivity type drain region, and a lightly doped second conductivity type drift region stacked sequentially, wherein the shielding gate trench structure is disposed on the side of the lightly doped second conductivity type drift region away from the drain metal layer.

6. The shielded gate trench type device according to claim 5, characterized in that, The source structure includes a moderately doped first conductivity type body region, a heavily doped first conductivity type ohmic contact region, a heavily doped second conductivity type source region, and a source metal layer; the moderately doped first conductivity type body region is disposed on the side of the lightly doped second conductivity type drift region away from the heavily doped second conductivity type drain region; the heavily doped first conductivity type ohmic contact region and the heavily doped second conductivity type source region are disposed on the moderately doped first conductivity type body region and located on the side of the shielding gate trench structure, and the heavily doped second conductivity type source region is disposed on the side close to the shielding gate trench; the source metal layer covers the top of the shielding gate structure and is electrically connected to the heavily doped first conductivity type ohmic contact region and the heavily doped second conductivity type source region, and the side of the moderately doped first conductivity type body region close to the lightly doped second conductivity type drift region is located between the first mesa and the second mesa.

7. The shielded grid trench type device according to claim 1, characterized in that, The materials of the shielded trench device include silicon, silicon carbide, gallium arsenide, indium phosphide, gallium oxide, or germanium silicon.

8. The shielding trench type device according to claims 5-7, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type; or the first conductivity type is N-type, and the second conductivity type is P-type.

9. The shielded gate trench type device according to claim 6, characterized in that, The concentration of lightly doped impurities is ≤1e16cm-3, the concentration of moderately doped impurities is ∈(1e16cm-3,1e18cm-3], and the concentration of heavily doped impurities is >1e18cm-3.

10. A method for manufacturing a shielding trench structure device according to any one of claims 1-9, characterized in that, include: A semiconductor substrate layer is provided and trenches are formed in the semiconductor substrate layer; A first gate oxide layer is grown in the trench, and a first insulating dielectric layer is deposited on the basis of the first gate oxide layer; A shielding gate polycrystalline material is deposited on the first insulating dielectric layer; A mask material is deposited, and a shielding gate and active region are formed by exposure etching, and then the mask is removed; A portion of the first gate oxide layer and the first insulating dielectric layer are etched from top to bottom along the inner wall of the trench, and a second gate oxide layer is thermally oxidized and grown inside the trench, the second gate oxide layer being in contact with the first gate oxide layer; a second insulating dielectric layer is grown, the second insulating dielectric layer bridging the platform of the first stepped structure formed by the first gate oxide layer and the first insulating dielectric layer, so as to form a structure that encloses the shielding gate with the first insulating dielectric layer. A gate polycrystalline material is deposited within the trench to form a control gate that fills the trench; Ion implantation and push-junction are performed in the active region to form a moderately doped first conductivity type body region and a heavily doped second conductivity type source region. A third insulating dielectric layer is formed covering the active region and the trench after surface oxidation and passivation; Contact holes are photolithographically formed at the location corresponding to the active region in the third insulating dielectric layer, and ohmic doping and annealing are performed to form a heavily doped first conductivity type ohmic contact region. Metal is deposited to form a source metal layer, and source pads and gate pads are formed by photolithography.

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