Image sensor

Abstract

An image sensor includes: a substrate having a pixel region; and a deep isolation pattern disposed between the pixel regions within the substrate, in which the deep isolation pattern includes: a liner film covering sidewalls of a trench in the substrate; a first pattern disposed on an inner sidewall of the liner film and having a height less than a height of the liner film; a separation film on an inner sidewall of the first pattern; and a second pattern covering an upper portion of an inner sidewall of the liner film and an inner sidewall of the separation film, a void being provided in the second pattern, the second pattern being spaced apart from the first pattern by the separation film, and a grain size of the second pattern being larger than a grain size of the first pattern.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0062728, filed with the Korean Intellectual Property Office on May 13, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to an image sensor. Background Technology

[0003] An image sensor is a device that converts optical images into electrical signals. Image sensors can be divided into charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CMOS image sensors are abbreviated as CMOS image sensors (CIS). A CIS consists of multiple pixels arranged in two dimensions. Each pixel includes a photodiode (PD). The PD converts incident light into an electrical signal. Summary of the Invention

[0004] In some implementations, the disclosed image sensor has improved image characteristics and intensity compared to conventional image sensors.

[0005] The objectives of this invention are not limited to the technical objectives described above, and those skilled in the art will clearly understand from the following description other objectives not stated herein.

[0006] In a first general aspect, an image sensor includes: a substrate having photoelectric conversion regions; and a deep isolation pattern disposed between the photoelectric conversion regions within the substrate, wherein the deep isolation pattern includes: a pad film covering the sidewalls of trenches in the substrate; a first pattern disposed on the inner sidewall of the pad film and having a height less than the height of the pad film; an isolation film on the inner sidewall of the first pattern; and a second pattern covering the upper portion of the inner sidewall of the pad film and the inner sidewall of the isolation film, wherein a gap is provided in the second pattern, the second pattern is spaced apart from the first pattern by the isolation film, and the grain size of the second pattern is larger than the grain size of the first pattern.

[0007] In a second general aspect, an image sensor includes: a substrate having a first surface and a second surface facing each other; and a deep isolation pattern defining a photoelectric conversion region in the substrate, wherein the deep isolation pattern includes: a pad film covering the sidewalls of a trench in the substrate; a first pattern on an inner sidewall of the pad film; a second pattern disposed on the first pattern; and an isolation film between the first pattern and the second pattern, the second pattern being spaced apart from the first pattern by the isolation film, the isolation film comprising a material different from the material of the first pattern, and a first additional element disposed in the isolation film comprising the same element as a first dopant in the first pattern.

[0008] In a third general aspect, an image sensor includes: a substrate having a first surface, a second surface facing the first surface, and a plurality of photoelectric conversion regions disposed between the first and second surfaces of the substrate; a deep isolation pattern disposed within the substrate and between the photoelectric conversion regions; an impurity region located within the substrate and adjacent to the first surface of the substrate; a gate pattern disposed on the first surface of the substrate; a wiring layer disposed on the first surface of the substrate and including an insulating layer and a conductive structure; a color filter disposed on the second surface of the substrate; a grid pattern located between the color filters; and a microlens pattern disposed on the color filters, wherein the deep isolation pattern includes: a pad film covering the sidewalls of trenches in the substrate; a first pattern disposed on the inner sidewall of the pad film and having a height less than the height of the pad film; an isolation film on the inner sidewall of the first pattern; and a second pattern covering the upper portion of the inner sidewall of the pad film and the inner sidewall of the isolation film, the second pattern having gaps, the second pattern being spaced apart from the first pattern by the isolation film, the isolation film comprising a material different from the first and second patterns, and a first additional element disposed in the isolation film comprising the same element as the first dopant in the first pattern. Attached Figure Description

[0009] Figure 1 This is a circuit diagram of an example pixel of an image sensor.

[0010] Figure 2A This is a diagram showing an example of the pixel array region of an image sensor.

[0011] Figure 2B It is along Figure 2A The cross-sectional view taken from line I-I'.

[0012] Figure 2C yes Figure 2B A magnified view of region III.

[0013] Figure 2D yes Figure 2C A magnified view of region IV.

[0014] Figure 2E It is along Figure 2A An enlarged cross-sectional view of an example of a deep isolation pattern in a section taken from line II-II'.

[0015] Figure 3 This is an example diagram of a deep isolation pattern.

[0016] Figure 4A This is a cross-sectional view of an example image sensor.

[0017] Figure 4B yes Figure 4A A magnified view of region III.

[0018] Figure 4C This is an example diagram of a deep isolation pattern.

[0019] Figure 4D This is an example diagram of a deep isolation pattern.

[0020] Figure 5A This is a plan view showing an example of the arrangement of color filters in an image sensor.

[0021] Figure 5B This is a plan view showing an example of the arrangement of color filters in an image sensor.

[0022] Figure 5C It is along Figure 5B A cross-sectional view taken from line I''-I'''.

[0023] Figure 5D This is a plan view showing an example of the arrangement of color filters in an image sensor.

[0024] Figures 6A to 6K This is a diagram illustrating an example of a method for manufacturing an image sensor.

[0025] In this specification, the same reference numerals may always refer to the same elements. Detailed Implementation

[0026] Figure 1 This is a circuit diagram of an example pixel of an image sensor.

[0027] Reference Figure 1 Each pixel of an image sensor includes a photoelectric conversion region PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a select transistor Ax. The transfer transistor Tx, source follower transistor Sx, reset transistor Rx, and select transistor Ax may each include a transfer gate TG, a source follower gate SG, a reset gate RG, and a select gate AG.

[0028] The photoelectric conversion region PD may include a photodiode comprising an n-type impurity region and a p-type impurity region. The floating diffusion region FD may serve as the drain of the transfer transistor TX. The floating diffusion region FD may serve as the source of the reset transistor Rx. The floating diffusion region FD may be electrically connected to the source follower gate SG of the source follower transistor Sx. The source follower transistor Sx is connected to the select transistor Ax.

[0029] The following will refer to Figure 1 Describe the operation of the image sensor. First, with light blocked, the drain of the reset transistor Rx and the drain of the source follower transistor Sx are supplied with a power supply voltage V. DDThe reset transistor Rx is turned on to release the charge remaining in the floating diffusion region FD. Then, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs are generated in the photoelectric conversion region PD. Holes move to the p-type impurity region of the photoelectric conversion region PD, while electrons move to the n-type impurity region and accumulate therein. When the transfer transistor Tx is turned on, charges (such as electrons and holes) are transferred to the floating diffusion region FD and accumulate. The gate bias of the source follower transistor Sx changes proportionally to the accumulated charge, causing a change in the source potential of the source follower transistor Sx. In this case, when the select transistor Ax is turned on, the signal generated due to the charge is read through the column line.

[0030] The wiring can be electrically connected to at least one of the transmission gate TG, source follower gate SG, reset gate RG, and select gate AG. The wiring can be configured to apply a power supply voltage to the drain of the reset transistor Rx or the drain of the source follower transistor Sx. VDD The wiring may include column lines connected to the selected transistor Ax. The wiring may include a first conductive structure 355, which will be referred to later. Figure 2B and Figure 4A Describe it.

[0031] although Figure 1 The illustration shows a pixel comprising a photoelectric conversion region PD and four transistors Tx, Rx, Ax, and Sx, but the implementation is not limited to this. For example, multiple pixels can be provided, and the reset transistor Rx, source follower transistor Sx, or select transistor Ax can be shared by adjacent pixels. Accordingly, the integration density of the image sensor can be improved.

[0032] Figure 2A This is a diagram showing an example of the pixel array region of an image sensor. Figure 2B It is along Figure 2A The cross-sectional view taken from line I-I'. Figure 2C yes Figure 2B A magnified view of region III. Figure 2D yes Figure 2C A magnified view of region IV. Figure 2E It is along Figure 2A An enlarged cross-sectional view of an example of a deep isolation pattern in a section taken from line II-II'.

[0033] Reference Figures 2A to 2E The image sensor 1 includes a substrate 100, a deep isolation pattern 200, a device isolation pattern 260, a gate pattern 310, a wiring layer 350, a color filter CF, and a microlens pattern 600.

[0034] Figure 2A The planar view depicts the substrate 100, including the pixel array region and the edge region. Figure 2A In the planar view, the pixel array region is located in the central portion of the substrate 100. The pixel array region comprises multiple pixel regions PX. (Refer to...) Figure 1 The described pixels can be formed in each pixel region PX of the substrate 100. For example, pixel components can be disposed on each pixel region PX. The pixel region PX can output photoelectric signals based on incident light. When viewed in a planar view, the pixel regions PX can define rows and columns and can be arranged in two dimensions. The rows can be parallel to a first direction D1. The columns can be parallel to a second direction D2.

[0035] Substrate 100 may have, for example Figure 2B The first surface 100a and the second surface 100b of the substrate 100 are shown facing each other. The first surface 100a of the substrate 100 can be the front surface, and the second surface 100b can be the rear surface. Light can be incident on the second surface 100b of the substrate 100. A first direction D1 can be parallel to the first surface 100a of the substrate 100. A second direction D2 can be parallel to the first surface 100a of the substrate 100 and can be different from the first direction D1. For example, the second direction D2 can be substantially perpendicular to the first direction D1. A third direction D3 can intersect the first surface 100a of the substrate 100. The third direction D3 can be vertical. A fourth direction D4 can be substantially parallel to the first surface 100a of the substrate 100 and can intersect the first direction D1 and the second direction D2. The fourth direction D4 can be a diagonal direction, but is not limited thereto.

[0036] Substrate 100 may be a semiconductor substrate or a silicon-on-insulator (SOI) substrate. Semiconductor substrate 100 may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Substrate 100 may include a crystalline semiconductor material. Substrate 100 may include and have a first conductivity type impurity. The first conductivity type impurity may include group 3 elements. For example, the first conductivity type impurity may include p-type impurities such as aluminum (Al), boron (B), phosphorus (P), indium (In), and / or gallium (Ga). Substrate 100 may have a first trench 191 and a second trench 192.

[0037] The substrate 100 may include a photoelectric conversion region PD. The photoelectric conversion regions PD may be respectively disposed in pixel regions PX within the substrate 100. Each photoelectric conversion region PD can perform [functions related to] [the function of ... Figure 1The photoelectric conversion region PD has the same function and role as the first conductivity type impurity. The photoelectric conversion region PD can be a region in the substrate 100 doped with an impurity of a second conductivity type. The second conductivity type impurity can have a conductivity type opposite to that of the first conductivity type impurity. The second conductivity type impurity can include group 5 elements. The second conductivity type impurity can include, for example, n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. The photoelectric conversion region PD can be located deep within the first surface 100a of the substrate 100.

[0038] A deep isolation pattern 200 is disposed within the substrate 100 and can define a pixel region PX. For example, the deep isolation pattern 200 can be disposed between photoelectric conversion regions PD. The deep isolation pattern 200 can be disposed in a first trench 191, and the first trench 191 can be formed to extend through a first surface 100a of the substrate 100. For example, the first trench 191 can be recessed from the first surface 100a of the substrate 100. The deep isolation pattern 200 can be a deep trench isolation pattern. The deep isolation pattern 200 can be formed to extend through the first surface 100a of the substrate 100. The deep isolation pattern 200 can be formed to further extend through a second surface 100b of the substrate 100. For example, the deep isolation pattern 200 can contact the first surface 100a and the second surface 100b of the substrate 100. The width of the upper surface of the deep isolation pattern 200 can be greater than the width of the lower surface of the deep isolation pattern 200, but is not limited thereto.

[0039] The deep isolation pattern 200 may include a pad film 210, a first pattern 221, a second pattern 222, and an isolation film 230. The pad film 210 may be disposed along the sidewall of the first trench 191. The pad film 210 may be formed through a first surface 100a and a second surface 100b of the substrate 100. The pad film 210 may include an oxide film. For example, the pad film 210 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-dielectric material (e.g., hafnium oxide, tantalum silicate (TaSiOx), and / or aluminum oxide). The pad film 210 may be an insulating film. The pad film 210 may have a lower refractive index than the substrate 100. The thickness T1 of the pad film 210 (in...) Figure 2C and Figure 2D The thickness (T1) of the liner film 210 can be from about 150 Å to about 400 Å. The thickness T1 of the liner film 210 can be the thickness of a point between the first surface 100a and the second surface 100b of the substrate 100 in one direction, which can be parallel to the first surface 100a of the substrate 100. The liner film 210 can be a single layer or multiple layers.

[0040] A first pattern 221 may be disposed on the inner sidewall of the pad film 210 to cover the inner sidewall of the pad film 210. The first pattern 221 may be a first semiconductor pattern, but is not limited thereto. The first pattern 221 may be spaced apart from the substrate 100 by the pad film 210. Accordingly, when the image sensor 1 is operating, the first pattern 221 may be electrically isolated from the substrate 100. The inner sidewalls of the pad film 210 may face each other. The first pattern 221 may be formed through the second surface 100b of the substrate 100, but may be spaced apart from the first surface 100a of the substrate 100. The height of the first pattern 221 may be less than the height of the pad film 210. Accordingly, the first pattern 221 may not extend to the upper part of the inner sidewall of the pad film 210, and may expose the upper part of the inner sidewall of the pad film 210. The first pattern 221 may be spaced apart from the upper part of the inner sidewall of the pad film 210.

[0041] For example, the first pattern 221 may be one of the first patterns 221 that are laterally spaced from each other. The first pattern 221 may include a crystalline semiconductor material, such as polycrystalline silicon. In the following description, for simplicity, a single first pattern 221 will be described.

[0042] The second pattern 222 may be disposed on the first pattern 221. The second pattern 222 may be disposed between the inner sidewalls of the first pattern 221 and may fill the space between the inner sidewalls of the first pattern 221. The second pattern 222 may be a second semiconductor pattern, but is not limited thereto. The second pattern 222 may include a crystalline semiconductor material, such as polycrystalline silicon. However, the second pattern 222 may include, for example, undoped polycrystalline silicon. Alternatively, the second pattern 222 may include doped polycrystalline silicon.

[0043] A separating membrane 230 may be disposed between the first pattern 221 and the second pattern 222. The first pattern 221 may conformally cover the inner sidewall of the first pattern 221. The separating membrane 230 may extend continuously on the inner sidewall of the first pattern 221 to prevent the outer sidewall of the first pattern 221 from being exposed. The second pattern 222 may be spaced apart from the first pattern 221 by the separating membrane 230. For example, the second pattern 222 may not be in direct contact with the first pattern 221; for example, the first pattern 221 and the second pattern 222 may be spaced apart by the separating membrane 230. For example, the first pattern 221 may be spaced apart from the substrate 100 by a pad film 210 in a first direction D1. The uppermost surface of the separating membrane 230 may be disposed at a lower height than the upper surface of the second pattern 222. In this specification, the height of a component may represent the vertical height measured in the vertical direction. The height difference (e.g., distance) between two components may be measured in a direction parallel to a third direction D3.

[0044] A separator 230 can be disposed between the first pattern 221 and the second pattern 222, and therefore the grain size of the second pattern 222 can be different from the grain size of the first pattern 221. The grain size of the second pattern 222 can be larger than the grain size of the first pattern 221. In a cross-sectional view, the crystal orientation of the second pattern 222 can be different from the crystal orientation of the first pattern 221. When the first pattern 221 and the second pattern 222 are in direct contact with each other, the grain size of the second pattern 222 can be the same as or similar to the grain size of the first pattern 221. When the first pattern 221 and the second pattern 222 are in direct contact with each other, the crystal orientation of the second pattern 222 can be the same as the crystal orientation of the first pattern 221. The grain size of a component is the average diameter of the grains of that component in a cross-sectional view along a reference crystal orientation. The reference crystal orientation can be determined from... <110> direction, <111> direction and <110> The orientation is selected. The first pattern may include multiple grains. The grain size of the first pattern 221 may be the average diameter of the multiple grains of the first pattern 221. The diameters of the multiple grains of the first pattern 221 can be measured in a reference crystal orientation for each grain of the first pattern 221. For example, when in <110> When measuring the diameter of a grain of the first pattern 221 in the direction, it is also possible to... <110> The diameter of other grains in the first pattern 221 is measured in the direction of the reference crystal orientation. The second pattern 222 may include multiple grains. The grain size of the second pattern 222 may be the average of the diameters of the multiple grains of the second pattern 222. The diameters of the multiple grains of the second pattern 222 can be measured in the reference crystal orientation of each grain of the second pattern 222. For example, when in... <110> When measuring the diameter of a grain of the second pattern 222 in the direction, it is also possible to... <110> The diameter of other grains in the second pattern 222 is measured in the same direction. The grain size of the first pattern 221 and the grain size of the second pattern 222 can be measured in the same reference crystal orientation.

[0045] The separator 230 may comprise a material different from the first pattern 221 and the second pattern 222. Accordingly, the separator 230 may have properties different from the first pattern 221 and the second pattern 222. For example, the separator 230 may comprise an oxide film. The separator 230 may comprise silicon oxide. Alternatively, the separator 230 may comprise silicon oxynitride. For example, the separator 230 may comprise the same material as the pad film 210. In this case, the interface between the separator 230 and the pad film 210 may not be apparent. As another example, the separator 230 may comprise a material different from the pad film 210. The thickness T2 of the separator 230 may be less than the thickness T1 of the pad film 210. For example, the thickness T2 of the separator 230 may be from about 6 Å to about 15 Å. The thickness T2 of the separator 230 may be the thickness in one direction at a point between the first surface 100a and the second surface 100b of the substrate 100. This direction may be parallel to the first surface 100a of the substrate 100. In this specification, when referring to a range, the term “about” means a value within ±10%.

[0046] like Figure 2D As shown, the first pattern 221 may further include a first dopant 221Z. The first dopant 221Z may include an impurity of a first conductivity type. For example, the first dopant 221Z may include boron (B). As another example, the first dopant 221Z may include phosphorus (P). The concentration of the first dopant 221Z in the first pattern 221 may be 5.0 × 10⁻⁶. 19 atom / cm 3 Up to 5.0×10 22 atom / cm 3 .

[0047] The isolation film 230 may further include a first additional element 230Z. The first additional element 230Z may be the same element as the first dopant 221Z. For example, the first additional element 230Z may include boron (B). As another example, the first additional element 230Z may include phosphorus (P). The isolation film 230 may include a first portion 231 and a second portion 232. The first portion 231 of the isolation film 230 may be disposed between the second portion 232 and the first pattern 221. For example, the first portion 231 of the isolation film 230 may contact the inner sidewall of the first pattern 221. The thickness of the first portion 231 of the isolation film 230 may be less than the thickness of the second portion 232. Each of the first portion 231 and the second portion 232 of the isolation film 230 may include the first additional element 230Z. The first dopant 221Z of the first pattern 221 may diffuse into the isolation film 230 to form the first additional element 230Z, but is not limited thereto. For example, the first dopant 221Z of the first pattern 221 can diffuse into the first portion 231 of the separator 230 to form the first additional element 230Z. The concentration of the first additional element 230Z in the first portion 231 of the separator 230 can be greater than the concentration of the first additional element 230Z in the second portion 232 of the separator 230.

[0048] The pad film 210 may further include a second additional element 210Z. The second additional element 210Z may include the same element as the first dopant 221Z and the first additional element 230Z. For example, the second additional element 210Z may include boron (B). As another example, the second additional element 210Z may include phosphorus (P). The pad film 210 may include a first lateral portion 211 and a second lateral portion 212. The first lateral portion 211 of the pad film 210 may be disposed between the second lateral portion 212 and the first pattern 221. For example, the first lateral portion 211 of the pad film 210 may contact the outer wall of the first pattern 221. The thickness of the first lateral portion 211 of the pad film 210 may be less than the thickness of the second lateral portion 212. Each of the first lateral portion 211 and the second lateral portion 212 of the pad film 210 may include the second additional element 210Z. The concentration of the second additional element 210Z in the first lateral portion 211 of the pad film 210 can be greater than the concentration of the second additional element 210Z in the second lateral portion 212 of the pad film 210. The first dopant 221Z of the first pattern 221 can diffuse into the pad film 210 to form the second additional element 210Z, but is not limited thereto.

[0049] The deep isolation pattern 200 may have gaps 290. Gap 290 may be provided in the second pattern 222. For example... Figure 2AAs shown, when viewed in a plan view, the deep isolation pattern 200 may have a first region R1, a second region R2, and an intersection region CR. The first region R1 of the deep isolation pattern 200 may extend along a first direction D1. The second region R2 of the deep isolation pattern 200 may extend along a second direction D2. The intersection region CR of the deep isolation pattern 200 may be the area where the first region R1 and the second region R2 intersect each other.

[0050] The gap 290 can be one of multiple gaps 290. For example, the gap 290 may include a first gap 291 and a second gap 292. The second gap 292 may be located in the intersection region CR of the deep isolation pattern 200. The first gap 291 may be located in the first region R1 or the second region R2 of the deep isolation pattern 200. Figure 2A , Figure 2C and Figure 2E As shown, the size of the second gap 292 can be larger than the size of the first gap 291. The cross-sectional area of ​​the second gap 292 can be larger than the cross-sectional area of ​​the first gap 291. The cross-sectional areas of the first gap 291 and the second gap 292 can be measured at a point between the first surface 100a and the second surface 100b of the substrate 100. Each of the first gap 291 and the second gap 292 can be spaced apart from the first pattern 221.

[0051] When the gap 290 is larger than a predetermined size, defects may appear in the image sensor 1. Defects may include white spots or dark features. In some embodiments, an isolation membrane 230 may be provided, and therefore the gap 290 may be smaller than the predetermined size. Accordingly, defects can be prevented from appearing in the image sensor 1. As a result, the image sensor 1 can have improved image characteristics.

[0052] When the gap 290 is larger than a predetermined size, it may damage the image sensor chip during the packaging process. The image sensor chip may include the image sensor 1. For example, damage to the image sensor chip may include the formation of cracks within the image sensor chip. In some embodiments, because the gap 290 is smaller than the predetermined size, the image sensor chip can have improved strength even when the gap 290 is formed within the deep isolation pattern 200.

[0053] The deep isolation pattern 200 may also include a capping pattern 240. The capping pattern 240 may be disposed on the second pattern 222. The capping pattern 240 may fill the upper portion of the first trench 191. A pad film 210 may also extend between the substrate 100 and the capping pattern 240. For example, the pad film 210 may be located between the device isolation pattern 260 and the capping pattern 240. For example, the capping pattern 240 may include a silicon-containing insulating material (e.g., silicon oxide, tetraethyl orthosilicate (TEOS), and / or silicon oxynitride).

[0054] Image sensor 1 may also include, for example Figure 2C The doped region 120 is shown. The doped region 120 can be disposed within the substrate 100 adjacent to the deep isolation pattern 200. For example, the doped region 120 can be disposed along the outer wall of the deep isolation pattern 200. The first trench 191 can expose the doped region 120. The doped region 120 can be a region doped with an impurity of a first conductivity type. The doped region 120 can prevent dark current from being generated in the image sensor 1. In the following text, for simplicity, except... Figures 2B to 2D In addition, the doped region 120 is omitted in the figure, but the concept of the present invention is not limited thereto.

[0055] like Figure 2B As shown, substrate 100 may have impurity regions 111. Impurity regions 111 may be located within pixel regions PX within substrate 100. Impurity regions 111 may be located adjacent to a first surface 100a of substrate 100. Impurity regions 111 may be spaced apart from photoelectric conversion regions PD. Impurity regions 111 may be regions doped with impurities of a second conductivity type (e.g., n-type impurities). Accordingly, impurity regions 111 may have a second conductivity type. Impurity regions 111 may be active regions or ground regions. In this case, the active region is a region used for transistor operation and may include reference... Figure 1 The floating diffusion region FD and the source / drain regions of the transistor are described. The transistor may include references. Figure 1 The described transistors are the transfer transistor Tx, the source follower transistor Sx, the reset transistor Rx, or the select transistor Ax.

[0056] Device isolation pattern 260 may be disposed within substrate 100, adjacent to a first surface 100a of substrate 100. Device isolation pattern 260 may be formed through the first surface 100a of substrate 100. Device isolation pattern 260 may define an active region or a ground region. Specifically, in each pixel region PX, device isolation pattern 260 may define an impurity region 111, and the impurity regions 111 may be separated from each other by device isolation pattern 260. For example, device isolation pattern 260 may be located on one side of one of the impurity regions 111 within substrate 100. The lower portion of device isolation pattern 260 may be disposed within substrate 100. For example, device isolation pattern 260 may be disposed in a second trench 192. The second trench 192 may be recessed from the first surface 100a of substrate 100. Device isolation pattern 260 may be a shallow trench isolation (STI) pattern. For example, the height of device isolation pattern 260 may be less than the height of deep isolation pattern 200. At least a portion of the device isolation pattern 260 may be located on the upper part of the outer sidewall of the deep isolation pattern 200 and may be connected to the upper part of the outer sidewall of the deep isolation pattern 200. For example, at least a portion of the device isolation pattern 260 may be connected to the upper part of the outer sidewall of the pad film 210. The sidewall of the device isolation pattern 260, the lower surface of the device isolation pattern 260, and the outer sidewall of the deep isolation pattern 200 may have a stepped structure. The device isolation pattern 260 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. When the device isolation pattern 260 comprises the same material as the pad film 210, the interface between the device isolation pattern 260 and the pad film 210 that are in contact with each other may not be a distinct structure. However, the implementation is not limited to this.

[0057] like Figure 2B As shown, the gate pattern 310 can be disposed on the first surface 100a of the substrate 100. The gate pattern 310 can be used as a reference above. Figure 1 The gate electrode of the transfer transistor Tx, source follower transistor Sx, reset transistor Rx, or select transistor Ax. For example, gate pattern 310 may include a transfer gate TG, a source follower gate SG, a reset gate RG, or a select gate AG. For simplicity, although... Figure 2B A single gate pattern 310 is shown located on each pixel region PX, but multiple gate patterns 310 may be located on each pixel region PX. For simplicity, a single gate pattern 310 will be described below.

[0058] The gate pattern 310 may have a buried gate structure. For example, the gate pattern 310 may include a first portion 311 and a second portion 312. The first portion 311 of the gate pattern 310 may be disposed on a first surface 100a of the substrate 100. The second portion 312 of the gate pattern 310 may protrude into the substrate 100. The second portion 312 of the gate pattern 310 may be connected to the first portion 311. In some embodiments, the gate pattern 310 may have a planar gate structure. In this case, the gate electrode may not include the second portion 312. The gate pattern 310 may include a metallic material, a metal silicide material, polysilicon, or combinations thereof. In this case, the polysilicon may include doped polysilicon.

[0059] The image sensor 1 may also include a gate insulating pattern 320. The gate insulating pattern 320 may be located between the gate pattern 310 and the substrate 100. The gate insulating pattern 320 may include, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) and / or a high-dielectric material (e.g., hafnium oxide and / or aluminum oxide).

[0060] Wiring layer 350 may be disposed on first surface 100a of substrate 100. Wiring layer 350 may include first insulating layer 351, second insulating layer 352, and first conductive structure 355. First insulating layer 351 may be disposed on first surface 100a of substrate 100 and sidewalls of gate pattern 310. Second insulating layer 352 may be stacked on first insulating layer 351. First insulating layer 351 and second insulating layer 352 may include, for example, silicon-based insulating materials, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0061] A first conductive structure 355 may be disposed in insulating layers 351 and 352. Each first conductive structure 355 may include a contact plug portion, a wiring portion, and a via portion. The contact plug portion may be disposed in at least one of the first insulating layer 351 and the lowermost second insulating layer 352. The contact plug portion may be electrically connected to one of the impurity region 111 and the gate pattern 310. The wiring portion of each conductive structure 355 may be located between two adjacent insulating layers 351 and 352. The wiring portion may be connected to the contact plug portion. The via portion of each conductive structure 355 may be formed to pass through at least one second insulating layer 352 and may be connected to the wiring portion. The conductive structure 355 may receive photoelectric signals output from the photoelectric conversion region PD.

[0062] Image sensor 1 may also include a back surface insulating layer 500. The back surface insulating layer 500 may be disposed on the second surface 100b of substrate 100 and may cover the second surface 100b of substrate 100 and the lower surface of deep isolation pattern 200. Although not shown, the back surface insulating layer 500 may include multiple layers. Two adjacent layers of the back surface insulating layer 500 may include different materials. For example, the back surface insulating layer 500 may include a metal oxide (e.g., alumina or hafnium oxide) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride). Each layer of the back surface insulating layer 500 may perform different functions. For example, the back surface insulating layer 500 may include at least one of a bottom antireflective coating (BARC) layer, a fixed charge layer, an adhesive layer, and a protective layer.

[0063] Color filters CF can be disposed on the lower surface of the rear surface insulating layer 500 at positions corresponding to pixel regions PX. For example, color filters CF can be located on pixel regions PX. In some embodiments, color filters CF can be embedded in the rear surface insulating layer 500. Color filters CF can include red, blue, and green color filters. At least one color filter CF may also include a white color filter, but the inventive concept is not limited thereto.

[0064] Image sensor 1 may also include a grid pattern 550. The grid pattern 550 may be disposed on the lower surface of the rear surface insulating layer 500 and may be located between color filters CF. The grid pattern 550 may include a metal (such as tungsten), a metal nitride (such as titanium nitride), or a silicon-containing material (such as silicon oxide).

[0065] Microlens patterns 600 can be disposed on the second surface 100b of the substrate 100. For example, microlens patterns 600 can be disposed on the lower surface of a color filter CF. Microlens patterns 600 can be disposed at positions corresponding to photoelectric conversion regions PD. For example, microlens patterns 600 can be vertically overlapped with photoelectric conversion regions PD. Each microlens pattern 600 can protrude from the second surface 100b of the substrate 100. Microlens patterns 600 can be connected to each other. Microlens patterns 600 are transparent and can transmit light. Microlens patterns 600 can include organic materials (such as polymers). For example, microlens patterns 600 can include photoresist materials or thermosetting resins.

[0066] Image sensor 1 may also include a protective film 510. The protective film 510 may be located between the back surface insulating layer 500 and the color filter CF, and between the grid pattern 550 and the color filter CF. The protective film 510 may include an insulating material (such as a high-dielectric material). For example, the protective film 510 may include aluminum oxide or hafnium oxide.

[0067] Figure 3This is an example diagram of a deep isolation pattern, and corresponds to... Figure 2B Enlarged cross section of region III.

[0068] Reference Figure 3 In addition to the gasket film 210, the first pattern 221, the second pattern 222, and the separator film 230, the deep insulating pattern 200 also includes the shallow insulating pattern 250. However, in some embodiments, the deep insulating pattern 200 does not include the capping pattern 240.

[0069] A shallow insulating pattern 250 may be disposed within the substrate 100. For example, the shallow insulating pattern 250 may be disposed in a third trench 193 of the substrate 100. The third trench and the shallow insulating pattern 250 may be formed to extend through a first surface 100a of the substrate 100. The shallow insulating pattern 250 may be located between the deep insulating pattern 200 and the first insulating layer 351, and may extend horizontally along the lower surface of the first insulating layer 351. The width of the shallow insulating pattern 250 may be greater than the width of the deep insulating pattern 200. For example, the width of the lower portion of the shallow insulating pattern 250 may be greater than the width of the upper portion of the deep insulating pattern 200. The lower surface 250b of the shallow insulating pattern 250 may be in physical contact with the deep insulating pattern 200 and the substrate 100.

[0070] For example, the lower surface 250b of the shallow insulating pattern 250 may be uneven. The lower surface 250b of the shallow insulating pattern 250 may include at least one of a protrusion and a recess, but is not limited thereto. For example, the lower surface 250b of the shallow insulating pattern 250 may be located at... Figure 2B The device isolation pattern 260 is located at approximately the same height as the lower surface, but is not limited thereto. For example, the shallow insulating pattern 250 may include, but is not limited to, the device isolation pattern 260 at a height substantially the same as the lower surface. Figure 2B The device isolation pattern 260 is made of the same material, but is not limited to it.

[0071] For example, the upper surface 250a of the shallow insulating pattern 250 may not be flat. For example, the upper surface 250a of the shallow insulating pattern 250 may include at least one of a protrusion and a recess, but is not limited thereto.

[0072] The shallow insulating pattern 250 may include a capping portion 254 and a device isolation portion 256. The capping portion 254 may be located between the deep insulating pattern 200 and the first insulating layer 351. For example, the capping portion 254 may be located between the second pattern 222 and the first insulating layer 351. The device isolation portion 256 may be disposed on the sidewall of the capping portion 254. The shallow insulating pattern 250 may include a silicon-based insulating material. The shallow insulating pattern 250 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0073] Figure 4A This is a cross-sectional view of an example image sensor, and corresponds to the view along... Figure 2A The cross section intercepted by line I-I'. Figure 4B yes Figure 4A An enlarged view of region III. The above description will not be repeated below.

[0074] Reference Figures 4A to 4B The image sensor 1A includes a substrate 100, a deep isolation pattern 200, a device isolation pattern 260, a gate pattern 310, a wiring layer 350, a color filter CF, and a microlens pattern 600. The image sensor 1A may also include a back surface insulating layer 500, a protective film 510, and a grid pattern 550.

[0075] A deep isolation pattern 200 can be disposed within a substrate 100 and can define a pixel region PX. The deep isolation pattern 200 can be disposed in a rear surface trench 191A. The rear surface trench 191A can be formed to extend through a second surface 100b of the substrate 100. The bottom surface of the rear surface trench 191A can be disposed within the substrate 100. The upper surface of the deep isolation pattern 200 can correspond to the bottom surface of the rear surface trench 191A. The upper surface of the deep isolation pattern 200 can be spaced apart from a first surface 100a of the substrate 100 and can be located at a height lower than the first surface 100a. Contrary to the illustration, the rear surface trench 191A and the deep isolation pattern 200 can also be formed to extend through the first surface 100a of the substrate 100. The width of the upper surface of the deep isolation pattern 200 can be greater than the width of the lower surface of the deep isolation pattern 200.

[0076] The substrate 100 may also have a pixel isolation region 130. The pixel isolation region 130 may define a pixel region PX together with the deep isolation pattern 200. The pixel isolation region 130 may be disposed within the substrate 100. The pixel isolation region 130 may be disposed between the upper surface of the deep isolation pattern 200 and the first surface 100a of the substrate 100. For example, a device isolation pattern 260 may also be located between the pixel isolation region 130 and the impurity region 111. The pixel isolation region 130 may include group 3 elements. For example, the pixel isolation region 130 may be a region doped with impurities of a first conductivity type (e.g., p-type).

[0077] The upper surface of the deep isolation pattern 200 can be disposed within the pixel isolation region 130. The upper part of the deep isolation pattern 200 can be surrounded by the pixel isolation region 130.

[0078] The deep isolation pattern 200 may include a gasket film 210, a first pattern 221, a second pattern 222, and an isolation film 230. The gasket film 210, the first pattern 221, the second pattern 222, and the isolation film 230 can be combined with… Figures 2A to 2EThe examples described are the same or similar. However, the pad film 210 may cover the inner sidewalls and bottom surface of the rear surface groove 191A. The pixel isolation region 130 may contact the upper surface of the pad film 210. The first pattern 221 may cover the inner sidewalls of the pad film 210. The first pattern 221 may extend to the bottom surface of the rear surface groove 191A and may also cover the pad film 210. The height of the first pattern 221 may be less than the height of the pad film 210. The first pattern 221 may expose a portion of the inner sidewalls of the pad film 210. For example, the first pattern 221 may expose the lower portion of the inner sidewalls of the pad film 210. The second pattern 222 may be disposed between the inner sidewalls of the first pattern 221 and may fill the space between the inner sidewalls of the first pattern 221. The second pattern 222 may cover the lower portion of the inner sidewalls of the pad film 210. The isolation film 230 may be disposed between the first pattern 221 and the second pattern 222. The isolation membrane 230 can conformally cover the inner sidewall of the first pattern 221. The deep isolation pattern 200 may not include... Figure 2B The capping pattern 240. As shown, the deep isolation pattern 200 may also include... Figure 2B The cover pattern 240 may be located in the rear surface groove 191A between the second pattern 222 and the rear surface insulating layer 500.

[0079] Figure 4C This is an example diagram of a deep isolation pattern, and corresponds to... Figure 4A An enlarged cross-section of region III. The above description will not be repeated below.

[0080] Reference Figure 4C The deep isolation pattern 200 can be formed through the second surface 100b of the substrate 100. For example, the deep isolation pattern 200 can be disposed in the rear surface trench 191A. The deep isolation pattern 200 may include a pad film 210, a first pattern 221, a second pattern 222, and an isolation film 230.

[0081] The upper surface 200a of the deep isolation pattern 200 can be circular. For example, the central region of the upper surface 200a of the deep isolation pattern 200 can be located at a higher height than the edge region of the upper surface 200a of the deep isolation pattern 200. The upper surface 200a of the deep isolation pattern 200 can be located within the pixel isolation region 130 and can be surrounded by the pixel isolation region 130.

[0082] The deep isolation pattern 200 can have a shape similar to a baseball bat. For example, the width of the upper part of the deep isolation pattern 200 can be smaller than the width of the middle part. The width of the lower part of the deep isolation pattern 200 can be smaller than the width of the middle part. The cross-sectional shape of the deep isolation pattern 200 can be modified in various ways.

[0083] Figure 4D This is an example diagram of a deep isolation pattern, and corresponds to... Figure 4A Enlarged cross section of region III.

[0084] Reference Figure 4D and Figure 4A The image sensor 1A may also include a shallow insulating pattern 250. The shallow insulating pattern 250 may, together with the deep insulating pattern 200, define a pixel region PX. The shallow insulating pattern 250 may, together with... Figure 3 The shallow insulating pattern 250 is the same as or similar to the deep insulating pattern 200. For example, the shallow insulating pattern 250 may be disposed in the third trench 193 of the substrate 100. The shallow insulating pattern 250 may be disposed between the upper surface 200a of the deep insulating pattern 200 and the first surface 100a of the substrate 100. The upper surface 250a of the shallow insulating pattern 250 may be uneven, but is not limited thereto. The lower surface 250b of the shallow insulating pattern 250 may be uneven. For example, the lower surface 250b of the shallow insulating pattern 250 may have a downwardly convex shape. The shallow insulating pattern 250 may include a silicon-based insulating material.

[0085] Shallow insulating pattern 250 can be with Figure 2B The device isolation pattern 260 is formed through a single process, but is not limited thereto. For example, the shallow insulating pattern 250 may include... Figure 4A The device isolation pattern 260 is made of the same material, but is not limited to it.

[0086] The upper surface 200a of the deep insulating pattern 200 may be disposed within the shallow insulating pattern 250. For example, the upper part of the deep insulating pattern 200 may be surrounded by the shallow insulating pattern 250. The upper surface 200a of the deep insulating pattern 200 may not be flat. For example, the upper surface 200a of the deep insulating pattern 200 may include at least one of a protrusion and a recess.

[0087] Figure 5A This is a plan view showing an example of the arrangement of color filters in an image sensor. Figure 5A The section cut along line I-I' corresponds to Figure 2B For the sake of simplicity, in Figure 5A , Figure 5B and Figure 5D The padding film 210, the first pattern 221, the second pattern 222, and the separator film 230 are omitted.

[0088] Combination Figure 2A Reference Figure 5A The pixel array region of the substrate 100 may include multiple pixel regions PX. A deep isolation pattern 200 may be located between the pixel regions PX. When viewed in a planar view, the deep isolation pattern 200 may surround each pixel region PX.

[0089] Color filters (CF) can be located on pixel regions (PX). Color filters (CF) can be combined with... Figure 2B The color filters CF described in the examples are essentially the same. A color filter CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 may be a green color filter. A green color filter allows green light in the visible spectrum to pass through. When a photoelectric conversion region PD is disposed on the first color filter CF1, the photoelectric conversion region PD can generate photoelectrons corresponding to green light. The second color filter CF2 may include a red color filter, and the third color filter CF3 may include a blue color filter.

[0090] The color filters CF can be arranged in a Bayer pattern. For example, the number of first color filters CF1 can be greater than the number of second color filters CF2. For example, the number of first color filters CF1 can be equal to or greater than twice the number of second color filters CF2. The number of first color filters CF1 can be greater than the number of third color filters CF3. For example, the number of first color filters CF1 can be equal to or greater than twice the number of third color filters CF3. The first color filters CF1 can be arranged along a fourth direction D4. Each second color filter CF2 can be located between two adjacent first color filters CF1. Each third color filter CF3 can be located between two adjacent first color filters CF1. The third color filter CF3 can be arranged with the second color filters CF2 along a fifth direction D5. The fifth direction D5 can be parallel to the first surface 100a of the substrate 100 and can intersect with the first direction D1, the second direction D2, and the fourth direction D4. For example, the fifth direction D5 can be substantially perpendicular to the fourth direction D4.

[0091] Figure 5B This is a plan view showing an example of the arrangement of color filters in an image sensor. Figure 5C It is along Figure 5B The cross-sectional view taken by line I''-I'''. In the following text, for simplicity, a single first color filter, a single second color filter, and a single third color filter will be described.

[0092] Reference Figure 5B and Figure 5C The image sensor 1B may include a substrate 100, a deep isolation pattern 200, a device isolation pattern 260, a gate pattern 310, a wiring layer 350, a color filter CF, and a microlens pattern 600.

[0093] Substrate 100 may include a pixel group PG. When viewed in a plan view, the pixel group PG may be arranged in two dimensions along a first direction D1 and a second direction D2. Each pixel group PG may include multiple pixel regions PX. For example, the pixel regions PX of the pixel group PG may be arranged in two dimensions, defining two rows and two columns.

[0094] Color filters CF can be located in pixel groups PG on the second surface 100b of substrate 100. Color filters CF can be... Figure 5A The color filters CF described in the examples are essentially the same. A color filter CF can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be... Figure 5A The Bayer pattern arrangement is shown. However, when viewed in a plan view, a single color filter CF can be disposed on one of the pixel groups PG and overlap with multiple pixel regions PX of one of the pixel groups PG. A single color filter CF can also be disposed on the photoelectric conversion region PD of the multiple pixel regions PX of the pixel group PG. Accordingly, the multiple pixel regions PX of the pixel group PG can share a single color filter CF. For example, a first color filter CF1 can be disposed on multiple pixel regions PX of one pixel group PG. A second color filter CF2 can be disposed on multiple pixel regions PX of another pixel group PG. A third color filter CF3 can be disposed on multiple pixel regions PX of another pixel group PG. The image sensor 1B can have a four-unit structure.

[0095] Figure 5D This is a plan view showing an example of the arrangement of color filters in an image sensor.

[0096] Reference Figure 5D The pixel array region of the image sensor 1C can have a nine-unit structure. In this case, each pixel group PG can include nine pixel regions PX. The nine pixel regions PX can be arranged in two dimensions, defining three rows and three columns. A single color filter CF can be placed on any of the nine pixel regions PX of a pixel group PG to overlap with the nine pixel regions PX. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be arranged in a Bayer pattern.

[0097] In this specification, features from different examples can be combined with each other. For example, Figures 2A to 2E Implementation examples Figure 3 Implementation examples Figure 4A and Figure 4B Implementation examples Figure 4C Implementation examples Figure 4D Implementation examples Figure 5A Implementation examples Figure 5B and Figure 5C Implementation examples, and Figure 5D Implementations can be combined with each other in a single device.

[0098] Figures 6A to 6K This is a diagram illustrating an example of a method for manufacturing an image sensor. Figure 6F It is a diagram used to explain the process of forming the second preliminary pattern, and corresponds to Figure 6EA magnified view of region V. Figure 6G This is a diagram illustrating the process of forming the second preliminary pattern when the separator is omitted. The above description will not be repeated below. In the description of the image sensor manufacturing example, the pixel region can be interpreted as including areas where a reference pattern has been formed. Figure 1 The region of the pixel being described and the region used to form that pixel.

[0099] Reference Figure 6A A substrate 100 having a first surface 100a and a second surface 100b facing each other can be fabricated. A photoelectric conversion region PD can be formed in a pixel region PX within the substrate 100. A second trench 192 can be formed on the first surface 100a of the substrate 100. The formation of the second trench 192 can be performed using an etching process employing a mask film.

[0100] A preliminary device isolation pattern 260P can be formed in the second trench 192 and on the first surface 100a of the substrate 100. The preliminary device isolation pattern 260P can fill the second trench 192.

[0101] Reference Figure 6B A first trench 191 can be formed between pixel regions PX within the substrate 100. Forming the first trench 191 may include performing an etching process on a first surface 100a of the substrate 100. The first trench 191 may be formed deeper than a second trench 192. For example, the bottom surface of the first trench 191 may be located at a lower height than the bottom surface of the second trench 192. A portion of the first trench 191 may be formed through a preliminary device isolation pattern 260P. In this case, the lower portion of the sidewalls of the first trench 191 may expose the substrate 100, and the upper portion of the sidewalls of the first trench 191 may expose the preliminary device isolation pattern 260P. Interface defects may be formed on the bottom surface and sidewalls of the first trench 191 by the etching process.

[0102] A first cleaning process can also be performed on the first surface 100a of the substrate 100 and in the first trench 191. The first cleaning process can remove residues from the etching process. After the first cleaning process, an impurity implantation process can be performed on the first surface 100a of the substrate 100. The impurity implantation process can form [something] in the substrate 100. Figure 2C The doped region 120 is described in the diagram. The doped region may be adjacent to the sidewalls of the first trench 191. Although not shown, a doped region may also be formed within the substrate 100 in a region adjacent to the bottom surface of the first trench 191. In this case, the doped region may be in contact with the bottom surface of the first trench 191. After the impurity implantation process, a second cleaning process may also be performed on the first surface 100a of the substrate 100 and in the first trench 191.

[0103] Reference Figure 6C A preliminary liner film 210P can be formed on the sidewalls and bottom surface of the first trench 191 to cover the sidewalls and bottom surface of the first trench 191. The preliminary liner film 210P can further cover the first surface 100a of the substrate 100. The formation of the preliminary liner film 210P can be performed by a deposition process. As another example, the formation of the preliminary liner film 210P can be performed by an oxidation process. For example, the portion of the substrate 100 exposed through the first trench 191 can be oxidized to form the preliminary liner film 210P.

[0104] A first pattern 221 can be formed on the preliminary pad film 210P. For example, a deposition process can be performed on the preliminary pad film 210P to form the first preliminary pattern. The deposition process can be performed under a first temperature condition. The first temperature can be from about 400°C to about 550°C. The deposition process can be performed once or multiple times. The first preliminary pattern can cover the preliminary pad film 210P on the bottom surface of the first trench 191, the sidewalls of the first trench 191, and the first surface 100a of the substrate 100. An etching process can be performed on the first preliminary pattern to form the first pattern 221. The upper portion of the first preliminary pattern can be removed by the etching process. Accordingly, the first pattern 221 may not extend over the first surface 100a of the substrate 100. The first pattern 221 may expose the upper portion of the inner sidewalls of the preliminary pad film 210P. The first pattern 221 may include, but is not limited to, an amorphous semiconductor material. For example, the first pattern 221 may include amorphous silicon.

[0105] As an example, the deposition process may include depositing a semiconductor material comprising a first dopant. In this case, the first pattern 221 may include the first dopant 221Z (in... Figure 2D middle).

[0106] As another example, the first preliminary pattern may not include the first dopant after the deposition process. After the etching process of the first preliminary pattern, a doping process can be performed on the first pattern 221. Accordingly, the first pattern 221 may include the first dopant 221Z (in... Figure 2D (In this case, an additional cleaning process can be performed after the doping process).

[0107] Reference Figure 6DAn isolation film 230 can be formed on the first pattern 221. For example, forming the isolation film 230 can include performing an oxidation process on the first pattern 221. The oxidation process can include providing oxygen or ozone to the first pattern 221. Accordingly, the first pattern 221 can be oxidized to form the isolation film 230. The isolation film 230 can include an oxide film. The isolation film 230 can be formed by an oxidation process, and the thickness T2 of the isolation film 230 can be from about 6 Å to about 15 Å. Forming a natural oxide film with a thickness of 6 Å or greater is generally difficult. A natural oxide film can expose the underlying film. In some embodiments, the isolation film 230 can extend continuously on the inner sidewall of the first pattern 221. The isolation film 230 can prevent the exposure of the first pattern 221. The isolation film 230 can be formed by a different method or under different process conditions than the initial liner film 210P, and the thickness T2 of the isolation film 230 can be less than the thickness T1' of the initial liner film 210P. The thickness T1' of the initial liner film 210P can be... Figure 2C The thickness T1 of the liner film 210 is basically the same.

[0108] The separator 230 comprises a material different from that of the first pattern 221, and therefore the first separator 230 may have properties different from those of the first pattern 221. For example, the planar density of the separator 230 may be greater than that of the first pattern 221.

[0109] When the first pattern 221 comprises undoped semiconductor material, an impurity implantation process can be performed on the separator 230. In this case, the impurity implantation process can be omitted. Figure 6C The doping process described in the example. Due to the impurity implantation process, the first pattern 221 may include a first dopant 221Z ( Figure 2D ), and the separator 230 may include a first additional element 230Z ( Figure 2D First additional element 230Z ( Figure 2D The implantation process of ) can be combined with the first dopant 221Z ( Figure 2D The injection process is performed in a single process. For example... Figure 2D As shown, the first additional element 230Z may include the same element as the first dopant 221Z. A cleaning process may also be performed after the impurity implantation process.

[0110] Reference Figure 6E and Figure 6FA second preliminary pattern 222P can be formed on the separator 230. The second preliminary pattern 222P can be formed in the first trench 191 and on the first surface 100a of the substrate 100 to cover the separator 230 and the preliminary liner film 210P. The second preliminary pattern 222P can fill the gap between the opposing inner sidewalls of the separator 230. The second preliminary pattern 222P can be in physical contact with the separator 230 and the preliminary liner film 210P.

[0111] Forming the second preliminary pattern 222P may include performing a deposition process. The deposition process may include, for example, a low-pressure chemical vapor deposition process. The deposition process may be performed at a second temperature condition. The second temperature may be higher than... Figure 6C The first temperature is used. For example, the second temperature can be from about 570°C to about 670°C. Due to the deposition process conditions, the second preliminary pattern 222P can have a crystalline structure.

[0112] Reference Figure 6G When the separator 230 is omitted, a second preliminary pattern 222P can be formed on the first pattern 221 and the preliminary liner film 210P. The second preliminary pattern 222P can directly contact the inner wall of the first pattern 221. The second preliminary pattern 222P can directly contact the upper part of the inner wall of the preliminary liner film 210P. The first pattern 221 can include a material different from the material of the preliminary liner film 210P. The planar density of the preliminary liner film 210P can be less than the planar density of the first pattern 221. Accordingly, in the deposition process, the deposition rate of the second preliminary pattern 222P on the preliminary liner film 210P can be higher than the deposition rate of the second preliminary pattern 222P on the first pattern 221. Accordingly, the overhang portion 222OH of the second preliminary pattern 222P on the upper part of the inner wall of the first pattern 221 can be formed to be relatively thick. Therefore, after the deposition process is completed, relatively large voids 290 may be formed in the second preliminary pattern 222P.

[0113] Reference Figure 6F A separating membrane 230 can be provided on the first pattern 221, so that the first pattern 221 is not exposed. The planar density of the separating membrane 230 can be the same as or similar to the planar density of the preliminary liner membrane 210P. Accordingly, the incubation time of the second preliminary pattern 222P on the separating membrane 230 can be the same as or similar to the incubation time of the second preliminary pattern 222P on the preliminary liner membrane 210P. The deposition rate of the second preliminary pattern 222P on the separating membrane 230 can be the same as or similar to the deposition rate of the second preliminary pattern 222P on the preliminary liner membrane 210P. Accordingly, the formation of voids 290 can be prevented. Alternatively, voids 290 can be formed to be smaller than a predetermined size.

[0114] Reference Figure 6HThe upper portion of the second preliminary pattern 222P can be removed to form the second pattern 222. The second pattern 222 can be located in the first trench 191. Removing the upper portion of the second preliminary pattern 222P can be performed by an etching process (e.g., wet etching). As a result of the etching process, the upper surface of the second pattern 222 can be positioned at a lower height than the first surface 100a of the substrate 100. A portion of the preliminary liner film 210P on the first surface 100a of the substrate 100 can be exposed. The upper portion of the inner sidewall of the preliminary liner film 210P in the first trench 191 can be exposed.

[0115] A preliminary capping pattern 240P can be formed in the first trench 191 to cover the upper surface of the second pattern 222 and the upper portion of the inner sidewall of the preliminary pad film 210P. The preliminary capping pattern 240P can fill the first trench 191. The preliminary capping pattern 240P can be formed on the first surface 100a of the substrate 100 to cover the upper surface of the preliminary pad film 210P. The preliminary capping pattern 240P can be formed by a deposition process.

[0116] Reference Figure 6H and Figure 6I A planarization process can be performed on the preliminary capping pattern 240P and the preliminary padding film 210P to form the capping pattern 240 and the padding film 210. The planarization process removes the upper portion of the preliminary capping pattern 240P to form the capping pattern 240. The capping pattern 240 can be located in the first trench 191. The planarization process also removes the upper portion of the preliminary padding film 210P to form the padding film 210. The padding film 210 can be located in the first trench 191. The padding film 210 and the capping pattern 240 may not extend on the first surface 100a of the substrate 100. Accordingly, a deep isolation pattern 200 can be formed in the first trench 191. The deep isolation pattern 200 may include the padding film 210, the first pattern 221, the second pattern 222, the isolation film 230, and the capping pattern 240.

[0117] A planarization process can be performed on the initial device isolation pattern 260P to form the device isolation pattern 260. For example, the upper portion of the isolation film 230 can be removed to form the device isolation pattern 260. The device isolation pattern 260 can be located in the second trench 192. As a result of the planarization process, the first surface 100a of the substrate 100 can be exposed. The device isolation pattern 260 may not extend on the first surface 100a of the substrate 100.

[0118] Reference Figure 6JA gate insulating pattern 320 and a gate pattern 310 can be formed on the first surface 100a of the substrate 100. The gate insulating pattern 320 and the gate pattern 310 can also extend into the substrate 100. A second conductivity type impurity can be implanted into the substrate 100 to form an impurity region 111.

[0119] A first insulating layer 351, a second insulating layer 352, and conductive structures 355 can be formed on the first surface 100a of the substrate 100 to form a wiring layer 350. One of the conductive structures 355 can be electrically connected to a corresponding impurity region 111, and another of the conductive structures 355 can be electrically connected to the gate pattern 310.

[0120] even though Figure 2B The first pattern 221 comprises an amorphous semiconductor material, and may also have a crystalline structure after the conductive structure 355 is formed. During the formation process of the gate pattern 310 or the conductive structure 355, heat may be applied to the isolation pattern. The first pattern 221 can be crystallized by heat.

[0121] When the second pattern 222 is in direct physical contact with the first pattern 221, as a result of the crystallization process of the first pattern 221, the grain size of the first pattern 221 can be the same as the size of the second pattern 222. In some embodiments, a separating film 230 is provided, so the grain size of the second pattern 222 can be larger than the grain size of the first pattern 221.

[0122] Reference Figure 6K A thinning process can be performed on the second surface 100b of the substrate 100 to expose the deep isolation pattern 200 on the second surface 100b of the substrate 100. In the thinning process, the bottom of the liner 210 can be removed, exposing the liner 210 and the first pattern 221 on the second surface 100b of the substrate 100. The bottom of the first pattern 221 can also be removed, exposing the isolation film 230 and the second pattern 222 on the second surface 100b of the substrate 100. That is, the liner 210, the first pattern 221, the second pattern 222, and the isolation film 230 can be exposed on the second surface 100b of the substrate 100. Alternatively, at least one of the liner 210, the first pattern 221, the second pattern 222, and the isolation film 230 may not be exposed on the second surface 100b of the substrate 100. The thinning process can be performed by an etching process or a chemical mechanical polishing (CMP) process.

[0123] Reference Figure 2A A back surface insulating layer 500, a grid pattern 550, a protective film 510, a color filter CF, and a microlens pattern 600 can be formed on the second surface 100b of the substrate 100. The examples described so far can be used to fabricate [the substrate]. Figure 2AThe image sensor 1 described herein.

[0124] In the manufacturing process of the image sensor, heat can be applied to the deep isolation pattern 200. The manufacturing process may include subsequent processes for forming the deep isolation pattern 200. For example, subsequent processes may include, but are not limited to, those following... Figure 6J The fabrication process of wiring layer 350 or gate pattern 310. Due to heat applied in subsequent processes, material in voids 290 or second pattern 222 may move.

[0125] For example, such as Figure 2A As shown, a plurality of first gaps 291 in the first region R1 or the second region R2 can be moved to the intersection region CR and can combine with each other to form a second gap 292. Therefore, the size of the second gap 292 in the intersection region CR can be increased. The second gap 292 can have a relatively large size. When the second pattern 222 is in direct contact with the first pattern 221, the gaps 290 in the second pattern 222 can move together with the semiconductor material in the first pattern 221. For example, the gaps 290 can extend into the first pattern 221. Therefore, the gaps 290 can be formed to be larger than a predetermined size.

[0126] In some embodiments, the isolation membrane 230 may also be located between the first pattern 221 and the second pattern 222. The isolation membrane 230 can serve as a barrier membrane and can prevent the migration of the voids 290. Therefore, the voids 290 may be difficult to migrate or extend into the isolation membrane 230 or the first pattern 221. Therefore, the voids 290 can be formed to be smaller than a predetermined size. The image sensor 1 can have improved image characteristics and improved intensity.

[0127] Advantageously, the isolation pattern may include a backing film, a first pattern, a second pattern, and an isolation membrane. The isolation membrane may be disposed between the first pattern and the second pattern. The isolation pattern may include an isolation membrane, thus the image sensor can have improved image characteristics and increased intensity.

[0128] The foregoing detailed description of the inventive concept is not intended to limit the inventive concept to the disclosed embodiments, and can be used in various other combinations, variations, and environments without departing from the spirit of the inventive concept. The appended claims should also be construed as including other embodiments.

[0129] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in the context of individual implementations in this disclosure may also be implemented in combination in a single implementation. Conversely, different features described in a single implementation context may also be implemented individually in multiple implementations, or in appropriate sub-combinations. Furthermore, although the foregoing features may be described as functioning in certain combinations, in some cases, one or more features in a combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0130] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: The substrate has a photoelectric conversion region; as well as A deep isolation pattern is disposed between the photoelectric conversion regions within the substrate, wherein the deep isolation pattern comprises: A liner film that covers the sidewalls of the trenches in the substrate; The first pattern is disposed on the inner sidewall of the liner film and has a height less than the height of the liner film. An isolation membrane is located on the inner wall of the first pattern; and The second pattern covers the upper portion of the inner sidewall of the liner film and the inner sidewall of the separator film. In the second pattern, gaps are provided. Wherein, the second pattern is spaced apart from the first pattern by the insulating film, and The grain size of the second pattern is larger than that of the first pattern.

2. The image sensor according to claim 1, wherein, The separating membrane comprises a material different from the materials of the first pattern and the second pattern, and The first additional element disposed in the isolation film includes the same element as the first dopant in the first pattern.

3. The image sensor according to claim 1, wherein, The separating membrane comprises the same material as the liner membrane.

4. The image sensor according to claim 1, wherein, The thickness of the gasket film at a point between the first surface and the second surface of the substrate in a first direction is greater than the thickness of the separator film, and Wherein, the first direction is parallel to the first surface of the substrate.

5. The image sensor according to claim 1, wherein, The insulating membrane extends continuously along the inner sidewall of the first pattern, and Wherein, the inner sidewall of the first pattern is spaced apart from the second pattern in a first direction at a point between the first surface and the second surface of the substrate, and Wherein, the first direction is parallel to the first surface of the substrate.

6. The image sensor according to claim 1, wherein, When viewed in a plan view, the deep isolation pattern includes: The first region extends along the first direction; The second region extends along a second direction that intersects with the first direction; The intersection region is located in the portion where the first region and the second region intersect. The gap includes: The first gap is in the intersection region; and A second gap exists in at least one of the first region and the second region.

7. The image sensor according to claim 6, wherein, The cross-sectional area of ​​the second gap is larger than that of the first gap.

8. The image sensor according to claim 1, wherein, The gap is spaced apart from the first pattern, and The isolation membrane is located between the gap and the first pattern.

9. The image sensor according to claim 1, further comprising: Gate pattern on the first surface of the substrate; as well as A shallow insulating pattern is disposed between the deep insulating pattern and the first surface of the substrate. The upper surface of the shallow insulating pattern further includes at least one of a protrusion and a recess.

10. The image sensor according to claim 1, wherein, The isolation film has a thickness between 6 Å and 15 Å in a first direction at a point between the first surface and the second surface of the substrate, and Wherein, the first direction is parallel to the first surface of the substrate.

11. An image sensor, comprising: A substrate having a first surface and a second surface facing each other; as well as A deep isolation pattern defines a photoelectric conversion region in the substrate, wherein the deep isolation pattern includes: A liner film that covers the sidewalls of the trenches in the substrate; The first pattern is on the inner wall of the liner film; A second pattern is disposed on the first pattern; and A separating film is located between the first pattern and the second pattern. The second pattern is separated from the first pattern by the insulating film. The separating membrane comprises a material different from that of the first pattern, and The first additional element disposed in the isolation film includes the same element as the first dopant in the first pattern.

12. The image sensor according to claim 11, wherein, The isolation membrane comprises a first part and a second part. Wherein, the first portion of the separating membrane is disposed between the first pattern and the second portion, and Wherein, the concentration of the first additional element in the first part of the isolation membrane is greater than the concentration of the first additional element in the second part.

13. The image sensor according to claim 11, wherein, The crystal orientation of the second pattern is different from that of the first pattern.

14. The image sensor according to claim 11, wherein, The first pattern exposes the upper portion of the inner sidewall of the liner film. The second pattern is disposed between the inner sidewalls of the isolation membrane, and The second pattern directly contacts the upper part of the inner sidewall of the liner film and the inner sidewall of the first pattern.

15. The image sensor according to claim 11, wherein, The liner film comprises a material different from the material of the first pattern, and The second additional element disposed in the liner film includes the same element as the first dopant.

16. The image sensor according to claim 11, wherein, The first additional element includes boron.

17. An image sensor, comprising: The substrate has a first surface, a second surface facing the first surface, and a plurality of photoelectric conversion regions disposed between the first surface and the second surface of the substrate; A deep isolation pattern is disposed within the substrate and between the photoelectric conversion regions; An impurity region is located within the substrate and adjacent to the first surface of the substrate; A gate pattern is disposed on the first surface of the substrate; A wiring layer is disposed on the first surface of the substrate and includes an insulating layer and a conductive structure; A color filter is disposed on the second surface of the substrate; A grid pattern is located between the color filters; as well as A microlens pattern is disposed on the color filter. The deep isolation pattern includes: A liner film that covers the sidewalls of the trenches in the substrate; The first pattern is disposed on the inner sidewall of the liner film and has a height less than the height of the liner film. An isolation membrane is located on the inner wall of the first pattern; and The second pattern covers the upper portion of the inner sidewall of the liner film and the inner sidewall of the separator film. In the second pattern, gaps are provided. The second pattern is separated from the first pattern by the insulating film. The separating membrane comprises a material different from the materials of the first pattern and the second pattern, and The first additional element disposed in the isolation film includes the same element as the first dopant in the first pattern.

18. The image sensor according to claim 17, wherein, The grain size of the second pattern is larger than that of the first pattern.

19. The image sensor according to claim 17, wherein, The trench is formed as at least one of the first surface and the second surface of the substrate.

20. The image sensor according to claim 17, wherein, One of the color filters overlaps with the plurality of pixel regions.

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