Orthogonal duty cycle correction circuit

Abstract

A duty cycle correction circuit (100) includes four pairs of transistors coupled in series. The first two transistor pairs (M1, M2 and M3, M4) of these series transistor pairs are coupled between an internal node (121) for complementary output clock signals (outb) and ground. The latter two transistor pairs (P1, P2 and P3, P4) of the series transistor pairs are coupled between the internal node (121) and a supply node for a supply voltage (Vdd). Each series pair is controlled by a respective pair of quadrature clock signals, wherein one of the quadrature clock signals is delayed by a quarter of a clock cycle relative to the other. Thus, the first two series transistor pairs combine to discharge the internal node for a half clock cycle, while the latter two series transistor pairs combine to charge the internal node for a half clock cycle, such that the complementary output clock signal has a 50% duty cycle.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to U.S. nonprovisional patent application No. 18 / 312,317, filed May 4, 2023, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] This application relates to duty cycle correction, and more specifically to a duty cycle correction circuit configured to process quadrature clock signals to provide clock signals with corrected duty cycles. Background Technology

[0004] High-frequency clock signals often suffer from duty cycle distortion. For example, a clock signal might require a 50% duty cycle, but duty cycle distortion can result in a duty cycle that is either smaller or larger than the desired one. Therefore, duty cycle correction circuits are conventionally used to correct the duty cycle of distorted clock signals. However, duty cycle correction circuits can consume significant amounts of power and semiconductor die area. Furthermore, duty cycle correction can have a considerable time delay (e.g., several clock cycles are required before the corrected clock signal has the desired duty cycle). Summary of the Invention

[0005] According to one aspect of this disclosure, a duty cycle correction circuit is provided, the duty cycle correction circuit comprising: an internal node; an inverter configured to invert the voltage of the internal node to generate an output clock signal having a corrected duty cycle; a first transistor coupled in series with a second transistor between the internal node and ground, wherein the first node for a first quadrature clock signal is coupled to the gate of the first transistor, and a second node for a second quadrature clock signal is coupled to the gate of the second transistor; and a third transistor coupled in series with a fourth transistor between the internal node and ground, wherein the third node for a third quadrature clock signal is coupled to the gate of the third transistor, and a fourth node for a fourth quadrature clock signal is coupled to the gate of the fourth transistor.

[0006] According to another aspect of this disclosure, a duty cycle correction method is provided, the method comprising: in response to an assertion of a first quadrature clock signal, turning on a first transistor in a first series transistor pair coupled between an internal node and ground to discharge the internal node to ground through the first series transistor pair; in response to an assertion of a second quadrature clock signal, turning off a second transistor in the first series transistor pair, the second quadrature clock signal being delayed by a quarter of a period relative to the first quadrature clock signal; in response to the assertion of the second quadrature clock signal, turning on a third transistor in the second series transistor pair coupled between the internal node and ground to couple the internal node to ground through the second transistor pair; and in response to an assertion of a third quadrature clock signal, turning off a fourth transistor in the second transistor pair, the third quadrature clock signal being delayed by a half of a period relative to the first quadrature clock signal.

[0007] Finally, according to another aspect of this disclosure, a duty cycle correction circuit is provided, the duty cycle correction circuit comprising: an orthogonal clock source configured to generate a first orthogonal clock signal, a second orthogonal clock signal delayed by a quarter of a clock period relative to the first orthogonal clock signal, a third orthogonal clock signal delayed by a half of the clock period relative to the first orthogonal clock signal, and a fourth orthogonal clock signal delayed by a three-quarters of the clock period relative to the first orthogonal clock signal; an internal node; and a first series switch pair coupled to the internal node and a... Between power nodes of the power supply voltage, the first series switch pair is configured to couple the internal node to the power node in response to an assertion of the third quadrature clock signal, and to isolate the internal node from the power node in response to an assertion of the fourth quadrature clock signal; and a second series switch pair, coupled between the internal node and the power node, is configured to couple the internal node to the power node in response to the assertion of the third quadrature clock signal, and to isolate the internal node from the power node in response to the assertion of the first quadrature clock signal.

[0008] These and other advantageous features can be better understood through the detailed description below. Attached Figure Description

[0009] Figure 1 An example of a duty cycle correction circuit according to one aspect of the present disclosure is illustrated, the duty cycle correction circuit being configured to perform duty cycle correction in response to four quadrature clock signals from quadrature clock sources.

[0010] Figure 2It is a timing diagram of four orthogonal clock signals and a complementary output clock signal with a corrected duty cycle, according to one aspect of this disclosure.

[0011] Figure 3 This is a flowchart of a duty cycle correction method according to one aspect of this disclosure.

[0012] Figure 4 Some example electronic systems according to one aspect of this disclosure are illustrated, the example electronic systems including integrated circuits with duty cycle correction circuitry.

[0013] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0014] Duty cycle correction for quadrature clock signals typically requires a separate duty cycle correction circuit for each quadrature phase. Alternatively, duty cycle correction may require separate circuits for each complementary clock phase pair (such as a 0° clock signal and a 180° clock signal, or a 90° clock signal and a 270° clock signal). For example, an AC-coupled buffer can be used as a duty cycle correction circuit. However, AC-coupled buffers typically consume a relatively large amount of power and semiconductor die space, and may require several clock cycles until the output clock has stabilized at the desired duty cycle. If the clock frequency varies, the resulting delay can be problematic. Alternative methods for duty cycle correction circuitry include memory elements such as set-reset (SR) latches and single-pulse generators, but implementing such duty cycle correction can be risky.

[0015] A duty cycle correction circuit is provided that processes four quadrature clock signals to generate an output clock with a desired duty cycle (such as 50%). The resulting duty cycle correction circuit avoids the power consumption and die requirements of AC-coupled buffers, and also eliminates the need for memory circuitry or single-pulse circuitry. Figure 1The diagram illustrates an example quadrature clock source 105 and a duty cycle correction circuit 100. The quadrature clock source 105 generates 0° quadrature clock signals, 90° quadrature clock signals, 180° quadrature clock signals, and 270° quadrature clock signals. However, these quadrature clock signals may be affected by duty cycle distortion. To generate clock signals with the same period but with corrected clock signals, the duty cycle correction circuit 100 processes selected quadrature clock signals and their complementary signals. The complementary signals of the quadrature clock signals can be generated by corresponding inverters. For example, a first inverter 110 inverts the 90° clock signal to generate a 90° complementary clock signal. Similarly, a second inverter 115 inverts the 180° clock signal to generate a 180° complementary clock signal. Finally, a third inverter 120 inverts the 270° clock signal to generate a 270° complementary clock signal.

[0016] To handle the selected phase and its complementary phase of the quadrature clock signal, the duty cycle correction circuit includes four n-type metal-oxide-semiconductor (NMOS) transistors M1, M2, M3, and M4, and four p-type metal-oxide-semiconductor (PMOS) transistors P1, P2, P3, and P4. The PMOS and NMOS transistors are arranged in series pairs relative to internal node 121 for complementary output clock signals (outb) with corrected duty cycles. Specifically, the drains of transistors M1 and M2 are coupled to internal node 121. The drain of transistor M2 is coupled to the source of transistor M1, while the source of transistor M2 is coupled to ground. Thus, transistors M1 and M2 are coupled in series between internal node 121 and ground. When both transistors M1 and M2 are on, internal node 121 is coupled to ground for discharge. Similarly, the drain of transistor M4 is coupled to the source of transistor M3, while the source of transistor M4 is coupled to ground. Therefore, transistors M3 and M4 are coupled in series between internal node 121 and ground, so that internal node 121 is also grounded when both transistors M3 and M4 are turned on.

[0017] The drains of transistors P1 and P4 are also coupled to internal node 121. The source of transistor P1 is coupled to the drain of transistor P2, which in turn has a source coupled to the power node for the power supply voltage Vdd. Therefore, transistors P1 and P2 are coupled in series between the power node and internal node 121. When both transistors P1 and P2 are on, internal node 121 is thus charged to the power supply voltage. The source of transistor P4 is coupled to the drain of transistor P3, which in turn has a source coupled to the node for the power supply voltage Vdd. Therefore, transistors P3 and P4 are coupled in series between the power node and internal node 121. When both transistors P3 and P4 are on, internal node 121 is charged to the power supply voltage. PMOS transistors P1, P2, P3, and P4 can therefore also be represented as pull-up transistors, as they are used to charge (or pull up) internal node 121. Regarding this pull-up function, it will be understood that, in alternative implementations, the order of the pull-up transistors in each cascaded pair may be relative to... Figure 1 The order shown is reversed. For example, the source of transistor P1 can alternatively be coupled to the power node, while the drain of transistor P2 can alternatively be coupled to the internal node 121. Similarly, the source of transistor P4 can alternatively be coupled to the power node, while the drain of transistor P3 can alternatively be coupled to the internal node 121.

[0018] NMOS transistors M1, M2, M3, and M4 can also be represented as pull-down transistors because they are used to discharge (or pull down) the internal node 121. Transistors M1 and M2 form the first pair of series-connected pull-down transistors. Similarly, transistors M3 and M4 form the second pair of series-connected pull-down transistors. Similar to what has been discussed regarding series pairs of pull-up transistors, in an alternative embodiment, the order of the pull-down transistors in each series pair of pull-down transistors may be relative to... Figure 1 The order shown is reversed. For example, the source of transistor M1 can alternatively be coupled to ground, while the drain of transistor M2 can alternatively be coupled to internal node 121. Similarly, the source of transistor M3 can alternatively be coupled to ground, while the drain of transistor M4 can alternatively be coupled to internal node 121.

[0019] Inverter 125 inverts the complementary output clock signal outb carried on internal node 121 to generate an output clock signal (out) with a corrected 50% duty cycle. To provide this 50% duty cycle correction, the 0° quadrature clock signal drives the gates of transistors P1 and M1, although the duty cycle of the quadrature clock signal is not corrected. Therefore, the node for the 0° quadrature clock signal is coupled to the gates of transistors P1 and M1. Similarly, the node for the 180° complementary quadrature clock signal is coupled to the gates of transistors P4 and M3. The node for the 90° complementary quadrature clock signal is coupled to the gate of transistor M2, and the node for the 90° quadrature clock signal is coupled to the gate of transistor M4. Finally, the node for the 270° complementary quadrature clock signal is coupled to the gate of transistor P2, and the node for the 270° quadrature clock signal is coupled to the gate of transistor P3.

[0020] By considering Figure 2 The timing diagram of the quadrature clock signal and the complementary output clock signal outb shown provides a better understanding of the resulting duty cycle correction provided by the duty cycle correction circuit 100. Note that the rising edges of the quadrature clock signals have the desired quadrature relationship. For example, the rising edge of the 0° quadrature clock signal occurs at time t0. After the full clock cycle, the 0° quadrature clock signal has a subsequent rising edge at time t4. Given this clock cycle extending from t0 to t4, the 90° quadrature clock signal has a rising edge at time t1, which occurs one-quarter of the clock cycle after time t0. Similarly, the 180° quadrature clock signal has a rising edge at time t2, which occurs one-half of the clock cycle after time t0. Finally, the 270° quadrature clock signal has a rising edge at time t3, which occurs three-quarters of the clock cycle after time t0.

[0021] If a quadrature clock signal has a 50% duty cycle, the 0° quadrature clock signal will have a falling edge at time t2 (transitioning from the supply voltage to ground). However, duty cycle distortion causes this falling edge to fall within a certain range around time t2, depending on whether the duty cycle distortion is less than or greater than 50%. Similarly, if a 90° quadrature clock signal has a 50% duty cycle, it should have a falling edge at time t3, but due to duty cycle distortion, this falling edge falls within a certain range around time t3. The falling edges of the 180° and 270° quadrature clock signals have similar duty cycle distortion.

[0022] Refer again Figure 1Note that transistor M1 will turn on at time t0 because the 0° clock signal has a rising edge at this time (transitioning from ground to supply voltage). Since the 90° quadrature clock signal has a falling edge before time t0, the 90° complementary quadrature clock signal ( Figure 2 (Not illustrated) A rising edge has already occurred before time t0, causing transistor M2 to be turned on before transistor M1 is turned on. Therefore, internal node 121 is discharged at time t0, which causes the complementary output clock signal outb to have a falling edge at time t0. This, in turn, causes the output clock signal out to have a rising edge at time t0 (assuming the processing delay through inverter 125 is relatively small). The 90° quadrature clock signal has a rising edge at time t1, meaning the 90° complementary clock signal has a falling edge at time t1 turning off transistor M2. The series transistor pair consisting of transistors M1 and M2 is thus used to ground internal node 121 for one-quarter of the clock cycle (from time t0 to time t1).

[0023] Each transistor in this series-connected transistor pair conducts for a similar quarter-clock cycle. For example, due to the rising edge of the 90° quadrature clock signal, transistor M4 in the series-connected pair consisting of transistors M4 and M3 begins to conduct at time t1. Before time t1, the 180° quadrature clock signal is low, meaning the 180° complementary clock signal (…) Figure 2 (Not illustrated in the diagram) is high. Therefore, the series pair consisting of transistors M4 and M3 is turned on at time t1 to continue coupling the internal node 121 to ground. At time t2, the 180° quadrature clock signal has a rising edge, which means that the 180° complementary quadrature clock signal has a falling edge to turn off transistor M3. The series pair consisting of transistors M3 and M4 is thus used to ground the internal node 121 for one-quarter of the clock cycle (from time t1 to time t2). From the combined operation of the series pair of transistors M1 and M2 and the series pair of transistors M3 and M4, it can be seen that the complementary output clock signal outb has a desired 50% duty cycle for being discharged, which in turn makes the output clock signal out asserted from time t0 to time t2 so that it also has a 50% duty cycle.

[0024] The series pair of transistors P3 and P4 is used to charge internal node 121 from time t2 to time t3. At time t2, the 180° quadrature clock signal has a rising edge, meaning the 180° complementary quadrature clock signal will have a falling edge (transitioning from being charged to the supply voltage to ground). Therefore, transistor P4 will turn on at time t2. The 270° clock signal has been discharged before time t2, so that transistor P3 is already conducting when transistor P4 turns on at time t2. Therefore, it can be seen that the series pair of transistors P3 and P4 begins to conduct at time t2 to charge internal node 121 to the supply voltage. The 270° clock signal has a rising edge at time t3, which turns off transistor P3. Therefore, the series pair of transistors P3 and P4 is used to charge internal node 121 from time t2 to time t3 (one-quarter of the clock cycle).

[0025] The series pair of transistors P1 and P2 is used to charge the internal node from time t3 to time t4 (which is also a quarter of the clock cycle). Specifically, the 270° quadrature clock signal has a rising edge at time t3, meaning the 270° complementary quadrature clock signal has a falling edge at time t3. This turns on transistor P2. Transistor P1 is already turned on at time t3 because it is controlled by the 0° quadrature clock signal. Therefore, the series pair of transistors P1 and P2 begins to couple the power node to the internal node 121 at time t3 to maintain the charging of the internal node 121 to the supply voltage. At time t4, the 0° quadrature clock signal has a rising edge, which turns off transistor P1. The series pair consisting of transistors P1 and P2 thus ensures that the complementary output clock signal outb remains charged from time t3 to time t4, achieving the desired 50% duty cycle.

[0026] More generally, quadrature clock source 105 is an example of a quadrature clock source configured to generate a first quadrature clock signal, a second quadrature clock signal, a third quadrature clock signal, and a fourth quadrature clock signal. An example of the first quadrature clock signal is a 0° quadrature clock signal. Each successive quadrature clock signal is delayed by a quarter of a clock cycle. In such an example, the second quadrature clock signal is a 90° quadrature clock signal because it is delayed by a quarter of a clock cycle relative to the 0° quadrature clock signal. Similarly, an example of the third quadrature clock signal is a 180° quadrature clock signal because it is delayed by a quarter of a clock cycle relative to the 90° quadrature clock signal. Similarly, a 270° quadrature clock signal is delayed by a quarter of a clock cycle relative to the 180° quadrature clock signal, making the 270° quadrature clock signal an example of the fourth quadrature clock signal.

[0027] It should be noted that in this type of quadrature continuity, which quadrature clock signal is designated as the first quadrature clock signal is arbitrary. For example, if a 270° quadrature clock signal is designated as the first quadrature clock signal, then a 0° quadrature clock signal would be an example of the second quadrature clock signal, and so on. Given this quadrature continuity of quadrature clock signals, four cascaded transistor pairs can be considered to form four corresponding cascaded switch pairs. For example, the cascaded pair of P3 and P4 transistors is an example of a first cascaded switch pair coupled between the internal node 121 and the power node, which is configured to couple the internal node 121 to the power node in response to an assertion of a third quadrature clock signal, and to isolate the internal node from the power node in response to an assertion of a fourth quadrature clock signal. Similarly, the series pair of transistors P1 and P2 is an example of a second series switch pair coupled between internal node 121 and the power supply node. This second series switch pair is configured to couple internal node 121 to the power supply node in response to an assertion of a fourth quadrature clock signal, and to isolate internal node 121 from the power supply node in response to an assertion of a first quadrature clock signal. Additionally, the series pair of transistors M1 and M2 is an example of a third series switch pair coupled between internal node 121 and ground. This third series switch pair is configured to couple internal node 121 to ground in response to an assertion of a first quadrature clock signal, and to isolate the internal node from ground in response to an assertion of a second quadrature clock signal. Finally, the series pair of transistors M3 and M4 is an example of a fourth series switch pair coupled between an internal node and ground. This fourth series switch pair is configured to couple the internal node to ground in response to an assertion of a second quadrature clock signal, and to isolate the internal node from ground in response to an assertion of a third quadrature clock signal.

[0028] The resulting operation of the duty cycle correction circuit 100 is quite advantageous. For example, 50% duty cycle correction is achieved through quadrature clock control of only eight transistors, making the duty cycle correction circuit 100 relatively compact and thus requiring relatively little semiconductor die space. Furthermore, transistors M1, M2, M3, and M4 conduct current only during the initial discharge of internal node 121 (ignoring any leakage current when these transistors are off and internal node 121 is charging). Similarly, transistors P1, P2, P3, and P4 conduct current only during the initial charging of internal node 121 (ignoring any leakage current when these transistors are off and internal node 121 is grounded).

[0029] Now refer to Figure 3The flowchart describes a method for correcting the duty cycle of a clock signal. The method includes action 300: in response to an assertion of a first quadrature clock signal, turning on a first transistor in a first series-connected transistor pair coupled between an internal node and ground to discharge the internal node to ground through the first series-connected transistor pair. Transistor M1 in the series-connected pair of transistors M1 and M2, turned on in response to an assertion of a 0° quadrature clock signal, is an example of action 300. The method also includes action 305: in response to an assertion of a second quadrature clock signal, turning off a second transistor in the first series-connected transistor pair, the second quadrature clock signal being delayed by one-quarter of the clock signal period relative to the first quadrature clock signal. Transistor M2, turned off in response to an assertion of a 90° quadrature clock signal, is an example of action 305. Additionally, the method includes action 310: in response to the assertion of the second quadrature clock signal, turning on a third transistor in a second series-connected transistor pair coupled between the internal node and ground to couple the internal node to ground through the second series-connected transistor pair. An example of action 310 is turning on transistor M4 in the series pair of transistors M3 and M4 in response to an assertion of a 90° quadrature clock signal. Finally, the method includes action 315: turning off the fourth transistor in the second series pair of transistors in response to an assertion of a third quadrature clock signal, which is delayed by half a period relative to the first quadrature clock signal. An example of action 315 is turning off transistor M3 in response to an assertion of a 180° quadrature clock signal.

[0030] Integrated circuits having duty cycle correction circuits as disclosed herein can be advantageously used in a wide variety of electronic systems. For example, such as Figure 4 As shown, cellular phone 400, laptop computer 405, and tablet PC 410 may all include an integrated circuit with duty cycle correction circuitry according to this disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with integrated circuits with duty cycle correction circuitry constructed according to this disclosure.

[0031] This disclosure will now be outlined in the following terms.

[0032] Clause 1. A duty cycle correction circuit, the duty cycle correction circuit comprising:

[0033] Internal nodes;

[0034] An inverter configured to invert the voltage of the internal node to generate an output clock signal with a corrected duty cycle;

[0035] A first transistor, wherein the first transistor and a second transistor are coupled in series between the internal node and ground, wherein a first node for a first quadrature clock signal is coupled to the gate of the first transistor, and a second node for a second quadrature clock signal is coupled to the gate of the second transistor; and

[0036] A third transistor, which is coupled in series with a fourth transistor between the internal node and ground, wherein a third node for a third quadrature clock signal is coupled to the gate of the third transistor, and a fourth node for a fourth quadrature clock signal is coupled to the gate of the fourth transistor.

[0037] Clause 2. The duty cycle correction circuit according to Clause 1, wherein the first quadrature clock signal is a 0° quadrature clock signal.

[0038] Clause 3. The duty cycle correction circuit according to Clause 2, wherein the second quadrature clock signal is a complementary signal to the 90° quadrature clock signal, the 90° quadrature clock signal being delayed by one-quarter of the period of the output clock signal relative to the 0° quadrature clock signal.

[0039] Clause 4. The duty cycle correction circuit according to Clause 3, wherein the third quadrature clock signal is the 90° quadrature clock signal.

[0040] Clause 5. The duty cycle correction circuit according to Clause 4, wherein the fourth quadrature clock signal is a complementary signal to the 180° quadrature clock signal, the 180° quadrature clock signal being delayed by half the period of the output clock signal relative to the 0° quadrature clock signal.

[0041] Clause 6. The duty cycle correction circuit according to any one of Clauses 1 to 5, wherein the first transistor, the second transistor, the third transistor and the fourth transistor each comprise an n-type metal-oxide-semiconductor (NMOS) transistor.

[0042] Clause 7. The duty cycle correction circuit according to Clause 6, wherein the drain of the first transistor and the drain of the fourth transistor are both coupled to the internal node, the drain of the second transistor is coupled to the source of the first transistor, the source of the second transistor is coupled to ground, the drain of the third transistor is coupled to the source of the fourth transistor, and the source of the third transistor is coupled to ground.

[0043] Clause 8. The duty cycle correction circuit according to Clause 5, wherein the duty cycle correction circuit further comprises:

[0044] An orthogonal clock source, configured to provide the 0° orthogonal clock signal, the 90° orthogonal clock signal, and the 180° orthogonal clock signal;

[0045] A first inverter, configured to invert the 90° quadrature clock signal to provide the complementary signal of the 90° quadrature clock signal; and

[0046] A second inverter is configured to invert the 180° quadrature clock signal to provide the complementary signal of the 180° quadrature clock signal.

[0047] Clause 9. The duty cycle correction circuit according to Clause 5, wherein the duty cycle correction circuit further comprises:

[0048] A fifth transistor, which is coupled in series with a sixth transistor between the internal node and the power node for the power supply voltage, wherein the fourth node is coupled to the gate of the fifth transistor, and the fifth node for a 270° quadrature clock signal is coupled to the gate of the sixth transistor, the 270° quadrature clock signal being delayed by three-quarters of the period of the output clock signal relative to the 0° quadrature clock signal; and

[0049] A seventh transistor, which is coupled in series with an eighth transistor between the internal node and the power node, wherein a first node is coupled to the gate of the seventh transistor, and a sixth node for the complementary signal of the 270° quadrature clock signal is coupled to the gate of the eighth transistor.

[0050] Clause 10. The duty cycle correction circuit according to Clause 9, wherein the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor each comprise a p-type metal-oxide-semiconductor (PMOS) transistor.

[0051] Clause 11. The duty cycle correction circuit according to Clause 10, wherein the drain of the fifth transistor and the drain of the seventh transistor are both coupled to the internal node, the source of the fifth transistor is coupled to the drain of the sixth transistor, the source of the seventh transistor is coupled to the drain of the eighth transistor, and the source of the fifth transistor and the source of the eighth transistor are both coupled to the power supply node.

[0052] Clause 12. The duty cycle correction circuit according to any one of Clauses 1 to 11, wherein the duty cycle correction circuit is integrated into a cellular phone.

[0053] Clause 13. A method for correcting the duty cycle of a clock signal, the method comprising:

[0054] In response to an assertion of a first quadrature clock signal, the first transistor in a first series transistor pair coupled between the internal node and ground is turned on to discharge the internal node to ground through the first series transistor pair;

[0055] In response to an assertion of a second quadrature clock signal, the second transistor in the first series transistor pair is turned off, the second quadrature clock signal being delayed by one-quarter of the period of the first quadrature clock signal.

[0056] In response to the assertion regarding the second quadrature clock signal, a third transistor in the second series-coupled transistor pair between the internal node and ground is turned on to couple the internal node to ground via the second transistor pair; and

[0057] In response to an assertion of a third quadrature clock signal, the fourth transistor in the second transistor pair is turned off, the third quadrature clock signal being delayed by half the period of the first quadrature clock signal.

[0058] Clause 14. The method described in Clause 13, further comprising:

[0059] The voltage of the internal node is inverted to generate an output clock signal with a corrected duty cycle.

[0060] Clause 15. The method described in Clause 14, wherein the corrected duty cycle is a 50% duty cycle.

[0061] Clause 16. The method described in Clause 14, further comprising:

[0062] In response to an assertion of the first quadrature clock signal, the fifth transistor in the third series transistor pair coupled between the internal node and the power node for the power supply voltage is turned on to couple the internal node to the power node through the third series transistor pair.

[0063] In response to an assertion of a fourth quadrature clock signal, the sixth transistor in the third series transistor pair is turned off, the fourth quadrature clock signal being delayed by three-quarters of the period of the clock signal relative to the first quadrature clock signal;

[0064] In response to the assertion regarding the fourth quadrature clock signal, the seventh transistor in the fourth series-connected transistor pair coupled between the internal node and the power supply voltage is turned on to couple the internal node to the power supply node via the fourth series-connected transistor pair; and

[0065] In response to an assertion on the first quadrature clock signal, the eighth transistor in the fourth series transistor pair is turned off.

[0066] Clause 17. A duty cycle correction circuit, the duty cycle correction circuit comprising:

[0067] An orthogonal clock source is configured to generate a first orthogonal clock signal, a second orthogonal clock signal delayed by one-quarter of a clock period relative to the first orthogonal clock signal, a third orthogonal clock signal delayed by one-half of the clock period relative to the first orthogonal clock signal, and a fourth orthogonal clock signal delayed by three-quarters of the clock period relative to the first orthogonal clock signal.

[0068] Internal nodes;

[0069] A first series switch pair, coupled between the internal node and a power node for the power supply voltage, is configured to couple the internal node to the power node in response to an assertion of the third quadrature clock signal, and to isolate the internal node from the power node in response to an assertion of the fourth quadrature clock signal; and

[0070] A second series switch pair, coupled between the internal node and the power node, is configured to couple the internal node to the power node in response to the assertion of the third quadrature clock signal, and to isolate the internal node from the power node in response to the assertion of the first quadrature clock signal.

[0071] Clause 18. The duty cycle correction circuit according to Clause 17, wherein the duty cycle correction circuit further comprises:

[0072] An inverter configured to invert the voltage of the internal node to generate an output clock signal with a corrected duty cycle.

[0073] Clause 19. The duty cycle correction circuit as described in Clause 18, wherein the corrected duty cycle is a 50% duty cycle.

[0074] Clause 20. The duty cycle correction circuit according to any one of Clauses 17 to 19, wherein the duty cycle correction circuit further comprises:

[0075] A third series switch pair, coupled between the internal node and ground, is configured to couple the internal node to ground in response to the assertion of the first quadrature clock signal, and to isolate the internal node from ground in response to the assertion of the second quadrature clock signal; and

[0076] A fourth series switch pair, coupled between the internal node and ground, is configured to couple the internal node to ground in response to the assertion of the second quadrature clock signal, and to isolate the internal node from ground in response to the assertion of the third quadrature clock signal.

[0077] As those skilled in the art will understand to date and depending on the specific application at hand, many modifications, substitutions, and variations may be made to the materials, apparatus, configurations, and methods of using the devices disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A duty cycle correction circuit, the duty cycle correction circuit comprising: Internal nodes; An inverter configured to invert the voltage of the internal node to generate an output clock signal with a corrected duty cycle; A first transistor, wherein the first transistor and a second transistor are coupled in series between the internal node and ground, wherein a first node for a first quadrature clock signal is coupled to the gate of the first transistor, and a second node for a second quadrature clock signal is coupled to the gate of the second transistor; and A third transistor, which is coupled in series with a fourth transistor between the internal node and ground, wherein a third node for a third quadrature clock signal is coupled to the gate of the third transistor, and a fourth node for a fourth quadrature clock signal is coupled to the gate of the fourth transistor.

2. The duty cycle correction circuit according to claim 1, wherein the first quadrature clock signal is a 0° quadrature clock signal.

3. The duty cycle correction circuit according to claim 2, wherein the second quadrature clock signal is a complementary signal to the 90° quadrature clock signal, and the 90° quadrature clock signal is delayed by one-quarter of the period of the output clock signal relative to the 0° quadrature clock signal.

4. The duty cycle correction circuit according to claim 3, wherein the third quadrature clock signal is the 90° quadrature clock signal.

5. The duty cycle correction circuit according to claim 4, wherein the fourth quadrature clock signal is a complementary signal to the 180° quadrature clock signal, the 180° quadrature clock signal being delayed by half the period of the output clock signal relative to the 0° quadrature clock signal.

6. The duty cycle correction circuit according to claim 1, wherein the first transistor, the second transistor, the third transistor and the fourth transistor each comprise an n-type metal-oxide-semiconductor (NMOS) transistor.

7. The duty cycle correction circuit according to claim 6, wherein the drain of the first transistor and the drain of the fourth transistor are both coupled to the internal node, the drain of the second transistor is coupled to the source of the first transistor, the source of the second transistor is coupled to ground, the drain of the third transistor is coupled to the source of the fourth transistor, and the source of the third transistor is coupled to ground.

8. The duty cycle correction circuit according to claim 5, wherein the duty cycle correction circuit further comprises: An orthogonal clock source, configured to provide the 0° orthogonal clock signal, the 90° orthogonal clock signal, and the 180° orthogonal clock signal; A first inverter, configured to invert the 90° quadrature clock signal to provide the complementary signal of the 90° quadrature clock signal; and A second inverter is configured to invert the 180° quadrature clock signal to provide the complementary signal of the 180° quadrature clock signal.

9. The duty cycle correction circuit according to claim 5, further comprising: A fifth transistor, which is coupled in series with a sixth transistor between the internal node and the power node for the power supply voltage, wherein the fourth node is coupled to the gate of the fifth transistor, and the fifth node for the 270° quadrature clock signal is coupled to the gate of the sixth transistor, the 270° quadrature clock signal being delayed by three-quarters of the period of the output clock signal relative to the 0° quadrature clock signal; and A seventh transistor, which is coupled in series with an eighth transistor between the internal node and the power node, wherein the first node is coupled to the gate of the seventh transistor, and a sixth node for the complementary signal of the 270° quadrature clock signal is coupled to the gate of the eighth transistor.

10. The duty cycle correction circuit of claim 9, wherein the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor each comprise a p-type metal-oxide-semiconductor (PMOS) transistor.

11. The duty cycle correction circuit according to claim 10, wherein the drain of the fifth transistor and the drain of the seventh transistor are both coupled to the internal node, the source of the fifth transistor is coupled to the drain of the sixth transistor, the source of the seventh transistor is coupled to the drain of the eighth transistor, and the source of the fifth transistor and the source of the eighth transistor are both coupled to the power supply node.

12. The duty cycle correction circuit of claim 1, wherein the duty cycle correction circuit is integrated into a cellular phone.

13. A method for correcting the duty cycle of a clock signal, the method comprising: In response to an assertion of a first quadrature clock signal, the first transistor in a first series transistor pair coupled between the internal node and ground is turned on to discharge the internal node to ground through the first series transistor pair; In response to an assertion of a second quadrature clock signal, the second transistor in the first series transistor pair is turned off, the second quadrature clock signal being delayed by one-quarter of the period of the first quadrature clock signal. In response to the assertion of the second quadrature clock signal, the third transistor in the second series transistor pair coupled between the internal node and ground is turned on to couple the internal node to ground through the second series transistor pair; as well as In response to an assertion of a third quadrature clock signal, the fourth transistor in the second series transistor pair is turned off, the third quadrature clock signal being delayed by half the period of the first quadrature clock signal.

14. The method according to claim 13, further comprising: The voltage of the internal node is inverted to generate an output clock signal with a corrected duty cycle.

15. The method of claim 14, wherein the corrected duty cycle is a 50% duty cycle.

16. The method of claim 14, further comprising: In response to an assertion of the first quadrature clock signal, the fifth transistor in the third series transistor pair coupled between the internal node and the power node for the power supply voltage is turned on to couple the internal node to the power node through the third series transistor pair. In response to an assertion of a fourth quadrature clock signal, the sixth transistor in the third series transistor pair is turned off, the fourth quadrature clock signal being delayed by three-quarters of the period of the clock signal relative to the first quadrature clock signal; In response to the assertion of the fourth quadrature clock signal, the seventh transistor in the fourth series transistor pair coupled between the internal node and the power supply voltage is turned on to couple the internal node to the power supply node through the fourth series transistor pair. as well as In response to an assertion on the first quadrature clock signal, the eighth transistor in the fourth series transistor pair is turned off.

17. A duty cycle correction circuit, the duty cycle correction circuit comprising: An orthogonal clock source is configured to generate a first orthogonal clock signal, a second orthogonal clock signal delayed by one-quarter of a clock period relative to the first orthogonal clock signal, a third orthogonal clock signal delayed by one-half of the clock period relative to the first orthogonal clock signal, and a fourth orthogonal clock signal delayed by three-quarters of the clock period relative to the first orthogonal clock signal. Internal nodes; A first series switch pair, coupled between the internal node and a power node for the power supply voltage, is configured to couple the internal node to the power node in response to an assertion of the third quadrature clock signal, and to isolate the internal node from the power node in response to an assertion of the fourth quadrature clock signal. and A second series switch pair, coupled between the internal node and the power node, is configured to couple the internal node to the power node in response to the assertion of the third quadrature clock signal, and to isolate the internal node from the power node in response to the assertion of the first quadrature clock signal.

18. The duty cycle correction circuit according to claim 17, further comprising: An inverter configured to invert the voltage of the internal node to generate an output clock signal with a corrected duty cycle.

19. The duty cycle correction circuit according to claim 18, wherein the corrected duty cycle is a 50% duty cycle.

20. The duty cycle correction circuit according to claim 17, further comprising: A third series switch pair, coupled between the internal node and ground, is configured to couple the internal node to ground in response to the assertion of the first quadrature clock signal, and to isolate the internal node from ground in response to the assertion of the second quadrature clock signal. and A fourth series switch pair, coupled between the internal node and ground, is configured to couple the internal node to ground in response to the assertion of the second quadrature clock signal, and to isolate the internal node from ground in response to the assertion of the third quadrature clock signal.

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