Partially good block handling in memory devices

Abstract

A program failure at a block of a memory device is detected. Based on detecting the programming failure, it is determined that the block is partially good based on a number of failed bytes in the block. A non-failed portion of the block is identified in response to determining that the block is partially good. A record is stored that indicates that the block is partially good and identifies the non-failed portion of the block.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Application No. 63 / 455,811, filed March 30, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to identifying and disposing of certain good blocks in a memory device. Background Technology

[0004] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Attached Figure Description

[0005] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0006] Figure 1 This is a block diagram illustrating an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2A This is a conceptual diagram illustrating instance interactions between components of a memory subsystem when identifying partially good blocks according to some embodiments of the present disclosure.

[0008] Figure 2B This is a conceptual diagram illustrating instance interactions between components of a memory subsystem when using partially good blocks according to some embodiments of the present disclosure.

[0009] Figure 3 and 4 This is a flowchart illustrating an example method for identifying a subset of good blocks in a memory device according to some embodiments of the present disclosure.

[0010] Figure 5 This is a flowchart illustrating an example method for using a portion of a good block in a memory device according to some embodiments of the present disclosure.

[0011] Figure 6 A block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0012] This disclosure relates to a method for identifying and using partially good blocks (PGBs) of a memory device in a memory subsystem. The memory subsystem may be a storage device (e.g., a solid-state drive (SSD)), a memory module, or a combination of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of other storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a NAND flash memory device. Other examples of non-volatile memory devices are described below. Figure 1 The following description is provided. A NAND memory device may comprise multiple NAND dies. Each die may comprise one or more planes, and each plane comprises multiple blocks. Each block comprises an array including pages (rows) and strings (columns). A string comprises multiple memory cells connected in series. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logic states related to the number of bits stored. The logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0014] Various memory access operations can be performed on memory cells. Data can be written to, read from, and erased from memory cells. Memory cells can be divided into write units, such as pages. For some types of memory devices, a page is the smallest write unit. The page size represents a specific number of cells in a page. For some types of memory devices (such as NAND), memory cells can be divided into erase units, such as blocks. Data can be written page by page to a block. Data can be erased at the block level. However, portions of a block cannot be erased.

[0015] One or more line decoders may be contained within a block of the memory device. The line decoder is used to select a specific word line within a page based on a line address received as input. Signals (e.g., programming data) are transmitted from the line decoder to the selected word line. For some architectures, the line decoder may be placed on the right or left edge of the page, and signals from the line decoder are transmitted across the page from left to right or from right to left.

[0016] Other architectures utilize a central line decoder placed within the page (e.g., at the center of the page). In these architectures, signals from the line decoder are transmitted from within the page (e.g., at the center) to the page edge. This architecture reduces word line load by physically isolating a single page into two, which also helps reduce word line skew and stabilize timing, while also improving the timing of read and program operations.

[0017] Bad blocks (also referred to herein as “invalid blocks”) refer to blocks that are no longer reliably usable for storing or retrieving data, for example, due to defects (e.g., manufacturing defects) or wear and tear, and may incorrectly store bit values. Incorrect bit values ​​are referred to below as invalid bits or faulty bits. Similarly, incorrect byte values ​​are referred to below as invalid bytes or faulty bytes. Growing bad blocks (GBB) refer to blocks that are unreliable due to wear or defects. Growing bad blocks can be identified based on thresholds (e.g., bit error rate (BER) thresholds). Through conventional methods of bad block management, bad blocks are detected and thus marked to prevent data from being written to them.

[0018] In some cases, when a block failure is detected, the failure only affects a portion of the block (also called the "failed portion"), while the other portion (also called the "unfailed portion") can still reliably be used to store and retrieve data. A block with both a failed and unfailed portion is referred to below as a partially good block (PGB). In cases where the failed and unfailed portions constitute half of the block, the block may be called a half-good block (HGB). As an example, as described above, a central row decoder can physically isolate a single page into two, thereby dividing the block into two parts, or more specifically, two halves: a left half and a right half. A block failure may only affect half of the block (the failed half), while the second half (the unfailed half) can still reliably store data. Many conventional methods of bad block management cannot distinguish between fully bad blocks and PGBs, thus wasting the available unfailed portion of the PGB. Other methods of bad block management involve vertically distinguishing between good and bad blocks and adjusting the read level of the HGB based on the serial current mismatch between the use of the full block and the HGB. These methods also utilize other countermeasures, such as reducing the voltage or other programming compensation techniques during read operations, to realign the pre-verification voltage (PVFY) with the read level.

[0019] This disclosure addresses the shortcomings of existing methods for bad block management by using an improved method for identifying and using PGB (Partially Good Block). In contrast to existing methods, this improved method involves horizontally distinguishing between good (non-failed) and bad (failed) portions (e.g., halves) of a block. In an example, the PGB management component of a memory subsystem determines whether a block is a partially good block in response to detecting a failure of a programming operation on the block. The PGB management component determines that a block in the memory device is a PGB based on whether the number of failed bytes in the block meets a first threshold condition (e.g., defining a threshold number of failed bytes). Based on the determination that the block is a PGB, the PGB management component identifies the non-failed (good) portions of the block based on a comparison of the number of failed bytes in each portion of the block. In an example where the row decoder physically isolates the block into left and right halves, the PGB management component determines whether the left or right half is a good (non-failed) half based on a comparison of the number of failed bytes in the left half and the number of failed bytes in the right half. When comparing the number of faulty bytes in each part of a block, the PGB management component can determine the difference between the number of faulty bytes in two parts (e.g., the left and right halves) and determine which part is the good part based on whether the difference meets a second threshold condition (e.g., threshold difference). The PGB management component stores records indicating that the block is a PGB and identifying the non-faulty parts of the block. The PGB management component can store these records in a file system area (e.g., in a lookup table) of the memory subsystem associated with the memory device.

[0020] When a command to perform data operations on a block is received, the memory subsystem accesses the record associated with the block, as described above, whereby the record indicates the block is a PGB and identifies the unfailed (good) portion of the block. Based on the fact that the record indicates the block is a PGB, the PGB management component shuts down the transistor switches of the line decoder on the failed portion side of the block to disable the failed portion and perform data operations on the unfailed portion without interference from the failed portion.

[0021] The PGB handling method, discussed above and described in more detail below, enables the memory subsystem to avoid wasting available memory resources that would otherwise be marked as bad and prevented from storing data. Furthermore, this method simplifies read level handling in the memory subsystem. Additionally, the memory subsystem can reduce power consumption during programming and read operations using this method.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include SSDs, flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or a computing device that includes memory and processing devices.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Fast (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110 (e.g.) to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a host interface. Examples of host interfaces include (but are not limited to) SATA interfaces, PCIe interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, DIMM interfaces (such as DIMM slot interfaces supporting Double Data Rate (DDR), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Fast (NVMe) interface to access components (such as memory device 130). The host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as three-dimensional cross-point (3D cross-point) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on volume resistance variations combined with stackable cross-gate format data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0030] Each of the memory devices 130 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. Memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. For example, a memory device may contain a set of blocks. Design specifications may define constraints on the minimum number of valid blocks in the memory device 130, which may differ from the number of blocks in a block group on the device.

[0031] Although non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0034] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, and the like. Local memory 119 may also include ROM for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0037] The memory subsystem 110 also includes a partial good block (PGB) management component 113 responsible for identifying and handling PGBs in memory devices 130 and 140. More specifically, based on the detection of a programming failure at a block in memory device 130, the PGB management component 113 determines whether a block is a PGB based on the number of faulty bytes in the block. Based on the determination that the block is a PGB, the PGB management component 113 identifies the good (non-faulty) portion of the block and stores a record indicating that the block is a PGB and identifying the non-faulty portion of the block (e.g., in a lookup table in a file storage area associated with memory device 130). When a command to perform a data operation (e.g., a read or write operation) on the block is received, the PGB management component 113 identifies the faulty portion of the block based on the record and disables the faulty portion of the block so that data operations can be performed on the non-faulty portion of the block without interference from the faulty portion. In the foregoing example, the block in memory device 130 is horizontally divided into two halves by a central line decoder: a left half and a right half. After detecting a programming failure at a block, the PGB management component 113 determines that the block is a PGB based on the number of faulty bytes in the block. The PGB management component 113 identifies the left half of the block as the good half and stores a record indicating that the block is a PGB and that the left half of the block is identified as the good half. When a command to perform data operations on the block is received, the PGB component 113 disables the right half of the block by turning off the switching transistor of the line decoder on the right half, and performs data operations on the left half (good half) of the block.

[0038] In some embodiments, the memory subsystem controller 115 includes at least a portion of the data PGB management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the data PGB management component 113 is part of the host system 120, an application, or an operating system. In some embodiments, the local media controller 135 includes at least a portion of the data PGB management component 113.

[0039] Figure 2A and 2B This is a conceptual diagram illustrating instance interactions between components of a memory subsystem when identifying and using certain good blocks in memory device 202 according to some embodiments of the present disclosure. Figure 2A and 2BIn the example described, memory device 202 is an example memory device 130 in the form of a NAND memory device. Memory device 202 includes a plurality of NAND dies. Specifically, in the illustrated example, the memory device includes n dies (dies 0 to n-1). Each die may include one or more planes, and each plane includes multiple blocks, such as block 204. Each block includes a 2D array comprising pages (rows) and strings (columns). A string contains a plurality of memory cells connected in series. Each memory cell is used to represent one or more bit values. A single NAND flash cell includes a transistor that stores charge on a memory layer isolated by upper and lower oxide insulating layers.

[0040] One or more line decoders within a page within a block can physically isolate the page (and therefore the block) into multiple parts. For example, as shown, a line decoder 206 placed at the center of the page within block 204 divides block 204 into a left half 208 and a right half 210. Signals from line decoder 206 are transmitted from the center of the page to the page edge. Physically isolating parts of the page in this way reduces word line load, which helps reduce word line skew and stabilize timing, while also improving the timing of read and program operations.

[0041] As shown, at operation 212, the memory subsystem controller 115 (e.g., from the host system 120) receives a command to program data into memory device 202. At operation 214, the memory subsystem controller 115 performs a programming operation to program data into block 204 of memory device 202. At operation 216, the memory subsystem controller 115 detects a programming failure at block 204.

[0042] Based on the programming failure at block 204, at operation 218, the PGB management component 113 determines whether block 204 is a PGB based on the number of failed bytes in block 204. The PGB management component 113 may determine the number of failed bytes based on a block scan (e.g., counting failed bytes (CFByte)). As an example, the PGB management component 113 may determine that the block is a partially good block based on the number of failed bytes in the block meeting a threshold condition (e.g., based on determining that the number of failed bytes exceeds a threshold number of failed bytes defined by the threshold condition).

[0043] Based on the determination that the block is a partially good block, at operation 220, the PGB management component 113 identifies the non-failed (good) portion of block 204. That is, the PGB management component 113 determines that either the left half 208 or the right half 210 is the good half (non-failed portion) of block 204.

[0044] PGB management component 113 determines which half of block 204 is the non-failed portion based on a comparison of the number of failed bytes in the left half 208 and the number of failed bytes in the right half 210. More specifically, PGB management component 113 determines the difference between the number of failed bytes in the left half 208 and the number of failed bytes in the right half 210 and identifies the non-failed portion based on whether the difference exceeds a threshold difference. For example, PGB management component 113 may determine that the left half 208 of block 204 is the non-failed portion based on the difference exceeding a threshold and may determine that the right half 210 of block 204 is the non-failed portion based on the difference not exceeding a threshold. In this example, the threshold number of failed bytes is greater than the threshold difference.

[0045] At operation 222, the PGB management component 113 stores records indicating that block 204 is a partially good block and identifies the non-invalid portion of the block (e.g., the left half 208 or the right half 210). For example, the PGB management component 113 may store records as a portion of lookup table 224 maintained in a file system area associated with the memory device 202.

[0046] refer to Figure 2B At operation 226, controller 115 receives a command to perform a data operation (e.g., a read operation or a programming operation) on block 204 of memory device 202. In response to receiving the command, at operation 228, controller 115 accesses the storage record associated with block 204. For example, the record may be accessed from lookup table 224 stored in a file system area of ​​memory subsystem 110 associated with memory device 202.

[0047] Based on the fact that the recording indicator block 204 is a PGB, at operation 230, the PGB management component 113 disables the failed portion of the block (left half 208 or right half 210). The processing device can disable the failed half of block 204 (e.g., left half 208 or right half 210) by turning off the switching transistor of the line decoder 206 on the failed half side of block 204.

[0048] At operation 232, controller 115 performs programming or reading operations on the unfailed half of block 204 (e.g., left half 208 or right half 210) without being affected by the (disabled) failed half of block 204.

[0049] It should be understood that although the above examples and other examples described below refer to blocks horizontally divided into two parts (two halves), the techniques for identifying and using PGB described herein are not limited to blocks divided into any specific number of parts. That is, the techniques for identifying and using PGB described herein can be used on blocks divided into more than two parts. For example, the techniques for identifying and using PGB described herein can be used on blocks containing three line decoders that physically isolate the block into four quarters.

[0050] Figure 3 This is a flowchart illustrating an example method 300 for performing identification of a PGB in a memory device according to some embodiments of the present disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The PGB management component 113 is executed. Although the processes are shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0051] Method 300 begins at operation 305, where a processing device (e.g., from host system 120) receives a command to program data into a memory device (e.g., memory device 130). At operation 310, the processing device performs a programming operation to program the data into a block of the memory device.

[0052] At operation 315, the processing device detects a programming failure at the block. That is, the processing device detects a failure of the programming operation performed at operation 310. In response to detecting the programming failure, at operation 320, the processing device determines the number of failed bytes in the block. The processing device may determine the number of failed bytes based on a block scan. In a more specific instance, the processing device may determine the number of failed bytes by performing a count failed byte (CFByte) scan on the block.

[0053] The processing device determines that the block is partially good based on the number of failed bytes (operation 325). As an example, the processing device may determine that the block is a PGB based on the number of failed bytes in the block satisfying a threshold condition (e.g., based on determining that the number of failed bytes does not exceed a threshold number of failed bytes defined by the threshold condition).

[0054] Based on the determination that the block is partially good, at operation 330, the processing device identifies the non-failed (good) portion of the block. The processing device can identify the non-failed portion of the block based on a comparison of the number of failed bytes in each part of the block. In this example, the block is horizontally divided into two halves by the center line decoder, and the processing device identifies the left or right half as the non-failed portion of the block based on a comparison of a first number of failed bytes in the left half of the block and a second number of failed bytes in the right half of the block.

[0055] At operation 335, the processing device stores a record indicating that the block is a PGB and identifying a non-invalid portion of the block. For example, the processing device may store the record as a portion of a lookup table maintained in a file system area associated with the memory device.

[0056] like Figure 4 As shown, in some embodiments, method 300 may include operations 405, 410, 415, 420, and 425. According to these embodiments, operation 405 may be performed as part of operation 325 in which the processing device determines that a block is partially good based on the number of failed bytes. At operation 405, the processing device determines that the number of failed bytes in the block satisfies a first threshold condition. As an example, the first threshold condition may define a threshold number of failed bytes in the block, and determining that satisfying the first threshold condition includes determining that the number of failed bytes in the block does not exceed the threshold number of failed bytes.

[0057] According to these embodiments, operations 410, 415, 420, and 425 can be performed as part of operation 330, in which the processing device identifies the non-failed portions of the block. At operation 410, the processing device determines a first number of failed bytes in a first portion of the block (e.g., a first half of the block), and at operation 415, the processing device determines a second number of failed bytes in a second portion of the block (e.g., a second half of the block). The processing device can determine the first and second numbers of failed bytes by performing an individual scan (e.g., a failed byte scan) of each portion of the block.

[0058] The processing device compares a first number of failed bytes with a second number of failed bytes to determine which part of the block is not failed. For example, as shown, at operation 420, the processing device determines the difference between the first number of failed bytes and the second number of failed bytes, and at operation 425, the processing device identifies the not failed portion based on a comparison of the difference with a difference threshold defined by a second threshold condition. As an example, the second threshold condition may define a threshold difference, and the processing device identifies which part of the block is not failed based on whether the difference exceeds the threshold difference. That is, the processing device may determine that a first part (e.g., the left half) of the block is not failed based on the difference exceeding the threshold, and when the difference does not exceed the threshold, the processing device may identify a second part (e.g., the right half) as not failed. According to some embodiments, the threshold number of failed bytes defined by the first threshold condition is greater than the threshold difference defined by the second threshold condition.

[0059] Figure 5 This is a flowchart illustrating an example method 500 for using a PGB in a memory device according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The PGB management component 113 is executed. Although the processes are shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 505, the processing device receives a command to perform a data operation on a block of a memory device (e.g., memory device 130). In response to receiving the command, at operation 510, the processing device accesses a record associated with the block. The record indicates that the block is a PGB and identifies a non-invalid portion of the block. For example, the record may be accessed from a lookup table stored in a file system area associated with the block. At operation 515, the processing device identifies an invalid portion of the block based on the non-invalid portion indicated by the record. In an example, the record indicates that the first half (e.g., the left half) of the block is an invalid portion, and based on the record indicating that the first half is an invalid portion, the processing device identifies the second half (e.g., the right half) of the block as an invalid portion.

[0061] Since the block is partially good, at operation 520, the processing device disables the failed portion of the block, thereby allowing the processing device to perform data operations on the unfailed portion of the block, which is performed at operation 525. As an example, the block may include two halves physically isolated by the line decoder. That is, the block may include a first half (e.g., the left half) and a second half (e.g., the right half) separated by the line decoder. The processing device can disable the failed half of the block by turning off the switching transistors of the line decoder on the failed half, so that data operations are directed to the unfailed half.

[0062] The implementation scheme of the subject matter described may include one or more features individually or in combination, as illustrated by examples below.

[0063] Example 1. A memory subsystem comprising: a memory device; and a processing means operatively coupled to the memory device and configured to perform operations including: detecting a programming failure at a block of the memory device; determining, based on the number of failed bytes in the block, that the block is partially good, based on the detected programming failure; identifying a non-failed portion of the block in response to determining that the block is partially good; and storing a record indicating that the block is partially good and identifying the non-failed portion of the block.

[0064] Example 2. The memory subsystem according to Example 1, wherein the operation further includes: receiving a command to perform a data operation on the block; accessing the record in response to the command; deactivating a failed portion of the block based on the command indicating that the block is partially good; and performing the data operation on the unfailed portion of the block when the failed portion of the block is deactivated.

[0065] Example 3. A memory subsystem according to either Example 1 or 2, wherein the operation further includes identifying the failed portion of the block based on the record.

[0066] Example 4. A memory subsystem according to any one of Examples 1 to 3, wherein: the block includes a row decoder that horizontally divides the failed portion and the unfailed portion of the block; and the deactivation of the failed portion of the block includes deactivating one or more switching transistors of the row decoder corresponding to the failed portion of the block.

[0067] Example 5. A memory subsystem according to any of Examples 1 to 4, wherein determining that the block is a partially good block includes determining that the number of faulty bytes satisfies a threshold condition.

[0068] Example 6. A memory subsystem according to any one of Examples 1 to 5, wherein: the threshold condition defines a threshold number of invalid bytes; and determining that the number of invalid bytes satisfies the threshold condition includes determining that the number of invalid bytes does not exceed the threshold number of invalid bytes.

[0069] Example 7. A memory subsystem according to any one of Examples 1 to 6, wherein identifying the non-failed portion of the block includes: determining a first number of failed bytes in a first portion of the block; determining a second number of failed bytes in a second portion of the block; and comparing the first number of failed bytes with the second number of failed bytes.

[0070] Example 8. A memory subsystem according to any one of Examples 1 to 7, wherein comparing the first number of invalid bytes with the second number of invalid bytes includes: determining the difference between the first number of invalid bytes and the second number of invalid bytes; and determining whether the difference satisfies a threshold condition.

[0071] Example 9. A memory subsystem according to any one of Examples 1 to 8, wherein the block includes a central row decoder that horizontally divides the block into a left half and a right half, and the non-failed portion of the block corresponds to the left half or the right half of the block.

[0072] Example 10. A memory subsystem according to any one of Examples 1 to 9, wherein the operation further includes performing a failed byte count scan on the block to determine the number of failed bytes.

[0073] Example 11. A method comprising: executing programming commands on a block of a memory device by a processing means, the block of the memory device being divided into a first portion and a second portion; detecting a programming failure at the block of the memory device based on the execution of the programming commands by the processing means; determining, based on the detected programming failure, that the block is partially good by the processing means based on the number of failed bytes in the block; identifying, by the processing means, the first portion or the second portion as a non-failed portion of the block in response to determining that the block is partially good; and storing, by the processing means, a record indicating that the block is partially good and identifying the non-failed portion of the block.

[0074] Example 12. The method according to Example 11 further includes: receiving a command to perform a data operation on the block; accessing the record in response to the command; deactivating a faulty portion of the block based on the command indicating that the block is partially good; and performing the data operation on the non-faulty portion of the block when the faulty portion of the block is deactivated.

[0075] Example 13. The method according to any one of Examples 11 or 12, wherein the operation further includes identifying the failed portion of the block based on the record.

[0076] Example 14. The method according to any of Examples 11 to 13, wherein: the block includes a line decoder that horizontally divides the failed portion and the unfailed portion of the block; and the deactivation of the failed portion of the block includes deactivating one or more switching transistors of the line decoder corresponding to the failed portion of the block.

[0077] Example 15. The method according to any of Examples 11 to 14, wherein determining that the block is a partially good block includes determining that the number of invalid bytes satisfies a threshold condition.

[0078] Example 16. The method according to any of Examples 11 to 15, wherein: the threshold condition defines a threshold number of invalid bytes; and determining that the number of invalid bytes satisfies the threshold condition includes determining that the number of invalid bytes does not exceed the threshold number of invalid bytes.

[0079] Example 17. The method according to any one of Examples 11 to 16, wherein identifying the non-failed portion of the block includes: determining a first number of failed bytes in a first portion of the block; determining a second number of failed bytes in a second portion of the block; and comparing the first number of failed bytes with the second number of failed bytes.

[0080] Example 18. The method according to any of Examples 11 to 17, wherein comparing the first number of invalid bytes with the second number of invalid bytes includes: determining the difference between the first number of invalid bytes and the second number of invalid bytes; and determining whether the difference satisfies a threshold condition.

[0081] Example 19. The method according to any one of Examples 11 to 18, wherein the block includes a central row decoder that horizontally divides the block into a left half and a right half, and the non-failed portion of the block corresponds to the left half or the right half of the block.

[0082] Example 20. A non-transitory computer-readable storage medium comprising instructions, which, when executed by a processing means, configure the processing means to perform operations including: detecting a programming failure at a block of a memory means, the block of the memory means being horizontally divided into a first half and a second half; determining, based on the detection of the programming failure, that the block is partially good based on the number of failed bytes in the block; determining, in response to determining that the block is partially good, that the first half of the block is a non-failed portion of the block; and storing a record indicating that the block is partially good and identifying the first half as the non-failed portion of the block.

[0083] Figure 6 An example machine in the form of a computer system 600 is described, within which a set of instructions can be executed to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the PGB management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines on a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0084] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0085] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., ROM, flash memory, DRAM (e.g., SDRAM or RDRAM)), a static memory 606 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 618, which communicate with each other via a bus 630.

[0086] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an ASIC, FPGA, digital signal processor (DSP), network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0087] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 626 or software embodying any or more of the methodologies or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0088] In one embodiment, instruction 626 includes instructions for implementing a data corruption component (e.g., Figure 1 The data PGB management component 113) provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0089] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived here as self-consistent sequences of operations that lead to desired results. Operations are those that require physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0090] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0091] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), ROM, RAM, EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0092] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the appended claims. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0093] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as ROM, RAM, disk storage media, optical storage media, flash memory components, etc.

[0094] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It should be understood that various modifications may be made to the present disclosure without departing from the broader scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A memory subsystem comprising: Memory devices; and A processing device, operatively coupled to the memory device, configured to perform operations including: The programmable block of the memory device failed to be programmed. Based on the detected programming failure, the block is determined to be partially good based on the number of invalid bytes in the block; In response to determining that the block is partially good, the non-failed portion of the block is identified; and The storage indicates that the block is partially good and identifies the non-failed portion of the block.

2. The memory subsystem according to claim 1, wherein the operation further comprises: Receive commands to perform data operations on the block; Access the record in response to the command; Based on the command indicating that the block is partially good, the faulty part of the block is deactivated; and When the failed portion of the block is deactivated, the data operation is performed on the unfailed portion of the block.

3. The memory subsystem of claim 2, wherein the operation further includes identifying the failed portion of the block based on the record.

4. The memory subsystem according to claim 2, wherein: The block includes a line decoder that horizontally divides the failed portion and the unfailed portion of the block; and The deactivation of the failed portion of the block includes deactivating one or more switching transistors of the line decoder corresponding to the failed portion of the block.

5. The memory subsystem of claim 1, wherein determining that the block is a partially good block includes determining that the number of invalid bytes satisfies a threshold condition.

6. The memory subsystem according to claim 5, wherein: The threshold condition defines the threshold number of invalid bytes; and Determining that the number of invalid bytes satisfies the threshold condition includes determining that the number of invalid bytes does not exceed the threshold number of invalid bytes.

7. The memory subsystem of claim 1, wherein identifying the non-failed portion of the block comprises: Determine the first number of invalid bytes in the first part of the block; Determine a second number of invalid bytes in the second part of the block; and Compare the first number of invalid bytes with the second number of invalid bytes.

8. The memory subsystem of claim 7, wherein comparing the first number of invalid bytes with the second number of invalid bytes comprises: Determine the difference between the first number of invalid bytes and the second number of invalid bytes; and Determine whether the difference satisfies the threshold condition.

9. The memory subsystem of claim 1, wherein the block includes a central row decoder that horizontally divides the block into a left half and a right half, and the non-failed portion of the block corresponds to the left half or the right half of the block.

10. The memory subsystem of claim 1, wherein the operation further comprises performing a failed byte count scan on the block to determine the number of failed bytes.

11. A method comprising: The processing device executes programming commands on a block of the memory device, the block of the memory device being divided into a first part and a second part; The processing device detects programming failures at the block of the memory device based on the execution of the programming commands. Based on the detection of the programming failure, the processing device determines that the block is partially good based on the number of faulty bytes in the block; In response to determining that the block is partially good, the processing device identifies the first portion or the second portion as the non-failed portion of the block; and The processing device stores records indicating that the block is partially good and identifying the non-failed portions of the block.

12. The method of claim 11, further comprising: Receive commands to perform data operations on the block; Access the record in response to the command; Based on the command indicating that the block is partially good, the faulty part of the block is deactivated; and When the failed portion of the block is deactivated, the data operation is performed on the unfailed portion of the block.

13. The method of claim 12, wherein the operation further comprises identifying the failed portion of the block based on the record.

14. The method according to claim 12, wherein: The block includes a line decoder that horizontally divides the failed portion and the unfailed portion of the block; and The deactivation of the failed portion of the block includes deactivating one or more switching transistors of the line decoder corresponding to the failed portion of the block.

15. The method of claim 11, wherein determining that the block is a partially good block includes determining that the number of invalid bytes satisfies a threshold condition.

16. The method of claim 15, wherein: The threshold condition defines the threshold number of invalid bytes; and Determining that the number of invalid bytes satisfies the threshold condition includes determining that the number of invalid bytes does not exceed the threshold number of invalid bytes.

17. The method of claim 11, wherein identifying the non-failed portion of the block comprises: Determine the first number of invalid bytes in the first part of the block; Determine a second number of invalid bytes in the second part of the block; and Compare the first number of invalid bytes with the second number of invalid bytes.

18. The method of claim 16, wherein comparing the first number of invalid bytes with the second number of invalid bytes comprises: Determine the difference between the first number of invalid bytes and the second number of invalid bytes; and Determine whether the difference satisfies the threshold condition.

19. The method of claim 11, wherein the block includes a central line decoder that horizontally divides the block into a left half and a right half, and the non-failed portion of the block corresponds to the left half or the right half of the block.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, configure the processing means to perform operations including: A programming failure was detected at a block of the memory device, and the block of the memory device was horizontally divided into a first half and a second half; Based on the detected programming failure, the block is determined to be partially good based on the number of invalid bytes in the block; In response to determining that the block is partially good, the first half of the block is determined to be the unfailed part of the block; and The storage indicates that the block is partially good and identifies the first half as the non-failed part of the block.

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