Integrated mems inertial device and method of fabrication

Abstract

This invention relates to a method for fabricating an integrated MEMS inertial device and the MEMS inertial device fabricated based on this method. The method includes: bonding a blank wafer onto an ASIC wafer; thinning the blank wafer; performing photolithographic alignment based on alignment marks on the ASIC wafer; subsequently etching the blank wafer into a device layer wafer to obtain a first bond; bonding a cap wafer onto the first bond; thinning both the ASIC wafer and the cap wafer to obtain a second bond; dicing the second bond to obtain a single MEMS inertial device; and performing signal extraction operations on the MEMS inertial device. In this invention, bonding a blank wafer onto the ASIC wafer first, and then fabricating the blank wafer into a device layer wafer, avoids pattern deviations caused by the alignment and bonding operations of two wafers. Moreover, pre-fabricating alignment marks on the ASIC wafer, based on the precision of photolithographic alignment, ensures the alignment accuracy between the device layer wafer and the ASIC wafer, thus guaranteeing the product quality and performance of the MEMS inertial device.

Description

Technical Field

[0001] This invention relates to a method for fabricating an integrated MEMS inertial device and the integrated MEMS inertial device prepared based on the method. Background Technology

[0002] MEMS inertial sensors include accelerometers, gyroscopes, or a combination thereof. Accelerometers are used to measure the acceleration of an object, gyroscopes are used to measure the angular velocity of an object, and the combined test of acceleration and angular velocity can be used to describe the motion state of an object.

[0003] Existing MEMS inertial sensors encapsulate discrete MEMS sensing chips and ASIC signal processing chips within a single housing via wire bonding. Current MEMS inertial sensing chips typically employ multilayer wafer bonding (specifically, bonding a substrate wafer, a device wafer, and a cap wafer) to seal the inertial measurement device structure within a miniature cavity. However, misalignment between the wafers due to the bonding process causes misalignment of the support anchor points in the movable device structure, resulting in unnecessary internal stress and impacting device performance stability.

[0004] Then, the MEMS inertial sensing chip and the ASIC signal processing chip are packaged in a single package using wire bonding. Whether the two chips are laid flat or stacked, the final sensor size is large, the manufacturing process is complex, the cost is high, and the signal between the chips is transmitted through wires, resulting in long transmission distances, low efficiency, and high noise. Summary of the Invention

[0005] This invention relates to a method for fabricating an integrated MEMS inertial device and an integrated MEMS inertial device fabricated based on this method, which can at least solve some of the defects of the prior art.

[0006] This invention relates to a method for fabricating an integrated MEMS inertial device, comprising:

[0007] S1 provides an ASIC wafer;

[0008] S2, a blank wafer is bonded on the ASIC wafer, the blank wafer is thinned, photolithographic alignment is performed based on the alignment marks on the ASIC wafer, and then the blank wafer is etched into a device layer wafer to obtain a first bond containing the ASIC wafer and the device layer wafer;

[0009] S3, a cap wafer is bonded to the first bonding body, and the ASIC wafer and the cap wafer are thinned to obtain a second bonding body;

[0010] S4, the second bond body is diced to obtain a single MEMS inertial device, and a signal extraction operation is performed on the MEMS inertial device.

[0011] As one implementation method, photolithographic alignment based on alignment marks on the ASIC wafer specifically includes:

[0012] Photolithographic alignment is performed by detecting the long-wave infrared light emitted from the alignment marks on the ASIC wafer using a long-wave infrared lens.

[0013] As one implementation method, photolithographic alignment based on alignment marks on the ASIC wafer specifically includes:

[0014] The corresponding area of ​​the blank wafer is etched to expose the alignment marks on the ASIC wafer, and then photolithographic alignment is performed.

[0015] As one implementation method, in S1, a conductive portion and a bonding connection portion are fabricated on the ASIC wafer; in S2, the bonding connection portion is used to realize the bonding between the ASIC wafer and the blank wafer, and the conductive portion is used to realize the electrical conduction between the device layer wafer and the ASIC wafer.

[0016] As one implementation method, pre-fabricating the conductive portion and bonding connection portion on the ASIC wafer specifically includes:

[0017] A passivation layer is grown on the ASIC wafer, and electrical connection holes and bonding anchors are fabricated on the ASIC wafer through photolithography, etching and cleaning processes.

[0018] Conductive metal is grown in the electrical connection hole, bonding metal is grown on the bonding anchor, and patterning is performed.

[0019] As one implementation method, in S1, an electrical interface and a sensing signal interface are prefabricated on the ASIC wafer, and then the conductive part and the bonding connection part are fabricated. The electrical interface is used for signal output, and the conductive part is fabricated on the sensing signal interface.

[0020] As one implementation method, a metal wiring layer is grown on the ASIC wafer, and the metal wiring layer is patterned to form a sensing signal interface and an electrical interface on the surface of the ASIC wafer.

[0021] As one implementation method, in S1, a TSV structure is fabricated inside the ASIC wafer; in S3, when the ASIC wafer is thinned, the ASIC wafer is thinned to the end of the TSV structure and a solder joint is fabricated at the end of the TSV structure; in S4, a signal lead-out structure is connected by pressure welding at the solder joint.

[0022] As one implementation method, the ASIC wafer is eutectic bonded to the blank wafer; the cap wafer is bonded to the first bond body by eutectic bonding or fusion bonding.

[0023] The present invention also relates to an integrated MEMS inertial device fabricated using the fabrication method described above.

[0024] The present invention has at least the following beneficial effects:

[0025] In this invention, a method is adopted to first bond a blank wafer onto an ASIC wafer and then fabricate the blank wafer into a device layer wafer. This avoids pattern deviations caused by the alignment and bonding operations of the two wafers, ensures the alignment accuracy between the device layer wafer and the ASIC wafer, thereby ensuring the product quality of MEMS inertial devices and improving the performance of MEMS inertial devices.

[0026] In this invention, by pre-fabricating alignment marks on the ASIC wafer, the alignment accuracy between the device layer wafer and the ASIC wafer can be guaranteed based on the precision of photolithographic alignment. This includes, but is not limited to, the alignment accuracy between the pattern on the device layer wafer and the anchor point on the ASIC wafer, thereby ensuring the product quality of MEMS inertial devices and improving the performance of MEMS inertial devices. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram illustrating the preprocessing of ASIC wafers;

[0029] Figure 2 This is a schematic diagram showing the integration of the ASIC wafer and the device layer wafer.

[0030] Figure 3 This is a flowchart of the fabrication method using a TSV-structured electrical interface (intermediate steps omitted). Detailed Implementation

[0031] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Example 1: As Figure 1 and Figure 2 This invention provides a method for fabricating an integrated MEMS inertial device 200, comprising:

[0033] S1 provides an ASIC wafer 1;

[0034] S2, a blank wafer 2 is bonded on the ASIC wafer 1, and the blank wafer 2 is fabricated into a device layer wafer 20 to obtain the first bond;

[0035] S3, bond the cap wafer 3 to the first bonding body, thin the ASIC wafer 1 and the cap wafer 3, and obtain the second bonding body 100;

[0036] S4, the second bonding body 100 is diced to obtain a single MEMS inertial device 200, and a signal extraction operation is performed on the MEMS inertial device 200.

[0037] Specifically, the blank wafer 2 refers to a wafer without a pattern.

[0038] The blank wafer 2 and the ASIC wafer 1 are preferably bonded using a eutectic bonding method. Since it is a blank wafer 2, this process can avoid pattern deviations caused by dual wafer alignment and eutectic bonding.

[0039] In one embodiment, S2, fabricating the blank wafer 2 into a device layer wafer 20 specifically includes:

[0040] Thinning the blank wafer 2,

[0041] Photolithographic alignment is performed based on the alignment marks on the ASIC wafer 1, and then the blank wafer 2 is etched to obtain the device layer wafer 20.

[0042] Optionally, when thinning the blank wafer 2, the thickness of the blank wafer 2 can be reduced to the range of 5~80μm, which is beneficial to the fabrication of the device layer wafer 20.

[0043] By pre-fabricating alignment marks on the ASIC wafer 1, the alignment accuracy between the device layer wafer 20 and the ASIC wafer 1 can be guaranteed based on the precision of photolithographic alignment. This includes, but is not limited to, the alignment accuracy between the pattern on the device layer wafer 20 and the anchor point on the ASIC wafer 1, thereby ensuring the product quality of the MEMS inertial device 200 and improving the performance of the MEMS inertial device 200.

[0044] In one embodiment, photolithographic alignment based on alignment marks on the ASIC wafer 1 specifically includes: using a long-wave infrared lens to detect the long-wave infrared emitted by the alignment marks on the ASIC wafer 1 (long-wave infrared can penetrate silicon material), thereby performing photolithographic alignment. This alignment method can ensure the alignment accuracy between the device layer wafer 20 and the ASIC wafer 1.

[0045] In another embodiment, photolithographic alignment based on the alignment marks on the ASIC wafer 1 specifically includes: etching the corresponding area of ​​the blank wafer 2 to expose the alignment marks on the ASIC wafer 1, and then performing photolithographic alignment. This method can be performed using a conventional visible light lens, making it convenient and reliable. In this method, the alignment accuracy is mainly determined by the performance of the photolithography machine, and the pattern offset can generally be controlled within 100nm.

[0046] Understandably, the blank wafer 2 is etched by photolithography, and an inertial sensitive structure is formed in the device layer wafer 20.

[0047] The ASIC wafer 1 and the blank wafer 2 are preferably bonded using a eutectic bonding method.

[0048] In one embodiment, such as Figure 1 and Figure 2 By prefabricating a bonding connection portion on the ASIC wafer 1, and realizing the bonding between the ASIC wafer 1 and the blank wafer 2 based on the bonding connection portion, the bonding efficiency and quality between the ASIC wafer 1 and the blank wafer 2 can be improved.

[0049] Optionally, such as Figure 1 The pre-fabrication of bonding connections on the ASIC wafer 1 specifically includes:

[0050] A passivation layer 13 is grown on the ASIC wafer 1, and bonding anchors are fabricated on the ASIC wafer 1 through photolithography, etching, and cleaning processes.

[0051] Bonding metal is grown on the bonded anchor post and patterned.

[0052] When ASIC wafer 1 is bonded to blank wafer 2, blank wafer 2 is connected to the aforementioned bonding anchor.

[0053] In one embodiment, such as Figure 1 A conductive part is prefabricated on the ASIC wafer 1, and electrical conduction between the device layer wafer 20 and the ASIC wafer 1 is realized based on the conductive part, which can ensure the reliability of signal transmission between the device layer wafer 20 and the ASIC wafer 1.

[0054] Optionally, such as Figure 1 The pre-fabrication of the conductive portion on the ASIC wafer 1 specifically includes:

[0055] A passivation layer 13 is grown on the ASIC wafer 1, and electrical connection holes 14 are fabricated on the ASIC wafer 1 through photolithography, etching, and cleaning processes.

[0056] Conductive metal 15 is grown in the electrical connection hole 14 and patterned.

[0057] The electrical conduction and signal transmission between the device layer wafer 20 and the ASIC wafer 1 are achieved through the aforementioned conductive part. This not only results in a short transmission distance and high efficiency, but also improves the quality of signal transmission, reduces noise, and ensures high reliability of the electrical connection.

[0058] Preferably, the conductive portion and the bonding connection portion are fabricated simultaneously. For example, after growing a passivation layer 13 on the ASIC wafer 1, electrical connection holes 14 and bonding anchors are fabricated on the ASIC wafer 1 through photolithography, etching, and cleaning processes; conductive metal 15 is grown in the electrical connection holes 14, bonding metal is grown on the bonding anchors, and patterning is performed. Figure 1 The conductive part and the bonding connection part can adopt the same structure, which can further simplify the process.

[0059] Optionally, the thickness of the passivation layer 13 is in the range of 1 to 10 μm, and it can be silicon oxide, silicon nitride or undoped polycrystalline silicon; the thickness of the conducting metal and the bonding metal is preferably controlled in the range of 1 to 5 μm, and the conducting metal can be titanium, tungsten or aluminum, etc., and the bonding metal can be aluminum germanium or gold, etc.

[0060] In one embodiment, in S1, a sensing signal interface 12 is pre-fabricated on the ASIC wafer 1. This sensing signal interface 12 is used for electrical communication with the device layer wafer 20. When the aforementioned conductive portion is fabricated, the conductive portion is electrically connected to the sensing signal interface 12; for example, the conductive portion is fabricated on the sensing signal interface 12. Optionally, as... Figure 1 A metal wiring layer is grown on the ASIC wafer 1, and the metal wiring layer is patterned to form a sensing signal interface 12 on the surface of the ASIC wafer 1.

[0061] In one embodiment, in S1, an electrical interface 11 is pre-fabricated on the ASIC wafer 1, the electrical interface 11 being used for signal output. As an alternative approach, such as... Figure 1 A metal wiring layer is grown on the ASIC wafer 1, and the metal wiring layer is patterned to form an electrical interface 11 on the surface of the ASIC wafer 1; preferably, as shown in the figure. Figure 2In step S4, the electrical interface 11 for signal extraction is located outside the projection range of the cap wafer 3 on the ASIC wafer 1. Signal extraction can be performed based on this electrical interface 11, which is convenient to operate. The electrical interface 11 can be fabricated simultaneously with the aforementioned sensing signal interface 12. Specifically, after growing a metal wiring layer on the ASIC wafer 1, the metal wiring layer is patterned to form the sensing signal interface 12 and the electrical interface 11 on the surface of the ASIC wafer 1.

[0062] The aforementioned metal wiring layer can be made of metals such as titanium, tungsten, gold, or aluminum, and its thickness is preferably in the range of 100~1000nm; the patterning of the metal wiring layer can be achieved by etching or stripping processes.

[0063] As another alternative, such as Figure 3 In step S3, a TSV structure 110 is prefabricated inside the ASIC wafer 1. In step S4, when thinning the ASIC wafer 1, it is thinned to the end of the TSV structure 110, thus exposing one end of the TSV structure 110. A solder joint 111 is fabricated at the end of the TSV structure 110. In step S5, based on the solder joint 111, signal leads are made using pressure bonding, specifically by bonding signal lead-out structures (including but not limited to signal connection lines) at the solder joint 111. Preferably, the TSV structure 110 is fabricated during ASIC design and wafer fabrication.

[0064] The cap wafer 3 can be bonded to the device layer wafer 20 or to the ASIC wafer 1. The bonding method can be eutectic bonding, and correspondingly, metals such as aluminum germanium / gold can be grown in the bonding area (which can be on the cap wafer 3 and / or on the first bond body), with a thickness preferably of 500~1000um; or a fusion bonding method can be used, and correspondingly, glass paste is printed in the bonding area, with a thickness preferably of 1~10μm.

[0065] Optionally, the cavity depth of the cap wafer 3 is in the range of 5~20μm.

[0066] Optionally, after the ASIC wafer 1 and the cap wafer 3 are thinned, the total wafer thickness of the resulting second bond 100 is in the range of 300~600μm.

[0067] Example 2: This embodiment of the invention provides an integrated MEMS inertial device 200, which is fabricated using the same method as the integrated MEMS inertial device 200 described in Example 1.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating an integrated MEMS inertial device, characterized in that, include: S1 provides an ASIC wafer; S2, a blank wafer is bonded on the ASIC wafer, the blank wafer is thinned, photolithographic alignment is performed based on the alignment marks on the ASIC wafer, and then the blank wafer is etched into a device layer wafer to obtain a first bond containing the ASIC wafer and the device layer wafer; Specifically, photolithographic alignment based on alignment marks on the ASIC wafer includes: The corresponding area of ​​the blank wafer is etched to expose the alignment marks on the ASIC wafer, and then photolithographic alignment is performed using a visible light lens; S3, a cap wafer is bonded to the first bonding body, and the ASIC wafer and the cap wafer are thinned to obtain a second bonding body; S4, the second bond body is diced to obtain a single MEMS inertial device, and a signal extraction operation is performed on the MEMS inertial device.

2. The method for fabricating an integrated MEMS inertial device as described in claim 1, characterized in that, In S1, the ASIC wafer is fabricated with conductive parts and bonding connection parts; In S2, the bonding connection portion is used to bond the ASIC wafer to the blank wafer, and the conductive portion is used to conduct electricity between the device layer wafer and the ASIC wafer.

3. The method for fabricating an integrated MEMS inertial device as described in claim 2, characterized in that, Pre-fabrication of conductive parts and bonding connections on the ASIC wafer specifically includes: A passivation layer is grown on the ASIC wafer, and electrical connection holes and bonding anchors are fabricated on the ASIC wafer through photolithography, etching and cleaning processes. Conductive metal is grown in the electrical connection hole, bonding metal is grown on the bonding anchor, and patterning is performed.

4. The method for fabricating an integrated MEMS inertial device as described in claim 2, characterized in that, In S1, an electrical interface and a sensing signal interface are prefabricated on the ASIC wafer, and then the conductive part and the bonding connection part are fabricated. The electrical interface is used for signal output, and the conductive part is fabricated on the sensing signal interface.

5. The method for fabricating an integrated MEMS inertial device as described in claim 4, characterized in that, A metal wiring layer is grown on the ASIC wafer, and the metal wiring layer is patterned to form a sensing signal interface and an electrical interface on the surface of the ASIC wafer.

6. The method for fabricating an integrated MEMS inertial device as described in claim 1, characterized in that, In S1, a TSV structure is fabricated inside the ASIC wafer; In step S3, when thinning the ASIC wafer, the ASIC wafer is thinned to the end of the TSV structure, and solder joints are formed at the end of the TSV structure. In S4, a signal lead-out structure is pressure welded at the solder joint.

7. The method for fabricating an integrated MEMS inertial device as described in claim 1, characterized in that, The ASIC wafer is eutectic bonded to the blank wafer; the cap wafer is bonded to the first bond body by eutectic bonding or fusion bonding.

8. An integrated MEMS inertial device, characterized in that, The integrated MEMS inertial device is fabricated using the method described in any one of claims 1 to 7.

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