Supply voltage detection circuit and circuit system using same

Abstract

The invention provides a supply voltage detection circuit and a circuit system using the same. The supply voltage detection circuit is provided with a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives a supply voltage and is used for detecting the supply voltage to generate a low-voltage detection signal. When the supply voltage is lower than a set level, the low-voltage detection signal output by the voltage detection circuit closes the current clamping circuit, and transistor current flowing through the voltage detection circuit is in direct proportion to the supply voltage; when the supply voltage is greater than or equal to the set level, the low-voltage detection signal output by the voltage detection circuit starts the current clamping circuit, and the current clamping circuit provides a fixed current to maintain the operation of the voltage detection circuit. Wherein the transistor current flowing through the voltage detection circuit is proportional to the fixed current. The supply voltage detection circuit provided by the invention has the characteristics of high accuracy, low temperature drift and low power consumption.

Description

[0001] This application is a divisional application of the original application with the application number 202110504830.8 and the original filing date of May 10, 2021, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to a supply voltage detection circuit, and in particular to a supply voltage detector with stable temperature coefficient, low power consumption and fast response, and a circuit system using the same. BACKGROUND

[0003] A supply voltage detection circuit is also known as a brown out detector (BOD) or a low voltage detector (LVD). After the circuit system is powered on, the microcontroller will start the power supply voltage detection mechanism to determine the working mode under low voltage, and even as the basis for switching different power sources. Therefore, the accuracy and temperature characteristics of voltage detection are very important, and the power consumption and response speed of voltage detection are also discussed in the specification. Since the supply voltage detection circuit needs to detect the supply voltage (for example, VDD), one of the common methods is to use a voltage divider resistor string to divide the supply voltage to generate a sensing voltage, and compare the sensing voltage with the reference voltage generated by the band gap voltage generator to determine whether to operate the circuit system in the low voltage working mode or start to enter the normal working mode. Generally, the response speed and power consumption of the supply voltage detection circuit are usually a trade-off relationship with respect to the circuit area.

[0004] Please refer to Figure 1 , Figure 1Figure 1 is a circuit diagram of a conventional supply voltage detection circuit. In the supply voltage detection circuit 1, MOS transistor MN1, PMOS transistor MP1 and resistor R3 form a latch circuit, and resistors R1 and R2 are used as a voltage divider resistor string. The low voltage detection signal BODOUT outputted by the supply voltage detection circuit 1 is related to the threshold voltage (VTH) of the MOS transistor MN1 and the PMOS transistor MP1. In the integrated circuit manufacturing process, the variation of the threshold voltage is as high as ±20%, and even in the slow-fast (SF) or fast-slow (FS) corner, the variation of the threshold voltage can reach 40%. This will cause the supply voltage detection circuit 1 to output an incorrect low voltage detection signal BODOUT. For example, the expected start-up voltage is 1.7 volts (i.e., when the supply voltage VDD is greater than or equal to 1.7 volts, the low voltage detection signal BODOUT outputted is a logic low level, so that the circuit system starts up and operates in the normal mode), but the actual start-up voltage falls between 1.36 and 2.04 volts.

[0005] Please refer to Figure 2 , Figure 2 Figure 2 is a circuit diagram of another conventional supply voltage detection circuit. The supply voltage detection circuit 2 includes an energy gap voltage generator 21 (formed by comparator CMP2, PMOS transistors MP1- MP3, resistors R3- R6 and BJT transistors Q1- Q3), a voltage divider resistor string (formed by resistors R1 and R2 in series) and a comparator CMP1. At the beginning, the supply voltage detection circuit 2 operates the energy gap voltage generator 21, and then uses the sensing voltage VSEN generated by the resistor voltage divider resistor string to compare with the reference voltage VBG generated by the energy gap voltage generator 21 through the comparator CMP1 to complete the detection of the supply voltage. The method of the supply voltage detection circuit 2 can obtain a higher accuracy start-up voltage, but this method sacrifices the power consumption.

[0006] Please refer to Figure 3A , Figure 3AThis is a circuit diagram of another conventional supply voltage detection circuit. The supply voltage detection circuit 3 includes multiple BJT transistors Q1 and Q2, resistors R1-R4, comparator CMP1, PMOS transistor MP1, AND logic gate AND1, and inverter module 301 (composed of multiple inverters connected in series). BJT transistor Q2 and resistor R4 form a circuit similar to a bandgap voltage generator. PMOS transistor MP1 is controlled by the enable signal EN output from AND logic gate AND1 to turn on or off, causing the bandgap voltage generator-like circuit to generate a reference voltage VBE2, and causing BJT transistor Q1 and resistors R1-R3 to generate a sense voltage VBER, where the sense voltage VBE2 is equal to the base-emitter voltage of BJT transistor Q2. Comparator CMP1 is enabled according to the enable signal EN and is used to compare the sense voltage VBER with the reference voltage VBE2 to output a low-voltage detection signal. Inverter module 301 is used to generate a reverse low-voltage detection signal BODOUT_B. The AND logic gate AND1 receives the reverse low-voltage detection signal BODOUT_B and the external signal STB, thereby resetting or starting the supply voltage detection circuit 3 through the generated enable signal EN.

[0007] Please refer to the following at the same time Figure 3A and Figure 3B , Figure 3B yes Figure 3A The waveform diagram of the supply voltage detection circuit is shown. When the supply voltage VDD rises, the sensed voltage VBER also rises. When the supply voltage VDD is greater than the set level BOD... L When the external signal STB is equal to the logic high level ("1"), the sensed voltage VBER is greater than the reference voltage VBE2, causing the reverse low-voltage detection signal BODOUT_B to be at the logic high level. The supply voltage detection circuit 3 has higher accuracy when the supply voltage VDD is a low input voltage, but the detection potential is more difficult to adjust and requires the external signal STB to start and reset. After the circuit system starts (the reverse low-voltage detection signal BODOUT_B is at the logic high level), the supply voltage detection circuit 3 will be locked and cannot continue to be used, so it must be restarted through the external signal STB. Summary of the Invention

[0008] An embodiment of the present invention provides a supply voltage detection circuit, comprising: a voltage detection circuit for receiving a supply voltage and detecting the supply voltage to generate a low-voltage detection signal; and a current clamping circuit electrically connected to the voltage detection circuit; wherein when the supply voltage is lower than a set level, the low-voltage detection signal output by the voltage detection circuit shuts off the current clamping circuit, and the transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is greater than or equal to the set level, the low-voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a fixed current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the fixed current.

[0009] In one embodiment, the voltage detection circuit includes a switching PMOS transistor, a first resistor to a third resistor, a comparator, and a first diode circuit and a second diode circuit. The source of the switching PMOS transistor receives the supplied voltage, the gate of the switching PMOS transistor is electrically connected to the output terminal of the comparator, and the drain of the switching PMOS transistor is electrically connected to the first terminals of the second and third resistors. The second terminals of the second and third resistors are respectively electrically connected to the negative and positive input terminals of the comparator. The output terminal of the comparator outputs the low-voltage detection signal and is electrically connected to the current clamping circuit to control the opening and closing of the current clamping circuit. The first diode circuit is electrically connected to the second terminal of the second resistor, the first terminal of the first resistor is electrically connected to the second terminal of the third resistor, the second terminal of the first resistor is electrically connected to the second diode circuit, and the drain of the switching PMOS transistor is also electrically connected to one end of the current clamping circuit to receive a current proportional to the fixed current when the current clamping circuit is turned on.

[0010] In one embodiment, the current clamping circuit includes a first PMOS transistor and a second PMOS transistor, a first NMOS transistor and a current source. The sources of the first PMOS transistor and the second PMOS transistor receive the supply voltage. The gate of the first PMOS transistor is electrically connected to the gate and drain of the second PMOS transistor. The drain of the first PMOS transistor is electrically connected to the voltage detection circuit to provide a current proportional to the fixed current when the current clamping circuit is turned on. The gate of the first NMOS transistor is electrically connected to the voltage detection circuit to receive the low-voltage detection signal. The drain of the first NMOS transistor is electrically connected to the drains of the first PMOS transistor and the second PMOS transistor, and the source of the first NMOS transistor is electrically connected to the current source to receive the fixed current provided by the current source.

[0011] In one embodiment, each of the first diode circuit and the second diode circuit consists of one or more BJT transistors.

[0012] In one embodiment, the voltage detection circuit further includes a fourth resistor and a trimming resistor, the first end of the trimming resistor being electrically connected to the drain of the switching PMOS transistor, the second end of the trimming resistor being electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor being electrically connected to the first ends of the second resistor and the third resistor.

[0013] In one embodiment, the fourth resistor and the trimming resistor are variable resistors, and their resistance values ​​are changed according to two control signals, respectively.

[0014] An embodiment of the present invention further provides a supply voltage detection circuit, comprising: a voltage detection circuit; and an adjustable voltage generation circuit electrically connected to the voltage detection circuit, receiving a supply voltage and generating a bias voltage for biasing the voltage detection circuit; wherein the voltage detection circuit receives the bias voltage, and when the supply voltage is lower than a set level, the low-voltage detection signal output by the voltage detection circuit is a logic low level; and when the supply voltage is greater than or equal to the set level, the low-voltage detection signal output by the voltage detection circuit is a logic high level.

[0015] In one embodiment, the voltage detection circuit includes a first resistor to a fourth resistor, a first comparator, a first diode circuit, and a second diode circuit. The first terminal of the fourth resistor is electrically connected to an adjustable voltage generating circuit to receive the bias voltage. The second terminal of the fourth resistor is electrically connected to the first terminals of the second and third resistors. The second terminals of the second and third resistors are respectively electrically connected to the negative and positive input terminals of the comparator. The output terminal of the comparator outputs the low-voltage detection signal. The first diode circuit is electrically connected to the second terminal of the second resistor. The first terminal of the first resistor is electrically connected to the second terminal of the third resistor, and the second terminal of the first resistor is electrically connected to the second diode circuit. The fourth resistor is a variable resistor and receives a first control signal to change its resistance value.

[0016] In one embodiment, the adjustable voltage generating circuit includes a trimming resistor, a fifth resistor, and a second comparator. The first end of the trimming resistor receives the supplied voltage, the second end of the trimming resistor is electrically connected to the first end of the fifth resistor and the positive input terminal of the second comparator, and the output terminal of the second comparator is electrically connected to the negative input terminal of the second comparator to output the bias voltage. The trimming resistor is a variable resistor and receives a second control signal to change its resistance value.

[0017] This invention further provides a circuit system, including: a load; and any of the aforementioned supply voltage detection circuits, which are electrically connected to the load.

[0018] In summary, compared to prior art, the embodiments of the present invention provide a supply voltage detection circuit with high accuracy, low temperature drift and low power consumption, and a circuit system using the same.

[0019] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0020] The present invention can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a circuit diagram of a traditional supply voltage detection circuit;

[0022] Figure 2 This is a circuit diagram of another traditional supply voltage detection circuit;

[0023] Figure 3A This is a circuit diagram of another traditional power supply voltage detection circuit;

[0024] Figure 3B yes Figure 3A Waveform diagram of the supply voltage detection circuit;

[0025] Figure 4 This is a block diagram of the supply voltage detection circuit according to the first embodiment of the present invention;

[0026] Figure 5A This is a circuit diagram of the supply voltage detection circuit according to the second embodiment of the present invention;

[0027] Figure 5B yes Figure 5A A graph showing the reference voltage and sensed voltage of the supply voltage detection circuit relative to the supply voltage;

[0028] Figure 5C yes Figure 5A The supply voltage detection circuit operates in the first mode and the second mode, and the transistor current is compared with the supply voltage.

[0029] Figure 6 This is a circuit diagram of the supply voltage detection circuit according to the third embodiment of the present invention;

[0030] Figure 7This is a circuit diagram of the supply voltage detection circuit according to the fourth embodiment of the present invention; and

[0031] Figure 8 This is a circuit diagram of the supply voltage detection circuit according to the fifth embodiment of the present invention.

[0032] The symbols shown in the diagram are explained as follows: 1 to 8 supply voltage detection circuit; R1 to R6, R TRIM Resistors; VDD, AVDD supply voltages; BODOUT low voltage detection signal; BODOUT_B reverse low voltage detection signal; MP1~MP3, MSW PMOS transistors; MN1 NMOS transistor; CMP1, CMP2 comparators; VBG, VBE2, VBE1 reference voltages; VSEN, VBER sensing voltages; Q1~Q3, Q 24 BJT transistor; 21 bandgap voltage generator; 301 inverter module; AND1 AND logic gate; STB external signal; BOD L Setting level; 42, 51, 61, 71, 82 voltage detection circuits; 41, 52, 62, 72 current clamping circuits; BODSEL[2:0], VBGTRIM[3:0] control signals; VBOD, VBP, VBGR, VX, VBE24, VBE voltages; VSS low voltage; CS current source; IHOLD fixed current; 511, 512, 611, 612, 711, 712 diode circuits; IBJT transistor current; mode1 first mode; mode2 second mode; 81 adjustable voltage generation circuit; and VF voltage follower. Detailed Implementation

[0033] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0034] This invention provides a high-accuracy, low-temperature-drift, and low-power supply voltage detection circuit and a circuit system using the same. It uses the base-emitter voltage difference (ΔVBE) to generate a bias voltage to detect whether the supply voltage is greater than a set level BOD. L And the supply voltage is greater than the set level BOD L At this time, the overall current of the supply voltage detection circuit is clamped, thus reducing power consumption. Furthermore, the supply voltage detection circuit can continue to be used after startup without needing to be reset or started by an external signal.

[0035] First, please refer to 4. Figure 4This is a block diagram of the supply voltage detection circuit according to an embodiment of the present invention. The supply voltage detection circuit 4 includes a current clamping circuit 41 and a voltage detection circuit 42, wherein the current clamping circuit 41 and the voltage detection circuit 42 are electrically connected to each other and receive the supply voltage VDD, and the voltage detection circuit 42 outputs a low-voltage detection signal BODOUT to the current clamping circuit 41 and the load (not shown) electrically connected to the supply voltage detection circuit 4. Figure 4 (e.g., circuits or chips with specific functions).

[0036] The voltage detection circuit 42 detects the supply voltage VDD and outputs a low-voltage detection signal BODOUT to control whether the current clamping circuit 41 operates (closes or opens). When the supply voltage VDD is lower than the set level BODOUT... L When (defined as the first mode), the low-voltage detection signal BODOUT output by the voltage detection circuit 42 causes the current clamping circuit 41 to be turned off, and multiple currents flowing through the voltage detection circuit 42 (e.g., in the following...) Figure 5A , Figure 6 , Figure 7 In this embodiment, there are two currents that increase as the supply voltage VDD increases. However, when the supply voltage VDD is greater than or equal to the set level BOD... L When (defined as the second mode), the low-voltage detection signal BODOUT output by the voltage detection circuit 42 causes the current clamping circuit 41 to be turned on, and the current clamping circuit 41 provides a fixed current (e.g., in the following...). Figure 5A , Figure 6 , Figure 7 In this embodiment, a fixed current (IHOLD) is used to maintain the continuous operation of the voltage detection circuit 42. Thus, the overall power consumption of the voltage detection circuit 4 is limited by the fixed current provided by the current clamping circuit 41. On the other hand, the voltage detection circuit 42 uses at least two BJT transistors to generate a base-emitter voltage difference (delta VBE) to generate the voltage of the bias voltage detection circuit 42 (e.g., ...). Figure 5A , Figure 6 and Figure 7 The voltage VBOD is used to detect whether the supply voltage is greater than the set level BOD. L Therefore, the voltage detection circuit 4 is less affected by temperature drift, thus achieving high accuracy in detection.

[0037] Please refer to the following: Figure 5A , Figure 5A This is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. Figure 5AIn the circuit, the current clamping circuit 52 supplying voltage detection circuit 5 consists of two PMOS transistors MP1 and MP2, an NMOS transistor MN1, and a current source CS. The voltage detection circuit 51 supplying voltage detection circuit 5 consists of a PMOS transistor MSW and multiple resistors R. TRIM R1~R4, comparator CMP1 and diode circuits 511 and 512 (each composed of two BJT transistors Q1 and Q2) 24 It consists of (implementation).

[0038] The source of the PMOS transistor MSW receives the supply voltage VDD. The gate of the PMOS transistor MSW is electrically connected to the output of comparator CMP1 to receive the low-voltage detection signal BODOUT output by comparator CMP1. The drain of the PMOS transistor MSW is electrically connected to the drain of PMOS transistor MP2 in the current clamping circuit 52. In the second mode, the fixed current IHOLD provided by the current clamping circuit 52 maintains the bias level of VBOD and receives a bias current corresponding to the fixed current IHOLD (proportional to the fixed current IHOLD, whose value is fixed). Resistor R TRIM The two ends of resistor R1 are electrically connected to the drain of PMOS transistor MSW and one end of resistor R4, respectively. The other end of resistor R4 is electrically connected to one end of resistor R2 and one end of resistor R3. The other end of resistor R2 is electrically connected to the emitter of BJT transistor Q1 and the negative input of comparator CMP1, and the other end of resistor R3 is electrically connected to one end of resistor R1 and the positive input of comparator CMP1. The other end of resistor R1 is electrically connected to BJT transistor Q1. 24 The emitter of the BJT transistor Q1, Q2. 24 The base and collector are electrically connected to a low voltage VSS, such as ground. Note here that the resistor R... TRIM R4 is a non-essential component and can be removed in other implementations.

[0039] The sources of PMOS transistors MP1 and MP2 receive the supply voltage VDD. The gates of PMOS transistors MP1 and MP2 are electrically connected to each other, and the gate of PMOS transistor MP2 is electrically connected to its drain. The drain of NMOS transistor N1 is electrically connected to the drain of PMOS transistor MP2. The gate of NMOS transistor N1 is electrically connected to the output of comparator CMP1 to receive the low-voltage detection signal BODOUT output by comparator CMP1. The source of NMOS transistor N1 is connected to one end of current source CS. The other end of current source CS is electrically connected to a low voltage VSS.

[0040] When the supply voltage detection circuit 5 is connected to the supply voltage VDD, one current flows through resistor R2 and transistor Q1 (connected in a manner that allows it to function as a diode), thereby generating a reference voltage VBE1. VBE1 is the base-emitter voltage of transistor Q1, and it is received by the negative input of comparator CMP1. The other current flows through resistors R1 and R3 and transistor Q... 24 This generates a sensing voltage VBER and supplies it to the positive input of comparator CMP1, where the sensing voltage VBER is the voltage of transistor Q. 24 The base-emitter voltage VBE24 is applied across resistor R1. Resistor R... TRIM Resistor R4 can be a variable resistor, and it receives control signals BODSEL[2:0] and VBGTRIM[3:0] respectively to adjust its resistance value, thereby adjusting the level of voltage VBGR. Thus, resistor R... TRIM The resistor R4 makes circuit layout easier to match and reduces manufacturing process variations, but as mentioned earlier, resistor R... TRIM R4 is a non-essential component and can be removed, or replaced by a low-dropout regulator (LDO) buffer (i.e., resistor R4 can be replaced by a low-dropout regulator (LDO) buffer). TRIM R4 is removed, and a low-voltage linear regulator buffer is used to provide the voltage VBGR.

[0041] When the supply voltage VDD is lower than the set level BOD L When operating in the first mode, because the BJT transistor Q1 is designed to be small, it has a large internal resistance, making the reference voltage VBE1 higher than the sensing voltage VBER. The low-voltage detection signal BODOUT output by comparator CMP1 is at a logic low level ("0"), so the PMOS transistor MSW is turned on (conducted), making the voltage VBOD at the drain of the PMOS transistor MSW substantially equal to the supply voltage, thus reducing detection error. At this time, the two PMOS transistors MP1 and MP2 and the NMOS transistor MN1 in the current clamping circuit 52 are turned off, and the voltage VBP at the drain of PMOS transistors MP1 and MP2 is high, so the current consumed by the current clamping circuit 52 is substantially 0 (the current of PMOS transistors MP1 and MP2 is 0), and no power is consumed. In addition, the current flowing through BJT transistors Q1 and Q2 is reduced. 24 The two currents I_Q1 and I_Q24 are proportional to the magnitude of the supply voltage VDD.

[0042] When the supply voltage VDD gradually rises and becomes greater than or equal to the set level BOD LWhen operating in the second mode, the voltage VX across one end of resistors R2 and R3 gradually increases, causing the sensed voltage VBER to be greater than or equal to the reference voltage VBE1. Therefore, the low-voltage detection signal BODOUT output by comparator CMP1 is at a logic high level ("1"). At this time, PMOS transistor MSW is turned off (not conducting), NMOS transistor MN1 is turned on (conducting), and PMOS transistors MP1 and MP2 are turned on (conducting), providing a fixed current IHOLD to the drain of PMOS transistor MP2 to generate voltage VBOD to provide bias and maintain the operation of voltage detection circuit 51. At this time, even if the supply voltage VDD continues to rise, voltage detection circuit 51 is clamped by current clamping circuit 52 and maintains the same operating current, thus reducing power consumption. At this time, the current I_MP2 of PMOS transistor MP2 is set to be greater than the current flowing through BJT transistors Q1 and Q2. 24 The sum of the two currents plus 50 nanoamps. As mentioned earlier, the current flowing through BJT transistors Q1 and Q2 is... 24 The two currents are essentially proportional to the magnitude of the fixed current IHOLD.

[0043] In this embodiment, the convergence point is set when current IQ1 equals current IQ24, and the voltage level BOD is set. L It can be calculated from the currents IQ1 and IQ24 at the convergence point. At this point, IQ1 = ΔVBE / R1 = VTln(n) / R1, and the voltage VBOD = 2*IQ1*[(R2 / / R3)+R4+R... TRIM ]+VBE1, where ΔVBE is the base-emitter voltage difference (ΔVBE). Since the current IQ1 has a temperature coefficient proportional to its absolute temperature, it will affect the voltage VBOD. Therefore, resistors R2, R3, R4, and R... can be selected with negative temperature coefficients. TRIM This makes the supply voltage detection circuit 5 less susceptible to temperature drift. In one embodiment, the reference voltage VBE1 can be set to 1.25, 2.5, or 3.75 volts.

[0044] Figure 5B yes Figure 5A The graph shows the reference voltage and sensed voltage of the supply voltage detection circuit relative to the supply voltage. As mentioned earlier, the relationship between the reference voltage VBE1 and the sensed voltage VBER of the two input voltages (called voltage VBE) of comparator CMP1 relative to the supply voltage VDD is as follows. Figure 5B As shown. When the supply voltage VDD is greater than or equal to the set level BOD. L The sensed voltage VBER is greater than or equal to the reference voltage VBE1, and maintains a fixed voltage value at the reference voltage VBE1 (due to clamping by the current clamping circuit 52); when the supply voltage VDD is less than the set level BOD...L The sensed voltage VBER is less than the reference voltage VBE1.

[0045] Figure 5C yes Figure 5A The supply voltage detection circuit operates in the first and second modes, and the transistor current versus supply voltage curves are shown. As mentioned earlier, current flows through BJT transistors Q1 and Q2. 24 The sum of the two currents is represented by the transistor current IBJT, which is in the first mode (mode 1) when the supply voltage VDD is less than the set level BOD. L The current is proportional to the magnitude of the supply voltage VDD; and the transistor current IBJT in the second mode (mode 2) when the supply voltage VDD is greater than or equal to the set level BOD. L ), which is a fixed current proportional to the fixed current IHOLD.

[0046] Next, please refer to Figure 6 , Figure 6 This is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. The supply voltage detection circuit 6 includes a current clamping circuit 62 and a voltage detection circuit 61. The current clamping circuit 62 and... Figure 5A The current clamping circuit 52 is the same as that of the voltage detection circuit 61, and the diode circuits 611 and 612 are the same as those of the voltage detection circuit 61. Figure 5A The diode circuits 511 and 512 of the voltage detection circuit 51 are slightly different. Each of the diode circuits 511 and 612 is implemented by two BJT transistors (in a diode connection manner) to provide twice the bias voltage of the diode circuits 511 and 512. For example, Figure 5A The voltages VBE1 and VBE24 are 1.25 volts, while Figure 6 The voltages VBE1 and VBE24 are 2.5 volts.

[0047] Next, please refer to Figure 7 , Figure 7 This is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. The supply voltage detection circuit 7 includes a current clamping circuit 72 and a voltage detection circuit 71. The current clamping circuit 72 and... Figure 5A The current clamping circuit 52 is the same as that of the voltage detection circuit 71, and the diode circuits 711 and 712 are the same as those of the voltage detection circuit 71. Figure 5A The diode circuits 511 and 512 of the voltage detection circuit 51 are slightly different. Each of the diode circuits 511 and 712 is implemented by three BJT transistors (in a diode connection manner) to provide three times the bias voltage of the diode circuits 511 and 512. For example, Figure 5A The voltages VBE1 and VBE24 are 1.25 volts, while Figure 7 The voltages VBE1 and VBE24 are 3.75 volts.

[0048] Next, please refer to Figure 8 , Figure 8 This is a circuit diagram of a supply voltage detection circuit according to another embodiment of the present invention. The supply voltage detection circuit 8 does not have a current clamping circuit, but includes an adjustable voltage generation circuit 81 and a voltage detection circuit 82, wherein the voltage detection circuit 82 is substantially the same as... Figure 5A The voltage detection circuit 51 is approximated, where Figure 5A The resistor R in the voltage detection circuit 51 TRIM The PMOS transistor MSW is replaced by an adjustable voltage generation circuit 81 to form a supply voltage detection circuit 8.

[0049] The adjustable voltage generating circuit 81 includes a resistor R TRIM R5 and voltage follower VF. Resistor R TRIM The two ends of the resistor R5 are electrically connected to the supply voltage AVDD and one end of the resistor R5, respectively. The other end of the resistor R5 is electrically connected to the low voltage VSS. The voltage follower VF is implemented, for example, by a comparator, but this invention is not limited thereto. The output terminal of the voltage follower VF is electrically connected to the negative input terminal of the voltage follower VF, and the positive input terminal of the voltage follower VF is electrically connected to one end of the resistor R5 and the resistor R6. TRIM The other end (resistors R5 and R) TRIM The connection point is used to receive the voltage VBOD used to bias the voltage detection circuit 82. The voltage follower VF is connected in a way that allows it to function as a buffer; therefore, the voltage VBGR is essentially equal to the voltage VBOD, where the level of the voltage VBOD can be adjusted by the control signal BODSEL[2:0] to adjust the resistor R. TRIM The resistance value is used to achieve this. The operating principle of the supply voltage detection circuit 8 is similar to that of the supply voltage detection circuits 4-7. When the supply voltage AVDD is lower than the set level BOD, the supply voltage is detected. L When operating in the first mode, the low-voltage detection signal BODOUT output by the supply voltage detection circuit 8 is at a logic low level ("0"); and when the supply voltage AVDD is greater than or equal to the set level BOD... L When operating in the second mode, the low-voltage detection signal BODOUT output by the supply voltage detection circuit 8 is at a logic high level ("1"). In this embodiment, regardless of whether operating in the first or second mode, the current flowing through BJT transistors Q1 and Q2... 24 The two currents I_Q1 and I_Q24 are both proportional to the magnitude of the supply voltage AVDD.

[0050] In addition, embodiments of the present invention also provide a circuit system, which includes a load and any of the above-mentioned supply voltage detection circuits 4 to 8, wherein the load can be electrically connected to the supply voltage detection circuit, and the load can be any functional chip or functional circuit that needs to use the supply voltage detection result.

[0051] In summary, compared to prior art, this invention provides a supply voltage detection circuit and a circuit system using the same, characterized by high accuracy, low temperature drift, and low power consumption. Furthermore, when the supply voltage exceeds a set level, the voltage detection circuit in the supply voltage detection circuit is clamped to a fixed current, thus effectively reducing power consumption; and because a bias voltage is generated using the base-emitter voltage difference (ΔVBE) to detect whether the supply voltage exceeds the set level BOD... L Therefore, the impact of temperature drift is relatively small, and the accuracy can be improved. Furthermore, the supply voltage detection circuit can continue to be used after startup without requiring an external signal to reset or start.

[0052] It will be understood that the above embodiments are cited by way of example only, and the invention is not limited to what has been specifically shown and described above. Instead, the scope of the invention includes combinations and sub-combinations of the various features described above, variations and modifications that would occur to those skilled in the art upon reading the foregoing description, and anything not disclosed in the prior art. Documents incorporated herein by reference should be considered part of this application, and the definitions in this specification should be considered, except that the scope of any terms is defined in these incorporated documents in a manner that conflicts with the express or implied definitions in this specification.

Claims

1. A voltage detection circuit, characterized in that, The supply voltage detection circuit includes: A voltage detection circuit receives a supply voltage and detects the supply voltage to generate a low-voltage detection signal; and The current clamping circuit is electrically connected to the voltage detection circuit; When the supply voltage is lower than a set level, the low-voltage detection signal output by the voltage detection circuit shuts down the current clamping circuit, and the transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is greater than or equal to the set level, the low-voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a fixed current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the fixed current.

2. The supply voltage detection circuit as described in claim 1, characterized in that, The voltage detection circuit includes a switching PMOS transistor, a first resistor to a third resistor, a comparator, and a first diode circuit and a second diode circuit. The source of the switching PMOS transistor receives the supplied voltage, the gate of the switching PMOS transistor is electrically connected to the output terminal of the comparator, and the drain of the switching PMOS transistor is electrically connected to the first terminals of the second and third resistors. The second terminals of the second and third resistors are respectively electrically connected to the negative input terminal and the positive input terminal of the comparator. The output terminal of the comparator outputs the low-voltage detection signal and is electrically connected to the current clamping circuit to control the opening and closing of the current clamping circuit. The first diode circuit is electrically connected to the second terminal of the second resistor, the first terminal of the first resistor is electrically connected to the second terminal of the third resistor, the second terminal of the first resistor is electrically connected to the second diode circuit, and the drain of the switching PMOS transistor is also electrically connected to one end of the current clamping circuit so that when the current clamping circuit is turned on, it receives a current proportional to the fixed current.

3. The supply voltage detection circuit as described in claim 1, characterized in that, The current clamping circuit includes a first PMOS transistor and a second PMOS transistor, a first NMOS transistor and a current source. The sources of the first PMOS transistor and the second PMOS transistor receive the supplied voltage. The gate of the first PMOS transistor is electrically connected to the gate and drain of the second PMOS transistor. The drain of the first PMOS transistor is electrically connected to the voltage detection circuit to provide a current proportional to the fixed current when the current clamping circuit is turned on. The gate of the first NMOS transistor is electrically connected to the voltage detection circuit to receive the low-voltage detection signal. The drain of the first NMOS transistor is electrically connected to the drains of the first PMOS transistor and the second PMOS transistor. The source of the first NMOS transistor is electrically connected to the current source to receive the fixed current provided by the current source.

4. The supply voltage detection circuit as described in claim 2, characterized in that, Each of the first diode circuit and the second diode circuit consists of one or more BJT transistors.

5. The supply voltage detection circuit as described in claim 2, characterized in that, The voltage detection circuit further includes a fourth resistor and a trimming resistor. The first end of the trimming resistor is electrically connected to the drain of the switching PMOS transistor, the second end of the trimming resistor is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the first ends of the second resistor and the third resistor.

6. The supply voltage detection circuit as described in claim 5, characterized in that, The fourth resistor and the trimming resistor are variable resistors, and their resistance values ​​are changed according to two control signals.

7. A circuit system, characterized in that, include: load; And the supply voltage detection circuit according to any one of claims 1 to 6, wherein the supply voltage detection circuit is electrically connected to the load.

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