Segmented temperature compensation band-gap reference circuit capable of trimming low temperature drift

Abstract

The invention relates to the technical field of analog integrated circuit design, and particularly discloses a segmented temperature compensation band-gap reference circuit capable of trimming low temperature drift, which comprises a starting circuit, a first-order temperature compensation voltage circuit, a first-order temperature compensation current circuit and a segmented temperature compensation voltage circuit, the starting circuit is used for filling a target current into the first-order temperature compensation voltage circuit during power-on, so that the first-order temperature compensation voltage circuit is separated from a degeneracy point; the first-order temperature compensation voltage circuit is used for providing band-gap reference voltage and providing bias current for the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit. The first-order temperature compensation current circuit is used for providing reference current and providing bias current for the segmented temperature compensation voltage circuit; and the segmented temperature compensation voltage circuit is used for superposing the generated compensation voltage onto the band-gap reference voltage so as to further reduce the temperature coefficient of the band-gap reference voltage. The temperature drift of the band-gap reference voltage can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog integrated circuit design, and more particularly, to a segmented temperature compensation bandgap reference circuit with adjustable low temperature drift. BACKGROUND

[0002] As an important part of analog integrated circuit system, the bandgap reference circuit is widely used in various high-precision chips, such as power management chips, high-precision sensor chips, high-precision ADCs, etc., because it can provide a bandgap reference voltage independent of power supply voltage and temperature. The bandgap reference circuit usually provides a high-precision reference voltage for other modules, so the precision of the bandgap reference voltage affects the precision of other modules. The traditional bandgap reference usually adopts a first-order temperature compensation method, the basic principle of which is to eliminate the first-order temperature term by adding a negative temperature coefficient voltage and a positive temperature coefficient voltage with adjustable weight, thereby obtaining a bandgap reference voltage approximately independent of temperature.

[0003] In actual situations, the negative temperature coefficient voltage of the device is not an ideal first-order negative temperature coefficient voltage, and it has a high-order curvature, so the obtained bandgap reference voltage has a high-order temperature coefficient, which affects the precision of the bandgap reference. In order to improve the precision of the bandgap reference, high-order compensation is needed to design the circuit. SUMMARY

[0004] In order to solve the problems in the prior art, the present application provides a segmented temperature compensation bandgap reference circuit with adjustable low temperature drift, which performs segmented compensation on the bandgap reference voltage at high and low temperatures on the basis of first-order temperature compensation, thereby improving the precision of the bandgap reference voltage through temperature correction and realizing lower temperature drift.

[0005] As a first aspect of the present application, a segmented temperature compensation bandgap reference circuit with adjustable low temperature drift is provided, which comprises a start-up circuit, a first-order temperature compensation voltage circuit, a first-order temperature compensation current circuit and a segmented temperature compensation voltage circuit, the start-up circuit is connected with the first-order temperature compensation voltage circuit, the first-order temperature compensation voltage circuit is connected with the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit respectively, and the first-order temperature compensation current circuit is connected with the segmented temperature compensation voltage circuit. The start-up circuit is used for pouring a target current into the first-order temperature compensation voltage circuit when power is turned on, so that the first-order temperature compensation voltage circuit is away from the degenerate point. The first-order temperature compensation voltage circuit is used for providing a bandgap reference voltage with the first-order temperature coefficient eliminated, and providing PTAT bias currents for the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit respectively. The first-order temperature compensation current circuit is configured to provide a reference current with a first-order temperature coefficient cancelled and to provide a low temperature drift bias current for the segmented temperature compensation voltage circuit. The segmented temperature compensation voltage circuit is configured to generate a compensation voltage and to superimpose the compensation voltage on the bandgap reference voltage to further reduce the temperature coefficient of the bandgap reference voltage.

[0006] Further, the starting circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1 and a second resistor R2, the sources of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected to a power supply voltage VREF, the gate of the first PMOS transistor MP1 is connected to a power ground GND, the drain of the first PMOS transistor MP1 is connected to a first end of the first resistor R1, a second end of the first resistor R1 is connected to the drain of the first NMOS transistor MN1, the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are connected and connected to the drain of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is connected to the power ground GND, the source of the second NMOS transistor MN2 is connected to the first-order temperature compensation voltage circuit, the second PMOS transistor MP2 and the third PMOS transistor MP3 constitute a current mirror, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are connected and connected to the drain of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3 is connected to the first-order temperature compensation voltage circuit.

[0007] Further, the first-order temperature compensation voltage circuit comprises a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first triode QN1, a second triode QN2, a third triode QN3, a third resistor R3, a trimming resistor Rtrim, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 constitute a current mirror, the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5 and the drain of the fifth NMOS transistor MN5 are connected with a power supply voltage VREF, the drain of the fourth PMOS transistor MP4 is connected with the source of the sixth PMOS transistor MP6, the drain of the fifth PMOS transistor MP5 is connected with the source of the seventh PMOS transistor MP7, the gate of the fourth PMOS transistor MP4, the gate of the fifth PMOS transistor MP5, the gate of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7 are connected together and connected with the drain of the seventh PMOS transistor MP7, the drain of the sixth PMOS transistor MP6 is connected with the drain of the third NMOS transistor MN3 and connected with the drain of the third PMOS transistor MP3, the drain of the seventh PMOS transistor MP7 is connected with the drain of the fourth NMOS transistor MN4 and connected with the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit respectively, the gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the drain of the third NMOS transistor MN3 are connected together, the source of the third NMOS transistor MN3 is connected with the collector of the first triode QN1, the emitter, the base and the collector of the third triode QN3 are connected together and connected with the collector of the first triode QN1, the source of the fourth NMOS transistor MN4 is connected with the collector of the second triode QN2, the base of the first triode QN1 is connected with the base of the second triode QN2 and connected with the source of the fifth NMOS transistor MN5, the emitter of the first triode QN1 is connected with the second end of the third resistor R3, the emitter of the second triode QN2 is connected with the first end of the third resistor R3 and connected with the source of the second NMOS transistor MN2, the second end of the third resistor R3 is connected with the first end of the trimming resistor Rtrim, the second end of the trimming resistor Rtrim is connected with the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected with a power supply ground GND, the source of the fifth NMOS transistor MN5 is connected with the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected with the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected with the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected with the power supply ground GND.

[0008] Further, the ratio of the area of the emitter of the first transistor QN1 to the emitter of the second transistor QN2 is 1:8, and the first transistor QN1 is connected to the third transistor QN3 at the collector of the first transistor QN1, and the ratio of the area of the emitter of the first transistor QN1 to the emitter of the third transistor QN3 is 1:7.

[0009] Further, the bandgap reference voltage provided by the first-order temperature compensation voltage circuit is : ; wherein is the difference between the base-emitter voltage of the first transistor QN1 and the base-emitter voltage of the second transistor QN2, is the base-emitter voltage of the first transistor QN1, is the resistance of the trimming resistor Rtrim, is the resistance of the fourth resistor R4, is the resistance of the third resistor R3.

[0010] Further, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 constitute a voltage dividing resistor, which is used to divide the bandgap reference voltage , and output the divided voltage and the voltage to the segmented temperature compensation voltage circuit; the current mirror composed of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 is used to provide a bias voltage , and the gate of the bias voltage is connected to several groups of current mirrors to generate the PTAT bias current.

[0011] Further, the first-order temperature compensation current circuit comprises an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, and an eighth resistor R8, the source of the eighth PMOS transistor MP8 and the source of the ninth PMOS transistor MP9 are connected to a power supply voltage VREF, the drain of the eighth PMOS transistor MP8 is connected to the source of the tenth PMOS transistor MP10, the gate of the eighth PMOS transistor MP8 is connected to the gate of the tenth PMOS transistor MP10 and the drain of the seventh PMOS transistor MP7, the collector of the fourth transistor QN4, the base of the sixth transistor QN6, the base of the seventh transistor QN7, and the drain of the tenth PMOS transistor MP10 are connected together, the emitter of the fourth transistor QN4, the emitter of the fifth transistor QN5, and the second end of the eighth resistor R8 are connected to a power supply ground GND, the base of the fourth transistor QN4, the base of the fifth transistor QN5, the first end of the eighth resistor R8, and the emitter of the sixth transistor QN6 are connected together, the collector of the fifth transistor QN5 is connected to the emitter of the seventh transistor QN7, the collector of the sixth transistor QN6, the collector of the seventh transistor QN7, and the drain of the eleventh PMOS transistor MP11 are connected together, the drain of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11, the gate of the ninth PMOS transistor MP9, the gate of the eleventh PMOS transistor MP11, and the drain of the eleventh PMOS transistor MP11 are connected together and connected to the segmented temperature compensation voltage circuit.

[0012] Further, the first-order temperature compensation current circuit provides a reference current as follows: ; wherein, is a PTAT bias current, is the voltage between the base and the emitter of the fourth transistor QN4, is the resistance of the eighth resistor R8; wherein, the current mirror composed of the ninth PMOS transistor MP9 and the eleventh PMOS transistor MP11 is used to provide a bias voltage whose gate is connected to several groups of current mirrors for generating the reference current .

[0013] Further, the segmented temperature compensation voltage circuit comprises a twelfth PMOS MP12, a thirteenth PMOS MP13, a fourteenth PMOS MP14, a fifteenth PMOS MP15, a sixteenth PMOS MP16, a seventeenth PMOS MP17, an eighteenth PMOS MP18, a nineteenth PMOS MP19, a twentieth PMOS MP20, a twenty-first PMOS MP21 and a ninth resistor R9, the source of the twelfth PMOS MP12, the source of the thirteenth PMOS MP13 and the source of the sixteenth PMOS MP16 are connected with a power supply voltage VREF, the drain of the twelfth PMOS MP12 is connected with the source of the fourteenth PMOS MP14, the drain of the thirteenth PMOS MP13 is connected with the source of the fifteenth PMOS MP15, the drain of the sixteenth PMOS MP16 is connected with the source of the seventeenth PMOS MP17, the gate of the twelfth PMOS MP12, the gate of the fourteenth PMOS MP14, the gate of the thirteenth PMOS MP13 and the gate of the fifteenth PMOS MP15 are connected with the gate of the seventh PMOS MP7, the gate of the sixteenth PMOS MP16 and the gate of the seventeenth PMOS MP17 are connected with the gate of the eleventh PMOS MP11, the drain of the fourteenth PMOS MP14 is connected with the source of the eighteenth PMOS MP18, the drain of the fifteenth PMOS MP15 is connected with the first end of the ninth resistor R9, the drain of the seventeenth PMOS MP17 is connected with the source of the twentieth PMOS MP20, the source of the eighteenth PMOS MP18 is connected with the source of the nineteenth PMOS MP19, the source of the twentieth PMOS MP20 is connected with the source of the twenty-first PMOS MP21, the gate of the eighteenth PMOS MP18 is connected with the first end of the sixth resistor R6, the gate of the nineteenth PMOS MP19 and the gate of the twentieth PMOS MP20 are connected with the first end of the ninth resistor R9, the drain of the eighteenth PMOS MP18 and the drain of the twentieth PMOS MP20 are connected with the first end of the fourth resistor R4, the drain of the nineteenth PMOS MP19, the drain of the twenty-first PMOS MP21 and the second end of the ninth resistor R9 are connected with a power ground GND.

[0014] Further, the segmented temperature compensation voltage circuit generates a compensation voltage is: ; wherein, is a compensation current, is the resistance value of the fourth resistor R4; the compensation voltage superimposed to the bandgap reference voltage , to obtain the modified bandgap reference voltage is: .

[0015] The application provides a segmented temperature compensation bandgap reference circuit with adjustable low temperature drift, which has the following advantages: through the segmented temperature compensation voltage circuit, a parabolic temperature characteristic voltage opening upward is superimposed on the basis of a parabolic temperature characteristic voltage opening downward, so as to further reduce the temperature coefficient of the bandgap reference voltage, thereby reducing the temperature drift of the bandgap reference voltage. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, and are used together with the following detailed description to explain the application, but do not constitute a limitation on the application.

[0017] Figure 1 is a structural schematic diagram of the application.

[0018] Figure 2 is a voltage characteristic schematic diagram of the application.

[0019] Figure 3 is an output schematic diagram of the bandgap reference voltage of the application under the TT process angle.

[0020] Figure 4 is an output schematic diagram of the bandgap reference voltage of the application under the FF process angle after adjustment.

[0021] Figure 5 is an output schematic diagram of the bandgap reference voltage of the application under the SS process angle after adjustment. DETAILED DESCRIPTION

[0022] In order to further clarify the technical means and effects of the application adopted to achieve the predetermined application purpose, the following will combine the drawings and the preferred embodiments to specifically explain the specific embodiments, structure, characteristics and effects of the segmented temperature compensation bandgap reference circuit with adjustable low temperature drift according to the application. Obviously, the described embodiments are part of the embodiments of the application, not all the embodiments. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0023] It is to be noted that the terms "first", "second", and the like in the description and in the claims of the present application and in the above-described drawings are intended to distinguish similar objects and not necessarily to describe a particular sequential or chronological order. It is to be understood that the use of such terms in the description is solely intended to distinguish the corresponding parts of the embodiments of the application described here from other parts of the same, where the context allows. Moreover, the terms "comprising", "having", "including", and "containing" and any variations thereof used herein are intended to cover a non-exclusive inclusion, such that a process, method, system, product, or apparatus that comprises, has, includes or contains a list of steps or elements, but does not necessarily comprise, have, include, or contain only those steps or elements, but can include additional steps or elements not expressly listed or inherent to such process, method, product, or apparatus.

[0024] In the explanation of the present application, it is to be noted that the terms "mounting", "connecting", "connection" should be interpreted broadly, unless otherwise specified. For example, the connection can be a fixed connection, or a connection through a special interface, or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] In the present embodiment, a segmented temperature compensation bandgap reference circuit with adjustable low temperature drift is provided, as shown in the figure Figure 1 The segmented temperature compensation bandgap reference circuit with adjustable low temperature drift comprises a start-up circuit 1, a first-order temperature compensation voltage circuit 2, a first-order temperature compensation current circuit 3 and a segmented temperature compensation voltage circuit 4, the start-up circuit 1 is connected with the first-order temperature compensation voltage circuit 2, the first-order temperature compensation voltage circuit 2 is connected with the first-order temperature compensation current circuit 3 and the segmented temperature compensation voltage circuit 4 respectively, and the first-order temperature compensation current circuit 3 is connected with the segmented temperature compensation voltage circuit 4; wherein the output end of the segmented temperature compensation voltage circuit 4 is connected with the first-order temperature compensation voltage circuit 2. The start-up circuit 1 is used for pouring a target current into the first-order temperature compensation voltage circuit 2 at power-on to make the first-order temperature compensation voltage circuit 2 deviate from the degenerate point. The first-order temperature compensation voltage circuit 2 is used for providing a bandgap reference voltage with a first-order temperature coefficient cancelled out and providing a PTAT bias current for the first-order temperature compensation current circuit 3 and the segmented temperature compensation voltage circuit 4 respectively; wherein the first-order temperature compensation voltage circuit 2 provides a PTAT bias current for the first-order temperature compensation current circuit 3 , and the first-order temperature compensation voltage circuit 2 provides a PTAT bias current for the segmented temperature compensation voltage circuit 4 and a PTAT bias current . The first-order temperature compensation current circuit 3 is used to provide a reference current that has compensated for the first-order temperature coefficient. And provide a low-temperature drift bias current for the segmented temperature compensation voltage circuit 4. ; The segmented temperature compensation voltage circuit 4 is used to generate a compensation voltage and superimpose the compensation voltage onto the bandgap reference voltage to further reduce the bandgap reference voltage. Temperature coefficient.

[0026] Preferably, the startup circuit 1 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the power supply voltage VREF. The gate of the first PMOS transistor MP1 is connected to the power supply ground GND. The drain of the first PMOS transistor MP1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the drain of the first NMOS transistor MN1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected... The first NMOS transistor MN1 is connected to its drain. The source of the first NMOS transistor MN1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the power ground GND. The source of the second NMOS transistor MN2 is connected to the first-order temperature compensation voltage circuit 2. The second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2. The gate of the second PMOS transistor MP2 is connected to the gate of the third PMOS transistor MP3 and is also connected to the drain of the second PMOS transistor MP2. The drain of the third PMOS transistor MP3 is connected to the first-order temperature compensation voltage circuit 2.

[0027] It should be noted that in startup circuit 1, if the first-order temperature compensation voltage circuit 2 is at its degeneracy point when the power supply voltage VREF is applied, then as follows: Figure 1 shown As the power supply ground, when the power supply voltage VREF > VTHN1, since the second resistor R2 is very small, the current flowing through the first resistor R1 is... for: ; Wherein, VTHN1 is the threshold voltage of the first NMOS transistor MN1; It is the gate-source voltage of the first NMOS transistor MN1; because For the power ground, the second resistor R2 is small, the first NMOS MN1 and the second NMOS MN2 are approximately equivalent to a current mirror, and the width-length ratios of the first NMOS MN1 and the second NMOS MN2 are the same, and because the second PMOS MP2 and the third PMOS MP3 constitute a current mirror, then: ; The target current of the first-order temperature compensation voltage circuit 2 is When the target current of the first-order temperature compensation voltage circuit 2 is reached, the first-order temperature compensation voltage circuit 2 is removed from the degenerate point, and then rises to make the second NMOS MN2 close, so that the target current is zero, and no additional effect is generated on the first-order temperature compensation voltage circuit 2.

[0028] Preferably, the first-order temperature compensation voltage circuit 2 comprises a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first triode QN1, a second triode QN2, a third triode QN3, a third resistor R3, a trimming resistor Rtrim, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 form a current mirror, the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5 and the drain of the fifth NMOS transistor MN5 are connected with a power supply voltage VREF, the drain of the fourth PMOS transistor MP4 is connected with the source of the sixth PMOS transistor MP6, the drain of the fifth PMOS transistor MP5 is connected with the source of the seventh PMOS transistor MP7, the gate of the fourth PMOS transistor MP4, the gate of the fifth PMOS transistor MP5, the gate of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7 are connected together and connected with the drain of the seventh PMOS transistor MP7, the drain of the sixth PMOS transistor MP6 is connected with the drain of the third NMOS transistor MN3 and connected with the drain of the third PMOS transistor MP3, the drain of the seventh PMOS transistor MP7 is connected with the drain of the fourth NMOS transistor MN4 and connected with the first-order temperature compensation current circuit 3 and the segmented temperature compensation voltage circuit 4 respectively, the gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the drain of the third NMOS transistor MN3 are connected together, the source of the third NMOS transistor MN3 is connected with the collector of the first triode QN1, the emitter, the base and the collector of the third triode QN3 are connected together and connected with the collector of the first triode QN1, the source of the fourth NMOS transistor MN4 is connected with the collector of the second triode QN2, the base of the first triode QN1 is connected with the base of the second triode QN2 and connected with the source of the fifth NMOS transistor MN5, the emitter of the first triode QN1 is connected with the second end of the third resistor R3, the emitter of the second triode QN2 is connected with the first end of the third resistor R3 and connected with the source of the second NMOS transistor MN2, the second end of the third resistor R3 is connected with the first end of the trimming resistor Rtrim, the second end of the trimming resistor Rtrim is connected with the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected with a power supply ground GND, the source of the fifth NMOS transistor MN5 is connected with the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected with the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected with the first end of the seventh resistor R7.The second end of the seventh resistor R7 is connected with the power supply ground GND.

[0029] Specifically, in the first-order temperature compensation voltage circuit 2, QN1, QN2, R3, Rtrim, R4 constitute a traditional Brokaw reference structure. MP4, MP5, MP6, MP7 constitute a current mirror to ensure that the currents flowing through the transistors QN1 and QN2 are the same; the area ratio of the emitter of the first transistor QN1 to the emitter of the second transistor QN2 is 1:8, and the leakage current of the reverse diode from the collector to the substrate of both transistors QN1 and QN2 will increase with the increase of temperature. Since the area of the emitter of the first transistor QN1 is different from the area of the emitter of the second transistor QN2, the collector current lost by the two transistors QN1 and QN2 is also different. In order to match the current flowing through the emitters of the two transistors QN1 and QN2, the third transistor QN3 is introduced at the collector of the first transistor QN1, and the area ratio of the emitter of the first transistor QN1 to the emitter of the third transistor QN3 is 1:7, that is, the area ratio of the emitters of the transistors is QN1:QN2:QN3=1:8:7.

[0030] Specifically, according to the circuit analysis of Figure 1 , the bandgap reference voltage provided by the first-order temperature compensation voltage circuit 2 is : ; Since = , we have: ; In the formula, is the difference between the base-emitter voltage of the first transistor QN1 and the base-emitter voltage of the second transistor QN2, is the voltage between the base and the emitter of the first transistor QN1 (a voltage with a negative temperature coefficient), is the resistance value of the trimming resistor Rtrim, is the resistance value of the fourth resistor R4, is the resistance value of the third resistor R3; N2:N1 is the ratio of the emitter area of the transistor QN2 to the emitter area of the transistor QN1; It should be noted that for the voltage between the base and the emitter of any transistor , we have: ; In the formula, is the bandgap voltage at the reference temperature , which is about 1.2V; is the voltage at the reference temperature ​ , is the thermal voltage (constant), is a process dependent constant; m is related to the temperature coefficient of the current flowing through the transistor, m=1 when the current flowing through the transistor is PTAT current, m=-1 when the current flowing through the transistor is CTAT current, and m=0 when the current flowing through the transistor is temperature independent current.

[0031] From the above formula, the bandgap reference voltage At the reference temperature , after Taylor expansion and elimination of the first order term, it can be simplified as is a downward open parabola, therefore, only a upward open parabola type temperature-voltage curve voltage is needed, and by adding the first order bandgap reference voltage , a bandgap reference voltage with smaller temperature drift can be obtained.

[0032] Specifically, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 constitute a voltage dividing resistor, the voltage dividing resistor is used for voltage dividing the bandgap reference voltage , and outputting the voltage after voltage dividing and the voltage to the segmented temperature compensation voltage circuit 4; the current mirror composed of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 is used for providing a bias voltage , and the gate of the current mirror is connected with a plurality of groups of current mirrors, and the current mirror is used for generating the PTAT bias current.

[0033] Preferably, the first order temperature compensation current circuit 3 comprises an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7 and an eighth resistor R8, the source of the eighth PMOS transistor MP8 and the source of the ninth PMOS transistor MP9 are connected to a power supply voltage VREF, the drain of the eighth PMOS transistor MP8 is connected to the source of the tenth PMOS transistor MP10, the gate of the eighth PMOS transistor MP8 is connected to the gate of the tenth PMOS transistor MP10 and is connected to the drain of the seventh PMOS transistor MP7, the collector of the fourth transistor QN4, the base of the sixth transistor QN6, the base of the seventh transistor QN7 and the drain of the tenth PMOS transistor MP10 are connected together, the emitter of the fourth transistor QN4, the emitter of the fifth transistor QN5 and the second end of the eighth resistor R8 are connected to a power supply ground GND, the base of the fourth transistor QN4, the base of the fifth transistor QN5, the first end of the eighth resistor R8 and the emitter of the sixth transistor QN6 are connected together, the collector of the fifth transistor QN5 is connected to the emitter of the seventh transistor QN7, the collector of the sixth transistor QN6, the collector of the seventh transistor QN7 and the drain of the eleventh PMOS transistor MP11 are connected together, the drain of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11, the gate of the ninth PMOS transistor MP9, the gate of the eleventh PMOS transistor MP11 and the drain of the eleventh PMOS transistor MP11 are connected together and are connected to the segmented temperature compensation voltage circuit 4.

[0034] In particular, according to the circuit analysis of Figure 1 , in the first order temperature compensation current circuit 3, the PTAT bias current is copied by the current mirror composed of the PMOS transistors MP8 and MP9. Then the PTAT bias current is copied by the transistors QN4 and QN5. And is added to the current with negative temperature coefficient , that is, the reference current provided by the first order temperature compensation current circuit 3 is: ; In the formula, the PTAT bias current (the current with positive temperature coefficient) is copied by the current mirror composed of the PMOS transistors MP8 and MP9. The voltage between the base and the emitter of the fourth transistor QN4 (the voltage with negative temperature coefficient) is The eighth resistance R8 has a resistance value; The eighth resistance R8 has a resistance value; N2: N1 is the ratio of the emitter area of the transistor QN2 to the emitter area of the transistor QN1; the coefficient k1 is the ratio of the width-length ratio of the current mirror composed of MP8 and MP10 to the width-length ratio of the current mirror composed of MP5 and MP7; wherein the current with positive temperature coefficient plus the current with negative temperature coefficient The eighth resistance R8 has a resistance value; .

[0035] The ninth PMOS transistor MP9 and the eleventh PMOS transistor MP11 constitute a current mirror for providing a bias voltage The gate of the current mirror is connected to a plurality of groups of current mirrors for generating the reference current .

[0036] Preferably, the segmented temperature compensation voltage circuit 4 comprises a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21 and a ninth resistor R9, the source of the twelfth PMOS transistor MP12, the source of the thirteenth PMOS transistor MP13 and the source of the sixteenth PMOS transistor MP16 are connected with the power supply voltage VREF, the drain of the twelfth PMOS transistor MP12 is connected with the source of the fourteenth PMOS transistor MP14, the drain of the thirteenth PMOS transistor MP13 is connected with the source of the fifteenth PMOS transistor MP15, the drain of the sixteenth PMOS transistor MP16 is connected with the source of the seventeenth PMOS transistor MP17, the gate of the twelfth PMOS transistor MP12, the gate of the fourteenth PMOS transistor MP14, the gate of the thirteenth PMOS transistor MP13 and the gate of the fifteenth PMOS transistor MP15 are connected with the gate of the seventh PMOS transistor MP7, the gate of the sixteenth PMOS transistor MP16 and the gate of the seventeenth PMOS transistor MP17 are connected with the gate of the eleventh PMOS transistor MP11, the drain of the fourteenth PMOS transistor MP14 is connected with the source of the eighteenth PMOS transistor MP18, the drain of the fifteenth PMOS transistor MP15 is connected with the first end of the ninth resistor R9, the drain of the seventeenth PMOS transistor MP17 is connected with the source of the twentieth PMOS transistor MP20, the source of the eighteenth PMOS transistor MP18 is connected with the source of the nineteenth PMOS transistor MP19, the source of the twentieth PMOS transistor MP20 is connected with the source of the twenty-first PMOS transistor MP21, the gate of the eighteenth PMOS transistor MP18 is connected with the first end of the sixth resistor R6, the gate of the nineteenth PMOS transistor MP19 and the gate of the twentieth PMOS transistor MP20 are connected with the first end of the ninth resistor R9, the drain of the eighteenth PMOS transistor MP18 and the drain of the twentieth PMOS transistor MP20 are connected with the first end of the fourth resistor R4, the drain of the nineteenth PMOS transistor MP19, the drain of the twenty-first PMOS transistor MP21 and the second end of the ninth resistor R9 are connected with the power supply ground GND.

[0037] In particular, according to the circuit analysis of Figure 1 in the segmented temperature compensation voltage circuit 4: PTAT bias current is copied by the current mirror composed of PMOS transistors MP12 and MP14 The coefficient k2 is the ratio between the width-length ratio of the current mirror composed of MP12 and MP14 and the width-length ratio of the current mirror composed of MP5 and MP7, i.e. ; PTAT bias current The PTAT bias current I PTAT The coefficient k3 is the ratio between the width-length ratio of the current mirror composed of MP13 and MP15 and the width-length ratio of the current mirror composed of MP5 and MP7, i.e. ; Low temperature drift bias current The reference current I The coefficient k4 is the ratio between the width-length ratio of the current mirror composed of MP16 and MP17 and the width-length ratio of the current mirror composed of MP5 and MP7, i.e. ; Thus, we have ; In the above equation, and are the currents with positive temperature coefficient, is the current with low temperature coefficient, is the voltage with positive temperature coefficient, and are the voltage division of the bandgap reference voltage , and the temperature coefficient of can be approximately ignored; The PMOS transistors MP18 and MP19 work in the subthreshold region, and according to the subthreshold current expression , the expressions of the currents , are as follows: ; ; In the above equation, is the gate-source voltage; is the characteristic current under a specific process and size; is the subthreshold slope factor; From the above equation, we have , and substituting it into the equation + = , we have ; Similarly, PMOS transistors MP20 and MP21 work in sub-threshold region, and the current The expression of the current is: ; Thus, we have: ; Thus, we have: , From the above formula, with the increase of temperature, increases, - decreases, so increases with the increase of temperature, - increases, so decreases with the increase of temperature; the resistance R4 is a low temperature coefficient, so is a positive temperature coefficient voltage, is a negative temperature coefficient voltage; when T , is close to zero, and is dominant; when T , is close to zero, and is dominant; The temperature-voltage curve of Figure 2 is shown in the figure, which is approximately equivalent to an upward-opening parabola; wherein the compensation voltage generated by the segmented temperature compensation voltage circuit 4 is: ; In the formula, is the compensation current, is the resistance value of the fourth resistance R4; The compensation voltage is superimposed on the bandgap reference voltage , to obtain the modified bandgap reference voltage is: .

[0038] It should be noted that appropriate k2, k4, , and are selected to generate appropriate compensation voltage , so as to compensate the bandgap reference voltage , to obtain the modified bandgap reference voltage ; as shown in Figure 2 ​The temperature-voltage curve of the bandgap reference is approximately equivalent to a downward-opening parabola, and a voltage of an upward-opening parabola is superimposed on the temperature-voltage curve of the bandgap reference to obtain a voltage similar to a fourth-order function , so that the temperature drift of the bandgap reference voltage is reduced.

[0039] Specifically, due to non-ideal factors in the manufacturing process, the mismatch of resistors and the saturation circuit I S of the BJT, the variation of characteristics will cause errors in the output voltage of the bandgap reference circuit. In order to counteract the adverse effects of process deviation in chip production and manufacturing, a resistor trimming method is used in the present example. Figure 3 is a schematic diagram of the change of the bandgap reference voltage with temperature under ideal conditions, Figure 4 is to reduce the temperature coefficient of the bandgap reference voltage by increasing the trimming resistor at the FF process angle, Figure 5 is to reduce the temperature coefficient of the bandgap reference voltage by reducing the trimming resistor at the SS process angle, Figure 4 and Figure 5 It can be seen that the temperature coefficient of the bandgap reference voltage is good by resistor trimming.

[0040] The adjustable low-temperature-drift segmented temperature compensation bandgap reference circuit provided by the present application generates an upward-opening temperature-voltage parabola through a segmented temperature compensation voltage circuit, and superimposes the upward-opening temperature-voltage parabola generated by a first-order temperature compensation voltage circuit to further reduce the temperature coefficient of the bandgap reference voltage.

[0041] The above description is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any skilled person in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiment based on the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift, characterized in that, The adjustable low-temperature drift segmented temperature compensation bandgap reference circuit includes a startup circuit (1), a first-order temperature compensation voltage circuit (2), a first-order temperature compensation current circuit (3), and a segmented temperature compensation voltage circuit (4). The startup circuit (1) is connected to the first-order temperature compensation voltage circuit (2). The first-order temperature compensation voltage circuit (2) is connected to the first-order temperature compensation current circuit (3) and the segmented temperature compensation voltage circuit (4) respectively. The first-order temperature compensation current circuit (3) is connected to the segmented temperature compensation voltage circuit (4). The starting circuit (1) is used to inject a target current into the first-order temperature compensation voltage circuit (2) when it is powered on, so that the first-order temperature compensation voltage circuit (2) is removed from the degeneracy point; The first-order temperature compensation voltage circuit (2) is used to provide a bandgap reference voltage that has been offset by the first-order temperature coefficient, and to provide PTAT bias current for the first-order temperature compensation current circuit (3) and the segmented temperature compensation voltage circuit (4), respectively. The first-order temperature compensation current circuit (3) is used to provide a reference current that has been offset by the first-order temperature coefficient and to provide a low-temperature drift bias current for the segmented temperature compensation voltage circuit (4). The segmented temperature compensation voltage circuit (4) is used to generate a compensation voltage and superimpose the compensation voltage onto the bandgap reference voltage to further reduce the temperature coefficient of the bandgap reference voltage.

2. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 1, characterized in that, The startup circuit (1) includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2. The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to the power supply voltage VREF. The gate of the first PMOS transistor MP1 is connected to the power supply ground GND. The drain of the first PMOS transistor MP1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the drain of the first NMOS transistor MN1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected and connected to the power supply ground GND. The drain of the first NMOS transistor MN1 is connected, the source of the first NMOS transistor MN1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the power ground GND, the source of the second NMOS transistor MN2 is connected to the first-order temperature compensation voltage circuit (2), the second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are connected and connected to the drain of the second PMOS transistor MP2, and the drain of the third PMOS transistor MP3 is connected to the first-order temperature compensation voltage circuit (2).

3. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 2, characterized in that, The first-order temperature compensation voltage circuit (2) includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first transistor QN1, a second transistor QN2, a third transistor QN3, a third resistor R3, a trimming resistor Rtrim, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 form a current mirror. The source of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5 are... The drain of the fifth NMOS transistor MN5 is connected to the power supply voltage VREF. The drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6. The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7. The gates of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are connected to the gate of the seventh PMOS transistor MP7 and also to the drain of the seventh PMOS transistor MP7. The drain of the sixth PMOS transistor MP6 is connected to the drain of the third NMOS transistor MN3 and also to the drain of the third PMOS transistor MP3. The drain of the seventh PMOS transistor MP7 is connected to the drain of the fourth NMOS transistor MP6. The drain of MN4 is connected to the first-order temperature compensation current circuit (3) and the segmented temperature compensation voltage circuit (4) respectively. The gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5, and the drain of the third NMOS transistor MN3 are connected together. The source of the third NMOS transistor MN3 is connected to the collector of the first transistor QN1. The emitter, base, and collector of the third transistor QN3 are connected together and connected to the collector of the first transistor QN1. The source of the fourth NMOS transistor MN4 is connected to the collector of the second transistor QN2. The connection between the base of the first transistor QN1 and the base of the second transistor QN2 is connected to the fifth NMOS transistor MN4. The source of the first NMOS transistor MN5 is connected to the source. The emitter of the first transistor QN1 is connected to the second terminal of the third resistor R3. The emitter of the second transistor QN2 is connected to the first terminal of the third resistor R3 and also connected to the source of the second NMOS transistor MN2. The second terminal of the third resistor R3 is connected to the first terminal of the adjustment resistor Rtrim. The second terminal of the adjustment resistor Rtrim is connected to the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the power ground GND. The source of the fifth NMOS transistor MN5 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the first terminal of the seventh resistor R7.The second terminal of the seventh resistor R7 is connected to the power ground GND.

4. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 3, characterized in that, The area ratio of the emitter of the first transistor QN1 to the emitter of the second transistor QN2 is 1:

8. The third transistor QN3 is introduced into the collector of the first transistor QN1, and the area ratio of the emitter of the first transistor QN1 to the emitter of the third transistor QN3 is 1:

7.

5. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 3, characterized in that, The bandgap reference voltage provided by the first-order temperature compensation voltage circuit (2) for: ； In the formula, This is the difference between the base-emitter voltage of the first transistor QN1 and the base-emitter voltage of the second transistor QN2. This is the voltage between the base and emitter of the first transistor QN1. To adjust the resistance value of resistor Rtrim, This is the resistance value of the fourth resistor, R4. This is the resistance value of the third resistor, R3.

6. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 5, characterized in that, The fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 constitute a voltage divider resistor, which is used to divide the bandgap reference voltage. Perform voltage division and convert the divided voltage to voltage. and voltage The output is sent to the segmented temperature compensation voltage circuit (4); the current mirror composed of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the PTAT bias current.

7. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 3, characterized in that, The first-order temperature compensation current circuit (3) includes an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a fourth transistor QN4, a fifth transistor QN5, a sixth transistor QN6, a seventh transistor QN7, and an eighth resistor R8. The sources of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both connected to the power supply voltage VREF. The drain of the eighth PMOS transistor MP8 is connected to the source of the tenth PMOS transistor MP10. The gate of the eighth PMOS transistor MP8 is connected to the gate of the tenth PMOS transistor MP10 and also to the drain of the seventh PMOS transistor MP7. The collector of the fourth transistor QN4, the base of the sixth transistor QN6, the base of the seventh transistor QN7, and the drain of the tenth PMOS transistor MP10 are connected to a resistor R8. The emitter of the fourth transistor QN4, the emitter of the fifth transistor QN5, and the second end of the eighth resistor R8 are all connected to the power ground GND. The base of the fourth transistor QN4, the base of the fifth transistor QN5, the first end of the eighth resistor R8, and the emitter of the sixth transistor QN6 are connected together. The collector of the fifth transistor QN5 is connected to the emitter of the seventh transistor QN7. The collector of the sixth transistor QN6, the collector of the seventh transistor QN7, and the drain of the eleventh PMOS transistor MP11 are connected together. The drain of the ninth PMOS transistor MP9 is connected to the source of the eleventh PMOS transistor MP11. The gate of the ninth PMOS transistor MP9, the gate of the eleventh PMOS transistor MP11, and the drain of the eleventh PMOS transistor MP11 are connected together and connected to the segmented temperature compensation voltage circuit (4).

8. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 7, characterized in that, The reference current provided by the first-order temperature compensation current circuit (3) for: ； In the formula, This is the PTAT bias current. This is the voltage between the base and emitter of the fourth transistor QN4. This is the resistance value of the eighth resistor, R8; The current mirror formed by the ninth PMOS transistor MP9 and the eleventh PMOS transistor MP11 is used to provide the bias voltage. Its gate is connected to several sets of current mirrors to generate the reference current. .

9. The adjustable low-temperature drift segmented temperature-compensated bandgap reference circuit according to claim 7, characterized in that, The segmented temperature compensation voltage circuit (4) includes the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the fifteenth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the seventeenth PMOS transistor MP17, the eighteenth PMOS transistor MP18, the nineteenth PMOS transistor MP19, the twentieth PMOS transistor MP20, the twenty-first PMOS transistor MP21, and the ninth resistor R9. The sources of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, and the sixteenth PMOS transistor MP16 are all... Connected to the power supply voltage VREF, the drain of the twelfth PMOS transistor MP12 is connected to the source of the fourteenth PMOS transistor MP14, the drain of the thirteenth PMOS transistor MP13 is connected to the source of the fifteenth PMOS transistor MP15, and the drain of the sixteenth PMOS transistor MP16 is connected to the source of the seventeenth PMOS transistor MP17. The gates of the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, the thirteenth PMOS transistor MP13, and the fifteenth PMOS transistor MP15 are all connected to the gate of the seventh PMOS transistor MP7. The gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the gate of the eleventh PMOS transistor MP11. The drain of the fourteenth PMOS transistor MP14 is connected to the source of the eighteenth PMOS transistor MP18. The drain of the fifteenth PMOS transistor MP15 is connected to the first terminal of the ninth resistor R9. The drain of the seventeenth PMOS transistor MP17 is connected to the source of the twentieth PMOS transistor MP20. The source of the eighteenth PMOS transistor MP18 is connected to the source of the nineteenth PMOS transistor MP19. The twentieth PMOS transistor MP20... The source of the transistor is connected to the source of the twenty-first PMOS transistor MP21. The gate of the eighteenth PMOS transistor MP18 is connected to the first end of the sixth resistor R6. The gates of the nineteenth PMOS transistor MP19 and the twentieth PMOS transistor MP20 are both connected to the first end of the ninth resistor R9. The drains of the eighteenth PMOS transistor MP18 and the twentieth PMOS transistor MP20 are both connected to the first end of the fourth resistor R4. The drains of the nineteenth PMOS transistor MP19, the twenty-first PMOS transistor MP21, and the second end of the ninth resistor R9 are all connected to the power supply ground GND.

10. A segmented temperature-compensated bandgap reference circuit with adjustable low-temperature drift according to claim 9, characterized in that, The compensation voltage generated by the segmented temperature compensation voltage circuit (4) for: ； In the formula, To compensate for the current, Let R4 be the resistance value of the fourth resistor. The compensation voltage Superimposed on the bandgap reference voltage The corrected bandgap reference voltage is obtained from the above. for: 。

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