Low-temperature-drift CMOS band-gap reference circuit with high-order curvature compensation

Abstract

The invention provides a low-temperature-drift CMOS (complementary metal oxide semiconductor) band-gap reference circuit with high-order curvature compensation, belongs to the field of power management integrated circuits, and can supply power to low-voltage modules in LDO (low dropout regulator) and DCDC (direct current direct current) chips. The band-gap reference circuit comprises an NMOS (N-channel Metal Oxide Semiconductor) tube M7, an NMOS tube M12-M13, an NMOS tube M9 and an NMOS tube M20-M21; the circuit is characterized in that the circuit comprises PMOS (P-channel Metal Oxide Semiconductor) tubes M1-M6, M10-M11, M8, M18-M19 and M22-M25, BJT (Bipolar Junction Transistor) tubes Q1 and Q2, resistors R1-R3, a resistor RC, and operational amplifiers OP1 and OP2. CTAT current of the reference circuit is provided by base-emitter voltage of the tube Q1 and a resistor R2, and PTAT current is provided by base-emitter voltage difference of the tubes Q1 and Q2 and a resistor R1; and then the current is copied by current mirrors of M1-M5 and superposed to a branch where the resistor R3 is located to form a reference current. The current subtraction circuits (M10-M15 and M18-M23) and the current mirror circuits (M6-M9) are combined together to form a multi-segment curvature compensation circuit, low-temperature area compensation current and high-temperature area compensation current are obtained respectively, and the currents are superposed on a branch where a resistor RC is located to form high-order curvature compensation current. The band-gap reference circuit solves the problems of poor temperature drift coefficient, low output precision and the like in a traditional current mode, and meanwhile, the band-gap reference circuit is simple in design principle and low in power consumption, so that the band-gap reference circuit has very high use value and popularization value.

Description

Technical Field

[0001] This invention relates to the field of power management integrated circuits, and in particular to a low-temperature drift CMOS bandgap reference circuit with high-order curvature compensation. Background Technology

[0002] Bandgap reference circuits, as power supply units within chips, are fundamental modules in integrated circuits. An ideal bandgap reference circuit can provide a stable reference voltage unaffected by external factors such as process technology, power supply voltage, and temperature, thereby powering various circuit modules within the chip. Traditional bandgap reference circuits typically utilize the base-emitter voltage of a BJT transistor. The generated CTAT current and the base-emitter voltage difference of two BJT transistors operating at different current densities The resulting PTAT currents are superimposed and then replicated to the output path containing resistor R3, thus forming a temperature-insensitive reference voltage, such as... Figure 1 As shown. However, when we need a high-precision reference source, many factors affect the accuracy of the reference voltage, such as fluctuations in process parameters, Nonlinearity, bipolar transistor current gain variation, amplifier offset and noise, etc., among which The presence of nonlinear high-order temperature terms is the primary factor limiting the accuracy of the reference. A simple linear superposition of the PTAT and CTAT currents is insufficient to offset these terms. The nonlinear high-order temperature term leads to a large systematic output deviation. To solve the temperature drift problem of traditional bandgap reference circuits and obtain a more accurate reference voltage, this invention proposes a low-temperature-drift CMOS bandgap reference circuit with high-order curvature compensation. Summary of the Invention

[0003] The purpose of this invention is to provide a low-temperature drift CMOS bandgap reference circuit with high-order curvature compensation. It uses easily integrated devices suitable for various mainstream BCD processes, and adopts a low-power design to solve the problems of high static power consumption, large offset caused by process angle changes, and poor output accuracy that are common in existing bandgap reference circuits.

[0004] In view of the above problems, the technical solution proposed by the present invention is as follows:

[0005] The application provides a low temperature drift CMOS band gap reference circuit with high order curvature compensation, which comprises NMOS tubes M7, M12-M13, M9, M20-M21, PMOS tubes M1-M6, M10-M11, M8, M18-M19, M22-M25, BJT tubes Q1 and Q2, resistors R1-R3, a resistor RC, operational amplifiers OP1 and OP2, three external interfaces, a power input port VDD, a voltage output port VREF and a grounding port GND.

[0006] In order to better realize the technical scheme of the application, the connection relationship of the device is as follows:

[0007] The power input port VDD is connected with the source S of the PMOS tube M1~M6, M10~M11, M8, M14~M19, M22~M25; the PMOS tube M1 gate G is connected with the PMOS tube M2 gate G, M3 gate G, M10 gate G, M11 gate G, M8 gate G; the PMOS tube M5 gate G is connected with the PMOS tube M4 gate G, the PMOS tube M6 gate G, the PMOS tube M18 gate G, the PMOS tube M19 gate G; the PMOS tube M14 gate G is connected with the PMOS tube M14 gate D, the PMOS tube M16 gate G, the PMOS tube M10 drain D; the PMOS tube M15 gate G is connected with the PMOS tube M15 gate D, the PMOS tube M17 gate G, the PMOS tube M11 drain D; the PMOS tube M22 gate G is connected with the PMOS tube M22 gate D, the PMOS tube M24 gate G, the PMOS tube M18 drain D; the PMOS tube M23 gate G is connected with the PMOS tube M23 gate D, the PMOS tube M25 gate G, the PMOS tube M19 drain D; the NMOS tube M7 gate G is connected with the NMOS tube M7 drain D, the NMOS tube M12 gate G, the NMOS tube M13 drain G; the NMOS tube M9 gate G is connected with the NMOS tube M9 drain D, the NMOS tube M20 gate G, the NMOS tube M21 drain G; the PMOS tube M1 drain D is connected with the BJT tube Q1 emitter E, the operational amplifier OP1 inverting input end, the operational amplifier OP2 inverting input end; the PMOS tube M2 drain D is connected with the resistance R1 upper end, the operational amplifier OP1 noninverting input end; the PMOS tube M5 drain D is connected with the resistance R2 upper end, the operational amplifier OP2 noninverting input end; the PMOS tube M3 drain D is connected with the resistance R3 upper end, the PMOS tube M4 drain D; the PMOS tube M4 drain D is connected with the resistance R3 upper end, the PMOS tube M3 drain D; the PMOS tube M6 drain D is connected with the NMOS tube M7 gate G, the NMOS tube M7 drain D; the PMOS tube M10 drain D is connected with the NMOS tube M12 drain D, the PMOS tube M14 gate G, the PMOS tube M14 drain D; the PMOS tube M11 drain D is connected with the NMOS tube M13 drain D, the PMOS tube M15 gate G, the PMOS tube M15 drain D; the PMOS tube M8 drain D is connected with the NMOS tube M9 gate G, the NMOS tube M9 drain D; the PMOS tube M18 drain D is connected with the NMOS tube M20 drain D, the PMOS tube M22 gate G, the PMOS tube M22 drain D; the PMOS tube M23 drain D is connected with the NMOS tube M21 drain D, the PMOS tube M25 gate G, the PMOS tube M19 drain D.The PMOS tube M19 drain D is connected with the NMOS tube M21 drain D, the PMOS tube M23 gate G and the PMOS tube M23 drain D; the PMOS tube M16 drain D is connected with the PMOS tube M17 drain D and the upper end of the resistance RC; the PMOS tube M24 drain D is connected with the PMOS tube M25 drain D and the upper end of the resistance RC; the BJT tube Q1 emitter E is connected with the lower end of the resistance R1; the ground end GND is connected with the BJT tube Q1 collector C, the BJT tube Q1 base B, the BJT tube Q2 collector C, the BJT tube Q2 base B, the NMOS tube M7 source S, the NMOS tube M12 source S, the NMOS tube M13 source S, the NMOS tube M9 source S, the NMOS tube M20 source S, the NMOS tube M21 source S, the lower end of the resistance R2 and the lower end of the resistance RC.

[0008] The low-temperature drift CMOS bandgap reference circuit with high-order curvature compensation has the following beneficial effects:

[0009] Firstly, the present application realizes linear compensation of the temperature characteristics of the output voltage in multiple segments by designing multiple temperature segmentation points, combining addition and subtraction circuits and current mirror technology, and further efficiently improves the temperature coefficient.

[0010] Secondly, the use of the op-amps OP1 and OP2 with large gain for voltage clamping of the X, Y and Z nodes improves the accuracy of the obtained PTAT current and CTAT current, and further improves the accuracy of the output reference voltage.

[0011] Thirdly, stable 1.2V voltage output is realized in a wide temperature range of -40°C to 160°C, which can effectively support the industrial-grade working temperature range (-40°C to 85°C) and is compatible with a wider automotive-grade application temperature range (-40°C to 125°C).

[0012] Fourthly, the resistance and are adjusted by the resistance trimming method to more finely adjust their resistance values, optimize the temperature drift coefficient of the circuit when the process angle changes, and realize high-precision stable output of the bandgap reference circuit under the full process angle. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a schematic diagram of a traditional current-mode bandgap reference circuit.

[0014] Figure 2 is a structure schematic diagram of a high-order curvature compensation scheme suitable for a CMOS bandgap reference circuit provided by the present application.

[0015] Figure 3 is a schematic diagram of a low temperature drift CMOS bandgap reference circuit with high order curvature compensation provided by the present application. DETAILED DESCRIPTION

[0016] The present application of a low temperature drift CMOS bandgap reference circuit with high order curvature compensation is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description.

[0017] The present application provides a low temperature drift CMOS bandgap reference circuit with high order curvature compensation, the principle of which is shown in Figure 2 , first we need to set the temperature segmentation point ( , , , ), to segment the temperature interval; then realize temperature compensation in each interval. In short, the compensation circuit needs to provide a negative temperature coefficient compensation current ( , ) for BGR in the low temperature interval, and a positive temperature coefficient compensation current ( , ) in the high temperature interval. Then the generated compensation currents are superimposed in the main circuit to generate the total compensation current ( ), which finally flows into the compensation resistance to generate a compensation voltage that can be directly added to the BGR output. The advantage is that there is no need to introduce temperature insensitive resistance, reducing the difficulty of circuit design. Superimpose the compensation voltage and the original reference voltage together, and the output reference voltage with high precision and low temperature drift is obtained.

[0018] The circuit diagram is shown in Figure 3 , the circuit includes the following devices: NMOS tubes M7, M12-M13, M9, M20-M21; PMOS tubes M1-M6, M10-M11, M8, M18-M19, M22-M25, BJT tubes Q1, Q2, resistors R1-R3, resistor RC, operational amplifiers OP1, OP2. Three external interfaces: power input port VDD, voltage output port VREF, ground port GND. Among them, NMOS tubes M7, M12-M13, M9, M20-M21 are low voltage NMOS tubes; PMOS tubes M1-M6, M10-M11, M8, M18-M19, M22-M25 are low voltage PMOS tubes; bipolar transistor Q1 is a unit transistor, and Q2 is a parallel connection of n transistors.

[0019] The power input port VDD is connected with the source S of PMOS tubes M1~M6, M10~M11, M8, M14~M19, M22~M25; the gate G of PMOS tube M1 is connected with the gate G of PMOS tube M2, the gate G of PMOS tube M3, the gate G of PMOS tube M10, the gate G of PMOS tube M11, the gate G of PMOS tube M8; the gate G of PMOS tube M5 is connected with the gate G of PMOS tube M4, the gate G of PMOS tube M6, the gate G of PMOS tube M18, the gate G of PMOS tube M19; the gate G of PMOS tube M14 is connected with the gate D of PMOS tube M14, the gate G of PMOS tube M16, the drain D of PMOS tube M10; the gate G of PMOS tube M15 is connected with the gate D of PMOS tube M15, the gate G of PMOS tube M17, the drain D of PMOS tube M11; the gate G of PMOS tube M22 is connected with the gate D of PMOS tube M22, the gate G of PMOS tube M24, the drain D of PMOS tube M18; the gate G of PMOS tube M23 is connected with the gate D of PMOS tube M23, the gate G of PMOS tube M25, the drain D of PMOS tube M19; the gate G of NMOS tube M7 is connected with the drain D of NMOS tube M7, the gate G of NMOS tube M12, the gate G of NMOS tube M13; the gate G of NMOS tube M9 is connected with the drain D of NMOS tube M9, the gate G of NMOS tube M20, the gate G of NMOS tube M21; the drain D of PMOS tube M1 is connected with the emitter E of BJT tube Q1, the inverting input end of operational amplifier OP1, the inverting input end of operational amplifier OP2; the drain D of PMOS tube M2 is connected with the upper end of resistor R1, the non-inverting input end of operational amplifier OP1; the drain D of PMOS tube M5 is connected with the upper end of resistor R2, the non-inverting input end of operational amplifier OP2; the drain D of PMOS tube M3 is connected with the upper end of resistor R3, the drain D of PMOS tube M4; the drain D of PMOS tube M4 is connected with the upper end of resistor R3, the drain D of PMOS tube M3; the drain D of PMOS tube M6 is connected with the gate G of NMOS tube M7, the drain D of NMOS tube M7; the drain D of PMOS tube M10 is connected with the drain D of NMOS tube M12, the gate G of PMOS tube M14, the drain D of PMOS tube M14; the drain D of PMOS tube M11 is connected with the drain D of NMOS tube M13, the gate G of PMOS tube M15, the drain D of PMOS tube M15; the drain D of PMOS tube M8 is connected with the gate G of NMOS tube M9, the drain D of NMOS tube M9; the drain D of PMOS tube M18 is connected with the drain D of NMOS tube M20, the gate G of PMOS tube M22, the drain D of PMOS tube M22; the drain D of PMOS tube M19 is connected with the drain D of NMOS tube M21, the gate G of PMOS tube M23, the drain D of PMOS tube M23; the drain D of PMOS tube M16 is connected with the drain D of PMOS tube M17, the upper end of resistor RC; the drain D of PMOS tube M24 is connected with the drain D of PMOS tube M25, the upper end of resistor RC; the emitter E of BJT tube Q1 is connected with the lower end of resistor R1.The ground terminal GND is connected with the collector C of the BJT Q1, the base B of the BJT Q1, the collector C of the BJT Q2, the base B of the BJT Q2, the source S of the NMOS M7, the source S of the NMOS M12, the source S of the NMOS M13, the source S of the NMOS M9, the source S of the NMOS M20, the source S of the NMOS M21, the lower end of the resistor R2 and the lower end of the resistor RC.

[0020] The two operational amplifiers OP1 and OP2 clamp the voltages of the three nodes X, Y and Z to the same value, i.e. , and then obtain a positive temperature coefficient (PTAT) current and a negative temperature coefficient (CTAT) current . At the output end of the BGR, the PTAT current and the CTAT current are respectively copied and transmitted to the branch where the resistor R is located by the current mirror , and the currents are superimposed to form a temperature-independent reference current .

[0021] By designing multiple temperature segmentation points on the basis of the traditional current mode bandgap reference , , , , combining the addition and subtraction circuit and the current mirror technology, low-temperature compensation currents and high-temperature compensation currents are obtained, and the currents are superimposed in the branch where the resistor RC is located to form a high-order curvature compensation current , and the middle-temperature region does not need to be compensated. Finally, the reference current and the compensation current are superimposed in the output stage to form a bandgap reference output , which further improves the temperature coefficient efficiently.

[0022] The low-temperature drift CMOS bandgap reference circuit with high-order curvature compensation proposed in the present application is built using a 0.18 um BCD process and verified by Cadence simulation, and the bandgap reference circuit proposed in the present application can work in a wide temperature range of to . The output stable voltage of the BGR circuit designed in the present application is 1.2V, and the temperature drift coefficient reaches an incredible .

[0023] ​The preferred embodiments of the application have been described above in detail. It should be understood that modifications and variations to the preferred embodiments could be made by those skilled in the art in light of the teachings above. It is therefore contemplated that the application can encompass other variations and modifications that fall within the scope of the claims.

Claims

1. A low-temperature drift CMOS bandgap reference circuit with high-order curvature compensation, characterized in that, include: NMOS transistors M7, M12~M13, M9, M20~M21; PMOS transistors M1~M6, M10~M11, M8, M18~M19, M22~M25; BJT transistors Q1, Q2; resistors R1~R3; resistor RC; operational amplifiers OP1, OP2. Three external interfaces: power input port VDD, voltage output port VREF, and ground port GND.

2. The high-order curvature compensation low-temperature drift CMOS bandgap reference circuit according to claim 1, characterized in that: The NMOS transistors M7, M12~M13, M9, and M20~M21 are low-voltage NMOS transistors; the PMOS transistors M1~M6, M10~M11, M8, M18~M19, and M22~M25 are low-voltage PMOS transistors. The bipolar transistor Q1 is a single-unit transistor, and Q2 consists of n transistors connected in parallel.

3. The high-order curvature compensation low-temperature drift CMOS bandgap reference circuit according to claim 1, characterized in that: The power input port VDD is connected to the source S of PMOS transistors M1~M6, M10~M11, M8, M14~M19, and M22~M25; the gate G of PMOS transistor M1 is connected to the gates G of PMOS transistors M2, M3, M10, M11, and M8; the gate G of PMOS transistor M5 is connected to the gates G of PMOS transistors M4, M6, M18, and M19; the gate G of PMOS transistor M14 is connected to the gate D of PMOS transistor M14, the gate G of PMOS transistor M16, and the drain D of PMOS transistor M10; the PMOS... The gate G of transistor M15 is connected to the gate D of PMOS transistor M15, the gate G of PMOS transistor M17, and the drain D of PMOS transistor M11; the gate G of PMOS transistor M22 is connected to the gate D of PMOS transistor M22, the gate G of PMOS transistor M24, and the drain D of PMOS transistor M18; the gate G of PMOS transistor M23 is connected to the gate D of PMOS transistor M23, the gate G of PMOS transistor M25, and the drain D of PMOS transistor M19; the gate G of NMOS transistor M7 is connected to the drain D of NMOS transistor M7, the gate G of NMOS transistor M12, and the drain G of NMOS transistor M13; the gate G of NMOS transistor M9 is connected to the drain D of NMOS transistor M9. The drain D of the PMOS transistor M1 is connected to the gate G of the NMOS transistor M20 and the drain G of the NMOS transistor M21; the drain D of the PMOS transistor M1 is connected to the emitter E of the BJT transistor Q1, the inverting input terminal of the operational amplifier OP1, and the inverting input terminal of the operational amplifier OP2; the drain D of the PMOS transistor M2 is connected to the upper end of the resistor R1 and the non-inverting input terminal of the operational amplifier OP1; the drain D of the PMOS transistor M5 is connected to the upper end of the resistor R2 and the non-inverting input terminal of the operational amplifier OP2; the drain D of the PMOS transistor M3 is connected to the upper end of the resistor R3 and the drain D of the PMOS transistor M4; the drain D of the PMOS transistor M4 is connected to the upper end of the resistor R3 and the drain D of the PMOS transistor M3; the drain D of the PMOS transistor M6 is connected to the upper end of the resistor R3 and the drain D of the PMOS transistor M4; the drain D of the PMOS transistor M6 is connected to the upper end of the resistor R3 and the drain D of the PMOS transistor M3; the drain D of the PMOS transistor M6 is connected to the upper end of the resistor R3 and the drain D of the PMOS transistor M4; the drain D of the PMOS transistor M5 is connected to the upper end of the resistor R2 and the non-inverting input terminal of the operational amplifier OP2; the drain D of the PMOS transistor M5 is connected to the upper end of the resistor R2 and the drain D of the PMOS transistor M4; the drain D of the PMOS transistor M5 is connected to the upper end of the resistor R3 ... The drain D of PMOS transistor M10 is connected to the gate G and drain D of NMOS transistor M7; the drain D of PMOS transistor M10 is connected to the drain D of NMOS transistor M12, the gate G and drain D of PMOS transistor M14; the drain D of PMOS transistor M11 is connected to the drain D of NMOS transistor M13, the gate G and drain D of PMOS transistor M15; the drain D of PMOS transistor M8 is connected to the gate G and drain D of NMOS transistor M9; the drain D of PMOS transistor M18 is connected to the drain D of NMOS transistor M20, the gate G and drain D of PMOS transistor M22.The drain D of PMOS transistor M19 is connected to the drain D of NMOS transistor M21, the gate G of PMOS transistor M23, and the drain D of PMOS transistor M23; the drain D of PMOS transistor M16 is connected to the drain D of PMOS transistor M17 and the upper end of resistor RC; the drain D of PMOS transistor M24 is connected to the drain D of PMOS transistor M25 and the upper end of resistor RC; the emitter E of BJT transistor Q1 is connected to the lower end of resistor R1; The ground terminal GND is connected to the collector C of BJT transistor Q1, the base B of BJT transistor Q1, the collector C of BJT transistor Q2, the base B of BJT transistor Q2, the source S of NMOS transistor M7, the source S of NMOS transistor M12, the source S of NMOS transistor M13, the source S of NMOS transistor M9, the source S of NMOS transistor M20, the source S of NMOS transistor M21, the lower end of resistor R2, and the lower end of resistor RC.

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