Memory fault processing method and device and baseboard management controller
By dynamically setting the inspection cycle and utilizing BIOS fault repair and machine learning models to generate processing instructions, the problem of untimely handling of DDR5 memory faults was solved, improving memory fault handling efficiency and monitoring capabilities, and enabling predictive maintenance.
Patent Information
- Application Number
- CN202511072301.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-18
AI Technical Summary
In existing technologies, DDR5 memory lacks the ability to trigger interrupts, which may lead to untimely fault handling due to the fixed inspection cycle, thus reducing the efficiency of memory fault handling.
By responding to inspection commands, the target address of the memory chip under test is located, the fault sensitivity is determined based on the target inspection scenario, the inspection cycle is dynamically set, the fault is repaired using BIOS, and processing commands are automatically generated through machine learning models to achieve timely fault handling.
It improves the efficiency of memory fault handling, reduces manual operation steps, enhances fault monitoring capabilities, enables predictive maintenance, and avoids situations where fault handling is not timely.
Smart Images
Figure CN120973569A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of storage, in particular to a memory fault processing method and device and a baseboard management controller. BACKGROUND
[0002] With the rapid development of technology industry computing power, the current memory capacity is getting larger and larger. For double data rate synchronous dynamic random access memory (DDR SDRAM), it faces higher capacity, faster speed and smaller process technology. The possibility of unit error in the memory array increases, and the failure rate is also higher.
[0003] The DDR5 memory grain can correct single-bit errors internally, and support periodic error checking and erasing operations during memory refresh state. However, in the prior art, since the memory itself does not have the ability to trigger an interrupt, fixed patrol cycles to detect faults may cause the situation that fault processing is not timely, resulting in a decrease in the efficiency of the memory fault processing process. SUMMARY
[0004] In order to solve the above problems in the prior art, the present application provides a memory fault processing method, device and baseboard management controller.
[0005] In a first aspect, the embodiments of the present application provide a memory fault processing method, comprising:
[0006] In response to a patrol instruction, the identification of the to-be-tested memory grain contained in the patrol instruction is located to obtain the target address corresponding to the to-be-tested memory grain;
[0007] Based on the target address, the target patrol scene in which the to-be-tested memory grain is located is determined; different target addresses correspond to different patrol scenes;
[0008] Based on the corresponding relationship between the plurality of patrol scenes and the fault sensitivity, the target fault sensitivity corresponding to the target patrol scene is determined, and the patrol cycle corresponding to the target patrol scene is determined based on the target fault sensitivity; the target fault sensitivity is inversely proportional to the patrol cycle;
[0009] If the to-be-tested memory grain has a fault, the fault in the to-be-tested memory grain is processed after the patrol cycle ends.
[0010] After receiving the inspection instruction, the identification of the to-be-tested memory particle can be located in response to the inspection instruction, so as to obtain the target address corresponding to the to-be-tested memory particle. The target inspection scene is determined through the target address corresponding to the to-be-tested memory particle, so as to determine the corresponding inspection period according to the target fault sensitivity corresponding to the target inspection scene, and process the fault after the inspection period ends. By dynamically setting the inspection period, it can be avoided that the fixed inspection period for detecting faults may cause the situation that the fault processing is not timely, which speeds up the screening efficiency of the fault and improves the efficiency of the memory fault processing process.
[0011] In a possible implementation, the processing of the fault in the to-be-tested memory particle includes:
[0012] Based on the to-be-tested memory particle fault information, a processing instruction is determined;
[0013] The processing instruction is sent to the basic input and output system (BIOS) to make the BIOS repair the fault in the to-be-tested memory particle;
[0014] The repair time and repair content returned by the BIOS after executing the processing instruction are received.
[0015] By interacting with the BIOS, the BIOS can be directly made to execute the processing instruction, and the relevant information generated by the BIOS in the process of executing the processing instruction can be received. By obtaining the relevant information generated by the BIOS in the process of executing the processing instruction, the user or the BMC can monitor the condition of the BIOS executing the processing instruction, avoid possible hidden errors, and improve the efficiency of the memory fault processing process.
[0016] In a possible implementation, the processing instruction is determined based on the to-be-tested memory particle fault information, including:
[0017] The fault information in the to-be-tested memory particle is displayed, and a processing instruction is received. The fault information includes at least one of the number of data rows stored in the to-be-tested memory particle, the number of faults, and the address corresponding to the row with the most faults.
[0018] Through the above manner, the fault information can be displayed to the relevant staff. The relevant staff can input the processing instruction after obtaining the fault information. The display of the fault information can help the user to clearly determine the fault information, strengthen the monitoring ability of the fault, and enable the user to accurately solve the memory fault, thereby improving the efficiency of the memory fault processing process.
[0019] In a possible implementation, the processing instruction is determined based on the to-be-tested memory particle fault information, including:
[0020] classifying the fault information in the to-be-tested memory particle by using the trained machine learning model to generate a processing instruction corresponding to a category of the fault information;
[0021] The machine learning model is trained in the following manner:
[0022] inputting historical data as a training set into the machine learning model according to different categories until a loss value of the machine learning model reaches a target threshold value and the loss value is in a target interval within a set period of time; the historical data includes a plurality of historical fault information and a solution measure for each historical fault information.
[0023] In this way, the related staff can be free from inputting fault information, the machine learning model is trained by using historical data, the machine learning model classifies based on fault information, and a processing instruction is automatically generated, which reduces the steps of manual operation and improves the efficiency of the memory fault processing process.
[0024] In a possible implementation, after the fault in the to-be-tested memory particle is processed, the method further includes:
[0025] updating a total number of times of faults generated in a set number of inspection processes of the to-be-tested memory particle;
[0026] determining a state of the to-be-tested memory particle based on the total number of times;
[0027] determining a wear value of the to-be-tested memory particle in different states according to the state of the to-be-tested memory particle, and performing maintenance on to-be-tested memory particles with different wear values.
[0028] After the fault in the to-be-tested memory particle is processed, the predictive maintenance on to-be-tested memory particles with different wear values can be implemented by determining the wear value of the to-be-tested memory particle, which can replace the to-be-tested memory particle with a larger wear value in advance before the next inspection, thereby avoiding possible problems in the process of using the to-be-tested memory particle.
[0029] In a possible embodiment, the determining of the state of the to-be-tested memory particle based on the total number of times includes:
[0030] if the total number of times is less than or equal to a first threshold value, determining that the state of the to-be-tested memory particle is a first state;
[0031] if the total number of times is greater than the first threshold value and less than or equal to a second threshold value, determining that the state of the to-be-tested memory particle is a second state;
[0032] If the total number of tests is greater than the second threshold, then the state of the memory chip under test is determined to be the third state.
[0033] The step of determining the wear value of the memory chip under test in different states based on the state of the memory chip under test includes:
[0034] The wear value of the memory chip under test in the first state is less than the third threshold;
[0035] The wear value of the memory chip under test in the second state is greater than the third threshold but less than the fourth threshold;
[0036] The wear value of the memory chip under test in the third state is greater than the fourth threshold.
[0037] The above method can determine the total number of failures for each memory chip under test, thereby determining the state of each memory chip under test, and determining the corresponding wear value based on the state of each memory chip under test. The wear value determined in this way is more accurate and can be classified according to different thresholds for the wear of different memory chips under test.
[0038] In one possible implementation, the maintenance of the memory chips under test for different wear values includes:
[0039] If the wear value of the memory chip under test is greater than the third threshold but less than the fourth threshold, a frequency reduction request is sent to the BIOS to reduce the operating frequency of the memory block under test.
[0040] If the wear value of the memory chip under test is greater than the fourth threshold, the memory chip under test will be deactivated and a prompt will be made to replace the memory chip under test.
[0041] The above methods enable predictive maintenance of memory chips under test with different wear values, avoiding more and more serious failures during subsequent use or inspection, and improving the accuracy of the memory chips under test during use.
[0042] Secondly, embodiments of this application provide a memory fault handling apparatus, including:
[0043] The target inspection scenario determination unit is used to respond to the inspection command, locate the identifier of the memory chip to be tested contained in the inspection command, and obtain the target address corresponding to the memory chip to be tested.
[0044] The target inspection scenario of the memory chip under test is determined based on the target address; different target addresses correspond to different inspection scenarios.
[0045] The inspection cycle determination unit is used to determine the target fault sensitivity corresponding to the target inspection scenario based on the correspondence between multiple inspection scenarios and fault sensitivity, and to determine the inspection cycle corresponding to the target inspection scenario based on the target fault sensitivity; the target fault sensitivity is inversely proportional to the inspection cycle;
[0046] The memory fault handling unit is used to handle the fault in the memory chip under test after the inspection cycle ends if the memory chip under test has a fault.
[0047] Thirdly, embodiments of this application provide a substrate control manager (BMC), comprising:
[0048] Memory, used to store program instructions;
[0049] A processor is configured to invoke program instructions stored in the memory and execute the steps included in the method described in the first aspect according to the obtained program instructions.
[0050] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method described in the first aspect.
[0051] This application provides a memory fault handling method, apparatus, and baseboard management controller. Upon receiving a patrol inspection command, the method responds to the command by locating the identifier of the memory chip under test contained in the command, thereby obtaining the target address corresponding to the memory chip under test. The target patrol scene is determined by the target address of the memory chip under test, and the corresponding patrol cycle is determined based on the target fault sensitivity of the target patrol scene. The fault is then handled after the patrol cycle ends. By dynamically setting the patrol cycle, the method avoids the situation where a fixed patrol cycle may lead to untimely fault handling due to the memory's lack of interrupt triggering capability. This accelerates the fault screening efficiency and improves the efficiency of the memory fault handling process. Attached Figure Description
[0052] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0053] Figure 1 This is an application scenario diagram of a memory fault handling method provided in an embodiment of this application;
[0054] Figure 2 A flowchart illustrating a memory fault handling method provided in this application embodiment;
[0055] Figure 3 A detailed flowchart of a memory fault handling method provided in this application embodiment;
[0056] Figure 4 A structural block diagram of a memory fault handling device provided in an embodiment of this application;
[0057] Figure 5 This is a structural block diagram of a BMC provided in an embodiment of this application. Detailed Implementation
[0058] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0059] It should be noted that the terms "comprising" and "having" and their variations used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.
[0060] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.
[0061] The word “exemplary” as used below means “serving as an example, embodiment, or illustration.” Any embodiment illustrated as an “exemplary” need not be construed as superior to or better than other embodiments.
[0062] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0063] Figure 1 This illustration shows an application scenario diagram of a memory fault handling method provided in an embodiment of this application. (See attached diagram.) Figure 1As shown, the application scenario includes a Baseboard Management Controller (BMC) 100, a Basic Input Output System (BIOS) 200, and memory chips under test (DUT) 310, 320, and 330. The BMC 100 can execute a memory fault handling method provided in this embodiment, processing the DUT 310, 320, and 330. After obtaining processing instructions capable of repairing faults in the DUT memory chips, the BMC 100 can send these instructions to the BIOS 200, enabling the BIOS 200 to execute the instructions and repair the faults. It should be noted that this application is not limited to... Figure 1 The memory chips under test 310, 320, and 330 shown may have more or fewer memory chips under test, which is not limited here. In addition to the BMC100 being able to execute the memory fault handling method provided in the embodiments of this application, other electronic devices that can inspect the memory chips under test and interact with the BIOS200 can also be used, which is also not limited here.
[0064] The memory fault handling method provided by the exemplary embodiments of this application will be described below with reference to the accompanying drawings and the application scenarios described above. It should be noted that the above application scenarios are only shown to facilitate understanding of the spirit and principles of this application, and the embodiments of this application are not limited in any way in this respect.
[0065] In one possible embodiment, the DDR5 memory chip can internally correct single-bit errors and support periodic error checks and erase operations during memory refresh. However, in the prior art, since the memory itself does not have the ability to trigger interrupts, a fixed inspection cycle to detect faults may lead to untimely fault handling, resulting in reduced efficiency in the memory fault handling process. Therefore, this application proposes a memory fault handling method, apparatus, and baseboard management controller, which can be used to solve the aforementioned problem of reduced efficiency in the memory fault handling process.
[0066] Figure 2 A flowchart of a memory fault handling method provided in an embodiment of this application is shown, as follows: Figure 2 As shown, the method may include the following steps:
[0067] Step S201: Respond to the inspection command, locate the identifier of the memory chip to be tested contained in the inspection command, and obtain the target address corresponding to the memory chip to be tested.
[0068] In one possible embodiment, the inspection command can be input by the tester or it can be set to be automatically generated after each inspection. This application does not limit this. The inspection command may contain the identification information of the memory chip under test. The identification information of the memory chip under test corresponds one-to-one with the memory chip under test. Each memory chip under test has its own identification information. Therefore, the system can respond to the inspection command and locate the memory chip under test based on the identification information of the memory chip under test contained in the inspection command to obtain the target address corresponding to the memory chip under test. After decoding the target address corresponding to the memory chip under test, the specific location of the memory chip under test can be obtained; or a lookup table can be used to determine the specific location of the memory chip under test corresponding to the target address.
[0069] Step S202: Determine the target inspection scenario of the memory chip under test based on the target address.
[0070] In one possible embodiment, since the target address corresponding to the memory particle under test can be mapped to the specific location of the memory particle under test, the target inspection scenario of the memory particle under test can be determined based on the target address. Specifically, different specific locations of the memory particle under test indicate that the services served by the memory particle under test are different. For example, if the specific location of the memory particle under test is the storage space used by the core database in the process of storing data, then the target inspection scenario of the memory particle under test can be determined to be the core business; if the specific location of the memory particle under test is the storage space used by the offline database in the process of storing data, then the target inspection scenario of the memory particle under test can be determined to be the offline business.
[0071] Step S203: Based on the correspondence between multiple inspection scenarios and fault sensitivity, determine the target fault sensitivity corresponding to the target inspection scenario, and determine the inspection cycle corresponding to the target inspection scenario based on the target fault sensitivity.
[0072] In one possible embodiment, each inspection scenario may have a different correspondence with fault sensitivity. For example, the core business described in step S202 is more important and should have its failure frequency minimized, so its corresponding fault sensitivity is higher, meaning it is more sensitive to the occurrence of faults. The offline business described in step S202 is less sensitive to latency, so its fault sensitivity is lower compared to the core business.
[0073] In one possible embodiment, the inspection cycle corresponding to the target inspection scenario can be determined based on the target fault sensitivity. The inspection cycle corresponding to the target inspection scenario with higher fault sensitivity is shorter, and the inspection cycle corresponding to the target inspection scenario with lower fault sensitivity is longer. For example, core database services are sensitive to latency, so the inspection cycle can be shortened (e.g., 10 minutes); while offline storage services can have a longer cycle (e.g., 48 hours).
[0074] In another possible embodiment, different inspection cycles can be determined based on the load of different memory chips under test. For example, for any memory chip under test, if the load of the memory chip under test is large, the inspection cycle can be shortened to avoid irreparable failures. If the load of the memory chip under test is small and less data needs to be stored, the corresponding inspection cycle can be appropriately extended.
[0075] It should be noted that the two methods mentioned above (determining the inspection cycle through the target inspection scenario and determining the inspection cycle through the load of the memory chip under test) can be integrated. The dynamic cycle algorithm can simultaneously measure the two methods and perform weighted processing to determine the corresponding inspection cycle. This method can determine the inspection cycle more accurately. Compared with the existing technology that does not limit the inspection cycle or adjusts the inspection cycle manually, the method provided in this application can effectively reduce manual operation and thus improve the accuracy of the inspection cycle determination process.
[0076] Step S204: If the memory chip under test is faulty, the fault in the memory chip under test shall be handled after the inspection cycle ends.
[0077] In one possible embodiment, the data stored in the Mode Register (MR) 19 and MR20 of the memory chip under test can be read one by one. If the data stored in MR20 is not 0, it can be determined that the memory chip under test has a fault during the inspection cycle. Here, MR20 can be regarded as a fault counter, and the data stored in it is the number of faults that have occurred. If the data stored in MR20 is 0, it can be determined that the memory chip under test has no fault during the inspection cycle, and there is no need to handle the fault. The inspection can be returned to step S201 and repeated.
[0078] In one possible embodiment, if the memory chip under test is faulty, the fault can be processed after the inspection cycle ends. Specifically, data stored in MR14 to MR19 can be read to obtain fault information of the memory chip under test. The data stored in MR14 reflects the counting mode and Error Check and Scrub (ECS) mode in MR20. ECS mode allows the DRAM to internally read and correct single-bit errors and write the corrected data back to the array (cleaning up errors), while providing transparent error counting. The data stored in MR15 reflects the number of fault thresholds in the memory chip under test. The data stored in MR16 to MR18 reflect the row address with the most faults in the memory chip under test, and the data stored in MR19 reflects the number of rows of data stored in the memory chip under test. It is important to note that MR is the memory mode register defined in the JEDEC specification. It is a special register used to define various programmable operating modes of SDRAM (Synchronous Dynamic Random Access Memory). Therefore, MR will not experience data errors due to faults in the memory chip under test.
[0079] In one possible embodiment, processing instructions can be determined based on fault information in the memory chip under test in the following three ways: 1. After obtaining the fault information in the memory chip under test, the fault information can be displayed to the user, and an input box can be provided for the user to input processing instructions. After the user inputs the processing instructions in the input box, they can click the submit control, so that the BMC can receive the processing instructions input by the user; 2. Alternatively, a trained machine learning model can be used to classify the fault information in the memory chip under test to generate processing instructions corresponding to the categories of fault information. The machine learning model can be trained in the following way: it can be trained by including multiple historical fault information... Historical data on solutions for each historical error message are categorized and used as training sets for the machine learning model until the model's loss value reaches a target threshold and remains within a target range over a set time period. The machine learning model can be a decision tree or an LSTM; this application does not specify a particular model. The machine learning model can learn different handling methods for different types of faults from historical data, thereby generating corresponding processing instructions. 3. Determine the corresponding processing instructions based on the specific fault information. Specifically, if the row address error count in different memory groups within the same memory chip exceeds 1000, Adaptive Dual-Device Data Correction (Adaptive Dual-Device Data Correction) can be enabled. Double Device Data Correction (ADDDC) uses memory row-level fault region replacement as a processing instruction. If the count of different faulty line addresses in the same memory group within the same memory chip exceeds 100, ADDDC can be enabled to replace the faulty line at the memory row level as a processing instruction. If the count of the same faulty line address in the same memory chip exceeds 10, Post Package Repair (PPR) can be enabled to repair the faulty line as a processing instruction. Here, a memory row refers to a collection of physical storage units within a memory module, which share the same control signals and data bus; a memory group refers to an organizational unit within a memory module, which is a logical storage area used to manage data storage and access.
[0080] In another possible embodiment, for the second method of obtaining processing instructions described above, another machine learning model can be used to learn the "correlation between error patterns and hardware failures" from historical error data (such as a batch of memory chips being prone to specific address segment errors at high temperatures), to achieve "error classification warning" (distinguishing between temporary interference errors and hardware degradation errors), thereby generating corresponding processing instructions (such as prioritizing PPR repair for hardware degradation errors, and only recording without repairing interference errors).
[0081] In one possible embodiment, after determining the processing instructions, the processing instructions can be sent to the Basic Input / Output System (BIOS) to enable the BIOS to execute the processing instructions and repair the fault in the memory chip under test. Alternatively, the processing instructions can be stored in the shared memory of the Video Graphics Array (VGA). Shared memory initialization is performed during the BIOS boot phase. The BMC can fill the shared memory with the processing instructions and trigger a software system interrupt to notify the BIOS. The BIOS code then parses the data from the shared memory and executes the processing instructions. After the BIOS repairs the fault in the memory chip under test, the BMC can receive the repair time and repair details returned by the BIOS after executing the processing instructions, and can also display the received repair time and repair details.
[0082] In one possible embodiment, after handling the faults in the memory chip under test, the total number of faults generated by the memory chip under test during the inspection process within a set number of times can be updated. Specifically, a separate file can be created to store the total number of faults generated by each memory chip under test during the inspection process within a set number of times. After each inspection, the data saved in the file can be added to the data saved in MR20, thereby updating the total number of faults generated by the memory chip under test during the inspection process within a set number of times.
[0083] In one possible embodiment, after updating the total number of faults that occurred during the inspection of the memory chip under test within a set number of cycles, the state of the memory chip under test can be determined based on the total number of faults. If the total number of faults is less than or equal to a first threshold, the state of the memory chip under test is determined to be a first state; if the total number of faults is greater than the first threshold and less than or equal to a second threshold, the state of the memory chip under test is determined to be a second state; if the total number of faults is greater than the second threshold, the state of the memory chip under test is determined to be a third state. The first threshold can be 200 or other values, which are not limited herein; the second threshold can be 500 or other values, which are not limited herein; the third threshold can be 1000 or other values, which are not limited herein. The first state can be considered as a relatively good state of the memory chip under test, the second state as a generally good state, and the third state as a relatively poor state.
[0084] In one possible embodiment, after obtaining the state of the memory chip under test, the wear value of the memory chip under test in different states can be determined based on its state. Specifically, the wear value of the memory chip under test in the first state is less than a third threshold; the wear value of the memory chip under test in the second state is greater than the third threshold but less than a fourth threshold; and the wear value of the memory chip under test in the third state is greater than the fourth threshold. If the wear value of the memory chip under test is less than the third threshold, it can be considered that the wear value of the memory chip under test is small and will hardly have any impact on the memory chip under test; if the wear value of the memory chip under test is greater than the third threshold but less than the fourth threshold, it can be considered that the wear value of the memory chip under test is average and will occasionally fail; and if the wear value of the memory chip under test is greater than the fourth threshold, it can be considered that the wear value of the memory chip under test is large and will frequently fail.
[0085] In one possible embodiment, maintenance can be performed on the memory chips under test with different wear values. Specifically, for memory chips under test with wear values less than the third threshold, no substantial maintenance is required; only recording is needed. For memory chips under test with wear values greater than the third threshold but less than the fourth threshold, a frequency reduction request can be sent to the BIOS to reduce the operating frequency of the memory chips under test, thereby preventing the probability of occasional failures due to overload from increasing. For memory chips under test with wear values greater than the fourth threshold, the memory chips under test can be disabled, and the user can be prompted to replace them.
[0086] This application provides a memory fault handling method, apparatus, and baseboard management controller. Upon receiving a patrol inspection command, the method responds to the command by locating the identifier of the memory chip under test contained in the command, thereby obtaining the target address corresponding to the memory chip under test. The target patrol scene is determined by the target address of the memory chip under test, and the corresponding patrol cycle is determined based on the target fault sensitivity of the target patrol scene. The fault is then handled after the patrol cycle ends. By dynamically setting the patrol cycle, the method avoids the situation where a fixed patrol cycle may lead to untimely fault handling due to the memory's lack of interrupt triggering capability. This accelerates the fault screening efficiency and improves the efficiency of the memory fault handling process.
[0087] In one specific embodiment, Figure 3 A flowchart illustrating a memory fault handling method provided in an embodiment of this application is shown, such as... Figure 3 As shown, the method may include the following steps:
[0088] Step S301: Respond to the inspection command, locate the identifier of the memory chip to be tested contained in the inspection command, and obtain the target address corresponding to the memory chip to be tested.
[0089] Step S302: Determine the target inspection scenario of the memory chip under test based on the target address.
[0090] Step S303: Based on the correspondence between multiple inspection scenarios and fault sensitivity, determine the target fault sensitivity corresponding to the target inspection scenario, and determine the inspection cycle corresponding to the target inspection scenario based on the target fault sensitivity.
[0091] Step S304: Determine if the memory chip under test is faulty. If yes, proceed to step S305; otherwise, return to step S301.
[0092] Step S305: Determine the processing instructions based on the fault information of the memory chip under test.
[0093] In one possible embodiment, fault information in the memory chip under test is displayed, and processing instructions are received; the fault information includes at least one of the following: the number of data rows stored in the memory chip under test, the number of faults, and the address corresponding to the row with the most faults.
[0094] In another possible embodiment, a trained machine learning model is used to classify fault information in the memory chip under test in order to generate processing instructions corresponding to the category of fault information.
[0095] Machine learning models are trained in the following way:
[0096] Historical data is categorized into different classes and used as a training set to input into the machine learning model until the loss value of the machine learning model reaches the target threshold and the loss value is within the target range within a set time period. The historical data includes multiple historical fault information and solutions for each historical error message.
[0097] Step S306: Send the processing instruction to the Basic Input / Output System (BIOS) so that the BIOS can repair the fault in the memory chip under test.
[0098] Step S307: Receive the repair duration and repair content returned by the BIOS after executing the processing instructions.
[0099] Step S308: Update the total number of times the memory chip under test has failed during the inspection process within a set number of cycles.
[0100] Step S309: Determine the status of the memory chip under test based on the total number of tests.
[0101] If the total number of tests is less than or equal to the first threshold, then the state of the memory chip under test is determined to be the first state.
[0102] If the total number of tests is greater than the first threshold and less than or equal to the second threshold, then the state of the memory chip under test is determined to be the second state.
[0103] If the total number of tests exceeds the second threshold, the state of the memory chip under test is determined to be the third state.
[0104] Step S310: Based on the state of the memory chip under test, determine the wear value of the memory chip under test under different states, and perform maintenance on the memory chip under test with different wear values.
[0105] The wear value of the memory chip under test in the first state is less than the third threshold;
[0106] The wear value of the memory chip under test in the second state is greater than the third threshold but less than the fourth threshold;
[0107] The wear value of the memory chip under test in the third state is greater than the fourth threshold.
[0108] If the wear value of the memory chip under test is greater than the third threshold but less than the fourth threshold, a frequency reduction request is sent to the BIOS to reduce the operating frequency of the memory chip under test.
[0109] If the wear value of the memory chip under test is greater than the fourth threshold, the memory chip under test will be disabled and a prompt will be made to replace the memory chip under test.
[0110] Based on the same inventive concept Figure 4 A structural block diagram of a memory fault handling device provided in an embodiment of this application is shown below. Figure 4 As shown, the memory fault handling device 400 may include:
[0111] The target inspection scenario determination unit 401 is used to respond to the inspection command, locate the identifier of the memory chip to be tested contained in the inspection command, and obtain the target address corresponding to the memory chip to be tested.
[0112] The target inspection scenario of the memory chip under test is determined based on the target address; different target addresses correspond to different inspection scenarios.
[0113] The inspection cycle determination unit 402 is used to determine the target fault sensitivity corresponding to the target inspection scenario based on the correspondence between multiple inspection scenarios and fault sensitivity, and to determine the inspection cycle corresponding to the target inspection scenario based on the target fault sensitivity; the target fault sensitivity is inversely proportional to the inspection cycle;
[0114] The memory fault handling unit 403 is used to handle the fault in the memory chip under test after the inspection cycle ends if the memory chip under test has a fault.
[0115] In one possible implementation, the memory fault processing unit 403 is specifically used to determine processing instructions based on the fault information of the memory chip under test;
[0116] The processing instruction is sent to the Basic Input / Output System BIOS so that the BIOS can repair the fault in the memory chip under test.
[0117] Receive the repair time and repair content returned by the BIOS after executing the processing instruction.
[0118] In one possible implementation, the memory fault processing unit 403 is specifically used to display fault information in the memory chip under test and receive processing instructions; the fault information includes at least one of the following: the number of data rows stored in the memory chip under test, the number of faults, and the address corresponding to the row with the most faults.
[0119] In one possible implementation, the memory fault processing unit 403 is specifically used to classify the fault information in the memory chip under test using a trained machine learning model, so as to generate processing instructions corresponding to the category of the fault information.
[0120] The machine learning model is trained in the following manner:
[0121] Historical data is categorized into different classes and input into the machine learning model as a training set until the loss value of the machine learning model reaches the target threshold and the loss value is within the target range within a set time period; the historical data includes multiple historical fault information and solutions for each historical error message.
[0122] In one possible implementation, the memory fault handling unit 403 is specifically used to update the total number of faults that occurred during the inspection process of the memory chip under test within a set number of times.
[0123] The state of the memory chip under test is determined based on the total number of tests.
[0124] Based on the state of the memory chip under test, the wear value of the memory chip under test in different states is determined, and maintenance is performed on the memory chip under test with different wear values.
[0125] In one possible implementation, the memory fault handling unit 403 is specifically used to determine the state of the memory chip under test as a first state if the total number of failures is less than or equal to a first threshold.
[0126] If the total number of tests is greater than the first threshold and less than or equal to the second threshold, then the state of the memory chip under test is determined to be the second state.
[0127] If the total number of tests is greater than the second threshold, then the state of the memory chip under test is determined to be the third state.
[0128] The wear value of the memory chip under test in the first state is less than the third threshold;
[0129] The wear value of the memory chip under test in the second state is greater than the third threshold but less than the fourth threshold;
[0130] The wear value of the memory chip under test in the third state is greater than the fourth threshold.
[0131] In one possible implementation, the memory fault handling unit 403 is specifically used to send a frequency reduction request to the BIOS to reduce the operating frequency of the memory chip under test if the wear value of the memory chip under test is greater than the third threshold and less than the fourth threshold.
[0132] If the wear value of the memory chip under test is greater than the fourth threshold, the memory chip under test will be deactivated and a prompt will be made to replace the memory chip under test.
[0133] Based on the same inventive concept, this application provides a BMC that can implement the memory fault handling method discussed above. Please refer to... Figure 5 The electronic device includes a memory 501, a processor 502, and a bus 503.
[0134] The memory 501 is used to store computer programs executed by the processor 502. The memory 501 may mainly include a program storage area and a data storage area. The program storage area may store the operating system and programs required to run instant messaging functions, etc.; the data storage area may store various instant messaging information and operation instruction sets, etc.
[0135] Memory 501 may be volatile memory, such as random-access memory (RAM); memory 501 may also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or memory 501 may be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 501 may be a combination of the above-mentioned memories.
[0136] The processor 502 may include one or more central processing units (CPUs) or digital processing units, etc. The processor 502 is used to implement the memory fault handling method in the above embodiments when calling the computer program stored in the memory 501.
[0137] This application embodiment does not limit the specific connection medium between the memory 501 and the processor 502 described above. This application embodiment... Figure 5 The memory 501 and the processor 502 are connected via a bus 503, and the bus 503 is in Figure 5 The connections between other components are shown in thick lines only and are not intended to be limiting. The 503 bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.
[0138] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium. The computer program product includes computer program code, which, when executed on a computer, causes the computer to perform any of the memory fault handling methods discussed above. Since the principle by which the above-described computer-readable storage medium solves the problem is similar to that of the memory fault handling methods, the implementation of the above-described computer-readable storage medium can be found in the implementation of the methods, and repeated details will not be elaborated further.
[0139] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0140] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0141] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0142] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0143] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A memory fault handling method, characterized in that, include: In response to the inspection command, the identifier of the memory chip to be tested contained in the inspection command is located to obtain the target address corresponding to the memory chip to be tested; The target inspection scenario of the memory chip under test is determined based on the target address. Different target addresses correspond to different inspection scenarios; Based on the correspondence between multiple inspection scenarios and fault sensitivity, the target fault sensitivity corresponding to the target inspection scenario is determined, and the inspection cycle corresponding to the target inspection scenario is determined based on the target fault sensitivity. The target fault sensitivity is inversely proportional to the inspection cycle; If the memory chip under test is faulty, the fault in the memory chip under test will be handled after the inspection cycle ends.
2. The method according to claim 1, characterized in that, The process of handling faults in the memory chip under test includes: Based on the fault information of the memory chip under test, determine the processing instructions; The processing instruction is sent to the Basic Input / Output System BIOS so that the BIOS can repair the fault in the memory chip under test. Receive the repair time and repair content returned by the BIOS after executing the processing instruction.
3. The method according to claim 2, characterized in that, The step of determining processing instructions based on the fault information of the memory chip under test includes: Display fault information in the memory chip under test and receive processing instructions; the fault information includes at least one of the following: the number of data rows stored in the memory chip under test, the number of faults, and the address corresponding to the row with the most faults.
4. The method according to claim 2, characterized in that, Based on the fault information of the memory chip under test, processing instructions are determined, including: The fault information in the memory chip under test is classified using a trained machine learning model in order to generate processing instructions corresponding to the categories of the fault information. The machine learning model is trained in the following manner: Historical data is categorized into different classes and input into the machine learning model as a training set until the loss value of the machine learning model reaches the target threshold and the loss value is within the target range within a set time period; the historical data includes multiple historical fault information and solutions for each historical error message.
5. The method according to claim 1, characterized in that, After processing the fault in the memory chip under test, the method further includes: Update the total number of failures that occurred during the inspection process of the memory chip under test within a set number of cycles; The state of the memory chip under test is determined based on the total number of tests. Based on the state of the memory chip under test, the wear value of the memory chip under test in different states is determined, and maintenance is performed on the memory chip under test with different wear values.
6. The method according to claim 5, characterized in that, Determining the state of the memory chip under test based on the total number of tests includes: If the total number of tests is less than or equal to the first threshold, then the state of the memory chip under test is determined to be the first state. If the total number of tests is greater than the first threshold and less than or equal to the second threshold, then the state of the memory chip under test is determined to be the second state. If the total number of tests is greater than the second threshold, then the state of the memory chip under test is determined to be the third state. The step of determining the wear value of the memory chip under test in different states based on the state of the memory chip under test includes: The wear value of the memory chip under test in the first state is less than the third threshold; The wear value of the memory chip under test in the second state is greater than the third threshold but less than the fourth threshold; The wear value of the memory chip under test in the third state is greater than the fourth threshold.
7. The method according to claim 6, characterized in that, The maintenance of the memory chips under test for different wear values includes: If the wear value of the memory chip under test is greater than the third threshold but less than the fourth threshold, a frequency reduction request is sent to the BIOS to reduce the operating frequency of the memory chip under test. If the wear value of the memory chip under test is greater than the fourth threshold, the memory chip under test will be deactivated and a prompt will be made to replace the memory chip under test.
8. A memory fault handling device, characterized in that, include: The target inspection scenario determination unit is used to respond to the inspection command, locate the identifier of the memory chip to be tested contained in the inspection command, and obtain the target address corresponding to the memory chip to be tested. The target inspection scenario of the memory chip under test is determined based on the target address. Different target addresses correspond to different inspection scenarios; The inspection cycle determination unit is used to determine the target fault sensitivity corresponding to the target inspection scenario based on the correspondence between multiple inspection scenarios and fault sensitivity, and to determine the inspection cycle corresponding to the target inspection scenario based on the target fault sensitivity. The target fault sensitivity is inversely proportional to the inspection cycle; The memory fault handling unit is used to handle the fault in the memory chip under test after the inspection cycle ends if the memory chip under test has a fault.
9. A baseboard control manager (BMC), characterized in that, include: Memory, used to store program instructions; A processor is configured to invoke program instructions stored in the memory and execute the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a computer, cause the computer to perform the method as described in any one of claims 1 to 7.