Multi-phase clock calibration in receiver

Abstract

The invention relates to multi-phase clock calibration in a receiver. An example calibration circuit for a receiver includes a first circuit coupled to a decision circuit in the receiver. The decision circuit is configured to compare a signal to a reference voltage at a clock-based time. The clocks have different phases. The first circuit is configured to: receive an output of the decision circuit; generating the reference voltage in response to the output, the reference voltage shifted from a center of a data eye at the decision circuit; and generating a control signal based on the comparison of the reference voltages. The calibration circuit includes a second circuit coupled to the first circuit and the decision circuit, the second circuit configured to output the clocks to the decision circuit and apply at least one duty cycle correction to at least one of the clocks in response to the control signal received from the first circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of circuitry, and in particular to multi-phase clock calibration in a receiver. BACKGROUND

[0002] A serializer / deserializer (SerDes) is a circuit that can be used in high-speed communications to compensate for limitations of various media used for data transmission. A pair of SerDes circuits can convert between a serial interface and a parallel interface in both directions. A serial interface can send data, referred to as serial data, sequentially over a single channel. A parallel interface can send data, referred to as parallel data, simultaneously over multiple channels. Serial data can be transmitted between SerDes circuits via a transmission line. A transmission line can be a structure designed to carry electromagnetic waves. The term applies when the structure is long enough that the wave nature of the transmission must be considered. In an exemplary SerDes application, the transmission line can be electrical, optical, or a combination of electrical and optical.

[0003] A SerDes can include both a transmitter and a receiver. The transmitter can serialize data to be transmitted (e.g., convert parallel data to serial data) and couple a signal to a transmission line, referred to as a transmitted signal. The transmitter can encode the serial data in the amplitude of pulses (e.g., voltage pulses, current pulses, or light pulses) of the transmitted signal, which is referred to as pulse amplitude modulation (PAM). The number of discrete pulse amplitudes can be a power of two. For example, in two-level PAM (PAM-2), there are 2 1 (2) possible discrete pulse amplitudes; in four-level PAM (PAM-4), there are 2 2 (4) possible discrete pulse amplitudes; and so on. Each pulse amplitude in PAM can map to a symbol and each symbol can convey log2(N) bits, where N is the number of discrete pulse amplitudes. For example, in PAM-2, there are two symbols each conveying one bit; in PAM-4, there are four symbols each conveying two bits; and so on. PAM-2 modulation is also referred to as non-return-to-zero (NRZ) modulation. Thus, the transmitted signal can include a series of symbols representing the serial data. The transmitter can operate using a clock, the frequency of which determines the rate of the transmitted symbols, referred to as the symbol rate. The inverse of the symbol rate is referred to as the symbol period. In two-level modulation (e.g., PAM-2), since one symbol is one bit, the symbol rate can be referred to as the bit rate and the symbol period can be referred to as the bit period.

[0004] A receiver can measure a signal on a transmission line, referred to as a received signal. The receiver makes decisions on the value of a symbol. For example, the receiver can include a decision circuit that compares the amplitude of the received signal to a reference amplitude at times aligned with the symbol. The decision circuit can output the comparison result as an estimated symbol. The superposition of received signal transients at the decision circuit over a symbol period, also referred to as a unit interval (UI), can be referred to as an eye pattern. A data eye can be a region in the eye pattern that is not crossed by any received signal transient. The maximum width of the data eye can be referred to as the horizontal eye opening, and the maximum height of the data eye can be referred to as the vertical eye opening. The receiver can sample the signal anywhere inside the data eye to minimize symbol error. For robustness, the decision circuit can make the comparison at or near the center of the horizontal eye opening. The receiver can generate or derive a clock used by the decision circuit to control the timing of the comparison. The receiver can use a delay circuit to adjust the phase of the clock to perform the comparison at or near the center of the horizontal eye opening. The receiver can set the reference amplitude of the decision circuit to be at or near the center of the vertical eye opening, e.g., a reference amplitude that is midway between the peak-to-peak amplitude of the received signal.

[0005] A receiver can use a multiphase clock to overcome limitations on the distribution of high-speed clocks having a frequency at the symbol rate. For example, the receiver can use a multiphase clock with four clocks, each one quarter of the symbol rate. The four clocks can be 90 degrees of continuous phase difference, e.g., clock phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. The receiver can include four decision circuits that use the four clocks to compare the signal at four successive comparison times to estimate four successive symbols. However, the multiphase clock should be calibrated before use by the receiver.

[0006] One technique for multiphase clock calibration is to set the reference amplitude of the decision circuit to the center of the vertical eye opening. The receiver can then use a delay circuit for each clock to determine a first delay for the clock aligned with the left edge of the data eye and a second delay for the clock aligned with the right edge of the data eye. The receiver can then determine the average of the delays as the center of the horizontal eye opening. However, this technique is sensitive to the integral nonlinearity (INL) of the delay circuit for the delay of the clock across the data eye. SUMMARY

[0007] In an embodiment, a calibration circuit for a receiver is described. The calibration circuit includes a first circuit coupled to a decision circuit in the receiver. The decision circuit is configured to compare a signal to a reference voltage at times based on clocks having different phases. The first circuit is configured to receive an output of the decision circuit, generate the reference voltage shifted from a center of a data eye at the decision circuit in response to the output, and generate a control signal based on a comparison of the reference voltage. The calibration circuit includes a second circuit coupled to the first circuit and the decision circuit, the second circuit configured to output the clocks to the decision circuit and apply at least one duty cycle correction to at least one of the clocks in response to the control signal received from the first circuit.

[0008] In an embodiment, a receiver is described. The receiver includes a front end coupled to a transmission line to receive a signal. The receiver includes a decision circuit coupled to the front end, where the decision circuit is configured to compare the signal to a reference voltage at times based on clocks having different phases. The receiver includes a first circuit coupled to the decision circuit, the first circuit configured to receive an output of the decision circuit, generate the reference voltage shifted from a center of a data eye at the decision circuit in response to the output, and generate a control signal in response to a comparison of the reference voltage. The receiver includes a second circuit coupled to the first circuit and the decision circuit, the second circuit configured to output the clocks to the decision circuit and apply at least one duty cycle correction to at least one of the clocks in response to the control signal received from the first circuit.

[0009] In an embodiment, a method of calibration in a receiver is described. The method includes receiving a signal, comparing the signal to a reference voltage at times based on clocks having different phases using a decision circuit of the receiver, and receiving an output of the decision circuit. The method further includes generating the reference voltage shifted from a center of a data eye at the decision circuit in response to the output, generating a control signal in response to a comparison of the reference voltage, and applying at least one duty cycle correction to at least one of the clocks in response to the control signal. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram depicting a communication circuit in accordance with some embodiments.

[0011] Figure 2 is a block diagram depicting a transmitter in accordance with some embodiments.

[0012] Figure 3This is a block diagram depicting a clock generator according to some embodiments.

[0013] Figure 4 This is a block diagram depicting a receiver according to some embodiments.

[0014] Figure 5 It is a graphic depicting an eye diagram according to some embodiments.

[0015] Figure 6 It is a signal diagram depicting data and clocks according to some embodiments.

[0016] Figure 7 This is a flowchart depicting a method for aligning the bit periods of a clock and a signal at a decision circuit according to an embodiment.

[0017] Figure 8A It is a block diagram depicting the data recorded by the controller according to an embodiment.

[0018] Figure 8B It is a block diagram depicting the data recorded by the controller according to an embodiment.

[0019] Figure 9 This is a flowchart depicting a method for calibrating a multiphase clock according to an embodiment. Detailed Implementation

[0020] Multi-phase clock calibration in a receiver is described. A multi-phase clock can be a set of clocks having different phases. In some embodiments, the multi-phase clock includes a non-inverted clock, a quadrature clock, a logical inversion of the non-inverted clock, and a logical inversion of the quadrature clock. The receiver can include a calibration circuit to calibrate the multi-phase clock. As used herein, "calibration" can mean adjustment to within a desired accuracy to achieve a particular function. The calibration circuit can adjust the multi-phase clock by manipulating one or more constituent clocks of the multi-phase clock, where such manipulation includes, for example, adjusting the duty cycle of a clock, adjusting the relative phase between pairs of clocks, and delaying a clock. The accuracy of the clock adjustment can be determined by the accuracy of the circuit performing the manipulation (e.g., a delay circuit, a duty cycle correction circuit, etc.). The function achieved by the calibration circuit can be recovering data from a received signal. The calibration circuit can supply the multi-phase clock to a decision circuit in the receiver. In embodiments, the decision circuit compares a voltage of the received signal to a reference voltage at a time determined by a clock in the multi-phase clock. The calibration circuit can adjust the clock so that each decision circuit makes the comparison of the decision circuit at or near the center of a data eye. For each decision circuit, the calibration circuit can adjust its reference voltage until a data eye width is found as a function of a constant time interval, such as a width equal to or approximately equal to twice the constant time interval. The constant time interval can be less than half a UI. This centering technique improves centering accuracy by converting integral non-linear errors into quantization errors compared to the centering process described in the background above. These and other aspects of multi-phase clock calibration according to embodiments are described below with reference to the figures.

[0021] Figure 1 is a block diagram depicting a communication circuit 100 according to some embodiments. The communication circuit 100 includes a SerDes 10 coupled to a SerDes 12 by a transmission line 18. The SerDes 10 includes a digital signal processor (DSP) 14 coupled to a transmitter 16. The SerDes 12 includes a receiver 20 coupled to a DSP 22. A SerDes can be a circuit having a serializer function to convert parallel data into serial data and a deserializer function to convert serial data into parallel data. A DSP can be a circuit that manipulates data that is discrete in time and amplitude, such as values represented by binary codes. A transmitter can be a circuit that transmits data in a signal over a transmission medium. A receiver can be a circuit that observes a signal propagating over a transmission medium. The SerDes 10 can include circuitry for the deserializer function and the SerDes 12 can include circuitry for the serializer function, each of which is omitted for clarity.

[0022] The DSP 14 can supply parallel data to the transmitter 16, where the parallel data can be a plurality of binary code streams carried by a plurality of channels of a parallel interface between the DSP 14 and the transmitter 16. The transmitter 16 can serialize the parallel data into serial data, where the serial data can be a single binary code stream carried by a single channel of a serial interface. The transmitter 16 can couple a signal to the transmission line 18 that encodes the serial data (referred to as a transmitted signal). In an embodiment, the transmitter 16 encodes the serial data in the transmitted signal using PAM-2 modulation (also referred to as NRZ modulation). The transmitted signal can be a signal whose voltage continuously varies over time. The transmitted signal conveys a series of symbols, where the symbols represent bits. The bit rate of the transmitted signal can be determined by a clock in the transmitter 16 (as shown in Figure 2

[0023] The receiver 20 can measure a signal from the transmission line 18 (referred to as a received signal). In an embodiment, the received signal comprises a signal whose voltage continuously varies over time. The receiver 20 can include a decision circuit 24. The decision circuit can be a circuit that compares the voltage of the received signal to a reference voltage at discrete times and outputs discrete results of the comparison. The receiver 20 can supply the received signal to the decision circuit 24 on a signal path 19. The decision circuit 24 can receive a clock on a signal path 21 and a reference voltage on a signal path 23. The decision circuit 24 can compare the voltage of the received signal on the signal path 19 to the reference voltage on the signal path 23 at times determined by the clock on the signal path 21 and output comparison results. In some embodiments, the comparison results include estimated bit decisions (e.g., estimates of bits conveyed by the transmitted signal). The decision circuit 24 can output the estimated bit decisions on a signal path 25. The comparison results can also include estimated differences between the voltage of the received signal and the reference voltage at the times of comparison. The decision circuit 24 can output the estimated differences for the comparisons on a signal path 27. The decision circuit 24 can output the estimated differences as binary codes that represent magnitudes of the differences. The receiver 20 can include various other circuits for processing the estimated bit decisions, the estimated differences, or both, such as equalizers, clock recovery circuits, and so on (not shown). The receiver 20 generates serial data that includes the estimated bit decisions. The receiver 20 can deserialize the serial data into parallel data, which can be coupled to the DSP 22 for further processing.

[0024] ​SerDes 12 includes a clock source 32. A clock source can be a circuit that supplies one or more clock signals. A clock signal, also referred to herein as a clock, can be a logic signal that ideally oscillates between a high logic state and a low logic state at a constant frequency. Clock source 32 can supply two clocks having the same ideal frequency and different phases, referred to as a non-return-to-zero (NRZ) clock and a differential clock. The NRZ clock can be a clock and the differential clock can be a clock having an ideal phase shift of 90 degrees with respect to the NRZ clock (e.g., the NRZ clock and the differential clock are ideally 90 degrees out of phase). Clocks in various embodiments herein can be described as having ideal parameters (e.g., ideal frequency, ideal duty cycle, etc.) and ideal relationships with other clocks (e.g., ideal phase shift). Circuitry in communication circuit 100 can be non-ideal, which can result in clocks having non-ideal parameters, non-ideal relationships, or both (e.g., a clock frequency can differ from an ideal frequency, a phase shift between clocks can differ from an ideal phase shift, etc.).

[0025] In some embodiments, the frequencies of the NRZ clock and the differential clock are ideally set to one quarter of the bit rate of the transmitted signal. In some embodiments, clock source 32 can be a circuit that receives a clock forwarded from SerDes 10, which ideally has a frequency that matches one quarter of the bit rate of the transmitted signal. The forwarded clock can be used as a reference to generate the NRZ clock and the differential clock. In other embodiments, clock source 32 can be a phase-locked loop (PLL) or a similar type of known circuit configured to generate the NRZ clock and the differential clock. In such embodiments, clock source 32 can set its frequency according to a clock recovered from the received signal (e.g., using a clock recovery circuit that derives a clock from the received signal).

[0026] SerDes 12 can include a calibration circuit 15 for calibrating the clock in receiver 20. Calibration circuit 15 can be a circuit that calibrates a multiphase clock used by decision circuit 24. Calibration circuit 15 can receive a multiphase clock from clock source 32, calibrate the multiphase clock based on feedback from decision circuit 24, and supply the calibrated multiphase clock as an output for use by decision circuit 24. In an embodiment, the multiphase clock from clock source 32 is a two-phase clock that includes a non-inverted clock and a quadrature clock. In other embodiments, the multiphase clock from clock source 32 is a four-phase clock that includes a non-inverted clock, a logical inversion of the non-inverted clock, a quadrature clock, and a logical inversion of the quadrature clock. Calibration circuit 15 can supply the calibrated clock as a four-phase clock that includes a non-inverted clock, a logical inversion of the non-inverted clock, a quadrature clock, and a logical inversion of the quadrature clock. Calibration circuit 15 can include a clock generator 26, a reference generator 28, and a controller 30. The clock generator can be a circuit that manipulates an input clock based on a control signal to generate an output clock. The reference generator can be a circuit that manipulates a reference voltage supplied to decision circuit 24 based on a control signal. The controller can be a circuit that generates the control signals in response to input signals.

[0027] Controller 30 can receive the comparison difference on signal path 27 as an input. Controller 30 can supply control signals to clock generator 26 and to reference generator 28 as outputs. Controller 30 can also supply control signals to transmitter 16 on signal path 31 as an output. Clock generator 26 receives clocks from clock source 32, such as a non-inverted clock and a quadrature clock. Clock generator 26 manipulates the clocks received from clock source 32 based on control signals from controller 30. Clock generator 26 manipulates one or more of the input clocks, such as shifting the phase of one input clock relative to another input clock, adjusting the duty cycle of one or more input clocks, applying a delay to one or more input clocks, or any combination of such manipulations. In response to the manipulations of the input clocks, clock generator 26 can output a four-phase clock that includes a non-inverted clock (referred to as CLK 0), a quadrature clock (referred to as CLK 90), a logical inversion of the non-inverted clock (referred to as CLK 180), and a logical inversion of the quadrature clock (referred to as CLK 270). The logical inversion of the non-inverted clock can be a clock that has an ideal 180-degree phase shift relative to the non-inverted clock. The logical inversion of the quadrature clock can be a clock that has an ideal 180-degree phase shift relative to the quadrature clock and thus an ideal 270-degree phase shift relative to the non-inverted clock.

[0028] Reference generator 28 can supply a reference voltage on signal path 23 for decision circuit 24. Reference generator 28 can supply one reference voltage for each phase of the four-phase clock supplied on signal path 21 (e.g., four reference voltages). In response to a control signal from controller 30, reference generator 28 can vary the magnitude of the reference voltages. Controller 30 controls the operation of clock generator 26 and reference generator 28 during clock calibration is discussed below.

[0029] Figure 2 is a block diagram depicting transmitter 16 according to some embodiments. Transmitter 16 includes serializer 34, delay circuit 36, driver 38, and transmitter clock (TX clock 40). A serializer can be a circuit that converts parallel data into serial data. Serializer 34 implements the serializer function of SerDes 10. Serializer 34 can generate serial data as output based on a clock supplied by TX clock 40. The frequency of TX clock 40 controls the bit rate of the transmitted signal. Serializer 34 supplies the serial data to delay circuit 36. A delay circuit can be a circuit that delays a signal in time. The input signal to a delay circuit can be the signal at the input and the output signal of the delay circuit can be the input signal or a delayed version of the input signal. Unless otherwise indicated, the amount of delay of a delay circuit can be variable and selectable based on a control signal (e.g., selectable from a discrete number of delay amounts). Delay circuit 36 can delay the signal carrying the serial data by an amount determined by a control signal on signal path 31 (there can be some delay or no delay). A driver can be a circuit that couples a signal to a transmission line in response to an input. Driver 38 receives the input signal supplied by the output of data delay circuit 36. As discussed above, driver 38 couples the signal to transmission line 18 that encodes the serial data.

[0030] Figure 3 is a block diagram depicting clock generator 26 according to some embodiments. For context, Figure 3The clock generator 26 and the clock source 32 and the controller 30 are shown in FIG. 1. The clock generator 26 can include a delay circuit 46, a duty cycle correction (DCC) circuit 44, an inverter 48, fixed delay circuits 50i...504(collectively, fixed delay circuits 50), and delay circuits 52i...524(collectively, delay circuits 52). In-phase and quadrature clocks from the clock source 32 can be coupled to inputs of the delay circuit 46. The delay circuit 46 can delay one or both of the in-phase and quadrature clocks based on a control signal from the controller 30. Outputs of the delay circuit 46 can supply the in-phase and quadrature clocks to inputs of the DCC circuit 44. The DCC circuit can be a circuit that adjusts a duty cycle of one or more clocks. An input clock of the DCC circuit can be a clock and an output clock of the DCC circuit can be the input clock with an adjusted duty cycle or the input clock without an adjusted duty cycle. Based on a control signal from the controller 30, the DCC 44 can adjust a duty cycle of the in-phase clock, the quadrature clock, both the in-phase and quadrature clocks, or neither the duty cycle of the in-phase clock nor the duty cycle of the quadrature clock. Outputs of the DCC 44 can supply the in-phase and quadrature clocks to inputs of the fixed delay circuits 50iand 502, respectively. The outputs of the DCC 44 can supply the in-phase and quadrature clocks to inputs of the inverter 48. The inverter can be a circuit that inverts a logic signal. An input signal can be a logic signal at an input of the inverter and an output signal can be an inverted version of the input signal. The inverter 48 inverts the in-phase and quadrature clocks to generate an inverted in-phase clock and an inverted quadrature clock, respectively. The inverted in-phase clock is supplied to an input of the fixed delay circuit 503. The inverted quadrature clock is supplied to an input of the fixed delay circuit 504. In other embodiments, the clock source 32 can supply a four-phase clock signal, in which case the delay circuit 46 and the DCC circuit 44 can manipulate the four-phase clock signal and the inverter 48 can be omitted.

[0031] A fixed delay circuit can be a circuit that delays a signal by a fixed amount of time (applies a fixed delay also known as a constant delay). An input signal of a fixed delay circuit can be a signal at an input and an output signal of the fixed delay circuit can be the input signal or a version of the input signal that is delayed by the fixed delay. Fixed delay circuit 501 can receive in-phase clock (CLK 0) as an input and apply a fixed delay or no delay based on a control signal from controller 30. Fixed delay circuit 501 can supply in-phase clock (CLK 0) as an output. Fixed delay circuit 502 can receive quadrature clock (CLK 90) as an input and apply a fixed delay or no delay based on a control signal from controller 30. Fixed delay circuit 502 can supply quadrature clock (CLK 90) as an output. Fixed delay circuit 503 can receive inverted in-phase clock (CLK 180) as an input and apply a fixed delay or no delay based on a control signal from controller 30. Fixed delay circuit 503 can supply inverted in-phase clock (CLK 180) as an output. Fixed delay circuit 504 can receive inverted quadrature clock (CLK 270) as an input and apply a fixed delay or no delay based on a control signal from controller 30. Fixed delay circuit 504 can supply inverted quadrature clock (CLK 270) as an output.

[0032] Variable delay circuit 521 can receive in-phase clock (CLK 0) as an input and apply a variable delay or no delay based on a control signal from controller 30. Variable delay circuit 521 can supply in-phase clock (CLK 0) as an output on signal path 211. Variable delay circuit 522 can receive quadrature clock (CLK 90) as an input and apply a variable delay or no delay based on a control signal from controller 30. Variable delay circuit 522 can supply quadrature clock (CLK 90) as an output on signal path 212. Variable delay circuit 523 can receive inverted in-phase clock (CLK 180) as an input and apply a variable delay or no delay based on a control signal from controller 30. Variable delay circuit 523 can supply inverted in-phase clock (CLK 180) as an output on signal path 213. Variable delay circuit 524 can receive inverted quadrature clock (CLK 270) as an input and apply a variable delay or no delay based on a control signal from controller 30. Variable delay circuit 524 can supply inverted quadrature clock (CLK 270) as an output on signal path 214.

[0033] Figure 4is a block diagram depicting a receiver 20 according to some embodiments. The receiver 20 can include an analog front end 54 and decision circuits 241...244. The analog front end can be a circuit that measures a signal from a transmission medium, the amplitude of which varies continuously over time (e.g., an analog signal). The analog front end 54 can include various circuits such as termination impedance, coupling capacitors, biasing circuits, amplifiers, equalizers, and the like, or any combination thereof. The analog front end 54 supplies a received signal on the signal path 19 as input to the decision circuits 24. The decision circuit 241 can receive a reference voltage (Ref 0) via signal path 231 and an in-phase clock (CLK 0) via signal path 211. The decision circuit 241 can receive the received signal as input and output an estimated bit in a first bit position (bit position 0) on signal path 251 and an estimated difference for the first bit position (difference position 0) on signal path 271. The decision circuit 242 can receive a reference voltage (Ref 1) via signal path 232 and a quadrature clock (CLK 90) via signal path 212. The decision circuit 242 can receive the received signal as input and output an estimated bit in a second bit position (bit position 1) on signal path 252 and an estimated difference for the second bit position (difference position 1) on signal path 272. The decision circuit 243 can receive a reference voltage (Ref 2) via signal path 232 and an inverted in-phase clock (CLK 180) via signal path 213. The decision circuit 243 can receive the received signal as input and output an estimated bit in a third bit position (bit position 2) on signal path 253 and an estimated difference for the third bit position (difference position 2) on signal path 273. The decision circuit 244 can receive a reference voltage (Ref 3) via signal path 233 and an inverted quadrature clock (CLK 270) via signal path 214. The decision circuit 244 can receive the received signal as input and output an estimated bit in a fourth bit position (bit position 3) on signal path 254 and an estimated difference for the fourth bit position (difference position 3) on signal path 274. The receiver 20 can repeatedly multiplex the bit positions 0 through 3 into serial data having a bit rate of the transmitted signal.

[0034] Figure 5is a graph 500 depicting an eye diagram according to some embodiments. Graph 500 includes a horizontal axis representing time and a vertical axis representing voltage. A data eye at the input of a decision circuit can be the superposition of signal transients over a bit period equivalent to a UI. Graph 500 shows a data eye bounded by signal transients 5021 and 5022 of a received signal. The data eye includes a vertical eye opening 506 and a horizontal eye opening 504. Depending on the context, the center of the data eye can refer to the center of the horizontal eye opening 504, the center of the vertical eye opening 506, or the intersection of the horizontal eye opening 504 and the vertical eye opening 506. For example, in the context of adjusting a clock, the center of the data eye can be the center of the horizontal eye opening 504. In the context of adjusting a reference voltage, the center of the data eye can be the center of the vertical eye opening 506.

[0035] Figure 6 is a signal graph 600 depicting data and clocks according to some embodiments. Signal graph 600 shows bit positions 6021, 6022, 6023, and 6024 of a received signal (referred to as “data”) in receiver 20. To robustness in estimating bits, calibration circuit 15 can manipulate an in-phase clock (CLK 0) to cause decision circuit 241 to perform the decision circuit’s comparison at or near the center of bit position 6021. Calibration circuit 15 can manipulate a quadrature clock (CLK 90) to cause decision circuit 242 to perform the decision circuit’s comparison at or near the center of bit position 6022. Calibration circuit 15 can manipulate an inverted in-phase clock (CLK 180) to cause decision circuit 243 to perform the decision circuit’s comparison at or near the center of bit position 6023. Calibration circuit 15 can manipulate an inverted quadrature clock (CLK 270) to cause decision circuit 244 to perform the decision circuit’s comparison at or near the center of bit position 6024.

[0036] Figure 7 is a flowchart of a method 700 of aligning clocks with bit periods of a signal at a decision circuit according to embodiments. Method 700 can be used in the clock calibration methods described below with respect to Figure 9 For purposes of example clarity, method 700 is described with respect to aligning an in-phase clock with a first bit period. However, method 700 can be performed for each clock of the multiphase clocks supplied to decision circuit 24 for each of the four bit periods.

[0037] Method 700 begins at step 702, where controller 30 can perform left edge detection by sweeping a reference voltage (Ref 0) supplied to decision circuit 241. Controller 30 can control reference generator 28 to iterate through a range of reference voltages, for example from an initial voltage at the center of the data eye toward the top or bottom of the data eye (e.g., starting from the center of the data eye and moving toward the top of the data eye as in FIG. 5A, or starting from the center of the data eye and moving toward the bottom of the data eye as in FIG. 5B). Controller 30 can control reference generator 28 to sweep the reference voltage at a rate of, for example, 1 volt per second. Figure 5The controller 30 can control the clock generator 26 to adjust the delay of the clock supplied to the decision circuit and observe the comparison difference output from the decision circuit for each reference voltage in the scan. In an example, the controller 30 can control the clock generator 26 to adjust the delay of the non-inverted clock (CLK 1) supplied to the decision circuit 241 and observe the comparison difference on the signal path 272 (difference position 1). The controller 30 can adjust the delay of the non-inverted clock by controlling the delay applied by the delay circuit 512. In step 702, the fixed delay circuit 502 does not apply a fixed delay to the non-inverted clock. In step 704, for each reference voltage in the scan, the controller 30 can record the delay value applied by the delay circuit 512 that results in detection of the right edge of the data eye. The controller 30 can determine detection of the right edge by observing a minimum value of the comparison difference.

[0038] At step 706, the controller 30 can remove the constant delay from the clock (e.g., the non-inverted clock in this example). In an embodiment, the constant delay is equivalent to a constant time interval that is less than half of the UI (e.g., less than half of the bit period). This is shown in Figure 5 as the time interval 516, which is less than half of the horizontal eye opening 504. In an example, the controller 30 can control the fixed delay circuit 502 to apply a fixed delay to the non-inverted clock (CLK 1), where the fixed delay is equal to the constant delay. At step 708, the controller 30 can delay the data by the constant delay. The controller 30 can control the delay circuit 36 in the transmitter 16 via the signal path 31 to apply the constant delay (e.g., the same fixed delay applied by the fixed delay circuit 502). At this point, the controller 30 again detects the right edge of the data eye.

[0039] At step 710, the controller 30 can remove the constant delay from the clock and perform another scan of the reference voltages. For example, the controller 30 can control the fixed delay circuit 502 to not apply a fixed delay and then can control the reference generator 28 to iterate through the range of reference voltages. At step 712, for each reference voltage in the scan, the controller 30 can: (1) load the delay value recorded in step 704 (e.g., set the delay circuit 522 with the delay value determined in step 704); (2) adjust the delay of the clock until detection of the right edge of the data eye (e.g., by controlling the delay circuit 522 and observing the comparison difference from the decision circuit 241); and (3) record the updated delay value of the clock (e.g., record the delay value applied by the delay circuit 522).

[0040] At step 714, controller 30 can remove the constant delay from the data. Controller 30 can control delay circuit 36 in transmitter 16 through signal path 31 to remove the constant delay. At step 716, controller 30 can delay the clock by the constant delay (e.g., the in-phase clock in this example). In an example, controller 30 can control fixed delay circuit 501 to impose a fixed delay on the in-phase clock (CLK 0).

[0041] At step 718, controller 30 can perform another sweep of the reference voltage. For example, controller 30 can control reference generator 28 to iterate through a range of reference voltages. At step 720, for each reference voltage in the sweep, controller 30 can: (1) load the delay value recorded in step 712 (e.g., set delay circuit 521 with the delay value determined in step 712); and (2) determine whether a right edge is detected (e.g., by observing the comparison difference from decision circuit 241). If a right edge is detected in an iteration of the reference voltage sweep, controller 30 can record the current delay value (e.g., the current delay value imposed by delay circuit 521) and the reference voltage value (e.g., the current reference voltage supplied to decision circuit 241). The delay value recorded at step 720 aligns the clock at or near the center of the data eye. The reference voltage value recorded at step 720 is shifted from the center of the data eye at the decision circuit. As Figure 5 As shown in FIG. 8, at the reference voltage 508 recorded at step 720, the width 514 of the data eye is equal to or close to twice the constant delay represented by time interval 516. Thus, the delay value recorded at step 720 is determined by adjusting the reference voltage, which improves the centering accuracy and is affected by the quantization error of the reference voltage rather than the INL of the delay circuit.

[0042] Figure 8A is a block diagram depicting data 800 recorded by controller 30 according to an embodiment. Controller 30 can include memory circuitry for recording data 800. Data 800 can include a delay value recorded for each of the clocks of the multi-phase clock (e.g., delay CLK 0, delay CLK 90, delay CLK 180, and delay CLK 270). For each of the clocks, a delay value is recorded for each of the reference voltage values in the reference voltage sweep. Controller 30 can generate data 800 for each clock in step 704 and update data 800 for each clock in step 712.

[0043] Figure 8Bis a block diagram depicting data 801 recorded by controller 30 according to embodiments. Controller 30 can include memory circuitry for recording data 801. Data 801 can include a pair of delay values and reference voltage values for each of the clocks. Controller 30 can record data 801 for each of the clocks at step 720. The delay values in data 801 can be the delay values that align the clock with the center of the data eye (e.g., delay 0 for bit period 0; delay 1 for bit period 1; delay 2 for bit period 2; and delay 3 for bit period 3). The reference voltage values recorded in data 801 can be used in the clock calibration method described below in Figure 9 .

[0044] Figure 9 is a flowchart depicting a method 900 of calibrating a multi-phase clock according to embodiments. In embodiments, the multi-phase clock is the four-phase clock discussed above that is supplied to decision circuit 24 in receiver 20. Method 900 can be performed by controller 30 of calibration circuit 15. Method 900 begins at step 902, where controller 30 can center each of the clocks in its respective data eye using method 700 for each clock. This causes controller 30 to record data 801 shown in Figure 8B , in particular, reference voltage values RV 0, RV 1, RV 2, and RV 3. At step 904, controller 30 can determine whether reference voltage values RV 0, RV 1, RV 2, and RV 3 are equal or approximately equal. If so, method 900 continues to step 906, where controller 30 can exit the multi-phase clock calibration. Otherwise, method 900 continues from step 904 to step 908.

[0045] At step 908, controller 30 can compare the reference voltage values determined in step 902, where the comparison can be RV 0 + RV 1 > RV 2 + RV 3. At step 910, if the comparison at step 908 is true, this indicates that the duty cycle of the in-phase clock (CLK 0) and the inverse of the in-phase clock (CLK 180) is less than 50%. Thus, if the comparison at step 908 is true, method 900 continues to step 912, where controller 30 can increase the duty cycle of the in-phase clock (e.g., by controlling DCC 44). If at step 908, the comparison is false, method 900 continues to step 914, where controller 30 can decrease the duty cycle of the in-phase clock (e.g., by controlling DCC 44). Method 900 continues from step 912 or 914 to step 916.

[0046] At step 916, the controller 30 can make another comparison of the reference voltage values determined in step 902, where the comparison can be RV 1 + RV 2 > RV 0 + RV 3. At step 918, if the comparison at step 916 is true, this indicates that the duty cycle of the quadrature clock (CLK 90) and the inverse of the quadrature clock (CLK 270) is less than 50%. Thus, if the comparison at step 918 is true, the method 900 continues to step 920, where the controller 30 can increase the duty cycle of the quadrature clock (e.g., by controlling the DCC 44). If at step 918, the comparison is false, the method 900 continues to step 922, where the controller 30 can decrease the duty cycle of the quadrature clock (e.g., by controlling the DCC 44). The method 900 continues from step 920 or 922 to step 924.

[0047] At step 924, the controller 30 can make another comparison of the reference voltage values determined in step 902, where the comparison can be RV 0 + RV 2 > RV 1 + RV 3. At step 926, if the comparison at step 924 is true, this indicates that the duty cycle of the "exclusive or" of the in-phase clock and the quadrature clock is less than 50%. Thus, if the comparison at step 926 is true, the method 900 continues to step 928, where the controller 30 can increase the delay between the in-phase clock and the quadrature clock (e.g., by controlling the delay circuit 46). If at step 926, the comparison is false, the method 900 continues to step 930, where the controller 30 can decrease the delay between the in-phase clock and the quadrature clock (e.g., by controlling the delay circuit 46). The method 900 continues from step 930 or step 928 back to step 902.

[0048] Although certain processes and methods have been described with respect to various implementing operations, one or more embodiments also concern apparatuses or devices for performing the operations. The apparatuses can be specially constructed for the required purposes, or they can be a general purpose computer selectively activated or configured by a computer program stored in the computer. Various general purpose machines can be used with computer programs written in accordance with the teachings herein, or it can be more convenient to construct a more specialized apparatus to perform the required operations.

[0049] While one or more embodiments of the application have been described with respect to specific details, it is to be understood that certain changes and modifications can be made within the scope of the claims. Therefore, the described embodiments are to be considered as illustrative and not restrictive, and the scope of the claims to be not limited to the details given herein but can be modified within the scope and equivalents of the claims. In the claims, means-plus-function clauses are used where functionally equivalent devices are described for an equivalent purpose. It is to be understood that, unless otherwise explicitly provided, singular terms shall include pluralities and plural terms shall include the singular.

[0050] The boundaries of the components, operations, and data stores are somewhat arbitrary, and particular operations are shown as being performed by a particular instructional configuration. Other allocations of functionality are envisioned and can fall within the scope of the inventive subject matter. In general, the inventive subject matter can be implemented as a system, method, article of manufacture, or any combination thereof. For example, a computer program product can include a computer readable medium having computer readable program code portions stored therein, which can be executed by a computer processor.

Claims

1. A calibration circuit for a receiver, comprising: A first circuit, coupled to a decision circuit in the receiver, the decision circuit being configured to compare a signal with a reference voltage at clock-based times, the clock having a different phase, the first circuit being configured to: Receive the output of the decision circuit; In response to the output, the reference voltage is generated, which is shifted from the center of the data eye at the decision circuit; and A control signal is generated based on the comparison with the reference voltage; as well as A second circuit, coupled to the first circuit and the decision circuit, is configured to output the clock to the decision circuit in response to the control signal received from the first circuit and to apply at least one duty cycle correction to at least one of the clocks.

2. The calibration circuit of claim 1, wherein the first circuit is configured to set the reference voltage such that the width of each of the data eyes under the reference voltage is a constant time interval less than the unit interval UI of the signal.

3. The calibration circuit of claim 1, wherein the clock comprises a first clock, a second clock, a third clock, and a fourth clock having a first phase, a second phase, a third phase, and a fourth phase, respectively, and wherein the reference voltage comprises a first offset, a second offset, a third offset, and a fourth offset, and the decision circuit is configured to compare the signal with the first offset, the second offset, the third offset, and the fourth offset at times based on the first clock, the second clock, the third clock, and the fourth clock, respectively.

4. The calibration circuit of claim 3, wherein the comparison comprises: a first comparison of the sum of the first offset and the second offset with the sum of the third offset and the fourth offset; and a second comparison of the sum of the second offset and the third offset with the sum of the first offset and the fourth offset.

5. The calibration circuit of claim 4, wherein the second circuit is configured to apply a first duty cycle correction to the first clock based on the first comparison, and to apply a second duty cycle correction to the second clock based on the second comparison.

6. The calibration circuit of claim 3, wherein the comparison includes a first comparison of the sum of the first offset and the third offset with the sum of the second offset and the fourth offset, and wherein the second circuit is configured to adjust the delay between the first clock and the second clock based on the first comparison.

7. The calibration circuit according to claim 3, wherein the first clock is an in-phase clock, the second clock is a quadrature clock, the third clock is the logical inverse of the in-phase clock, and the fourth clock is the logical inverse of the quadrature clock.

8. The calibration circuit of claim 1, wherein the second circuit is configured to apply a delay to the clock, and wherein the first circuit is configured to set the reference voltage by adjusting the delay.

9. The calibration circuit of claim 8, wherein the first circuit is configured to set the delay such that the time at which the decision circuit compares the signal with the reference voltage occurs within the data eye.

10. The calibration circuit of claim 8, wherein the second circuit is configured to control the transmitter to apply a delay to the signal, and wherein the first circuit is further configured to set the reference voltage by adjusting the delay of the signal at the transmitter.

11. A receiver comprising: The front end, which is coupled to the transmission line to receive signals; A decision circuit coupled to the front end, the decision circuit being configured to compare the signal with a reference voltage at times based on clocks having different phases; A first circuit, coupled to the decision circuit, is configured to: Receive the output of the decision circuit; In response to the output, the reference voltage is generated, which is shifted from the center of the data eye at the decision circuit; and A control signal is generated in response to a comparison with the reference voltage; as well as A second circuit, coupled to the first circuit and the decision circuit, is configured to output the clock to the decision circuit in response to the control signal received from the first circuit and to apply at least one duty cycle correction to at least one of the clocks.

12. The receiver of claim 11, wherein the clock comprises an in-phase clock, a quadrature clock, a logically inverted in-phase clock, and a logically inverted quadrature clock.

13. The receiver of claim 12, wherein the reference voltage comprises a first offset, a second offset, a third offset, and a fourth offset, and wherein the decision circuitry is configured to compare the signal with the first offset, the second offset, the third offset, and the fourth offset at times based on the in-phase clock, the quadrature clock, the logical inversion of the in-phase clock, and the logical inversion of the quadrature clock, respectively.

14. The receiver of claim 13, wherein the comparison comprises: a first comparison of the sum of the first offset and the second offset with the sum of the third offset and the fourth offset; and a second comparison of the sum of the second offset and the third offset with the sum of the first offset and the fourth offset.

15. The receiver of claim 14, wherein the second circuitry is configured to apply a first duty cycle correction to the in-phase clock based on the first comparison, and to apply a second duty cycle correction to the quadrature clock based on the second comparison.

16. A method for calibration in a receiver, comprising: Receive signal; The decision circuitry of the receiver compares the signal with a reference voltage at times based on clocks with different phases. Receive the output of the decision circuit; In response to the output, the reference voltage is generated, which is shifted from the center of the data eye at the decision circuit; A control signal is generated in response to a comparison with the reference voltage; and In response to the control signal, at least one duty cycle correction is applied to at least one of the clocks.

17. The method of claim 16, wherein the clock comprises a non-inverting clock, a quadrature clock, a logically inverted non-inverting clock, and a logically inverted quadrature clock.

18. The method of claim 17, wherein the reference voltage comprises a first offset, a second offset, a third offset, and a fourth offset, and wherein the decision circuit is configured to compare the signal with the first offset, the second offset, the third offset, and the fourth offset at times based on the in-phase clock, the quadrature clock, the logical inversion of the in-phase clock, and the logical inversion of the quadrature clock, respectively.

19. The method of claim 18, wherein the step of generating the control signal comprises: In the first comparison, the sum of the first offset and the second offset is compared with the sum of the third offset and the fourth offset; and In the second comparison, the sum of the second offset and the third offset is compared with the sum of the first offset and the fourth offset.

20. The method of claim 19, wherein the step of applying the at least one work cycle correction comprises: The first working cycle correction is applied to the in-phase clock based on the first comparison; and The second working cycle correction is applied to the quadrature clock based on the second comparison.

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