Time sequence monitoring circuit

Abstract

The invention relates to the technical field of power electronic devices, in particular to a time sequence monitoring circuit, which forms a closed feedback loop through a first circulating unit, a second circulating unit and a circulating control unit, and configures a delay mismatch time interval on a signal transmission path of a first initial signal to be detected and / or a second initial signal to be detected, so that the time sequence monitoring circuit can monitor the time sequence. The time difference between the first initial to-be-measured signal and the second initial to-be-measured signal is cyclically attenuated, the circuit structure is greatly simplified, the consumption of space resources and power consumption resources of a chip is reduced, the time difference between the first initial to-be-measured signal and the second initial to-be-measured signal is amplified through the phase comparison unit and the output unit, and the time difference between the first initial to-be-measured signal and the second initial to-be-measured signal is reduced. In addition, the time sequence monitoring circuit can be directly applied to scenes needing analog signals, and the technical problems that an existing time sequence monitoring circuit is large in chip resource consumption, limited in gain and limited in application scenes are solved. And a timeout protection and reset mechanism is constructed, so that the robustness of the circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, in particular to a timing monitoring circuit. BACKGROUND

[0002] With the semiconductor process entering deep submicron and even nanometer level, the integration and working frequency of chips are rapidly increasing. High frequency means that the available transmission time window of the signal in a clock cycle is extremely compressed, which makes the requirement of the circuit on timing more and more stringent. Process deviation, voltage fluctuation and temperature change (i.e. PVT variation) will cause unpredictable drift of signal delay, which may erode or even exhaust the timing margin of the design, cause setup time or hold time violation, and finally cause chip function error. Therefore, it is crucial to monitor the timing margin of the critical path on the chip in real time and accurately to ensure the yield and reliability of high-performance chips. This timing online monitoring scheme can be used in chip factory test, system dynamic frequency adjustment and aging state early warning scenes, and achieve the purpose of chip life precision management.

[0003] However, in order to realize high precision and wide measurement range, the existing timing monitoring circuit usually needs to use a large number of delay unit arrays and decision maker arrays, which has a complex and large structure, needs to occupy more chip area and consume more power consumption, and has limited gain. Moreover, the timing information output by the existing timing monitoring circuit is difficult to be directly applied to the application scene of analog signal, and there is a problem of limited application scene. SUMMARY

[0004] The present application provides a timing monitoring circuit, which solves the technical problems of large chip resource consumption, limited gain and limited application scene of the existing timing monitoring circuit.

[0005] The present application provides a timing monitoring circuit, comprising: a first loop unit, a second loop unit, a loop control unit, a phase comparison unit and an output unit.

[0006] The first input end of the first loop unit is used for receiving a first initial to-be-measured signal; the output end of the first loop unit is connected with the second input end of the first loop unit and the first input end of the phase comparison unit respectively, and is used for outputting a first internal loop signal;

[0007] The first input end of the second loop unit is used for receiving a second initial to-be-measured signal; the output end of the second loop unit is connected with the second input end of the second loop unit and the second input end of the phase comparison unit respectively, and is used for outputting a second internal loop signal;

[0008] The input end of the cycle control unit is configured to receive the first initial test signal and the second initial test signal respectively, and the output end of the cycle control unit is connected to the controlled end of the first cycle unit and the second cycle unit respectively, and is configured to control the first cycle unit to select the first internal cycle signal when detecting a rising edge or a falling edge of the first initial test signal, and control the second cycle unit to select the second internal cycle signal when detecting a rising edge of the second initial test signal.

[0009] The output end of the phase comparison unit is connected to the input end of the output unit, and is configured to detect and control the output unit to output a pulse signal according to the time difference between the first internal cycle signal and the second internal cycle signal.

[0010] The signal transmission path formed by the timing monitoring circuit is configured with a delay mismatch time interval, and the delay mismatch time interval is configured to cause the first initial test signal and the second initial test signal to produce transmission delay, and cause the first internal cycle signal and the second internal cycle signal to produce transmission delay.

[0011] Optionally, the first cycle unit comprises a first signal selector and a first pulse generator.

[0012] The first input end of the first signal selector is configured to receive the first initial test signal.

[0013] The controlled end of the first signal selector is connected to the output end of the cycle control unit.

[0014] The output end of the first signal selector is connected to the input end of the first pulse generator.

[0015] The output end of the first pulse generator is connected to the second input end of the first signal selector and the first input end of the phase comparison unit respectively.

[0016] Optionally, the second cycle unit comprises a second signal selector and a second pulse signal generator.

[0017] The first input end of the second signal selector is configured to receive the second initial test signal.

[0018] The controlled end of the second signal selector is connected to the output end of the cycle control unit.

[0019] The output end of the second signal selector is connected to the input end of the second pulse generator.

[0020] An output terminal of the second pulse generator is connected with a second input terminal of the second signal selector and a second input terminal of the phase comparison unit respectively.

[0021] Optionally, the cycle control unit comprises a first D flip-flop, a second D flip-flop and an edge detection circuit.

[0022] An input terminal of the edge detection circuit is used for receiving the first initial test signal.

[0023] An output terminal of the edge detection circuit is connected with a clock terminal of the first D flip-flop.

[0024] An output terminal of the first D flip-flop is connected with a control terminal of the first signal selector.

[0025] A clock terminal of the second D flip-flop is used for receiving the second initial test signal.

[0026] An output terminal of the second D flip-flop is connected with a control terminal of the second signal selector.

[0027] Data terminals of the first D flip-flop and the second D flip-flop are used for receiving a power voltage signal.

[0028] Optionally, the phase comparison unit comprises a timing detection subunit and a first logic gate circuit, and the output unit comprises a third D flip-flop.

[0029] Input terminals of the timing detection subunit are used for receiving the first initial test signal and the second initial test signal respectively.

[0030] An output terminal of the timing detection subunit is connected with a data terminal of the third D flip-flop, and is used for outputting a target pulse signal to the third D flip-flop when it is detected that a time difference between the first initial test signal and the second initial test signal is not less than a preset time threshold.

[0031] Input terminals of the first logic gate circuit are used for receiving the first initial test signal and the second initial test signal respectively.

[0032] An output terminal of the first logic gate circuit is connected with a clock terminal of the third D flip-flop, and is used for outputting a trigger signal to the third D flip-flop when it is detected that the first initial test signal and the second initial test signal are in a target state.

[0033] Optionally, the edge detection circuit comprises a first buffer, a second buffer and a first XOR gate.

[0034] an input end of the first buffer and a first input end of the first XOR gate are connected to receive the first initial test signal;

[0035] an output end of the first buffer is connected to an input end of the second buffer, and an output end of the second buffer is connected to a second input end of the first XOR gate;

[0036] an output end of the first XOR gate is connected to a clock end of the first D flip-flop.

[0037] Optionally, the circuit further comprises a reset unit and an external reset control unit.

[0038] an input end of the reset unit is connected to the output unit and the external reset control unit, and the reset unit is connected to a reset end of the cycle control unit, for receiving and detecting an output signal of the pulse unit output by the output unit, and receiving an external reset pulse of the external reset control unit, and outputting a reset signal to the cycle control unit when detecting a falling edge of the pulse signal or receiving the external reset pulse of the external reset control unit.

[0039] Optionally, the reset unit comprises a falling edge detector and a reset AND gate.

[0040] an input end of the falling edge detector is connected to the output unit, and an output end of the falling edge detector is connected to an input end of the reset AND gate.

[0041] another input end of the reset AND gate is connected to the external reset control unit, and an output end of the reset AND gate is connected to the cycle control unit.

[0042] Optionally, the circuit further comprises a timeout counter and a logic gate circuit.

[0043] an input end of the timeout counter is connected to an output end of the first cycle unit, an output end of the second cycle unit, and an output end of the output unit respectively, and an output end of the timeout counter is connected to an input end of the logic gate circuit, for generating a count clock according to the cycle times of the first internal cycle signal and the second internal cycle signal when there is no falling edge of the pulse signal, and outputting a falling edge signal to the logic gate circuit when the count clock reaches a preset time threshold.

[0044] another input end of the logic gate circuit is connected to an output end of the output unit, and an output end of the logic gate circuit is connected to an input end of the falling edge detector, for transmitting the falling edge signal output by the timeout counter and / or the pulse signal to the falling edge detector.

[0045] Optionally, the falling edge detector comprises a third buffer, a first NOT gate and a first OR gate.

[0046] An input end of the third buffer is connected with an input end of the OR gate as an input end of the falling edge detector.

[0047] An output end of the third buffer is connected with an input end of the first NOT gate, an output end of the first NOT gate is connected with another input end of the OR gate, and an output end of the OR gate is an output end of the falling edge detector.

[0048] From the above technical solutions, the present application has the following advantages:

[0049] The present application provides a timing monitoring circuit, comprising: a first loop unit, a second loop unit, a loop control unit, a phase comparison unit, an output unit; a first input end of the first loop unit is used for receiving a first initial to-be-tested signal; an output end of the first loop unit is connected with a second input end of the first loop unit and a first input end of the phase comparison unit respectively, and is used for outputting a first internal loop signal; a first input end of the second loop unit is used for receiving a second initial to-be-tested signal; an output end of the second loop unit is connected with a second input end of the second loop unit and a second input end of the phase comparison unit respectively, and is used for outputting a second internal loop signal; an input end of the loop control unit is used for receiving the first initial to-be-tested signal and the second initial to-be-tested signal respectively, and an output end of the loop control unit is connected with controlled ends of the first loop unit and the second loop unit respectively, and is used for controlling the first loop unit to select the first internal loop signal when a rising edge or a falling edge of the first initial to-be-tested signal is detected, and controlling the second loop unit to select the second internal loop signal when a rising edge of the second initial to-be-tested signal is detected; an output end of the phase comparison unit is connected with an input end of the output unit, and is used for detecting and controlling the output unit to output a pulse signal according to a time difference between the first internal loop signal and the second internal loop signal; a delay mismatch time interval is configured on a signal transmission path formed by the timing monitoring circuit, and the delay mismatch time interval is used for causing the first initial to-be-tested signal and the second initial to-be-tested signal to produce transmission delay, and causing the first internal loop signal and the second internal loop signal to produce transmission delay.

[0050] Therefore, the timing monitoring circuit provided by the present application forms a closed feedback loop through the first loop unit, the second loop unit and the loop control unit, configures a delay mismatch time interval on the signal transmission path, causes the first initial to-be-tested signal and the second initial to-be-tested signal to generate transmission delay, and causes the first internal loop signal corresponding to the first initial to-be-tested signal and the second internal loop signal corresponding to the second initial to-be-tested signal to generate transmission delay in each loop, so as to attenuate the time difference between the first initial to-be-tested signal and the second initial to-be-tested signal based on the fixed delay mismatch time interval, to realize monitoring of the time difference between the first initial to-be-tested signal and the second initial to-be-tested signal, without a large number of delay unit arrays and decision maker arrays, greatly simplifying the circuit structure, reducing the consumption of space resources and power consumption resources of the chip, avoiding the case that the existing timing monitoring circuit consumes large chip resources, and realizing amplification of the time difference between the first initial to-be-tested signal and the second initial to-be-tested signal in the time dimension through the phase comparison unit and the output unit, improving the signal gain, and the output pulse signal can be directly applied to a scene requiring an analog signal, avoiding the case that the existing timing monitoring circuit is limited in gain and application scene. Therefore, the timing monitoring circuit provided by the present application solves the technical problems of large chip resource consumption, limited gain and limited application scene of the existing timing monitoring circuit. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0052] Figure 1 A structural schematic diagram of a vernier delay chain TDC;

[0053] Figure 2 A structural schematic diagram of a timing monitoring circuit provided by an embodiment of the present application;

[0054] Figure 3 A structural schematic diagram of a timing monitoring circuit provided by an embodiment of the present application;

[0055] Figure 4 A structural schematic diagram of a timing monitoring circuit provided by an embodiment of the present application;

[0056] Figure 5 A structural schematic diagram of a timing monitoring circuit provided by an embodiment of the present application;

[0057] Figure 6The structural schematic diagram of the cycle control unit provided for the embodiment of the present application is shown in the figure;

[0058] Figure 7 The structural schematic diagram of the timeout counter, reset unit and logic gate circuit provided for the embodiment of the present application is shown in the figure;

[0059] Figure 8 The structural schematic diagram of the pulse shaping circuit provided for the embodiment of the present application is shown in the figure;

[0060] Figure 9 The signal timing diagram under normal operation provided for the embodiment of the present application is shown in the figure;

[0061] Figure 10 The simulation waveform schematic diagram of the input and output of the timing monitoring circuit provided for the embodiment of the present application is shown in the figure;

[0062] Figure 11 The timeout reset timing diagram provided for the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0063] The professional terms involved in the present application will be explained below.

[0064] Timing Margin: In digital circuits, the difference between the actual arrival time of a signal and the last required arrival time of the clock, which is a key indicator of the timing robustness of the system.

[0065] TDC (Time-to-Digital Converter): Time-to-Digital Converter, a circuit that converts the time interval between two events into a digital value.

[0066] Setup Time: The minimum period of time during which a data input signal must remain stable before the arrival of a clock active edge (usually a rising edge) to ensure that the data is correctly latched.

[0067] SR Latch: A basic storage unit controlled by set and reset inputs, capable of latching states.

[0068] IR Drop: The voltage drop produced when current flows through a power supply or ground network with resistance, which is an important factor affecting the performance and stability of the chip.

[0069] Parasitic Parameters: Additional capacitance, resistance and inductance parameters that are not intentionally constructed by the designer but are inevitably produced due to the physical implementation of integrated circuits, such as wire capacitance and transistor input capacitance.

[0070] PVT (Process, Voltage, and Temperature): refers to the three external factors of process, voltage and temperature that affect the performance of a semiconductor chip.

[0071] MUX (Multiplexer): a kind of logic circuit that can select one of multiple input signals as output.

[0072] Monostable Circuit: a circuit that can generate a fixed-width pulse after receiving a trigger signal.

[0073] Currently, one of the commonly used circuits for measuring micro time difference is the TDC based on vernier delay chain, whose core principle is similar to vernier caliper. A typical vernier delay line TDC (VDL-TDC) based on vernier delay chain is shown in Figure 1 , which includes two parallel delay chains (Delay Line) respectively composed of multiple first and last connected delay units (such as inverters). One of them is the "slow" delay chain, and the delay of each unit is ; the other is the "fast" delay chain, and the delay of each unit is , and is slightly less than (e.g. ). , which is the measurement resolution of the TDC.

[0074] The two signals to be measured, for example: data and cp, are input to the two delay chains at the same time. At each stage of the two delay chains, an arbiter is placed. The arbiter can be an SR latch or a D flip-flop. Taking the D flip-flop as an example, the output of the data signal propagation path is connected to the data terminal D of the D flip-flop, and the output of the cp signal propagation path is connected to the clock terminal CLK.

[0075] Initially, if the data signal leads the cp signal by a time difference Tin, then at the beginning of the propagation, all D flip-flops will be latched to high level. Since the cp signal propagates in the "fast" chain, it will gradually catch up with the data signal. Every time a level is passed, cp will catch up with data by time. When it propagates to the Nth level, the arrival time of the cp signal first reverses the data signal, causing the output of the Nth D flip-flop to first become low. By detecting the position N of this "0-1" flip, the initial time difference can be calculated.

[0076] However, the time-to-digital converter has the following disadvantages:

[0077] 1. Large area and power consumption overhead. In order to obtain a higher measurement range and accuracy, the delay chain needs to contain a large number of delay units and decision makers, which requires a considerable area on the chip. At the same time, these units will produce a non-negligible static and dynamic power consumption, so a large amount of space resources and power consumption resources of the chip need to be consumed.

[0078] 2. Resolution and stability are difficult to balance. The resolution of the circuit is determined by the small delay difference of two delay units. It is very difficult to accurately control this small delay under advanced process, and it is very sensitive to PVT variation. In order to stabilize, complex calibration circuit is often introduced, which further increases the complexity and cost of circuit design.

[0079] 3. Gain is limited. The amplification of the time-to-digital converter is related to the driving ability of the inverter and the process, depends on the mismatch between devices (such as inverters, buffers), and is limited by the delay difference of two inverters. However, under a certain semiconductor process, the minimum delay difference that can be stably and reliably designed has a physical and process limit. This basic limitation leads to the fundamental restriction of the inherent amplification of VDL, and it is difficult to achieve higher gain by simply reducing the design difference.

[0080] 4. Application scenario is limited. The output of VDL-TDC is a "thermometer code", which needs to be further encoded into binary code to be used by digital system, that is, it is essentially to convert time difference into a digital code, not directly amplify time signal. For some application scenarios that require analog signal or wide pulse, supporting conversion circuit is needed to support. Therefore, the time-to-digital converter is difficult to directly support application scenarios that require to utilize amplified time signal, and there is a limited application scenario. Moreover, using the supporting conversion circuit for signal conversion further increases the construction cost of the circuit and the occupation of space resources.

[0081] In order to solve the defects of the prior art, the embodiment of the present application provides a timing monitoring circuit, which can directly amplify the small time difference of picosecond (ps) or even femtosecond (fs) level into nanosecond (ns) level pulse width, realizing time gain of hundreds of times; and has compact structure and low power consumption, avoiding using long delay chain structure; and skillfully utilizes inherent parasitic parameters of the circuit to realize the mechanism of reducing stable time difference, thereby simplifying the design and improving the robustness to process deviation; and contains complete timeout protection mechanism, ensuring that the circuit can work reliably and can be automatically reset under various input conditions. ​

[0082] In order to make the application purposes, features and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the following described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0083] Please refer to Figure 2 , Figure 2 The timing monitoring circuit provided by the embodiments of the present application comprises a first loop unit 1, a second loop unit 2, a loop control unit 3, a phase comparison unit 4 and an output unit 5.

[0084] The first input end of the first loop unit 1 is configured to receive a first initial to-be-detected signal. The output end of the first loop unit 1 is connected with the second input end of the first loop unit 1 and the first input end of the phase comparison unit 4 respectively, and is configured to output a first internal loop signal. The first input end of the second loop unit 2 is configured to receive a second initial to-be-detected signal. The output end of the second loop unit 2 is connected with the second input end of the second loop unit 2 and the second input end of the phase comparison unit 4 respectively, and is configured to output a second internal loop signal. The input end of the loop control unit 3 is configured to receive the first initial to-be-detected signal and the second initial to-be-detected signal respectively. The output end of the loop control unit 3 is connected with the controlled end of the first loop unit 1 and the controlled end of the second loop unit 2 respectively, and is configured to control the first loop unit 1 to select the first internal loop signal when the rising edge or the falling edge of the first initial to-be-detected signal is detected, and control the second loop unit 2 to select the second internal loop signal when the rising edge of the second initial to-be-detected signal is detected. The output end of the phase comparison unit 4 is connected with the input end of the output unit 5, and is configured to detect the time difference between the first internal loop signal and the second internal loop signal, and control the output unit 5 to output a pulse signal according to the time difference. A delay mismatch time interval for causing the first initial to-be-detected signal and the second initial to-be-detected signal to generate transmission delay is arranged on the signal transmission path of the first initial to-be-detected signal and / or the second initial to-be-detected signal.

[0085] It should be noted that, in the present application, the first loop unit 1 and the second loop unit 2 both have signal selection function and can select the signal input of one of the input ends. Taking the first loop unit 1 as an example, the first loop unit 1 can select the first initial to-be-detected signal as the signal input, or select the first internal loop signal output by itself as the signal input. After the input signal is determined, the first loop unit 1 and the second loop unit 2 both perform width normalization and amplitude normalization on the input signal, so as to output a pulse signal with fixed width and amplitude.

[0086] The signal selection function of the first loop unit 1 and the second loop unit 2 is triggered by the loop control unit 3. The loop control unit 3 is configured to detect the first initial test signal and the second initial test signal, and output a first switching signal to the first loop unit 1 when detecting the rising edge or the falling edge of the first initial test signal, so that the first loop unit 1 selects the first internal loop signal as the signal input. The loop control unit 3 is also configured to output a second switching signal to the second loop unit 2 when detecting the rising edge of the second initial test signal, so that the second loop unit 2 selects the second internal loop signal as the signal input. Therefore, when the first loop unit 1 does not receive the first switching signal, the first initial test signal is selected as the signal input. When the second loop unit 2 does not receive the second switching signal, the second initial test signal is selected as the signal input. Since there is a slight time difference between the first initial test signal and the second initial test signal, the rising edge or the falling edge of the first initial test signal detected by the loop control unit 3 and the rising edge of the second initial test signal detected by the loop control unit 3 have a sequence, and the triggering time of the first loop unit 1 and the second loop unit 2 also has a sequence, so that the initial time sequence relationship between the first initial test signal and the second initial test signal is locked in the first loop unit 1 and the second loop unit 2, and the time sequence relationship is used as a reference to perform a limited number of loops.

[0087] The first loop unit 1 and the second loop unit 2 respectively output normalized fixed-width and amplitude pulses (i.e., the first internal loop signal and the second internal loop signal) according to the received signals, and the time difference between the rising edges of the first internal loop signal and the second internal loop signal is equal to the time difference between the first initial test signal and the second initial test signal.

[0088] In this embodiment, the loop control unit 3, the first loop unit 1, the phase comparison unit 4, and the output unit 5 constitute a transmission path of the first initial test signal. The loop control unit 3, the second loop unit 2, the phase comparison unit 4, and the output unit 5 constitute a transmission path of the second initial test signal. The first internal loop signal and the second internal loop signal output by the first loop unit 1 and the second loop unit 2 are transmitted in the transmission path. The application is configured with a delay mismatch time interval for causing the first initial test signal and the second initial test signal to produce a transmission delay in the signal transmission path of the first initial test signal and / or the second initial test signal. Therefore, in each loop, the time difference between the first internal loop signal and the second internal loop signal is systematically and fixedly reduced by a fixed amount (the delay mismatch time interval For example:

[0089] Assuming that the transmission delay of the first initial test signal is greater than the transmission delay of the second initial test signal, then the time difference of the kth cycle is . Wherein, Tin is the time difference of the first initial test signal and the second initial test signal.

[0090] Wherein, the delay mismatch time interval of the embodiment can be configured by utilizing and designing the parasitic parameters of the layout, as shown in the following examples.

[0091] Example one: In the layout design stage, the embodiment configures the input transistors of the post-stage circuit (i.e. the phase comparison unit) driven by the first internal loop signal and the second internal loop signal asymmetrically. For example: the gate size of the input transistor connected to the first loop unit 1 can be set to be slightly larger than the gate size of the input transistor connected to the second loop unit 2. Since the gate capacitance of the transistor is positively correlated with its own size, the total load capacitance (i.e. the equivalent capacitance of the post-stage circuit) required to be driven by the signal transmission path of the first initial test signal is slightly larger than the total load capacitance required to be driven by the signal transmission path of the second initial test signal when transmitting, so that the signal transmission path of the first initial test signal needs to charge and discharge the capacitance with larger capacity for a longer time, thereby introducing a small delay difference (i.e. delay mismatch time interval ) between the transmission of the first initial test signal and the second initial test signal.

[0092] Example two: configured by IR Drop mismatch. Specifically, when performing layout wiring, the power supply network with a small resistance difference can be designed for the signal transmission path of the first initial test signal and the second initial test signal. For example, the effective voltage drop of the power supply network of the signal transmission path of the first initial test signal is set to be smaller than that of the signal transmission path of the second initial test signal, so that the effective supply voltage of each logic gate in the signal transmission path of the first initial test signal is systematically lower due to the voltage drop (IR Drop), thereby increasing the propagation delay of the path as a whole, and introducing a small delay difference (i.e. delay mismatch time interval ) between the signal transmission path of the first initial test signal and the signal transmission path of the second initial test signal.

[0093] Example three: In addition to the methods provided in examples one and two, a very small, fixed passive device (such as a micro-resistor or a capacitive load) can also be integrated on the signal transmission path of the first initial test signal or the second initial test signal to realize the delay mismatch time interval The configuration of the first initial test signal and the second initial test signal is as follows: the signal transmission path of the first initial test signal is integrated with a passive device, and the passive device is arranged on the path between the output end of the first loop unit 1 and the input end of the phase comparison unit 4 and is connected with the output end of the first loop unit 1 and the input end of the phase comparison unit 4 respectively to turn on the first loop unit 1 and the phase comparison unit 4.

[0094] Alternatively, the signal transmission path of the first initial test signal and the signal transmission path of the second initial test signal are configured with asymmetric drive gates (i.e. logic gates with different driving capabilities) to configure the delay mismatch time interval It can be understood that, by using logic gates with different driving capabilities, the required driving time is different, thereby affecting the output delay to complete the delay mismatch time interval .

[0095] The working process of the embodiment is as follows: after the first initial test signal and the second initial test signal are accessed to the first loop unit 1, the second loop unit 2 and the loop control unit 3, the loop control unit 3 waits for the rising edge or the falling edge of the first initial test signal and waits for the rising edge of the second initial test signal, during the waiting period, the input signal of the first loop unit 1 is the first initial test signal, and the input signal of the second loop unit 2 is the second initial test signal, when the loop control unit 3 detects the rising edge or the falling edge of the first initial test signal, the first loop unit 1 is triggered to select the first internal loop signal, and when the rising edge of the second initial test signal is detected, the second loop unit 2 is triggered to select the second internal loop signal, based on this, the first loop unit 1 and the second loop unit 2 constitute a closed feedback loop, isolate the external first initial test signal and the second initial test signal, and take the first internal loop signal and the second internal loop signal as the reference to perform the loop in the first loop unit 1 and the second loop unit 2. Assuming that the time between the first initial test signal and the second initial test signal is Tin, then in the first loop, the time difference of the rising edges of the fixed pulses output by the first loop unit 1 and the second loop unit 2 is about Tin. In each loop, the time difference between the first internal loop signal and the second internal loop signal is systematically and fixedly reduced by the delay mismatch time interval .

[0096] After the first loop unit 1 and the second loop unit 2 output the first internal loop signal and the second internal loop signal, both signals are input to the phase comparison unit 4. The phase comparison unit 4 detects the time difference between the two signals and outputs a corresponding control signal to the output unit 5 based on this time difference, causing the output unit 5 to output a corresponding pulse signal. Therefore, as long as the phase unit can detect a signal difference between the first and second internal loop signals, the output unit 5 will continuously output the corresponding pulse signal. In one example, for easier differentiation, the pulse signal output by the output unit 5 can be set to a high-level signal.

[0097] Taking the pulse signal output by output unit 5 as a high-level signal as an example, in this embodiment, "1" represents a high level and "0" represents a low level. As can be seen from the above, the width of the pulse signal output by output unit 5 starts from changing to "1" and ends at changing to "0," and its width is equal to the number of cycles multiplied by the time period of each cycle. The number of cycles N is proportional to the initial time difference Tin, i.e. Therefore, in this embodiment, the time difference between the first initial test signal and the second initial test signal is converted into a pulse signal width using the phase comparison unit 4 and the output unit 5. Furthermore, compared to the original first and second initial test signals, the pulse width of the pulse signal output by the output unit 5 is significantly amplified, with an amplification factor equal to the cycle period / In one application example, such as Figure 10 As shown, Figure 10 In the diagram, the horizontal axis represents the time difference between the rising edges of the two signal inputs (unit: ps), and the vertical axis represents the pulse width of the pulse signal output by output unit 5 (unit: ns). Figure 10 The slope in the equation represents the magnification factor, which is approximately 500 times.

[0098] As can be seen from the above, the timing monitoring circuit provided by the embodiment of the present application amplifies time through the circuit structure for amplifying time of the closed feedback loop, accumulates the slight delay based on the cyclic iteration, and thus converts a slight and fixed time in the input end into a pulse signal with a significantly amplified width in the output end. Through the principle of cyclic amplification, the present application can easily realize a time amplification multiple of about 500 times, convert the femtosecond-level time difference (250 fs) that is difficult to handle by the traditional scheme into a nanosecond-level pulse width that is easy to measure by the subsequent digital circuit, obtain extremely high gain and resolution, and solve the problems of the limited gain and the limited application scenarios of the traditional VDL-TDC. Moreover, the closed feedback loop provided by the embodiment of the present application has a compact structure, greatly saves the chip area compared to the huge delay cell array and the decision maker array required in the traditional VDL-TDC. Meanwhile, since most of the time circuits are in the standby state and only perform a limited number of cycles after being triggered, the dynamic power consumption is also much lower than that of the delay chain that continuously works.

[0099] Moreover, the embodiment of the present application utilizes the parasitic parameters to realize the mechanism of time difference reduction, intentionally and asymmetrically designs the parasitic input capacitance and IR Drop of the two signal paths in the layout design stage, and realizes the delay mismatch time interval with high stability at extremely low cost without relying on additional active delay cells, so that the time difference of the two signals to be measured can be stably reduced in the cycle. Moreover, the present application utilizes the inherent parasitic parameter mismatch to define the time reduction step, avoids the situation that the control accuracy is low and the control cost is high due to the difficulty in controlling the slight delay difference of two independent delay units under different process angles in the prior art. Moreover, the mismatch mode based on the physical effect provided by the embodiment shows better stability to PVT variation within a certain range.

[0100] In one embodiment, as shown in Figure 3 , it further comprises a reset unit 6 and an external reset control unit 9.

[0101] The input end of the reset unit 6 is connected with the output unit 5 and the external reset control unit 9, the reset unit 6 is connected with the reset end of the cycle control unit 3, for receiving and detecting the output signal of the pulse unit output by the output unit 5, receiving the external reset pulse of the external reset control unit 9, and outputting a reset signal to the cycle control unit 3 when the falling edge of the pulse signal is detected or the external reset pulse of the external reset control unit 9 is received.

[0102] It should be noted that the external reset pulse has two states of high level or low level, and the reset signal is valid at low level. Therefore, the reset unit 6 outputs a low level reset signal when detecting the falling edge of the pulse signal, or outputs a low level reset signal when receiving an external reset pulse at low level, and outputs a high level reset signal which is invalid in other cases.

[0103] Specifically, in combination with the foregoing embodiments, when the width of the pulse signal of the output unit 5 is from the beginning of becoming "1" to the end of becoming "0", therefore, when the falling edge of the pulse signal is detected, it indicates that the detection result of the phase comparison unit 4 is that there is no time difference between the first initial test signal and the second initial test signal, therefore, the iteration operation of the first loop unit 1 and the second loop unit 2 can be stopped, at this time, the reset unit 6 can output a low level reset signal to the loop control unit 3, so that the loop control unit 3 is reset to the standby state; and / or when an external reset pulse is received at low level, a low level reset signal is output to the loop control unit 3. Therefore, by setting the reset unit 6, the present application can stop the loop iteration process, and also can stop the loop iteration process of the circuit in response to the reset requirement of the external reset control unit 9.

[0104] As a further improvement, a special case is considered: when the time difference Tin between the first initial test signal and the second initial test signal is too small, so that the phase comparison unit 4 cannot detect the time difference between the first internal loop signal and the second internal loop signal in the first loop, thereby causing the output unit 5 to continuously output a low level signal "0", and further causing the pulse signal to fail to generate a normal falling edge reset signal, resulting in the timing monitoring circuit being continuously locked in the loop state, forming a "deadlock". In order to solve this technical problem, as shown in Figure 4 The embodiment of the present application further comprises: a timeout counter 7 and a logic gate circuit 8.

[0105] The input end of the timeout counter 7 is connected with the output end of the first loop unit 1, the output end of the second loop unit 2 and the output end of the output unit 5 respectively, and the output end of the timeout counter 7 is connected with an input end of the logic gate circuit 8, for generating a count clock according to the loop times of the first internal loop signal and the second internal loop signal when the pulse signal has no falling edge, and outputting a falling edge signal to the logic gate circuit 8 when the count clock reaches a preset number threshold.

[0106] The other input end of the logic gate circuit 8 is connected with the output end of the output unit 5, and the output end of the logic gate circuit 8 is connected with the input end of the falling edge detector, for transmitting the falling edge signal output by the timeout counter 7 and / or the pulse signal to the falling edge detector.

[0107] It should be noted that the embodiment detects the falling edge of the pulse signal by setting the timeout counter 7, and uses the first internal loop signal and the second internal loop signal to accumulate the number of times, and generates the corresponding count clock, and when the count clock reaches the preset number threshold and there is no falling edge of the pulse signal, it is determined that the system is in a "deadlock" state, and the falling edge signal is output to the logic gate circuit 8, and the logic gate circuit 8 receives the falling edge signal and / or the pulse signal.

[0108] Based on this, the reset unit 6 can output the corresponding reset signal by judging whether the pulse signal has a falling edge, and can also output the corresponding reset signal by judging the falling edge signal output by the timeout counter 7, and can also output the corresponding reset signal in response to the external reset pulse of the external reset control unit 9. The normal reset path triggered by the falling edge of the output signal and a timeout counter 7 reset path triggered by the loop activity when the output is abnormal (always low) are integrated, which prevents the circuit from being in a deadlock state in the case of extremely small input time difference, realizes a complete timeout protection and reset mechanism, and the construction of a dual-mode reset system, ensures the reliable operation and automatic recovery ability of the circuit under various working conditions, and improves the system robustness.

[0109] In one embodiment, the first loop unit comprises: a first signal selector and a first pulse generator;

[0110] The first input end of the first signal selector is used to receive the first initial signal to be tested;

[0111] The controlled end of the first signal selector is connected with the output end of the loop control unit;

[0112] The output end of the first signal selector is connected with the input end of the first pulse generator;

[0113] The output end of the first pulse generator is connected with the second input end of the first signal selector and the first input end of the phase comparison unit, respectively.

[0114] In one embodiment, the second loop unit comprises: a second signal selector and a second pulse signal generator;

[0115] The first input end of the second signal selector is used to receive the second initial signal to be tested;

[0116] The controlled end of the second signal selector is connected with the output end of the loop control unit;

[0117] The output end of the second signal selector is connected with the input end of the second pulse generator;

[0118] The output end of the second pulse generator is connected with the second input end of the second signal selector and the second input end of the phase comparison unit, respectively.

[0119] It should be noted that, as shown in Figure 5 11 is a first signal selector, and 12 is a second signal selector.

[0120] In one embodiment, the cycle control unit comprises: a first D flip-flop, a second D flip-flop, and an edge detection circuit.

[0121] An input end of the edge detection circuit, configured to receive a first initial test signal.

[0122] An output end of the edge detection circuit, connected to a clock end of the first D flip-flop.

[0123] An output end of the first D flip-flop, connected to a controlled end of the first signal selector.

[0124] A clock end of the second D flip-flop, configured to receive a second initial test signal.

[0125] An output end of the second D flip-flop, connected to a controlled end of the second signal selector.

[0126] A data end of the first D flip-flop and a data end of the second D flip-flop, configured to receive a power voltage signal.

[0127] It should be noted that, as shown in Figure 6 DFF1 and DFF2 are the first D flip-flop and the second D flip-flop respectively. VDD is a power voltage signal, data is a first initial test signal, and cp is a second initial test signal. D is a data end of the D flip-flop, Q is an output end of the D flip-flop, and CLK is a clock end of the D flip-flop.

[0128] In one embodiment, the edge detection circuit comprises: a first buffer, a second buffer, and a first XOR gate.

[0129] An input end of the first buffer and a first input end of the first XOR gate, configured to receive a first initial test signal.

[0130] An output end of the first buffer is connected to an input end of the second buffer, and an output end of the second buffer is connected to a second input end of the first XOR gate.

[0131] An output end of the first XOR gate is connected to a clock end of the first D flip-flop.

[0132] It should be noted that, as shown in Figure 6 31 is the first buffer, 32 is the second buffer, and 33 is the first XOR gate.

[0133] In one embodiment, the phase comparison unit comprises: a timing detection subunit, a first logic gate circuit; and the output unit comprises: a third D flip-flop.

[0134] an input terminal of the time sequence detection subunit, configured to receive the first initial to-be-detected signal and the second initial to-be-detected signal respectively;

[0135] an output terminal of the time sequence detection subunit, connected with a data terminal of the third D flip-flop, configured to output a target pulse signal to the third D flip-flop when it is detected that the time difference between the first initial to-be-detected signal and the second initial to-be-detected signal is not less than a preset time threshold;

[0136] an input terminal of the first logic gate circuit, configured to receive the first initial to-be-detected signal and the second initial to-be-detected signal respectively;

[0137] an output terminal of the first logic gate circuit, connected with a clock terminal of the third D flip-flop, configured to output a trigger signal to the third D flip-flop when it is detected that the first initial to-be-detected signal and the second initial to-be-detected signal are in a target state.

[0138] It should be noted that, as shown in Figure 5 , the DFF_out is the third D flip-flop. The time sequence detection subunit can include a latch and an inverter, and the first logic gate circuit can be a NAND gate (as shown in 41 in Figure 5 . The latch can be an SR latch. It can be understood that the phase comparator can also be replaced by other types of arbiter circuits, such as a full dynamic latch or a current mode logic comparator, as long as it can meet the femtosecond level resolution requirement. It can be understood that Figure 5 the phase comparator in

[0139] In one embodiment, the reset unit includes: a falling edge detector and a reset AND gate.

[0140] The input terminal of the falling edge detector is connected with the output unit, and the output terminal of the falling edge detector is connected with an input terminal of the reset AND gate.

[0141] The other input terminal of the reset AND gate is connected with an external reset control unit, and the output terminal of the reset AND gate is connected with the cycle control unit.

[0142] It should be noted that, as shown in Figure 7 , 61 is the reset AND gate.

[0143] In one embodiment, the falling edge detector includes: a third buffer, a first NAND gate and a first OR gate.

[0144] The input terminal of the third buffer is connected with an input terminal of the OR gate as the input terminal of the falling edge detector.

[0145] The output terminal of the third buffer is connected with the input terminal of the first NOT gate, the output terminal of the first NOT gate is connected with another input terminal of the OR gate, and the output terminal of the OR gate is the output terminal of the falling edge detector.

[0146] It should be noted that, as shown in Figure 7 , 62 is a third buffer, 63 is a first NOT gate, and 64 is a first OR gate.

[0147] In one embodiment, the timeout counter comprises: a first NOR gate, a second NOR gate, a fourth D flip-flop, a fifth D flip-flop, a second NOT gate, and a second XOR gate; and the logic gate circuit comprises a second OR gate.

[0148] An input terminal of the first NOR gate is connected with the output terminal of the first loop unit, another output terminal of the first NOR gate is connected with the output terminal of the second loop unit; an input terminal of the second NOR gate is connected with the output terminal of the first NOR gate; another input terminal of the second NOR gate is connected with the output terminal of the output unit; the output terminal of the second NOR gate is connected with the clock terminal of the fourth D flip-flop and the clock terminal of the fifth D flip-flop; the data terminal of the fourth D flip-flop is connected with the second NOT gate and the output terminal of the fourth D flip-flop through the second NOT gate; the output terminal of the fourth D flip-flop is connected with an input terminal of the second XOR gate; another input terminal of the second XOR gate is connected with the output terminal of the fifth D flip-flop; the output terminal of the second XOR gate is connected with the data terminal of the fifth D flip-flop; the output terminal of the fifth D flip-flop is connected with an input terminal of the second OR gate; another input terminal of the second OR gate is connected with the output terminal of the output unit, and the output terminal of the second OR gate is connected with the input terminal of the falling edge detector.

[0149] It should be noted that, as shown in Figure 7 , 71 is a first NOR gate, 72 is a second NOR gate, DFF4 is a fourth D flip-flop, DFF5 is a fifth D flip-flop, 73 is a second NOT gate, 74 is a second XOR gate, and 81 is a second OR gate.

[0150] It can be understood that the clock of the timeout counter can not use the NOR gate, but can be directly triggered by any one of the second internal loop signal c<1> or the first internal loop signal d<1> pulse, as long as it can respond to the loop activity. The OR gate logic in the final logic gate circuit can also be implemented by other equivalent logic combinations (such as NAND gate, NOR gate).

[0151] In one embodiment, the first pulse generator and the second pulse generator can be any circuit capable of generating a fixed-width pulse in each cycle, for example, can be a pulse shaping circuit, or can be a pulse generator composed of a delay line and a logic gate.

[0152] In one example, the structure of the selected pulse shaping circuit comprises: a fourth buffer to a seventh buffer, a third XOR gate, a third NOT gate, a sixth D flip-flop;

[0153] One end of the fourth buffer is connected with the fifth buffer and connected to one input end of the third XOR gate through the fifth buffer; the other end of the fourth buffer is connected with the other input end of the third XOR gate as an input end; the output end of the third XOR gate is connected to the clock end of the sixth D flip-flop, the data end of the sixth D flip-flop is used for receiving a power voltage signal, and the output end of the sixth D flip-flop, the sixth buffer, the seventh buffer, the third NOT gate and the CDN end of the sixth D flip-flop are connected in sequence.

[0154] It should be noted that, as shown in Figure 8 101 to 104 are the fourth buffer to the seventh buffer, 105 is the third XOR gate, 106 is the third NOT gate, and DFF6 is the sixth D flip-flop. VDD is the power voltage signal. D represents the input signal.

[0155] The timing monitoring circuit provided by the application will be described below. Figures 5 to 11

[0156] Figures 5 to 11 The first initial test signal is data, the second initial test signal is cp, and there is a small initial time difference Tin between them. q<0> is the pulse signal output by the output unit, and the width thereof is proportional to the initial time difference. c<1> and d<1> are two pulse signals normalized by the pulse shaping circuit and circulating in the feedback loop. d<1> is the first internal circulating signal output by the first circulating unit, and c<1> is the second internal circulating signal output by the second circulating unit. D_Lead: an intermediate signal generated by the SR latch in the high-sensitivity phase comparator, and the high and low levels thereof are used to represent the arrival order of c<1> and d<1>. Sample_Clk: a sampling clock signal generated by c<1> and d<1> through the NAND gate in the high-sensitivity phase comparator, used to latch the state of D_Lead at a specific time. The first signal selector is a 2-to-1 multiplexer MUX1, the second signal selector is a 2-to-1 multiplexer MUX2, the first D flip-flop is DFF1, and the second D flip-flop is DFF2. The two D flip-flops (DFF1, DFF2) constitute a lock controller, and the output of the lock controller directly controls the multiplexer. The third D flip-flop is DFF_out. Figure 5 The control logic module in the timing monitoring circuit comprises a timeout counter, a logic gate circuit, a reset unit and an external reset control unit.

[0157] The flow of the timing monitoring circuit can be divided into the following stages ​

[0158] First stage: standby and trigger lock.

[0159] (1) Standby state. Initially, the MUX<0:1> signal output by the lock controller is '0'. Both MUX1 and MUX2 select their external input ports, which are connected to the external signals data and cp respectively. At this time, the circuit is in standby state, waiting for the rising edge of the input signals.

[0160] (2) Trigger and lock. When the rising edges of data and cp appear successively, the two rising edges trigger DFF1 and DFF2 respectively, so that the MUX<0:1> signal output by the lock controller becomes '1', thus making MUX1 and MUX2 switch to their feedback input ports immediately. In this way, the external data and cp signals are isolated, and a closed feedback loop is formed in the system, which "locks in" the initial timing relationship in the loop. It can be understood that, since there is an edge detection circuit in front of the clock terminal of DFF1, the rising and falling edges of data can trigger DFF1, while DFF2 can only be triggered by the rising edge of cp, since the clock terminal of DFF2 is directly connected to the cp signal.

[0161] Second stage: cyclic amplification.

[0162] After the lock controller is locked, the signals output from MUX1 and MUX2 are sent to the pulse shaping circuit. The pulse shaping circuit generates a pair of pulse signals d<1> and c<1> with normalized width and amplitude in each cycle, so that the reference for comparison in each cycle is consistent. In the first cycle, the time difference between the rising edges of d<1> and c<1> is about Tin.

[0163] The d<1> and c<1> output by the pulse shaping circuit propagate in the loop and are finally fed back to the input terminals of MUX1 and MUX2. Since the two signal paths of d<1> and c<1> are designed to have a small, fixed delay mismatch In each cycle, the time difference between the two pulse signals is systematically and stably reduced by a fixed amount (the delay mismatch time interval ). For example, if the d<1> path has a larger delay, the time difference between the rising edges of d<1> and c<1> in the kth cycle , as shown in Figure 9 .

[0164] Third stage: high sensitivity comparison and output.

[0165] In each cycle, d<1> and c<1> are sent into the SR latch of the phase comparator. The SR latch receives d<1> and c<1>, and according to which signal arrives first, its output D_Lead through the inverter is set to '1' or '0'. For example, d<1> arrives first, D_Lead is '1'; c<1> arrives first, D_Lead is '0'. Since it is a latch, the state will be maintained.

[0166] At the same time, d<1> and c<1> are also sent into the NAND gate. When both pulses are high, the NAND gate output Sample_Clk is '0'; when both pulses end in succession and return to low, the NAND gate outputs a rising edge from '0' to '1'. This rising edge is used as the clock signal of the third D flip-flop DFF_out, and the output D_Lead of the SR latch through the inverter is input to the data end of DFF_out. Therefore, as long as the time difference between d<1> and c<1> is greater than the setup time of the comparator, the SR latch can correctly determine the order of arrival, so that the output q<0> of DFF_out is '1'. As the cycle progresses, when the time difference between d<1> and c<1> is reduced to less than the setup time of the comparator, the SR latch output is '0', eventually causing DFF_out to latch to '0'. Therefore, q<0> output by DFF_out is a pulse, and the width (from the start of q<0> becoming '1' to the end of becoming '0') is equal to the number of cycles multiplied by the period of each cycle. Since the number of cycles N is proportional to the initial time difference Tin (i.e. ), the final pulse width T out of q<0> is greatly amplified, and the amplification factor is the cycle period , Figure 10 The simulation results shown in the figure demonstrate that the slope display amplification factor is about 500 times.

[0167] Fourth stage: reset and timeout control

[0168] (1) Normal reset. The falling edge detector continuously monitors the output of q<0>. Once q<0> jumps from '1' to '0', indicating that the amplification process is complete, the detector immediately generates a reset pulse that resets the lock controller (DFF1, DFF2), causing the MUX<0:1> signal to return to '0', the loop is disconnected, and the system returns to standby state.

[0169] (2) Timeout protection: Consider a special case where Tin is too small, so that the time difference between d<1> and c<1> is less than the setup time of the comparator in the first cycle, resulting in q<0> always being '0' and unable to generate a normal falling edge reset signal, while the system is locked in a loop state, forming a "deadlock". To solve this problem, a timeout counter is designed.

[0170] The clock of the timeout counter is generated by the c<1> and d<1> pulses through a NOR Gate and then through an OR Gate with q<0> ), that is, a count clock is generated after the end of each cycle pulse. Based on Figure 7 It can be seen that the timeout counter is only enabled when the "MUX<0:1> signal is '1' and q<0> is '0', and in other cases, it is in standby state. When the counter counts to a preset value (for example, 4), it indicates that the system has fallen into "deadlock", at which time the timeout counter will forcibly generate a reset pulse.

[0171] (3) Final reset. Since the output reset signal RESET signal is low active. Therefore, the external reset pulse rst_n (forced reset) and the internal reset pulse clr (normal reset and timeout protection) are combined through an AND Gate to ensure that the system can be reliably reset in any case. The timeout reset timing diagram is shown in Figure 11 .

[0172] In several embodiments provided in the present application, it should be understood that the disclosed units are only schematic and can be implemented in other manners. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between units can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0173] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the embodiments.

[0174] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each functional unit can be a separate physical unit, or two or more functional units can be integrated into a processing unit.

[0175] The terms "first", "second", "third", "fourth" and the like in the description of this application and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of these terms herein is to be construed to cover the embodiments of the application whether or not the embodiments are described using the same term. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the application. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0176] The above embodiments are only used to illustrate the technical solutions of the present application, not limit the present application; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A timing monitoring circuit, characterized in that, include: First loop unit, second loop unit, loop control unit, phase comparison unit, output unit; The first input terminal of the first loop unit is used to receive the first initial test signal; The output terminal of the first loop unit is connected to the second input terminal of the first loop unit and the first input terminal of the phase comparison unit, respectively, for outputting a first internal loop signal; The first input terminal of the second loop unit is used to receive the second initial test signal; the output terminal of the second loop unit is connected to the second input terminal of the second loop unit and the second input terminal of the phase comparison unit respectively, and is used to output the second internal loop signal. The input terminal of the loop control unit is used to receive the first initial test signal and the second initial test signal respectively. The output terminal of the loop control unit is connected to the controlled terminals of the first loop unit and the second loop unit respectively. When the rising edge or falling edge of the first initial test signal is detected, the first loop unit is controlled to select the first internal loop signal; and when the rising edge of the second initial test signal is detected, the second loop unit is controlled to select the second internal loop signal. The output terminal of the phase comparison unit is connected to the input terminal of the output unit, and is used to detect and control the output unit to output a pulse signal based on the time difference between the first internal loop signal and the second internal loop signal. The signal transmission path formed by the timing monitoring circuit is configured with a delay mismatch time interval, which is used to cause the first initial test signal and the second initial test signal to have a transmission delay, and to cause the first internal loop signal and the second internal loop signal to have a transmission delay.

2. The circuit according to claim 1, characterized in that, The first loop unit includes: a first signal selector and a first pulse generator; The first input terminal of the first signal selector is used to receive the first initial test signal; The controlled terminal of the first signal selector is connected to the output terminal of the loop control unit; The output of the first signal selector is connected to the input of the first pulse generator; The output terminal of the first pulse generator is connected to the second input terminal of the first signal selector and the first input terminal of the phase comparison unit, respectively.

3. The circuit according to claim 2, characterized in that, The second loop unit includes: a second signal selector and a second pulse signal generator; The first input terminal of the second signal selector is used to receive the second initial test signal; The controlled terminal of the second signal selector is connected to the output terminal of the loop control unit; The output of the second signal selector is connected to the input of the second pulse generator; The output terminal of the second pulse generator is connected to the second input terminal of the second signal selector and the second input terminal of the phase comparison unit, respectively.

4. The circuit according to claim 3, characterized in that, The loop control unit includes: a first D flip-flop, a second D flip-flop, and an edge detection circuit; The input terminal of the edge detection circuit is used to receive the first initial test signal; The output of the edge detection circuit is connected to the clock terminal of the first D flip-flop; The output terminal of the first D flip-flop is connected to the controlled terminal of the first signal selector; The clock input of the second D flip-flop is used to receive the second initial test signal; The output of the second D flip-flop is connected to the controlled terminal of the second signal selector; The data terminals of the first and second D flip-flops are used to receive power supply voltage signals.

5. The circuit according to claim 4, characterized in that, The phase comparison unit includes: a timing detection subunit and a first logic gate circuit; the output unit includes: a third D flip-flop; The input terminal of the timing detection subunit is used to receive the first internal loop signal and the second internal loop signal, respectively. The output terminal of the timing detection subunit is connected to the data terminal of the third D flip-flop, and is used to output a target pulse signal to the third D flip-flop when the time difference between the first initial test signal and the second initial test signal is not less than a preset time threshold. The input terminal of the first logic gate circuit is used to receive the first initial test signal and the second initial test signal, respectively; The output of the first logic gate is connected to the clock terminal of the third D flip-flop, and is used to output a trigger signal to the third D flip-flop when the first initial test signal and the second initial test signal are detected to be in the target state.

6. The circuit according to claim 4, characterized in that, The edge detection circuit includes: a first buffer, a second buffer, and a first XOR gate; The input terminal of the first buffer and the first input terminal of the first XOR gate are used to receive the first initial test signal; The output of the first buffer is connected to the input of the second buffer, and the output of the second buffer is connected to the second input of the first XOR gate. The output of the first XOR gate is connected to the clock terminal of the first D flip-flop.

7. The circuit according to any one of claims 1-6, characterized in that, Also includes: Reset unit and external reset control unit; The input terminal of the reset unit is connected to the output unit and the external reset control unit. The reset unit is connected to the reset terminal of the loop control unit. It is used to receive and detect the output signal of the pulse unit output by the output unit, and receive the external reset pulse of the external reset control unit. When the falling edge of the pulse signal is detected or the external reset pulse of the external reset control unit is received, the reset unit outputs a reset signal to the loop control unit.

8. The circuit according to claim 7, characterized in that, The reset unit includes: a falling edge detector and a reset AND gate; The input terminal of the falling edge detector is connected to the output unit, and the output terminal of the falling edge detector is connected to one input terminal of the reset AND gate; The other input of the reset AND gate is connected to the external reset control unit, and the output of the reset AND gate is connected to the loop control unit.

9. The circuit according to claim 8, characterized in that, It also includes timeout counters and logic gates; The input terminal of the timeout counter is connected to the output terminal of the first loop unit, the output terminal of the second loop unit, and the output terminal of the output unit, respectively. The output terminal of the timeout counter is connected to an input terminal of a logic gate circuit. It is used to generate a counting clock based on the number of cycles of the first internal loop signal and the second internal loop signal when the pulse signal has no falling edge, and to output a falling edge signal to the logic gate circuit when the counting clock reaches a preset number threshold. The other input terminal of the logic gate circuit is connected to the output terminal of the output unit, and the output terminal of the logic gate circuit is connected to the input terminal of the falling edge detector, for transmitting the falling edge signal and / or the pulse signal output by the timeout counter to the falling edge detector.

10. The circuit according to claim 9, characterized in that, The falling edge detector includes: a third buffer, a first NOT gate, and a first OR gate; The input terminal of the third buffer is connected to one input terminal of the OR gate, serving as the input terminal of the falling edge detector; The output of the third buffer is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the other input of the OR gate, and the output of the OR gate is the output of the falling edge detector.

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