Memory device and manufacturing method of memory device

Abstract

Embodiments improve a communication band of a memory system. A memory system (1) according to an embodiment includes a first chip (MC) and a second chip (CC) bonded to the first chip. A memory system (1) according to an embodiment is provided with a semiconductor memory device (4) and a memory controller (3). A semiconductor memory device (4) is provided with a memory cell array (15), a peripheral circuit (18) for controlling the memory cell array (15), and an input / output module (10) connected to the peripheral circuit (18). The memory controller (3) receives an instruction from an external host device and controls the semiconductor memory device (4) via the input / output module (10). The first chip (MC) includes a memory cell array (15), and the second chip (CC) includes a peripheral circuit (18), an input / output module (10), and a memory controller (3).

Description

[0001] This application is a divisional application of the Chinese patent application No. 202110086115.7 filed by the applicant on January 22, 2021, entitled "Memory System".

[0002] Related applications

[0003] This application enjoys priority based on Japanese Patent Application No. 2020-111105 (filed on June 29, 2020). This application incorporates the entire contents of the basic application by reference. Technical Field

[0004] Embodiments of the present invention relate to memory systems. Background Technology

[0005] NAND flash memory is known to be capable of storing data non-volatilely. Summary of the Invention

[0006] The implementation method improves the communication bandwidth of the memory system.

[0007] The memory system of this embodiment includes a first chip and a second chip attached to the first chip. The memory system of this embodiment includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, peripheral circuitry for controlling the memory cell array, and an input / output module connected to the peripheral circuitry. The memory controller receives instructions from an external host device and controls the semiconductor memory device via the input / output module. The first chip includes the memory cell array, and the second chip includes peripheral circuitry, the input / output module, and the memory controller.

[0008] A memory device according to an embodiment includes a first chip including a first surface and a second chip including a second surface and bonded to the first chip. The memory device includes: a first memory cell array configured to non-volatilely store data; a register configured to store instructions; a control circuit configured to perform read and write operations on memory cells constituting the first memory cell array based on the instructions stored in the register; and an input / output module connected to the control circuit. The first chip includes the first memory cell array and a first bonding pad disposed on the first surface and electrically connected to the first memory cell array. The second chip includes the register, the control circuit, the input / output module, and a second bonding pad disposed on the second surface and electrically connected to the control circuit. The second bonding pad is bonded to and electrically connected to the first bonding pad.

[0009] Additionally, a memory device according to an embodiment includes: a first chip including a first surface; a second chip including a second surface and attached to the first chip; and at least one third chip electrically connected to the second chip. The memory device further includes: at least one memory cell array configured to non-volatilely store data; a register configured to store instructions; a control circuit configured to perform read and write operations on memory cells constituting the at least one memory cell array based on the instructions stored in the register; and an input / output module connected to the control circuit. The first chip includes the input / output module and a first bonding pad disposed on the first surface and electrically connected to the input / output module. The second chip includes the register, the control circuit, and a second bonding pad disposed on the second surface and electrically connected to the control circuit. The at least one third chip includes the at least one memory cell array, and the second bonding pad is attached to and electrically connected to the first bonding pad.

[0010] In addition, a method for manufacturing a memory device according to an embodiment, the memory device comprising a first chip including a first surface and a second chip including a second surface, the method comprising the following steps: fabricating a first chip, the first chip comprising a first memory cell array for non-volatile data storage and a first bonding pad disposed on the first surface and electrically connected to the first memory cell array; fabricating a second chip, the second chip comprising: a register configured to store instructions; a control circuit configured to execute read and write operations on memory cells constituting the first memory cell array based on the instructions stored in the register; an input / output module connected to the control circuit; and a second bonding pad disposed on the second surface and electrically connected to the control circuit; and bonding the second bonding pad to the first bonding pad.

[0011] Another embodiment of the method for manufacturing a memory device includes: a first chip including a first surface; a second chip including a second surface; and at least one third chip including at least one memory cell array. The method for manufacturing the memory device includes the following steps: fabricating the first chip, which includes an input / output module and a first bonding pad disposed on the first surface and electrically connected to the input / output module; fabricating the second chip, which includes: a register configured to store instructions; a control circuit configured to perform read and write operations on memory cells constituting the at least one memory cell array based on the instructions stored in the register; and a second bonding pad disposed on the second surface and electrically connected to the control circuit; fabricating the at least one third chip including the at least one memory cell array; bonding the second bonding pad to the first bonding pad; and electrically connecting the at least one third chip to the second chip, wherein the input / output module is electrically connected to the control circuit through the bonding. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a structural example of the memory system according to the first embodiment.

[0013] Figure 2 This is a block diagram illustrating a structural example of a semiconductor memory device included in the memory system of the first embodiment.

[0014] Figure 3 This is a perspective view showing an example of the structure of the memory system according to the first embodiment.

[0015] Figure 4 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the first embodiment.

[0016] Figure 5 This is a block diagram illustrating an example of the configuration of various structures in a memory system of a first modified example of the first embodiment.

[0017] Figure 6 This is a block diagram illustrating an example of the configuration of various structures in a memory system of a second variation of the first embodiment.

[0018] Figure 7 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the third variation of the first embodiment.

[0019] Figure 8 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the fourth variation of the first embodiment.

[0020] Figure 9This is a block diagram illustrating an example of the configuration of various structures in the memory system of the fifth variation of the first embodiment.

[0021] Figure 10 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the sixth variation of the first embodiment.

[0022] Figure 11 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the seventh variation of the first embodiment.

[0023] Figure 12 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the eighth variation of the first embodiment.

[0024] Figure 13 This is a cross-sectional view showing an example of the structure of the memory system according to the second embodiment.

[0025] Figure 14 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the second embodiment.

[0026] Figure 15 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the first variant of the second embodiment.

[0027] Figure 16 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the second variation of the second embodiment.

[0028] Figure 17 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the third variation of the second embodiment.

[0029] Figure 18 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the fourth variation of the second embodiment.

[0030] Figure 19 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the fifth variation of the second embodiment.

[0031] Figure 20 This is a block diagram illustrating an example of the configuration of various structures in the memory system of the sixth variation of the second embodiment. Detailed Implementation

[0032] Hereinafter, embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of the invention. The drawings are schematic or conceptual, and the dimensions and proportions of each drawing may not be identical to actual figures. The technical concept of the present invention is not determined by the shape, structure, or arrangement of its constituent elements.

[0033] Furthermore, in the following description, structural elements having substantially the same function and structure are labeled with the same reference numerals. Numbers following the characters constituting the reference numerals are referred to by reference numerals including the same characters, and are used to distinguish elements having the same structure from one another. Where it is not necessary to distinguish elements shown with reference numerals including the same characters from one another, these elements are referred to individually by reference numerals including only the characters.

[0034] [1] First Embodiment

[0035] The memory system 1 of the first embodiment will be described below.

[0036] [1-1] Structure

[0037] Figure 1 An example of the structure of the memory system according to the first embodiment is shown. Figure 1 As shown, the memory system 1 includes a memory controller 3 and a semiconductor storage device 4. The memory controller 3 is connected to the host bus HB. The memory controller 3 and the semiconductor storage device 4 are connected via a NAND bus NB. The memory system 1 is a storage device that conforms to, for example, a UFS (Universal Flash Memory) standard.

[0038] Host device 2 is, for example, a personal computer or a smartphone. The host bus HB connects the storage system 1 and host device 2. Communication between storage system 1 and host device 2 via the host bus HB conforms to the UFS standard.

[0039] The memory controller 3 receives commands from the host device 2 via the host bus HB. The memory controller 3 sends instructions to the semiconductor memory device 4 via the NAND bus NB, these instructions being based on the commands received from the host device 2. The memory controller 3 then sends data received from the semiconductor memory device 4 via the NAND bus NB back to the host device 2 via the host bus HB.

[0040] Semiconductor storage device 4 is a type of NAND flash memory capable of non-volatile data storage. Semiconductor storage device 4 performs data writing, reading, and other operations based on instructions received from memory controller 3 via the NAND bus NB.

[0041] Figure 2 This illustrates a structural example of the semiconductor memory device 4 included in the memory system 1 of the first embodiment. For example... Figure 2As shown, the semiconductor memory device 4 includes an input / output module 10, a serial / parallel conversion circuit 13, a register 14, a memory cell array 15, a line decoder 16, a sense amplifier 17, a sequencer 18, a first internal bus IB1, a second internal bus IB2, and a third internal bus IB3.

[0042] The input / output module 10 is connected to the NAND bus NB and transmits and receives signals with the memory controller 3. Multiple control signals communicated via the NAND bus NB include, for example, signals DQ0~DQ(i-1), DQS, DQSn, CEN, CLE, ALE, WEN, RE, REn, WPn, and RBn.

[0043] Signals DQ0 to DQ(i-1) are transmitted and received between the semiconductor memory device 4 and the memory controller 3. i is an integer greater than or equal to 2. Signals DQ0 to DQ(i-1) represent either a "H" level or an "L" level. Signals DQ0 to DQ(i-1) represent i bits of information through combinations of their respective "H" or "L" level representations. Signals DQ0 to DQ(i-1) are entities of data transmitted and received between the semiconductor memory device 4 and the memory controller 3, and can include any of the following: instructions, addresses, and data.

[0044] Signals DQS and DQSn are transmitted and received between the semiconductor memory device 4 and the memory controller 3. Signals DQS and DQSn are used to control the timing of the operation when receiving signals DQ0 to DQ(i-1).

[0045] The signal CEn is sent from the memory controller 3 to the semiconductor memory device 4. The signal CEn is used to set the semiconductor memory device 4 to a selected or non-selected state. For example, when multiple semiconductor memory devices 4 are connected to the memory controller 3, the memory controller 3 can use the signal to select which semiconductor memory device 4 to operate. When the signal CEn is at a "H" level, the memory controller 3 sets the semiconductor memory device 4 to a non-selected state. When the signal CEn is at a "L" level, the memory controller 3 sets the semiconductor memory device 4 to a selected state.

[0046] Signals CLE, ALE, WEN, RE, REn, and WPn are sent from the memory controller 3 to the semiconductor memory device 4. Signal CLE indicates that signals DQ0 to DQ(i-1) represent instructions. Signal ALE indicates that signals DQ0 to DQ(i-1) represent addresses. Signal WEN instructs the semiconductor memory device 4 to fetch signals DQ0 to DQ(i-1). Signals RE and REn instruct the semiconductor memory device 4 to output signals DQ0 to DQ(i-1). Furthermore, signals RE and REn control the timing of the semiconductor memory device 4's operation when outputting signals DQ0 to DQ(i-1). Signal WPn disables write and delete operations on the semiconductor memory device 4.

[0047] Signal RBn is sent from semiconductor memory device 4 to memory controller 3. Signal RBn is a signal indicating whether semiconductor memory device 4 is in a ready state (a state that accepts commands from the outside) or a busy state (a state that does not accept commands from the outside).

[0048] The NAND bus NB includes, for example, multiple wirings corresponding to various signals. Specifically, it includes i data lines DW corresponding to signals DQ0 to DQ(i-1) respectively, and multiple logic lines LW corresponding to signals DQS, DQSn, CEn, CLE, ALE, WEn, RE, REn, WPn, and RBn respectively.

[0049] In this specification, the amount of information that a bus can transmit at one time will be referred to as the bus width. For example, in the case of an internal bus with a 32-bit bus width, the bus includes 32 data lines and can transmit 32 bits of data at a time. For example, a NAND bus NB including 8 instruction, address, and data shared lines has an 8-bit bus width. Furthermore, the bus width of a NAND bus NB is not limited to 8 bits. It can also have any number of bits, such as a multiple of 4 or a power of 2.

[0050] Internal buses IB1, IB2, and IB3 serve as paths for transmitting information within the semiconductor memory device 4. For example, the width of internal bus IB1 is equal to the width of the NAND bus NB. Alternatively, for example, the width of internal bus IB1 is narrower than the width of internal bus IB2.

[0051] The input / output module 10 includes an input / output circuit 11 and a logic control circuit 12.

[0052] The input / output circuit 11 transmits and receives signals DQ0 to DQ(i-1), signal DQS, and signal DQSn with the memory controller 3. The input / output circuit 11 is connected to the first internal bus IB1. The input / output circuit 11 transmits information based on the received signals DQ0 to DQ(i-1) to the serial / parallel converter 13 via the first internal bus IB1. Additionally, the input / output circuit 11 outputs signals DQ0 to DQ(i-1) based on the information received from the serial / parallel converter 13 via the first internal bus IB1.

[0053] The logic control circuit 12 receives signals CEn, CLE, ALE, WEn, RE, REn, and WPn, and sends signal RBn. The logic control circuit 12 then sends signals based on the received signals to the input / output circuit 11 and the sequencer 18.

[0054] The serial / parallel converter 13 converts serial signals to parallel signals. The serial / parallel converter 13 is connected to the input / output circuit 11 via the first internal bus IB1 and to the register 14 via the second internal bus IB2. The serial / parallel converter 13 amplifies the bus width of the signal received from the first internal bus IB1 and sends it to the second internal bus IB2. The serial / parallel converter 13 also amplifies the bus width of the signal received from the second internal bus and sends it to the first internal bus IB1.

[0055] Register 14 stores the received information and outputs the stored information to the outside. Register 14 is connected to the serial / parallel converter circuit 13 via the second internal bus IB2 and to the sense amplifier 17 via the third internal bus IB3. For example, register 14 stores the information received from the serial / parallel converter circuit 13 and outputs it to the sense amplifier 17. Register 14 stores the information received from the sense amplifier 17 and outputs it to the serial / parallel converter circuit 13.

[0056] The storage cell array 15 stores data non-volatilely. The storage cell array 15 includes multiple bit lines BL, multiple word lines WL, and multiple storage cells MT. The multiple storage cells MT are arranged, for example, in the row and column directions. The multiple bit lines BL are arranged corresponding to the column direction and connected to the multiple storage cells MT corresponding to the same column. The multiple word lines WL are arranged corresponding to the row direction and connected to the multiple storage cells MT corresponding to the same row.

[0057] The row decoder 16 receives the row address from the register 14 and selects the memory cell MT in the row direction based on the row address. Furthermore, the row decoder 16 applies a voltage to the selected memory cell MT in the row direction.

[0058] When reading data, the read amplifier 17 reads the data read from memory cell MT to bit line BL and transfers the read data to register 14. When writing data, the read amplifier 17 transfers the write data written via bit line BL to memory cell MT. In addition, the read amplifier 17 receives the column address from register 14 and outputs the data of the column based on that column address.

[0059] The sequencer 18 controls the overall operation of the semiconductor memory device 4. For example, the sequencer 18 receives instructions from the register 14 and performs read operations based on the received instructions. In addition, the sequencer 18 controls the input / output circuit 11 based on the control of the logic control circuit 12.

[0060] Figure 3 An example of the structure of the memory system 1 according to the first embodiment is shown. For example... Figure 3 As shown, the memory system 1 includes a memory chip MC and a CMOS chip CC, with the lower surface of the memory chip MC and the upper surface of the CMOS chip CC attached together. The dimensions of the memory chip MC in the XY plane are approximately equal to the dimensions of the CMOS chip CC in the XY plane. The memory chip MC includes, for example, a structure corresponding to the memory cell array 15. The memory chip MC is manufactured using NAND technology. The CMOS chip CC includes, for example, a structure corresponding to the input / output module 10. The CMOS chip CC is manufactured using CMOS technology. Details regarding the circuitry included in each of the memory chip MC and the CMOS chip CC will be described later.

[0061] The memory chip MC has multiple bonding pads BP on its lower part. The bonding pads BP of the memory chip MC are electrically connected to the circuitry within the memory chip MC. The CMOS chip CC has multiple bonding pads BP on its upper part. The bonding pads BP of the CMOS chip CC are electrically connected to the circuitry within the CMOS chip CC. The bonding pads BP of the memory chip MC and the CMOS chip are arranged in an overlapping manner when the memory chip MC and the CMOS chip CC are aligned and overlapped. The bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are bonded together and electrically connected.

[0062] Figure 4 This illustrates an example of the configuration of the various structures in the memory system 1 of the first embodiment. For example... Figure 4As shown, in the memory system 1 of the first embodiment, the CMOS chip CC includes a memory controller 3 and a portion of the semiconductor memory device 4, while the memory chip MC includes the portion of the semiconductor memory device 4 not included in the CMOS chip CC. Specifically, the CMOS chip CC includes the memory controller 3, the input / output module 10 of the semiconductor memory device 4, the serial / parallel conversion circuit 13, the register 14, and the sequencer 18. The memory chip MC includes the memory cell array 15, the row decoder 16, and the sense amplifier 17 of the semiconductor memory device 4.

[0063] The NAND bus NB, for example, has an 8-bit bus width and is located within the CMOS chip CC. The first internal bus IB1, for example, has an 8-bit bus width and is located within the CMOS chip CC. The second internal bus IB2, for example, has a 32-bit bus width and is located within the CMOS chip CC. The third internal bus IB3, for example, has a 32-bit bus width and spans the CMOS chip CC and the memory chip MC. Specifically, the third internal bus IB3 includes electrical connections based on bonding pads BP.

[0064] [1-2] Effects of the first embodiment

[0065] The memory system 1 according to the first embodiment described above can improve the communication bandwidth of the memory system 1. Hereinafter, the effects of the memory system 1 according to the first embodiment will be explained in detail.

[0066] To achieve high capacity in semiconductor memory devices, it is preferable to increase the dedicated area of ​​the memory cell array. In this regard, a known semiconductor memory device has a bonding structure in which the NAND chip with the memory cell array and the CMOS chip with the peripheral circuitry of the memory cell array are made of different wafers and these chips are bonded together.

[0067] The bonding structure increases the dedicated area of ​​the memory cell array and reduces the chip area. Furthermore, the bonding structure can suppress the degradation of CMOS circuitry caused by the high-temperature thermal processing of NAND flash memory cell arrays. On the other hand, the bonding structure is formed by bonding two chips of approximately equal size together. Therefore, while reducing the area of ​​surrounding circuitry relative to the area of ​​the memory cell array, free space may be created within the CMOS chip's core area (CC).

[0068] Furthermore, with the increasing volume of data processed by host devices, there is a demand for higher communication speeds within memory systems. To achieve this, wiring-based losses, such as those in the bonding wires between the semiconductor memory device and the memory controller, and in the printed circuit board, must also be considered. Therefore, parasitic components such as parasitic resistance, capacitance, and inductance of the wiring should preferably be suppressed as much as possible.

[0069] Therefore, in the memory system 1 of the first embodiment, the memory controller 3 is disposed on the CMOS chip CC. Specifically, the memory controller 3 and the input / output module 10 of the semiconductor memory device 4 are disposed on the CMOS chip CC. With this configuration, the wiring between the memory controller 3 and the semiconductor memory device 4 is arranged within the CMOS chip CC at a very short distance, which can suppress parasitic components. As a result, the memory system 1 of the first embodiment can improve the operating frequency and increase the communication bandwidth.

[0070] Furthermore, in the memory system 1 of the first embodiment, since the memory controller 3 can be configured in the free space of the CMOS chip CC, a separate chip with the memory controller 3 installed is not required. Moreover, in the memory system 1 of the first embodiment, the process of connecting the memory controller 3 to the semiconductor memory device 4 is incorporated into the forming process of the CMOS chip CC, and the manufacturing process of forming the memory controller 3 is appropriately incorporated into the manufacturing process of forming the peripheral circuitry of the semiconductor memory device 4. As a result, the memory system 1 of the first embodiment can reduce the cost of forming and connecting the memory controller 3.

[0071] [1-3] Variations of the first embodiment

[0072] The memory system 1 of the first embodiment can be modified in various ways. Hereinafter, various examples of modifications are shown.

[0073] (First variation of the first embodiment)

[0074] Figure 5 An example of the configuration of the various structures in the memory system 1 of the first modification of the first embodiment is shown. For example... Figure 5As shown, in the memory system 1 of the first variation of the first embodiment, the bus widths of the NAND bus NB, the first internal bus IB1, the second internal bus IB2, and the third internal bus IB3 are different from those of the memory system 1 of the first embodiment. Specifically, in the memory system 1 of the first variation of the first embodiment, the NAND bus NB has a bus width of 32 bits, the first internal bus IB1 has a bus width of 32 bits, the second internal bus IB2 has a bus width of 64 bits, and the third internal bus IB3 has a bus width of 64 bits. The other structures of the memory system 1 of the first variation of the first embodiment are the same as those of the first embodiment.

[0075] The amount of information a bus can transmit at a time depends on its width. Increasing the bus width is considered as a method for high-speed communication. However, increasing the bus width increases the number of signal lines included in the bus, potentially increasing the area and volume required to mount the bus. For example, if the controller and semiconductor memory devices are located on separate chips and mounted on separate printed circuit boards, increasing the bus width of the NAND bus (NB) would further require additional pins on each chip and wiring on the printed circuit board to accommodate the increased signal lines.

[0076] In the memory system 1 of the first embodiment, the NAND bus NB is disposed within the CMOS chip CC. Therefore, when the bus width of the NAND bus NB is increased as in the memory system 1 of the first variation of the first embodiment, the design change accompanying the increase in bus width is completed within the CMOS chip CC. That is, the memory system 1 of the first variation of the first embodiment can increase the bus width of the NAND bus NB without increasing the number of chip pins or the wiring on the printed circuit board.

[0077] In the memory system 1 of the first variation of the first embodiment, corresponding to the case where the bus width of the NAND bus NB is increased to 32 bits, the bus width of the first internal bus IB1 is also increased to 32 bits. Furthermore, the bus widths of the second internal bus IB2 and the third internal bus IB3 are also increased to 64 bits. The first internal bus IB1 and the second internal bus IB2 are located within the CMOS chip CC, just like the NAND bus NB, thus allowing the bus width to be increased without increasing the number of chip pins or the wiring on the printed circuit board.

[0078] The third internal bus IB3 spans the CMOS chip CC and the memory chip MC, and includes electrical connections based on bonding pads BP. Therefore, if the bus width of the third internal bus IB3 is increased, the number of signal lines included in the third internal bus IB3 can also be increased. However, in the bonding structure, the process of connecting the bonding pads BP is performed together, so even if the number of bonding pads BP increases, the increase in cost can be suppressed. Therefore, the memory system 1 of the first modification of the first embodiment can suppress the increase in cost and increase the bus width of the third internal bus IB3.

[0079] Thus, the memory system 1 of the first variation of the first embodiment, compared with the memory system 1 of the first embodiment, can suppress the increase in cost and expand the bus width of each bus, and can improve the communication bandwidth.

[0080] Furthermore, increasing the bus width can, for example, suppress the rise in operating frequency and increase the communication bandwidth. In the first variation of the memory system 1 of the first embodiment, the NAND bus NB has a bus width four times that of the NAND bus NB of the memory system 1 of the first embodiment. Here, for example, if the operating frequency of the NAND bus NB of the memory system 1 of the first variation of the first embodiment is 1 / 3 of the operating frequency of the NAND bus NB of the memory system 1 of the first embodiment, the communication bandwidth of the memory system 1 of the first variation of the first embodiment can achieve 4 / 3 times the communication speed of the memory system 1 of the first embodiment. Thus, increasing the bus width can suppress the operating frequency and increase the communication bandwidth of the bus compared to not increasing the bus width. Furthermore, by reducing the operating frequency of the bus, the installation of the circuit can be simplified. Therefore, the development cost and installation cost of the memory system 1 can be reduced.

[0081] (Second variation of the first embodiment)

[0082] Figure 6 This illustrates an example of the configuration of various structures in the memory system 1 of the second modification of the first embodiment. For example... Figure 6As shown, the memory system 1 of the second modification of the first embodiment has the following structure: compared to the memory system 1 of the first modification of the first embodiment, the NAND bus NB is omitted, and a data bus DB and a logic bus LB are also included. Furthermore, the semiconductor memory device 4 included in the memory system 1 of the second modification of the first embodiment has the following structure: compared to the semiconductor memory device 4 included in the memory system 1 of the first modification of the first embodiment, the input / output module 10 is replaced by an input / output module 10a, and the serial / parallel conversion circuit 13, the first internal bus IB1, and the second internal bus IB2 are omitted.

[0083] In the memory system 1 of the second variation of the first embodiment, the memory controller 3 and the semiconductor memory device 4 are connected via a data bus DB and a logic bus LB. The data bus DB is a bus that transmits signals corresponding to the signals DQ0 to DQ(i-1) in the first embodiment. The logic bus LB is a bus that transmits signals corresponding to the signals DQS, DQSn, CEn, CLE, ALE, WEn, RE, REn, WPn, and RBn in the first embodiment. Other structures are the same as in the first variation of the first embodiment.

[0084] In the semiconductor memory device 4 of the second variation of the first embodiment, the memory controller 3 and the register 14 are directly connected by a data bus DB with a bus width of 64 bits. That is, the serial / parallel conversion circuit and the input / output module are not included in the signal path between the memory controller 3 and the register 14. Therefore, the memory system 1 of the second variation of the first embodiment can reduce the circuit size and can increase the bus width of the bus connecting the memory controller 3 and the semiconductor memory device 4. As a result, the memory system 1 of the second variation of the first embodiment can improve the communication bandwidth.

[0085] (Third variation of the first embodiment)

[0086] Figure 7 An example of the configuration of the various structures in the memory system 1 of the third variation of the first embodiment is shown. For example... Figure 7 As shown, the memory system 1 of the third variation of the first embodiment has the following structure: relative to the first variation of the first embodiment, the NAND bus NB is replaced by a first NAND bus NB1 and a second NAND bus NB2, and also includes a switching module 5, a first test bus TB1 and a second test bus TB2.

[0087] The memory controller 3 and the switching module 5 are connected via a first NAND bus NB1. The first NAND bus NB1 has, for example, a bus width of 32 bits. The switching module 5 is connected to the input / output module 10 included in the semiconductor memory device 4 via a second NAND bus NB2. The second NAND bus NB2 has, for example, a bus width of 32 bits. The switching module 5 is connected to a first test bus TB1 and a second test bus TB2, respectively. The first test bus TB1 and the second test bus TB2 are configured to be externally connected to the memory system 1. The first test bus TB1 has, for example, a bus width of 8 bits. The second test bus TB2 has, for example, a bus width of 8 bits.

[0088] The first test bus TB1 is connected, for example, to a memory controller 3a disposed externally to the memory system 1. The memory controller 3a is connected to a host device (not shown) via the host bus HB. The second test bus TB2 is connected, for example, to a semiconductor memory device 4a disposed externally to the memory system 1.

[0089] The switching module 5 receives the signal SW and switches the signal based on the signal SW. Furthermore, the switching module 5 has the function of performing serial / parallel switching when two buses with different bus widths are connected. For example, when the switching module 5 connects the first NAND bus NB1 to the second NAND bus NB2, the memory controller 3 communicates with the semiconductor memory device 4 and functions as the memory system 1. For example, when the switching module 5 connects the first test bus TB1 to the second NAND bus NB2, the memory controller 3a communicates with the semiconductor memory device 4 and can control the operation of the semiconductor memory device 4. For example, when the switching module 5 connects the first NAND bus NB1 to the second test bus TB2, the memory controller 3 communicates with the semiconductor memory device 4a and can control the operation of the semiconductor memory device 4a. Other structures are the same as in the first variation of the first embodiment.

[0090] For the memory controller 3 and the semiconductor memory device 4 constituting the memory system 1, it is considered to conduct operation tests separately. In the memory system 1 of the third variation of the first embodiment, the external memory controller 3a can be connected to the semiconductor memory device 4, or the memory controller 3 can be connected to the external semiconductor memory device 4a, via the switching module 5, the first test bus TB1, and the second test bus TB2. Therefore, the operation of the semiconductor memory device 4 within the memory system 1 can be confirmed via the external memory controller 3a. Furthermore, the operation of the memory controller 3 within the memory system 1 can be confirmed via the external semiconductor memory device 4a.

[0091] Furthermore, in the memory system 1 of the third variation of the first embodiment, the switching module 5 has the function of performing serial / parallel switching. Therefore, in the memory system 1 of the third variation of the first embodiment, an external memory controller 3a can be connected using a first test bus TB1 with a bus width narrower than the first NAND bus NB1. Additionally, an external semiconductor memory device 4a can be connected using a second test bus TB2 with a bus width narrower than the second NAND bus NB2.

[0092] To connect the memory system 1 to external circuitry, it is considered to provide pads for connection on the chip, or to provide pins for connection from the package including the memory system 1 to the outside. In the memory system 1 of the third variation of the first embodiment, the bus widths of the first test bus TB1 and the second test bus TB2 are smaller than those of the first NAND bus NB1 and the second NAND bus NB2. Therefore, the number of pads, pins, etc. used when connecting the memory system 1 to external circuitry can be reduced.

[0093] Furthermore, the operating frequencies of the first NAND bus NB1, the second NAND bus NB2, the first test bus TB1, and the second test bus TB2 can be arbitrarily set. For example, if the first NAND bus has a 32-bit bus width and the first test bus TB1 has an 8-bit bus width, the operating frequency of the first test bus TB1 can be set to four times that of the first NAND bus NB1. By setting the operating frequency in this way, the same amount of information can be transmitted even when the bus width of the first test bus TB1 is narrower than that of the first NAND bus NB1.

[0094] Alternatively, the operating frequency of the first test bus TB1 can be set below the operating frequency of the first NAND bus NB1. If the operating frequency is set in this way, communication via the first test bus TB1 can be slower than communication via the first NAND bus NB1, but operation tests can still be performed.

[0095] In the third variation of the first embodiment, the example described is that the bus widths of the first test bus TB1 and the second test bus TB2 are each narrower than the bus widths of the first NAND bus NB1 and the second NAND bus NB2. However, the relationship of bus widths is not limited to this. For example, the bus width of the first NAND bus NB1 and the bus width of the first test bus TB1 may also be equal.

[0096] Alternatively, the external memory controller 3a can be configured to connect to a different host device than the memory controller 3 included in the memory system 1. For example, if the memory controller 3 included in the memory system 1 meets the UFS standard, the external memory controller 3a can also meet the eMMC (embedded MMC) standard. In this configuration, by combining the memory system 1 and the external memory controller 3a, it is possible to meet a standard different from the standard met by the memory system 1, such as the eMMC standard.

[0097] (Fourth variation of the first embodiment)

[0098] Figure 8 An example of the configuration of the various structures in the memory system 1 of the fourth variation of the first embodiment is shown. For example... Figure 8 As shown, the memory system 1 of the fourth variation of the first embodiment has the following structure: relative to the memory system 1 of the first embodiment, the NAND bus NB is continuously provided outside the CMOS chip CC, and a semiconductor memory device 4b is also included.

[0099] In the memory system 1 of the fourth variation of the first embodiment, a NAND bus NB is continuously disposed inside and outside the CMOS chip CC. A memory controller 3, a semiconductor memory device 4, and a semiconductor memory device 4b are connected to the NAND bus NB. The semiconductor memory device 4b can be configured arbitrarily as long as it can perform operations such as storing or reading data based on instructions received from the memory controller 3 via the NAND bus NB. For example, it can have a structure in which the CMOS chip CC and the memory chip MC are bonded together, it can be constructed on a single semiconductor substrate, or it can have a structure in which multiple semiconductor substrates are stacked. Other structures are the same as in the fourth variation of the first embodiment.

[0100] The memory system 1 of the fourth variation of the first embodiment can expand its storage capacity by connecting multiple semiconductor memory devices to the NAND bus NB. Furthermore, in the fourth variation of the first embodiment, an example is shown where semiconductor memory devices 4 and 4b are connected to the NAND bus NB, but the number of semiconductor memory devices connected to the NAND bus NB is not limited to this. The memory system 1 of the fourth variation of the first embodiment can further expand its storage capacity by connecting multiple semiconductor memory devices to the NAND bus NB.

[0101] (Fifth variation of the first embodiment)

[0102] Figure 9An example of the configuration of the various structures in the memory system 1 of the fifth variation of the first embodiment is shown. For example... Figure 9 As shown, the memory system 1 of the fifth variation of the first embodiment further includes a chip AC, relative to the memory system 1 of the first embodiment, and a portion of the structure having the function of the memory controller 3 is disposed in the chip AC.

[0103] In the memory system 1 of the fifth variation of the first embodiment, the memory controller 3 includes a host interface module 31 (HOSTIF module), a control unit 32, and a NAND interface module 33 (NANDIF module). The host interface module 31 and the control unit 32 are disposed on the CMOS chip AC. The NAND interface module 33 is disposed on the CMOS chip CC.

[0104] The host interface module 31 is connected to the host bus HB and communicates with the host device 2 via the host bus HB. The host interface module 31 sends signals received from the host device 2 to the control unit 32. In addition, the host interface module 31 sends signals received from the control unit 32 to the host device 2 via the host bus HB.

[0105] The control unit 32 controls the overall operation of the memory controller 3. The control unit 32 is connected to the NAND interface module 33 via the controller bus CB. The control unit 32 receives signals from the host interface module 31 and sends signals to the NAND interface module 33. Additionally, the control unit 32 receives signals from the NAND interface module 33 and sends signals to the host interface module 31.

[0106] The NAND interface module 33 is connected to the control unit 32 via the controller bus CB, and to the input / output module 10 included in the semiconductor memory device 4 via the NAND bus NB. The NAND interface module 33 sends signals received from the control unit 32 to the input / output module 10. In addition, the NAND interface module 33 sends signals received from the input / output module to the control unit 32.

[0107] The controller bus CB is, for example, an AHB bus. The bus width of the controller bus CB is, for example, 32 bits.

[0108] For example, when the CMOS chip CC and memory chip MC are small in size, or when the circuitry of the memory controller 3 is large, it is difficult to install all the controllers on the CMOS chip CC. In the memory system 1 of the fifth variation of the first embodiment, the NAND interface module 33 of the memory controller 3 is provided in the CMOS chip CC. Moreover, the circuitry other than the NAND interface module 33 in the memory controller 3 is provided in the chip AC, and the chip AC is connected to the CMOS chip CC via the controller bus CB. Other structures are the same as in the first embodiment.

[0109] With this configuration, in the memory system 1 of the fifth variation of the first embodiment, even if all the memory controllers 3 are not provided on the CMOS chip CC, the NAND bus NB can be provided inside the CMOS chip CC in the same way as in the memory system 1 of the first embodiment. Furthermore, the controller bus CB connecting the chip AC and the CMOS chip CC is, for example, a wide bus with a 32-bit bus width. Therefore, in the memory system 1 of the fifth variation of the first embodiment, the communication between the chip AC and the CMOS chip CC can be accelerated.

[0110] (Sixth variation of the first embodiment)

[0111] Figure 10 This illustrates an example of the configuration of various structures in the memory system 1 of the sixth modification of the first embodiment. For example... Figure 10 As shown, the memory system 1 of the sixth variation of the first embodiment has the following structure: compared with the memory system 1 of the fifth variation of the first embodiment, it further includes a NAND interface module 33a and a semiconductor memory device 4c.

[0112] In the memory system 1 of the sixth variation of the first embodiment, the NAND interface module 33a is connected to the controller bus CB. The NAND interface module 33a is connected to the semiconductor memory device 4c via the NAND bus NB. The NAND interface module 33a and the semiconductor memory device 4c may, for example, have a structure in which a CMOS chip CC and a memory chip MC are bonded together, or they may be set as separate chips, or they may be formed on a single semiconductor substrate. Other structures are the same as in the fifth variation of the first embodiment.

[0113] Thus, by connecting multiple NAND interface modules and semiconductor memory devices to the controller bus CB, the storage capacity of the memory system 1 can be expanded. Furthermore, in the sixth variation of the first embodiment, an example is shown where NAND interface modules 33 and 33a are connected to the controller bus CB; however, the number of connected NAND interface modules and the number of semiconductor memory devices included in the memory system 1 are not limited to this. The memory system 1 of the sixth variation of the first embodiment can further expand its storage capacity by providing multiple NAND interface modules and semiconductor memory devices.

[0114] (Seventh and Eighth Modifications of the First Embodiment)

[0115] Figure 11 This illustrates an example of the configuration of various structures in the memory system 1 of the seventh modification of the first embodiment. For example... Figure 11 As shown, the memory system 1 of the seventh variation of the first embodiment differs from the memory system 1 of the first embodiment in that the line decoder 16 is located on the CMOS chip CC. Other structures are the same as in the first embodiment.

[0116] Figure 12 This illustrates an example of the configuration of various structures in the memory system 1 of the eighth modification of the first embodiment. For example... Figure 12 As shown, the memory system 1 of the eighth variation of the first embodiment differs from the memory system 1 of the first embodiment in that a line decoder 16 and a readout amplifier 17 are provided on the CMOS chip CC. The other structures are the same as those of the first embodiment.

[0117] The memory chip MC is a chip manufactured using NAND technology, which includes the fabrication process of a memory cell array. The memory chip MC may include at least a memory cell array 15, and each of the line decoder 16 and the sense amplifier 17 may be disposed on the memory chip MC or on the CMOS chip CC. Regarding the first to sixth modifications of the first embodiment, the same modifications as those in the seventh and eighth modifications of the first embodiment can also be made.

[0118] [2] Second Embodiment

[0119] The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in its chip structure and connection method. Hereinafter, the differences between the semiconductor memory device of the second embodiment and the first embodiment will be described.

[0120] [2-1] Structure

[0121] Figure 13An example of a cross-sectional structure of the memory system 1 according to the second embodiment is shown. For example... Figure 13 As shown, the memory system 1 of the second embodiment includes core chips 100-1 to 100-8, IF chip 200, controller chip 300, sealing resin 40, packaging substrate 51, a plurality of solder balls 52, a plurality of spacers 53, adhesive 54, support plate 55, a plurality of through electrodes 56, a plurality of solder balls 57, 58 and 59, and redistribution layers 61 and 62 and package 64.

[0122] Each of the core chips 100-1 to 100-8 includes at least a memory cell array. Each of the core chips 100-1 to 100-8 is manufactured using NAND technology. The IF chip 200 includes at least an input / output module 10. The controller chip 300 includes at least a portion of the memory controller 3. The controller chip 300 is manufactured using CMOS technology. Details regarding the circuitry included in each chip will be described later.

[0123] A redistribution layer 62 is disposed on the upper part of the package substrate 51. The package substrate 51 is a BGA (Ball Grid Array) substrate having a plurality of solder balls 52, which serve as terminals for connection to external devices such as host device 2. The package substrate 51 may include, for example, BT (bismaleimide triazine).

[0124] An IF chip 200 and a controller chip 300 are disposed on the upper part of the packaging substrate 51 and the redistribution layer 62. The IF chip 200 and the controller chip 300 are as used in the first embodiment. Figure 3 The example illustrated is similar, featuring a fitted structure. Figure 13 In the example shown, the configuration is such that the upper part is the IF chip 200 and the lower part is the controller chip 300. Figure 13 The cross-sectional lines are omitted, but the space between the packaging substrate 51 and the controller chip 300 is filled with sealing resin 40. Alternatively, the structure formed by bonding the IF chip 200 and the controller chip 300 can also be directly disposed on the packaging substrate 51 without passing through the sealing resin 40.

[0125] A redistribution layer 61 is disposed on the upper part of the structure in which the IF chip 200 and the controller chip 300 are bonded. A stack of core chips 100-1 to 100-8 is disposed on the upper part of the redistribution layer 61. A spacer 53 is provided between two adjacent core chips 100 to ensure spacing. The spacer 53 can be, for example, an adhesive insulating resin such as epoxy resin, polyimide resin, acrylic resin, phenolic resin, or pentenecyclobutene resin. Surface wiring and back wiring are formed on each core chip 100, and each core chip 100 is stacked with the surface wiring facing downwards (face down).

[0126] The upper surface of the core chip 100-8, which is stacked on top, is bonded to the support plate 55 via adhesive 54. The adhesive 54 can be an insulating resin or a touch film. The support plate 55 prevents the core chip 100 from being damaged by mechanical stress during processing of the stacked core chip 100. The support plate 55 can also be, for example, a metal plate such as a lead frame. The material of the support plate 55 can be, for example, Cu or 42 alloy (Fe-Ni alloy).

[0127] Multiple through electrodes 56 are provided on core chips 100-1 to 100-7, which are stacked above the top core chip 100-8. Although not shown in the figure, the through electrodes 56 are insulated from the core chip 100 by a sidewall insulating film. The material of the through electrodes 56 can be, for example, Cu, Ni, Al, etc. The through electrodes 56 of core chips 100-1 to 100-7 are connected to the through electrodes of core chips 100-2 to 100-8 provided on the upper side by solder balls 57. Thus, the through electrodes 56 located at the same position in the XY plane of core chips 100-1 to 100-8 are interconnected, and core chips 100-1 to 100-8 are interconnected by through electrodes 56 and solder balls 57.

[0128] The through-electrode of the bottom-layer core chip 100-1 is electrically connected to the wiring within the redistribution layer 61. The IF chip 200 is electrically connected to the wiring within the redistribution layer 61 via multiple solder balls 58. The wiring within the redistribution layer 61 is electrically connected to the wiring within the redistribution layer 62 via solder balls 59. The wiring within the redistribution layer 62 is connected to the solder balls 52 via wiring 63. That is, the stack of core chips 100 is electrically connected to the structure formed by bonding the IF chip 200 and the controller chip 300. In addition, the stack of core chips 100 and the structure formed by bonding the IF chip 200 and the controller chip 300 are each electrically connected to the external host device 2 via multiple wiring layers and solder balls.

[0129] The stacked core chip 100 and the structure formed by bonding the IF chip 200 and the controller chip 300 are disposed within a package 64 filled with sealing resin 40. That is, the stacked core chip 100, the IF chip 200, and the controller chip 300 are sealed in a single package by the sealing resin. The package 64 may also be made of the same material as the sealing resin 40.

[0130] Alternatively, the controller chip 300 can also be connected to the host device 2 via the IF chip 200. For example, the IF chip 200 may also include a through electrode extending from the bonding surface of the IF chip 200 to its back surface. Furthermore, the controller chip 300 can also be connected to the solder ball 58 via the through electrode disposed on the IF chip 200.

[0131] Furthermore, the controller chip 300 can also be connected to the host device 2 without going through the IF chip 200. Specifically, it can also be electrically connected to the wiring in the redistribution layer 61 without going through the IF chip 200. The wiring in the redistribution layer 61 is electrically connected to the wiring in the redistribution layer 62 via solder balls 59. The wiring in the redistribution layer 62 is connected to the solder balls 52 via wiring 63. Alternatively, the controller chip 300 can also be connected to the wiring in the redistribution layer 62 without going through the wiring in the redistribution layer 61, and connected to the solder balls 52 via wiring 63. In this case, the controller chip 300 can also be connected to the solder balls 58 via a through electrode provided on the controller chip 300.

[0132] Figure 14 This illustrates an example of the configuration of the various structures in the memory system 1 of the second embodiment. For example... Figure 14 As shown, in the memory system 1 of the second embodiment, multiple core chips 100 each include a memory cell array 15, a row decoder 16, a sense amplifier 17, a portion of a register 14, and a portion of a sequencer 18. The IF chip 200 includes an input / output module 10, a serial / parallel conversion circuit 13, a portion of the register 14, and a portion of the sequencer 18. The controller chip 300 includes a memory controller 3.

[0133] The NAND bus NB, for example, has an 8-bit bus width and is configured to span the controller chip 300 and the IF chip 200. The NAND bus NB includes electrical connections based on bonding pads. A third internal bus IB3 is located within the core chip 100. Other structures are the same as in the first embodiment.

[0134] In addition, Figure 14The example shown illustrates a scenario where a portion of register 14 and a portion of sequencer 18 are respectively configured in multiple core chips 100 and IF chip 200. The configuration of register 14 and sequencer 18 is not limited to this. For example, register 14 may be configured only in IF chip 200, or it may be configured in multiple core chips 100. Similarly, sequencer 18 may be configured only in IF chip 200, or it may be configured in multiple core chips 100.

[0135] [2-2] Effects of the second embodiment

[0136] The memory system 1 according to the second embodiment described above, similar to the first embodiment, can improve the communication bandwidth of the memory system 1. Hereinafter, details of the effects of the memory system 1 according to the second embodiment will be explained, highlighting the differences from the first embodiment.

[0137] In the memory system 1 of the second embodiment, the semiconductor memory device 4 is composed of multiple core chips 100 and IF chips 200. In the semiconductor memory device 4 included in the memory system 1 of the second embodiment, multiple core chips 100, including a memory cell array 15, are stacked, and the IF chips 200, including an input / output module 10, are shared by the multiple core chips 100. With this configuration, compared to the case of providing multiple semiconductor memory devices, cost can be suppressed and storage capacity increased.

[0138] Furthermore, the memory system 1 of the second embodiment has a structure in which an IF chip 200 including an input / output module 10 is bonded to a controller chip 300 including a memory controller 3. With this configuration, the NAND bus NB included in the memory system 1 of the second embodiment is arranged throughout the IF chip 200 and the controller chip 300 in a path that includes connections based on bonding pads.

[0139] Connections based on bonding pads, for example, can suppress parasitic components of signal lines compared to connections using wiring on a printed circuit board or connections using bonding wires. Therefore, in the memory system 1 of the second embodiment, similar to the memory system 1 of the first embodiment, communication between the memory controller 3 and the semiconductor memory device 4 can be accelerated.

[0140] [2-3] Variations of the second embodiment

[0141] The memory system 1 of the second embodiment can be modified in various ways. Examples of various modifications are shown below.

[0142] (First variation of the second embodiment)

[0143] Figure 15This illustrates an example of the configuration of various structures in the memory system 1 of the first modification of the second embodiment. For example... Figure 15 As shown, the memory system 1 of the first variant of the second embodiment undergoes the same modifications as the first variant of the first embodiment compared to the memory system 1 of the second embodiment. Specifically, the memory system 1 of the first variant of the second embodiment differs from the memory system 1 of the second embodiment in that the bus widths of the NAND bus NB, the first internal bus IB1, the second internal bus IB2, and the third internal bus IB3 are different. Specifically, in the memory system 1 of the first variant of the second embodiment, the NAND bus NB has a 32-bit bus width, the first internal bus IB1 has a 32-bit bus width, the second internal bus IB2 has a 64-bit bus width, and the third internal bus IB3 has a 64-bit bus width. Other structures are the same as those in the memory system 1 of the second embodiment.

[0144] The memory system 1 of the first variant of the second embodiment, like the memory system 1 of the first variant of the first embodiment, can suppress the increase in cost and expand the bus width of each bus, thereby increasing the communication bandwidth.

[0145] (Second variation of the second embodiment)

[0146] Figure 16 This illustrates an example of the configuration of various structures in the memory system 1 of the second modification of the second embodiment. For example... Figure 16 As shown, the memory system 1 of the second modification of the second embodiment undergoes the same modifications as the memory system 1 of the first modification of the second embodiment. Specifically, the memory system 1 of the second modification of the second embodiment differs from the memory system 1 of the first modification of the second embodiment in that it uses a data bus DB and a logic bus LB for communication instead of a NAND bus NB. Furthermore, the semiconductor memory device 4 included in the memory system 1 of the second modification of the second embodiment has the following structure: compared to the semiconductor memory device 4 included in the memory system 1 of the first modification of the second embodiment, the input / output module 10 is replaced with an input / output module 10a, and the serial / parallel conversion circuit 13, the first internal bus IB1, and the second internal bus IB2 are omitted.

[0147] The memory system 1 of the second modification of the second embodiment, like the memory system 1 of the second modification of the first embodiment, can reduce the circuit size and increase the bus width of the bus connecting the memory controller 3 and the semiconductor memory device 4. Therefore, the memory system 1 of the second modification of the second embodiment can increase the communication bandwidth.

[0148] (Third variation of the second embodiment)

[0149] Figure 17 An example of the configuration of the various structures in the memory system 1 of the third variation of the second embodiment is shown. For example... Figure 17 As shown, the memory system 1 of the third variation of the second embodiment differs from the memory system 1 of the second embodiment in that the controller is provided throughout the controller chip 300 and the IF chip 200, and the controller chip 300 and the IF chip 200 are connected through the controller bus CB.

[0150] In the memory system 1 of the third variation of the second embodiment, the memory controller 3 includes a host interface module 31 (HOST IF module), a control unit 32, and a NAND interface module 33 (NAND IF module). The host interface module 31 and the control unit 32 are disposed in the controller chip 300. The NAND interface module 33 is disposed in the IF chip 200.

[0151] The host interface module 31 is connected to the host bus HB and communicates with the host device 2 and the host bus HB. The host interface module 31 sends signals received from the host device 2 to the control unit 32. In addition, the host interface module 31 sends signals received from the control unit 32 to the host device 2 via the host bus HB.

[0152] The control unit 32 controls the overall operation of the memory controller 3. The control unit 32 is connected to the NAND interface module 33 via the controller bus CB. The control unit 32 receives signals from the host interface module 31 and sends signals to the NAND interface module 33. Additionally, the control unit 32 receives signals from the NAND interface module 33 and sends signals to the host interface module 31.

[0153] The NAND interface module 33 is connected to the control unit 32 via the controller bus CB, and to the input / output module 10 included in the semiconductor memory device 4 via the NAND bus NB. The NAND interface module 33 sends signals received from the control unit 32 to the input / output module 10. In addition, the NAND interface module 33 sends signals received from the input / output module to the control unit 32.

[0154] The controller bus CB is, for example, an AHB bus. The bus width of the controller bus CB is, for example, 32 bits.

[0155] For example, if the circuitry in the controller chip 300 is large and the circuitry in the IF chip 200 is small, and the controller chip 300 and the IF chip 200 are arranged with equal dimensions, the integration density of the smaller chip is reduced, potentially increasing cost. In the memory system 1 of the third variation of the second embodiment, the memory controller 3 is provided throughout the controller chip 300 and the IF chip 200. Specifically, the NAND interface module 33 of the memory controller 3 is provided in the IF chip 200. Circuitry other than the NAND interface module 33 in the memory controller 3 is provided in the controller chip 300. The controller chip 300 and the IF chip 200 are connected via a controller bus CB.

[0156] With this configuration, in the memory system 1 of the third variation of the second embodiment, the circuit size of the circuit included in the controller chip 300 can be made approximately equal to the circuit size of the circuit included in the IF chip 200. This improves the integration density of both the controller chip 300 and the IF chip 200, and reduces costs. Furthermore, by placing the NAND bus NB inside the IF chip 200, parasitic components of the signal lines constituting the NAND bus NB can be suppressed. Moreover, the controller bus CB connecting the controller chip 300 and the IF chip 200 is, for example, a wide bus with a 32-bit bus width. Therefore, the memory system 1 of the third variation of the second embodiment can increase the communication bandwidth.

[0157] (Fourth variation of the second embodiment)

[0158] Figure 18 An example of the configuration of the various structures in the memory system 1 of the fourth variation of the second embodiment is shown. For example... Figure 18 As shown, in the memory system 1 of the fourth variation of the second embodiment, the register 14 is changed to register 14a, and the chip on which each circuit is configured is changed, compared to the memory system 1 of the second embodiment.

[0159] Specifically, register 14a is a larger register than the register 14 included in the memory system 1 of the second embodiment. Register 14a is provided throughout the IF chip 200 and multiple core chips 100, but is mostly provided in the IF chip 200.

[0160] A large portion of register 14a and a portion of sequencer 18 are located in IF chip 200. Register 14a occupies a large portion of the area of ​​IF chip 200. Memory controller 3, input / output module 10, and serial / parallel conversion circuit 13 are located in controller chip 300. NAND bus NB is located within controller chip 300. First internal bus IB1 is located within controller chip 300. Second internal bus IB2 is located across controller chip 300 and IF chip 200, including connections based on bonding pads.

[0161] Register 14a can be used, for example, as a cache memory in semiconductor memory device 4. In the memory system 1 of the fourth variation of the second embodiment, a large-capacity cache memory can be implemented using a large number of registers 14a.

[0162] (Fifth variation of the second embodiment)

[0163] Figure 19 An example of the configuration of the various structures in the memory system 1 of the fifth variation of the second embodiment is shown. For example... Figure 19 As shown, the memory system 1 of the fourth variation of the second embodiment has the following structure: relative to the memory system 1 of the fourth variation of the second embodiment, the NAND bus NB is provided all the way to the outside of the controller chip 300, and a semiconductor storage device 4d is also included.

[0164] In the memory system 1 of the fifth variation of the second embodiment, a NAND bus NB is continuously disposed inside and outside the controller chip 300. A semiconductor memory device 4d is connected externally to the controller chip 300 via the NAND bus NB. The semiconductor memory device 4d can be configured arbitrarily as long as it can perform operations such as storing or reading data based on instructions received from the memory controller 3 via the NAND bus NB. For example, it can have a structure with multiple substrates attached, it can be constructed on a single semiconductor substrate, or it can have a structure with multiple semiconductor substrates stacked on top of each other.

[0165] Thus, by connecting multiple semiconductor memory devices to the NAND bus NB, the storage capacity of the memory system 1 can be expanded. Furthermore, in the fifth variation of the second embodiment, an example is shown where semiconductor memory devices 4 and 4d are connected to the NAND bus NB, but the number of semiconductor memory devices connected to the NAND bus NB is not limited to this. The memory system 1 of the fifth variation of the second embodiment can further expand its storage capacity by connecting multiple semiconductor memory devices to the NAND bus NB.

[0166] (Sixth variation of the second embodiment)

[0167] Figure 20 An example of the configuration of the various structures in the memory system 1 of the sixth variation of the second embodiment is shown. For example... Figure 20 As shown, the memory system 1 of the sixth variation of the second embodiment has the following structure: compared with the memory system 1 of the second embodiment, it further includes a chip 400, a NAND interface module 33b, and a semiconductor storage device 4e, but does not include a serial / parallel conversion circuit, and the input / output module 10 is replaced by an input / output module 10a. In addition, the chip on which each circuit is configured is changed.

[0168] In the memory system 1 of the sixth variation of the second embodiment, the memory controller 3 includes a host interface module 31 (HOST IF module), a control unit 32, and a NAND interface module 33 (NAND IF module). The functions of the host interface module 31, the control unit 32, and the NAND interface module 33 are the same as those described in the example of the third variation of the second embodiment.

[0169] The IF chip 200 includes an input / output module 10a, a portion of a register 14, and a portion of a sequencer 18. The controller chip 300 includes a NAND interface module 33. The chip 400 includes a host interface module 31 and a control unit 32.

[0170] The register 14 of the IF chip 200 is connected to the NAND interface module 33 of the controller chip 300 via the data bus DB. The input / output module 10a of the IF chip is connected to the NAND interface module 33 of the controller chip 300 via the logic bus LB. The functions of the input / output module 10a, the data bus DB, and the logic bus LB are the same as those described in the second variation of the first embodiment.

[0171] The IF chip 200 is bonded to the controller chip 300. Multiple signal lines, including connections based on bonding pads, constitute the data bus DB and the logic bus LB, respectively.

[0172] The NAND interface module 33 of the controller chip 300 is connected to the control unit 32 of the chip 400 via a controller bus CB. The controller bus CB is, for example, an AHB bus. The bus width of the controller bus CB is, for example, 32 bits. In the memory system 1 of the sixth variation of the second embodiment, the controller bus CB includes, for example, wiring on a printed circuit board.

[0173] A NAND interface module 33b is connected to the controller bus CB. The NAND interface module 33b is connected to the semiconductor memory device 4d. The NAND interface module 33b and the semiconductor memory device 4d can, for example, have a structure in which a CMOS chip CC and a memory chip MC are bonded together, or they can be set as separate chips, or they can be constructed on a single semiconductor substrate, or they can include a structure in which multiple semiconductors are stacked. In addition, the NAND interface module 33b and the semiconductor memory device 4d can be connected via a NAND bus, or they can be connected using a data bus and a logic bus.

[0174] In the memory system 1 of the sixth variation of the second embodiment, the memory controller 3 and the register 14 are directly connected via the data bus DB. That is, the serial / parallel conversion circuit and the input / output module are not included in the signal path between the memory controller 3 and the register 14. Therefore, the memory system 1 of the sixth variation of the second embodiment can reduce the circuit size and increase the bus width of the bus connecting the memory controller 3 and the semiconductor memory device 4. As a result, the memory system 1 of the sixth variation of the second embodiment can improve the communication bandwidth.

[0175] Furthermore, in the memory system 1 of the sixth variation of the second embodiment, the chip 400 and the controller chip 300 are connected via a controller bus CB. The controller bus CB is a bus with a wide bus width. Therefore, the memory system 1 of the sixth variation of the second embodiment enables high-speed communication between the chip 400 and the controller chip 300.

[0176] Furthermore, in the memory system 1 of the sixth variation of the second embodiment, multiple groups of NAND interface modules and semiconductor memory devices are connected to the controller bus CB. Thus, the memory system 1 of the sixth variation of the second embodiment can expand its storage capacity by providing multiple NAND interface modules and semiconductor memory devices.

[0177] [3] Other variations, etc.

[0178] In this implementation, the example given is that the memory system 1 meets the UFS standard. However, the standards met by the memory system 1 are not limited to this. As an example, the host bus HB is a bus used for serial communication. In this case, communication performed via the host bus HB meets USB (Universal Serial Bus), SAS (Serial Attached SCSI), or PCIe standards. TM The PCI Express standard. Alternatively, as another example, the host bus HB can also be the UHS-I standard for SDTM cards, or a parallel communication bus conforming to the eMMC standard.

[0179] In this specification, "wide" bus width means that the bus can transmit a large amount of information at a time. "Narrow" bus width means that the bus can transmit a small amount of information at a time. For example, a 32-bit bus is wider than an 8-bit bus. Conversely, an 8-bit bus is narrower than a 32-bit bus.

[0180] In this specification, "connection" means electrical connection, excluding cases where other components are involved. Furthermore, "electrical connection" can function in the same way as an electrical connection, and may also be via an insulator.

[0181] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0182] Explanation of reference numerals in the attached figures

[0183] 1…Memory system, 3…Memory controller, 4…Semiconductor memory device, 5…Switching module, 10…Input / output module, 11…Input / output circuit, 12…Logic control circuit, 13…Serial / parallel conversion circuit, 14…Register, 15…Memory cell array, 16…Line decoder, 17…Sense amplifier, 18…Sequencer, 31…Host interface module, 32…Control unit, 33…NAND interface module, 40…Sealing resin, 51…Packaging substrate, 52…Solder ball, 53…Spacer, 54…Adhesive, 55…Support plate, 56…Through electrode, 57…Solder ball, 58…Solder ball, 59…Solder ball, 61…Re… Routing layer, 62…rerouting layer, 63…routing, 64…package, 100…core chip, 200…IF chip, 300…controller chip, 400…chip, AC…chip, BL…bit line, BP…bonding pad, CB…controller bus, CC…CMOS chip, DB…data bus, DW…data line, HB…host bus, IB1…first internal bus, IB2…second internal bus, IB3…third internal bus, LB…logic bus, LW…logic line, MC…memory chip, MT…memory cell, NB…NAND bus, TB1…first test bus, TB2…second test bus, WL…word line.

Claims

1. A memory device comprising a first chip including a first surface and a second chip including a second surface and attached to the first chip, the memory device comprising: The first storage cell array is configured to store data non-volatilely; Registers are used to store instructions; The control circuit is configured to execute read and write operations on the memory cells constituting the first memory cell array based on the instructions stored in the register; and The input / output module is connected to the control circuit. The first chip includes the first memory cell array and a first bonding pad disposed on the first surface and electrically connected to the first memory cell array. The second chip includes the register, the control circuit, the input / output module, and a second bonding pad disposed on the second surface and electrically connected to the control circuit. The second bonding pad is bonded to the first bonding pad and is electrically connected to the first bonding pad.

2. The memory device according to claim 1, wherein, It also has: Substrate; and A package containing the first chip and the second chip. The second bonding pad of the second chip is bonded to the first bonding pad without passing through the lines on the substrate.

3. The memory device according to claim 1, wherein, The first chip and the second chip are manufactured using different processes.

4. The memory device according to claim 1, wherein, The first chip includes a plurality of bonding pads, including at least the first bonding pad. The second chip includes: a plurality of bonding pads, including at least the second bonding pad; a first data bus connected to the input / output module; and a bus conversion circuit connected to the first data bus. The plurality of bonding pads of the first chip and the plurality of bonding pads of the second chip are bonded together in such a manner that a second data bus is formed between the first chip and the second chip. The second data bus is connected to the first data bus via the bus conversion circuit. The first data bus has a narrower first bus width than the second data bus has a narrower second bus width.

5. The memory device according to any one of claims 1 to 4, wherein, The first chip further includes: a readout amplifier connected to the first memory cell array; and a line decoder connected to the first memory cell array.

6. A memory device comprising: The first chip, including the first side; A second chip comprising a second surface and bonded to the first chip; and At least one third chip electrically connected to the second chip, The memory device includes: At least one array of storage cells is configured to store data non-volatilely; Registers are used to store instructions; The control circuit is configured to execute read and write operations on memory cells constituting the at least one memory cell array based on the instructions stored in the register; and The input / output module is connected to the control circuit. The first chip includes the input / output module and a first bonding pad disposed on the first surface and electrically connected to the input / output module. The second chip includes the register, the control circuit, and a second bonding pad disposed on the second surface and electrically connected to the control circuit. The at least one third chip includes the at least one memory cell array. The second bonding pad is bonded to the first bonding pad and is electrically connected to the first bonding pad.

7. The memory device according to claim 6, wherein, It includes a plurality of stacked third chips, wherein the plurality of third chips includes the at least one third chip. The plurality of third chips are electrically connected to each other via through electrodes.

8. The memory device according to claim 7, wherein, It also includes a package containing the first chip, the second chip, and the third chip. The first chip, the second chip, and the plurality of third chips are sealed in the package with resin.

9. The memory device according to any one of claims 6 to 8, wherein, The at least one third chip further includes at least one sense amplifier connected to the at least one memory cell array, and at least one line decoder connected to the at least one memory cell array.

10. A method for manufacturing a memory device, the memory device comprising a first chip including a first surface and a second chip including a second surface, the method comprising the following steps: Fabricate a first chip, the first chip comprising a first memory cell array for non-volatile data storage, and a first bonding pad disposed on the first surface and electrically connected to the first memory cell array; Fabricating a second chip, the second chip comprising: a register configured to store instructions; a control circuit configured to execute read and write operations on memory cells constituting the first memory cell array based on the instructions stored in the register; an input / output module connected to the control circuit; and a second bonding pad disposed on the second surface and electrically connected to the control circuit; and The second bonding pad is bonded to the first bonding pad.

11. The method of manufacturing a memory device according to claim 10, wherein, It also includes the following steps: Fabrication of substrate; Connection lines on the substrate; and The first chip and the second chip are housed in a package. The second bonding pad is bonded to the first bonding pad without passing through the lines on the substrate.

12. The method of manufacturing a memory device according to claim 10, wherein, The first chip and the second chip are manufactured using different processes.

13. The method of manufacturing a memory device according to claim 10, wherein, The first chip includes a plurality of bonding pads, and the plurality of bonding pads includes at least the first bonding pad. The second chip includes: a plurality of bonding pads, including at least the second bonding pad; a first data bus connected to the input / output module; and a bus conversion circuit connected to the first data bus. The manufacturing method further includes the following step: attaching the plurality of bonding pads of the first chip to the plurality of bonding pads of the second chip in such a manner that a second data bus is formed between the first chip and the second chip. The second data bus is connected to the first data bus via the bus conversion circuit. The first data bus has a narrower first bus width than the second data bus has a narrower second bus width.

14. The method of manufacturing a memory device according to any one of claims 10 to 13, wherein, The first chip also includes a sense amplifier connected to the first memory cell array and a line decoder connected to the first memory cell array.

15. A method of manufacturing a memory device, the memory device comprising: a first chip including a first side; a second chip including a second side; and at least one third chip including at least one array of memory cells. The method for manufacturing the memory device comprises the following steps: Fabricate a first chip, which includes an input / output module and a first bonding pad disposed on the first surface and electrically connected to the input / output module; A second chip is fabricated, the second chip comprising: a register configured to store instructions; a control circuit configured to perform read and write operations on memory cells constituting the at least one memory cell array based on the instructions stored in the register; and a second bonding pad disposed on the second surface and electrically connected to the control circuit. Fabricate at least one third chip comprising the at least one memory cell array; The second bonding pad is bonded to the first bonding pad; and The at least one third chip is electrically connected to the second chip. Through this bonding, the input / output module is electrically connected to the control circuit.

16. The method of manufacturing a memory device according to claim 15, wherein, It also includes the following steps: Fabricate a plurality of third chips including at least one third chip; The plurality of third chips are stacked; Fabrication of through electrodes; and The plurality of third chips are electrically connected to each other via the through electrode.

17. The method of manufacturing a memory device according to claim 16, wherein, The first chip, the second chip, and the third chip are sealed with resin and housed in a package.

18. A method for manufacturing a memory device according to any one of claims 15 to 17, wherein, The at least one third chip further includes at least one sense amplifier connected to the at least one memory cell array, and at least one line decoder connected to the at least one memory cell array.

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