Fan-in wafer level chip stacking packaging method and packaging structure
By forming diced grooves on silicon wafers and filling them with molding compounds, a fan-in wafer-level chip stacking packaging method has been developed, which solves the problems of lengthy and costly traditional packaging processes, thereby achieving cost reduction and yield improvement.
Patent Information
- Application Number
- CN202511075404.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-18
AI Technical Summary
Traditional packaging processes are lengthy, increasing costs and resulting in yield losses, and therefore need to be simplified and optimized.
The fan-in wafer-level chip stacking packaging method uses a silicon wafer as a carrier. By forming a dicing groove on the silicon wafer and filling it with a molding compound, the chip is directly mounted on the silicon wafer, simplifying the process flow and obtaining a six-sided protected packaging structure through a half-cut process.
Reduce production costs, simplify process flow, and improve the reliability and yield of packaging structure.
Smart Images
Figure CN120977882A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a fan-in wafer level chip stack packaging method and packaging structure. BACKGROUND
[0002] As a key link of the semiconductor industry chain, the cost control and process optimization of chip packaging have a decisive influence on the competitiveness of enterprises. In the traditional packaging process, the wafer cleaning, grinding, cutting and other steps are needed to obtain the die, and then the die is bonded and compression molded at the reorganization station to obtain a six-face protection structure on the glass carrier. The more lengthy steps mean that the cost is increased and the yield loss is inevitable.
[0003] In view of the above problems, it is necessary to provide a fan-in wafer level chip stack packaging method and packaging structure which is reasonable in design and effective in solving the above problems. SUMMARY
[0004] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a fan-in wafer level chip stack packaging method and packaging structure.
[0005] An aspect of the embodiment of the present disclosure provides a fan-in wafer level chip stack packaging method, which comprises:
[0006] forming a plurality of chips;
[0007] providing a silicon wafer, and forming a plurality of conductive columns on the functional surface of the silicon wafer;
[0008] electrically connecting the plurality of chips to the functional surface of the silicon wafer in a flat manner;
[0009] cutting the silicon wafer along the cutting path to form a cutting groove on the silicon wafer, wherein the depth of the cutting groove is less than the thickness of the silicon wafer;
[0010] forming a plastic package, which wraps the silicon wafer, the plurality of chips and the plurality of conductive columns, and fills the cutting groove;
[0011] cutting the plastic package corresponding to the cutting groove to obtain a plurality of packaging structures.
[0012] Optionally, after the plastic encapsulation layer is formed, the method further comprises:
[0013] thinning the side of the plastic package away from the silicon wafer to expose the conductive columns.
[0014] Optionally, after the plastic package is thinned, the method further comprises:
[0015] Electroplating a positioning tin bar on the exposed surface of the conductive column.
[0016] Optionally, the cutting along the plastic package body at the corresponding cutting groove to obtain a plurality of packaging structures comprises:
[0017] The cutting groove is aligned by the positioning tin bar, and the plastic package body at the corresponding cutting groove is cut to sequentially cut the plastic package body and the silicon wafer to obtain a plurality of packaging structures.
[0018] Optionally, the forming a plurality of chips comprises:
[0019] Providing a wafer;
[0020] Coating a first dielectric layer on the functional surface of the wafer;
[0021] Patterning the first dielectric layer, and electroplating a plurality of first protrusions on the patterned first dielectric layer;
[0022] Cutting along the cutting path of the wafer to form a plurality of independent chips.
[0023] Optionally, before the forming a plurality of conductive columns on the functional surface of the silicon wafer, the method further comprises:
[0024] Coating a second dielectric layer on the functional surface of the silicon wafer;
[0025] Patterning the second dielectric layer, and electroplating a plurality of second protrusions on the patterned second dielectric layer, wherein the height of the second protrusions is less than the height of the conductive columns, and the conductive columns are located outside the plurality of second protrusions.
[0026] Optionally, the tiling and electrically connecting a plurality of chips to the functional surface of the silicon wafer comprises:
[0027] Electrically connecting the first protrusions of the plurality of chips to the second protrusions of the silicon wafer.
[0028] Optionally, after forming a plurality of packaging structures, the method further comprises:
[0029] According to the packaging needs, thinning the side of the silicon wafer away from the chips;
[0030] Forming a metal plating layer on the thinned silicon wafer.
[0031] Optionally, the forming a plastic package comprises:
[0032] Using plastic encapsulation glue to perform mold bottom filling on the silicon wafer to form the plastic package.
[0033] Another aspect of the embodiments of the present disclosure provides a fan-in wafer level chip stack package structure formed by the above-mentioned fan-in wafer level chip stack packaging method.
[0034] The fan-in wafer level chip stack packaging method and the package structure of the embodiments of the present disclosure, the packaging method comprises: forming a plurality of chips; providing a silicon wafer, forming a plurality of conductive columns on the functional surface of the silicon wafer; electrically connecting the plurality of chips to the functional surface of the silicon wafer; cutting the silicon wafer along the cutting path to form a cutting groove on the silicon wafer, wherein the depth of the cutting groove is less than the thickness of the silicon wafer; forming a plastic package body wrapping the silicon wafer, the plurality of chips and the plurality of conductive columns, and the plastic package body is filled in the cutting groove; cutting the plastic package body corresponding to the cutting groove to obtain a plurality of package structures. In the method, the silicon wafer is used as a carrier, and the plurality of chips are directly mounted on the silicon wafer, without using expensive glass carrier or complex wafer recombination technology, greatly reducing the production cost and simplifying the process flow; and the six-side protection package structure is obtained through the half-cut process, effectively improving the yield. BRIEF DESCRIPTION OF DRAWINGS
[0035] Figure 1 FIG. 1 is a flowchart of a fan-in wafer level chip stack packaging method according to an embodiment of the present disclosure;
[0036] Figures 2 to 12 FIG. 2 is a process diagram of a fan-in wafer level chip stack packaging method according to another embodiment of the present disclosure. DETAILED DESCRIPTION
[0037] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the drawings and specific embodiments.
[0038] As shown in FIG. 1, an aspect of the embodiments of the present disclosure provides a fan-in wafer level chip stack packaging method S100, the method S100 comprises: Figure 1
[0039] S110, forming a plurality of chips.
[0040] Specifically, as shown in FIG. 1, the method S100 comprises: Figure 2 As shown, a wafer 100 is provided. A first dielectric layer 111 is coated on the functional surface of the wafer 100. A first photoresist layer is formed on the first dielectric layer 111. The first photoresist layer is sequentially exposed and developed to form a plurality of first openings on the first photoresist layer. The first dielectric layer 111 is etched along the first openings to form a plurality of first windows on the first dielectric layer 111. A plurality of first bumps 112 are formed on the first windows by electroplating. The first bumps 112 can be copper-tin bumps, and the first dielectric layer 111 can be a PA layer.
[0041] like Figure 3 As shown, the non-functional surface of wafer 100 is ground and thinned according to packaging requirements, and then cut along the dicing groove of wafer 100 to form multiple independent chips 110. Among them, a first dielectric layer 111 and a first bump 112 are sequentially formed on the functional surface of each chip 110.
[0042] S120. A silicon wafer is provided, and a plurality of conductive pillars are formed on the functional surface of the silicon wafer.
[0043] like Figure 4 As shown, a silicon wafer 200 is provided. Specifically, in this embodiment, the silicon wafer 200 can be a 12-inch silicon wafer. The silicon wafer 200 serves as a carrier disk for holding multiple chips 110. The size of the chips 110 is smaller than the size of the silicon wafer 200.
[0044] like Figure 4 As shown, a second dielectric layer 211 is coated on the functional surface of the silicon wafer 200. A second photoresist layer is formed on the second dielectric layer 211. The second photoresist layer is sequentially exposed and developed to form a plurality of second openings. The second dielectric layer 211 is etched along the second openings to form a plurality of second windows. A plurality of second bumps 212 are formed on the second windows by electroplating. The second bumps 212 can be copper bumps, and the second dielectric layer 211 can be a PI layer. The positions of the second bumps 212 correspond to the first bumps 112 on the chip 110.
[0045] like Figure 5 As shown, multiple conductive pillars 213 are formed on the functional surface of the silicon wafer 200 using an electroplating process. In this embodiment, the conductive pillars 213 can be made of conductive copper. The height of the formed second protrusions 212 is less than the height of the conductive pillars 213, and the conductive pillars 213 are located outside the multiple second protrusions 212. The conductive pillars 213 enable vertical interconnection of the stacked chips, while also providing space between adjacent conductive pillars 213 for the stacking of the chips 110.
[0046] S130. Multiple chips are laid flat and electrically connected to the functional surface of the silicon wafer.
[0047] As shown in Figure 6 , a plurality of first bumps 112 of a plurality of chips 110 are electrically connected to a plurality of second bumps 212 corresponding to the first bumps 112 on the functional surface of the silicon wafer 200 to achieve the function of electrically connecting the plurality of chips 110 to the functional surface of the silicon wafer 200. In this embodiment, the plurality of chips 110 are flip-chip stacked on the silicon wafer 200. As shown in Figure 6 , a conductive column 213 is arranged on the outer side of each chip 110.
[0048] In this embodiment, the silicon wafer is provided as a carrier plate, and the plurality of chips are mounted directly on the silicon wafer, without the need for additional temporary carrier / glass carrier, greatly reducing production costs. In addition, the silicon wafer as a carrier plate can skip the carrier plate bonding and die bonding steps, effectively simplifying the process, reducing machine occupation, and reducing production costs.
[0049] S140, cutting the silicon wafer along the cutting path of the silicon wafer to form a cutting groove on the silicon wafer, wherein the depth of the cutting groove is less than the thickness of the silicon wafer.
[0050] As shown in Figure 7 , a half-cut process is used to cut the second dielectric layer 211 and the functional surface of the silicon wafer 200 in sequence along the cutting path of the silicon wafer 200 to form a cutting groove 210 on the silicon wafer 200. The depth of the cutting groove 210 is less than the thickness of the silicon wafer 200. That is, the silicon wafer 200 is half-cut and not completely cut.
[0051] It should be noted that the size and shape of the cutting groove 210 are not specifically limited in this embodiment and can be selected as needed. For example, the longitudinal cross-sectional shape of the cutting groove 210 can be rectangular, V-shaped, or the like.
[0052] S150, forming a plastic package, the plastic package wrapping the silicon wafer, the plurality of chips and the plurality of conductive columns, and filling the cutting groove.
[0053] As shown in Figure 8 , a plastic encapsulation is used to mold the bottom of the silicon wafer 200 to form a plastic package 120. The plastic package 120 wraps the silicon wafer 200, the plurality of chips 110 and the plurality of conductive columns 213, and fills the cutting groove 210. The silicon wafer 200, the plurality of chips 110 and the plurality of conductive columns 213 are protected.
[0054] After forming the plastic package 120, the method further comprises:
[0055] As shown in Figure 9As shown, the plastic package 120 is thinned by grinding or other processes from the side away from the silicon wafer 200 to expose the conductive pillars 213.
[0056] Then, as shown in FIG. 2D, the exposed conductive pillars 213 are plated with a plating process to form alignment tin bars 214. Figure 10 As shown, the alignment tin bars 214 can be used for alignment when the plastic package 120 is cut.
[0057] S160, cutting the plastic package along the cutting groove to obtain multiple package structures.
[0058] As shown, the plastic package 120 is thinned by grinding or other processes from the side away from the silicon wafer 200 to expose the conductive pillars 213. Figure 11 As shown, the plastic package 120 is thinned by grinding or other processes from the side away from the silicon wafer 200 to expose the conductive pillars 213.
[0059] In this embodiment, the silicon wafer is first cut by a half-cut process to form a cutting groove, and the cutting groove is filled with a plastic package. Then, the silicon wafer is cut again along the plastic package to obtain multiple individual package structures. Since the cutting groove is filled with a plastic package, the side of the chip is wrapped, and the chip is protected during the second cutting of the silicon wafer, resulting in a six-sided protective package structure. This avoids damage to the chip during subsequent operations and improves the reliability of the package structure.
[0060] After the multiple package structures are formed, the method further includes:
[0061] According to the packaging needs, the side of the silicon wafer 200 away from the chip 110 is thinned by a backgrinding process or the like.
[0062] A metal plating layer 130 is formed on the thinned silicon wafer 200 to obtain the final fan-in wafer level chip stack package structure as shown in FIG. 2H. Figure 12
[0063] The fan-in wafer level chip stack packaging method of the embodiments of the present disclosure uses a silicon wafer as a carrier, directly mounts multiple chips on the silicon wafer, does not need to use expensive glass carriers or complex wafer recombination technology, greatly reduces production costs, and simplifies the process flow. The packaging method can skip the carrier bonding and die bonding steps, freeing up equipment and reducing production costs.
[0064] As Figure 12 shown, another aspect of the present disclosure provides a fan-in wafer level chip scale package structure, which is formed by the above-mentioned fan-in wafer level chip scale package method S100. The specific process of the fan-in wafer level chip scale package method S100 has been described in detail above, and will not be repeated here.
[0065] The fan-in wafer level chip scale package structure of the present disclosure is formed by the above-mentioned fan-in wafer level chip scale package method, and a six-sided protection package structure is obtained, which has high reliability and effectively improves yield.
[0066] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered within the protection scope of the embodiments of the present disclosure.
Claims
1. A fan-in wafer-level chip stacking packaging method, characterized in that, The method includes: Multiple chips are formed; A silicon wafer is provided, and a plurality of conductive pillars are formed on the functional surface of the silicon wafer; Multiple chips are laid flat and electrically connected to the functional surface of the silicon wafer; The silicon wafer is cut along a dicing track to form a dicing groove on the silicon wafer, wherein the depth of the dicing groove is less than the thickness of the silicon wafer; A molding compound is formed, which encapsulates the silicon wafer, the plurality of chips, and the plurality of conductive pillars, and fills the dicing groove; The molding compound is cut along the corresponding cutting groove to obtain multiple encapsulation structures.
2. The method according to claim 1, characterized in that, After forming the molding layer, the method further includes: The side of the molding compound facing away from the silicon wafer is thinned to expose the conductive pillars.
3. The method according to claim 2, characterized in that, After thinning the encapsulated body, the method further includes: Alignment tin bars are formed by electroplating on the exposed surface of the conductive pillar.
4. The method according to claim 3, characterized in that, The molding compound is cut along the corresponding cutting groove to obtain multiple encapsulation structures, including: The aligning solder bar is used to align the cutting groove, and the molding compound is cut along the corresponding cutting groove. The molding compound and the silicon wafer are cut in sequence to obtain multiple package structures.
5. The method according to any one of claims 1 to 4, characterized in that, The formation of multiple chips includes: Provide wafers; A first dielectric layer is coated on the functional surface of the wafer; The first dielectric layer is patterned, and a plurality of first protrusions are electroplated on the patterned first dielectric layer; The wafer is cut along the dicing lines to form multiple individual chips.
6. The method according to claim 5, characterized in that, Before forming multiple conductive pillars on the functional surface of the silicon wafer, the method further includes: A second dielectric layer is coated on the functional surface of the silicon wafer; The second dielectric layer is visualized, and a plurality of second protrusions are electroplated on the visualized second dielectric layer, wherein the height of the second protrusions is less than the height of the conductive pillars, and the conductive pillars are located outside the plurality of second protrusions.
7. The method according to claim 6, characterized in that, The step of electrically connecting multiple chips flatly to the functional surface of the silicon wafer includes: The first bump of the plurality of chips is electrically connected to the second bump of the silicon wafer.
8. The method according to any one of claims 1 to 4, characterized in that, After forming multiple packaging structures, the method further includes: According to packaging requirements, the side of the silicon wafer facing away from the chip is thinned; A metal coating is formed on the thinned silicon wafer.
9. The method according to any one of claims 1 to 4, characterized in that, The formation of the encapsulation includes: The silicon wafer is molded with encapsulating adhesive to fill the bottom, forming the encapsulated body.
10. A fan-in wafer-level chip stacking packaging structure, characterized in that, It is packaged using the fan-in wafer-level chip stacking packaging method according to any one of claims 1 to 9.