Packaging body with multiple stacked chips

Abstract

The utility model belongs to the technical field of semiconductor chips, and discloses a multi-chip stacked packaging body, which comprises a packaging substrate, a plurality of groups of first-level chips are arranged on the packaging substrate, and a plurality of groups of second-level chips are arranged on one sides, deviating from the packaging substrate, of the plurality of groups of first-level chips. The plurality of groups of first-level chips and the plurality of groups of second-level chips are electrically connected with the packaging substrate, the plurality of groups of first-level chips and the plurality of groups of second-level chips are solidified and combined by adopting a packaging material, one surface, deviating from the packaging substrate, of a combined body is a passivation layer, a protective shell is arranged outside the combined body, the depth of the protective shell is higher than that of the passivation layer, and the passivation layer is arranged outside the protective shell. The packaging structure is compact and reasonable in structural design, the first-level chips and the second-level chips are stacked and packaged with the packaging substrate into a whole, more chips can be contained in the same occupied area, the packaging structure is compact and reasonable in structure design, the packaging structure is compact in structure, the packaging structure is compact in structure, the packaging structure is compact in structure, the packaging cost is low, and the packaging structure is suitable for large-scale popularization and application. And the integration level can be greatly improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor chip technology, specifically to a multi-chip stacked package. Background Technology

[0002] In today's era of rapid development in electronic technology, semiconductor chips are undoubtedly the core driving force behind many cutting-edge technologies. With their tiny and precise transistor structure, semiconductor chips can perform complex data processing, signal transmission, and other critical functions, and are widely used in everything from consumer electronics such as smartphones and computers to high-end fields such as autonomous driving and industrial automation.

[0003] As electronic products continue to advance towards multifunctionality and high performance, the demands on chip computing power and storage capacity are increasing. Single semiconductor chips are gradually becoming insufficient to meet these growing needs, prompting the emergence of multi-chip packaging technology. By integrating and packaging multiple semiconductor chips together, the advantages of different chips can be combined to collaboratively complete more complex tasks and achieve high-performance system-level results.

[0004] However, multi-chip packaging currently faces a significant challenge – its large size. On one hand, the physical space required for multiple chips necessitates considerable volume. Furthermore, the precise electrical connections between chips, such as wire bonding and micro-bump connections, along with the heat dissipation structures and protective layers necessary to ensure stable chip operation, inevitably increase the package's size. This not only contradicts the trend towards thinner and lighter electronic products but also limits the further promotion and application of large-volume multi-chip packaging in space-constrained applications such as wearable devices and micro-drones. Therefore, effectively reducing the size while maintaining the functionality of multi-chip packaging has become a critical technological challenge that urgently needs to be overcome. Utility Model Content

[0005] (a) Technical problems to be solved

[0006] To address the shortcomings of existing technologies, this invention provides a multi-chip stacked package, which solves the problems of large size in multi-chip packaging mentioned in the background art.

[0007] (II) Technical Solution

[0008] To achieve the above-mentioned objectives, the present invention provides the following technical solution: a multi-chip stacked package, comprising a package substrate, wherein multiple sets of first-level chips are disposed on the package substrate, and multiple sets of second-level chips are disposed on the side of the multiple sets of first-level chips facing away from the package substrate, the multiple sets of first-level chips and the multiple sets of second-level chips are electrically connected to the package substrate, and the multiple sets of first-level chips and the multiple sets of second-level chips are bonded together by using a package material, the side of the bond facing away from the package substrate is a passivation layer, a protective shell is disposed outside the bond, the depth of the protective shell is higher than that of the passivation layer, and the gap between the passivation layer and the protective shell is filled with a thermally conductive material.

[0009] Preferably, the packaging substrate has multiple sets of substrate metal pads on the side adjacent to the first-level chip, the first-level chip has multiple sets of chip pins on the side adjacent to the packaging substrate, and multiple sets of gold wires are provided between the chip pins and the substrate metal pads. The chip pins and the substrate metal pads are electrically coupled by metal bonding through the gold wires.

[0010] Preferably, the packaging substrate is provided with a support frame, and multiple sets of bridge connectors are provided between multiple sets of first-level chips on the packaging substrate. One end of the bridge connector is electrically connected to the packaging substrate, and the other end of the bridge connector is electrically connected to the second-level chip.

[0011] Preferably, the support frame includes multiple sets of intersecting horizontal and vertical support bars, which abut against the sides of the second-level chips, fixing and supporting the multiple sets of second-level chips on the side of the multiple sets of first-level chips away from the packaging substrate.

[0012] Preferably, the bridge connector includes a large electrical connecting piece, a small electrical connecting piece, and connecting posts. The large electrical connecting piece is provided with a connection contact point corresponding to the second-level chip, and the large electrical connecting piece is electrically coupled to the second-level chip. The small electrical connecting piece is placed in the gap between multiple sets of first-level chips, and is provided with a connection contact point corresponding to the packaging substrate, and is electrically coupled to the packaging substrate. Connecting posts are provided between the large electrical connecting piece and the small electrical connecting piece, and the large electrical connecting piece and the small electrical connecting piece are electrically connected through the connecting posts.

[0013] Preferably, the packaging substrate on the side opposite to the first-level chip uses a ball grid array (BGA) packaging process to bring out multiple sets of external pins, which are electrically connected to external devices.

[0014] (III) Beneficial Effects

[0015] Compared with the prior art, the present invention provides a multi-chip stacked package, which has the following advantages:

[0016] 1. The multi-chip stacked package is provided with a packaging substrate, a first-level chip and a second-level chip. The first-level chip and the second-level chip are stacked and packaged together with the packaging substrate. The same area can contain more chips, which can greatly improve the integration.

[0017] 2. Stacking multiple chips into first-level and second-level packages can reduce the horizontal size of the package and the area required by the package. It trades vertical space for horizontal space, which is conducive to improving integration and has certain practicality.

[0018] 3. It is equipped with a bridge connector, with a large electrical contact at one end and a small electrical contact at the other end. The small electrical contact is used for the packaging substrate, which is equivalent to scaling up the electrical connection area. This allows the packaging substrate to connect chips with a very large area with a relatively small area, which can significantly reduce the area occupied by the packaging substrate, i.e., the package, and make the package more compact, which is conducive to improving integration. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0020] Figure 2 This is a schematic diagram of the internal packaging structure of this utility model;

[0021] Figure 3 This is a schematic diagram of the internal packaging structure of this utility model;

[0022] Figure 4 This is a schematic diagram of gold wire bonding according to the present invention;

[0023] Figure 5 This is a schematic diagram of the internal packaging structure of this utility model;

[0024] Figure 6 This is a schematic diagram of the packaging substrate, bridge connector, and second-level chip structure of this utility model.

[0025] In the diagram: 1. Packaging substrate; 2. First-level chip; 3. Second-level chip; 4. Packaging material; 5. Passivation layer; 6. Thermally conductive material; 7. Protective shell; 8. Chip pins; 9. Gold wire; 10. Substrate metal pads; 11. Support frame; 12. Bridge connector; 13. Support strip; 14. Large electrical connector; 15. Small electrical connector; 16. Connecting post; 17. External pins. Detailed Implementation

[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0027] Please see Figure 1-6 This utility model provides a technical solution:

[0028] A multi-chip stacked package includes a packaging substrate 1, on which multiple sets of first-layer chips 2 are disposed. Multiple sets of second-layer chips 3 are disposed on the side of the multiple sets of first-layer chips 2 facing away from the packaging substrate 1. All sets of first-layer chips 2 and second-layer chips 3 are electrically connected to the packaging substrate 1 and are bonded together using a packaging material 4. The side of the bond facing away from the packaging substrate 1 is a passivation layer 5. A protective shell 7 is disposed outside the bond, with a depth greater than the passivation layer 5. The gap between the passivation layer 5 and the protective shell 7 is filled with a thermally conductive material 6. Multiple sets of first-layer chips 2 are placed on the packaging substrate 1, and second-layer chips 3 are stacked on top of them, all electrically connected to the substrate 1, and then bonded together using the packaging material 4. This design utilizes vertical space, accommodating more chips in the same area, improving integration, and reducing the lateral dimensions of the package. The bond has a passivation layer 5 and is covered by a protective shell 7, which is deeper than the passivation layer 5, with the gap filled with thermally conductive material 6. The passivation layer prevents corrosion, the protective shell resists impact, and the thermally conductive material dissipates heat from the chip in a timely manner, creating a safe, stable, and well-heat-dissipated operating environment for the chip.

[0029] Furthermore, the packaging substrate 1 has multiple sets of substrate metal pads 10 on the side adjacent to the first-layer chip 2, and the first-layer chip 2 has multiple sets of chip pins 8 on the side adjacent to the packaging substrate 1. Multiple sets of gold wires 9 are arranged between the chip pins 8 and the substrate metal pads 10, and the chip pins 8 and substrate metal pads 10 are electrically coupled through metal bonding via the gold wires 9. The packaging substrate 1 has substrate metal pads 10 near the first-layer chip 2, and the chip 2 has corresponding chip pins 8. The two are electrically coupled through metal bonding via the gold wires 9, accurately transmitting signals and laying a solid foundation for the electrical operation of the entire package, ensuring the coordinated operation of the chip and the substrate.

[0030] Furthermore, a support frame 11 is provided on the packaging substrate 1, and multiple sets of bridge connectors 12 are provided between multiple sets of first-level chips 2 on the packaging substrate 1. One end of the bridge connector 12 is electrically connected to the packaging substrate 1, and the other end of the bridge connector 12 is electrically connected to the second-level chip 3.

[0031] Furthermore, the support frame 11 includes multiple sets of intersecting horizontal and vertical support bars 13. These support bars 13 abut against the sides of the second-level chips 3, fixing the multiple sets of second-level chips 3 to the side of the multiple sets of first-level chips 2 facing away from the packaging substrate 1. The intersecting horizontal and vertical support bars 13 of the support frame 11 play a crucial role in abutting against the sides of the second-level chips 3, firmly fixing them on top of the first-level chips 2, maintaining the stability of the chip stacking structure, resisting external forces such as vibration and collision, and ensuring that the normal operation of the chips is not disturbed by displacement.

[0032] Furthermore, the bridge connector 12 includes a large electrical connecting piece 14, a small electrical connecting piece 15, and a connecting post 16. The large electrical connecting piece 14 has a connection contact point corresponding to the second-level chip 3, and the large electrical connecting piece 14 is electrically coupled to the second-level chip 3. The small electrical connecting piece 15 is placed in the gap between multiple sets of first-level chips 2, and the small electrical connecting piece 15 has a connection contact point corresponding to the packaging substrate 1, and the small electrical connecting piece 15 is electrically coupled to the packaging substrate 1. A connecting post 16 is provided between the large electrical connecting piece 14 and the small electrical connecting piece 15, and the large electrical connecting piece 14 and the small electrical connecting piece 15 are electrically connected through the connecting post 16. The bridge connector 12 includes large and small electrical connecting pieces 14 and 15 and a connecting post 16. The large electrical connector 14 is coupled to the second-level chip 3, and the small electrical connector 15 is connected to the packaging substrate 1. The two are connected by the connecting post 16, which scales the connection area with the substrate, adapts to different chips, and reduces the size of the package.

[0033] Furthermore, the side of the packaging substrate 1 facing away from the first-level chip 2 uses a ball grid array (BGA) packaging process to bring out multiple sets of external pins 17, which are electrically connected to external devices. These external pins 17, formed by the BGA packaging process on the side of the packaging substrate 1 facing away from the chip 2, serve as interfaces for electrical connection to external devices, enabling precise and efficient transmission of data and power, allowing the chip within the package to interact smoothly with the outside world and achieve diverse functions.

[0034] Working Principle: In this invention, multiple sets of substrate metal pads 10 on the side of the packaging substrate 1 adjacent to the first-level chip 2 are electrically coupled to the chip pins 8 on the side of the first-level chip 2 adjacent to the packaging substrate 1 via multiple sets of gold wires 9, ensuring accurate signal transmission. Based on this, multiple sets of external pins 17 are led out from the side of the packaging substrate 1 away from the first-level chip 2 using a ball grid array (BGA) packaging process, facilitating electrical connection with external devices and building a bridge for communication between the chip and the outside world. Next, the layered stacking structure improves space utilization. Multiple sets of first-level chips 2 are first placed on the packaging substrate 1, and second-level chips 3 are stacked on the side of the first-level chips 2 away from the packaging substrate 1. Both are electrically connected to the packaging substrate 1 and are solidified together by the packaging material 4, forming a stable whole. This layout replaces simple horizontal extension with vertical expansion, accommodating more chips in the same area, significantly improving integration, while reducing the horizontal dimensions of the package and minimizing the footprint. Furthermore, the support frame 11 ensures the stability of the chip stacking. It consists of multiple sets of intersecting horizontal and vertical support bars 13, which firmly abut against the sides of the second-level chip 3, securely fixing the second-level chip 3 on top of the first-level chip 2. Even under complex environments or equipment vibrations, the chip-level structure can maintain stability, avoiding displacement and collision damage to the chip. Finally, the bridge connector 12 optimizes connection adaptability. The large electrical connecting piece 14 at one end is laid out according to the shape of the second-level chip 3 to connect the contact points and electrically couple with it; the small electrical connecting piece 15 at the other end is placed in the gap between the first-level chips 2, matching the package substrate 1 for connection, and the two are electrically connected by the connecting post 16. This unique design scales up the electrical connection area with the package substrate 1, allowing the package substrate 1 to connect a large-area chip with a smaller area, further reducing the overall size of the package, making the package more compact, and continuously contributing to the improvement of integration. The protective shell 7 outside the package provides physical protection, and its depth is higher than the passivation layer 5. The gap between the two is filled with thermally conductive material 6, which can not only prevent external impact and dust corrosion, but also efficiently dissipate heat, ensuring that the chip operates efficiently in a safe and stable environment.

[0035] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-chip stacked package comprising a package substrate (1), characterized by: The packaging substrate (1) is provided with a plurality of groups of first-level chips (2), and the plurality of groups of first-level chips (2) are provided with a plurality of groups of second-level chips (3) away from the side of the packaging substrate (1), the plurality of groups of first-level chips (2) and the plurality of groups of second-level chips (3) are electrically connected with the packaging substrate (1), and the plurality of groups of first-level chips (2) and the plurality of groups of second-level chips (3) are combined by curing the packaging material (4), the side of the combination body away from the packaging substrate (1) is a passivation layer (5), the combination body is externally provided with a protective shell (7), the depth of the protective shell (7) is higher than that of the passivation layer (5), and the gap between the passivation layer (5) and the protective shell (7) is filled with a heat-conducting material (6).

2. The multi-chip stacked package of claim 1, wherein: The packaging substrate (1) is provided with a plurality of groups of substrate metal pads (10) near the side of the first-level chip (2), the first-level chip (2) is provided with a plurality of groups of chip pins (8) near the side of the packaging substrate (1), a plurality of groups of gold wires (9) are arranged between the chip pins (8) and the substrate metal pads (10), and the chip pins (8) and the substrate metal pads (10) are electrically coupled by metal bonding of the gold wires (9).

3. The multi-chip stacked package of claim 2, wherein: The packaging substrate (1) is provided with a support frame (11), and a plurality of groups of bridge connectors (12) are arranged between the plurality of groups of first-level chips (2) on the packaging substrate (1), one end of the bridge connector (12) is electrically connected with the packaging substrate (1), and the other end of the bridge connector (12) is electrically connected with the second-level chip (3).

4. The multi-chip stacked package of claim 3, wherein: The support frame (11) comprises a plurality of groups of horizontal and vertical intersecting support strips (13), and the plurality of groups of support strips (13) abut against the side edges of the second-level chips (3) to fix and support the plurality of groups of second-level chips (3) on the side away from the packaging substrate (1) of the plurality of groups of first-level chips (2).

5. The multi-chip stacked package of claim 3, wherein: The bridge connector (12) comprises a large electrically connected piece (14), a small electrically connected piece (15) and a connecting column (16), the large electrically connected piece (14) is provided with a connecting contact point corresponding to the second-level chip (3), the large electrically connected piece (14) is electrically coupled with the second-level chip (3), the small electrically connected piece (15) is arranged in the gap between the plurality of groups of first-level chips (2), the small electrically connected piece (15) is provided with a connecting contact point corresponding to the packaging substrate (1), the small electrically connected piece (15) is electrically coupled with the packaging substrate (1), the connecting column (16) is arranged between the large electrically connected piece (14) and the small electrically connected piece (15), and the large electrically connected piece (14) and the small electrically connected piece (15) are electrically connected through the connecting column (16).

6. The multi-chip stacked package of claim 1, wherein: The side away from the first-level chip (2) of the packaging substrate (1) is led out a plurality of groups of external pins (17) by using a ball grid array BGA packaging process, and the plurality of groups of external pins (17) are electrically connected with external equipment.

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