Semiconductor structure and forming method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor structure including a substrate having a circuit region, a seal ring region surrounding the circuit region, and a scribe line surrounding the seal ring region, where the scribe line includes a first scribe region and second scribe regions disposed on both sides of the first scribe region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region, the first gate stack including a metal electrode; a second active region formed in the first cutting region; a dielectric structure formed on the second active region in the first cutting region; and a second gate stack formed on the isolation feature in the second cutting region. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. Such miniaturization also increases the complexity of IC handling and manufacturing, and similar advancements in IC handling and manufacturing are needed to achieve these advancements.

[0003] For example, etching can cause metal residue, which is a critical issue in some areas, such as semiconductor via regions and plasma dicing tracks due to tooling capabilities. In another instance, gate height variations lead to process problems such as pattern density and processing uniformity. Therefore, while conventional IC devices are generally sufficient for their intended purpose, they are not satisfactory in every aspect. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a substrate having a circuit region and a sealing ring region surrounding the circuit region and a dicing channel surrounding the sealing ring region, wherein the dicing channel includes a first dicing region and second dicing regions disposed on both sides of the first dicing region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region, the first gate stack including a metal electrode; a second active region formed in the first dicing region; a dielectric structure formed on the second active region in the first dicing region; and a second gate stack formed on an isolation member in the second dicing region.

[0005] Other embodiments of this application provide a semiconductor structure including: a substrate having a circuit region and a sealing ring region surrounding the circuit region and a dicing channel surrounding the sealing ring region, wherein the dicing channel includes a first dicing region and second dicing regions disposed on both sides of the first dicing region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region; a second active region formed in the first dicing region; a first dielectric gate stack formed on the second active region in the first dicing region; and a second dielectric gate stack formed on an isolation member in the second dicing region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack.

[0006] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate having a circuit region and a sealing ring region surrounding the circuit region and a dicing channel surrounding the sealing ring region, wherein the dicing channel includes a first dicing region and second dicing regions disposed on both sides of the first dicing region; forming a first active region in the circuit region and forming a second active region in the first dicing region; forming a first gate stack on the first active region in the circuit region, forming a first dielectric gate stack on the second active region in the first dicing region, and forming a second dielectric gate stack on an isolation member in the second dicing region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack; and dicing the substrate along the dicing channel. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a top plan view of a semiconductor structure 100 according to an embodiment of the present disclosure.

[0009] Figure 2A and Figure 2F These are top views of the window portion 116 of a semiconductor structure 100 constructed according to some embodiments.

[0010] Figure 2B , Figure 2C , Figure 2D and Figure 2EThese are top views of window portions 118, 120, and 122 of a semiconductor structure 100 constructed according to some embodiments.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F It is constructed according to some embodiments. Figure 1 A top view of the semiconductor structure 100 in window 118.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F It is along Figure 1 or Figure 3B AA' cut Figure 1 A cross-sectional view of the semiconductor structure in window 120;

[0013] Figure 5A It is along Figure 1 CC' cut Figure 1 A cross-sectional view of the semiconductor structure in window 116;

[0014] Figure 5B It is along Figure 1 BB' cut Figure 1 A cross-sectional view of the semiconductor structure in window 118;

[0015] Figure 6A and Figure 6D It is constructed according to some embodiments along Figure 1 DD' cut Figure 1 A cross-sectional view of the semiconductor structure in window 116.

[0016] Figure 6B and Figure 6C It is constructed according to some embodiments along Figure 1 CC' cut Figure 1 A cross-sectional view of the semiconductor structure in window 116.

[0017] Figure 6E , Figure 6G , Figure 6H and Figure 6I It is constructed according to some embodiments along Figure 1 AA' cut Figure 1 A cross-sectional view of the semiconductor structure in window 118.

[0018] Figure 6F It is constructed according to some embodiments along Figure 1BB' cut Figure 1 A cross-sectional view of the semiconductor structure in window 118.

[0019] Figure 7 , Figure 8A , Figure 8B , Figure 8C and Figure 8D It is constructed according to some embodiments along Figure 1 BB' cut Figure 1 A cross-sectional view of the semiconductor structure in window 118.

[0020] Figure 9A , Figure 9B , Figure 9C and Figure 9D It is constructed according to some embodiments. Figure 1 A cross-sectional view of the semiconductor structure in window 120.

[0021] Figure 10A and Figure 10B Manufacturing according to various aspects of embodiments of this disclosure Figure 1 The flowchart shows the method for constructing semiconductor structures.

[0022] Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a cross-sectional view of a semiconductor structure constructed according to some embodiments. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Moreover, when using “about,” “approximately,” etc., to describe numbers or ranges of numbers, the term covers, based on the knowledge of those skilled in the art given the specific techniques disclosed herein, numbers within certain variations (such as + / -30%, + / -20%, + / -10%, or other variations) of the described numbers, unless otherwise stated. For example, the term “about 5 nm” may cover a size range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0025] The disclosed device structures and their fabrication methods relate to integrated circuit (IC) structures, such as 3D interconnect chips (3DIC), system-on-chip (SoC), integrated system-on-chip (SoIC), other suitable structures, or combinations thereof. The disclosed device structures relate to integrated circuit (IC) structures with multi-gate field-effect transistors (FETs), particularly FETs formed on vertically stacked multi-channel structures, such as gate-all-around (GAA) FETs. Specifically, the disclosed device structures include one or more plasmonic dicing (PD) structures.

[0026] Furthermore, the disclosed device structure includes one or more diced regions, such as a plasma dicing (PD) structure. The PD structure includes: a PD channel; a sealing ring structure; and a protective ring wall. The PD channel has no metal and includes dummy patterns. The PD channel includes: a first region; and a second region surrounding the first region. The first PD region includes a dummy active region and dummy gates disposed on the dummy active region; and the second PD region includes only dummy gates without an active region. In some embodiments, all dummy components in the PD channel 106 have no metal. In some embodiments, at least a subset of the dummy gates are metal gates.

[0027] Figure 1This is a top plan view of a semiconductor structure 100 according to an embodiment of the present disclosure. The semiconductor structure 100 (such as a fabricated wafer or a portion thereof) includes: a circuit region (or device region, IC die, chip region) 102; a sealing ring region 104, which, in the top view, surrounds the circuit region 102; a dicing region 106, which, in the top view, surrounds the sealing ring region 104; a protective ring wall 108, which, in the top view, surrounds the dicing region 106; and a boundary region 110, which, in the top view, surrounds the protective ring wall 108.

[0028] Circuit region 102 includes various devices formed on a substrate and interconnect structures formed thereon to electrically connect the devices to one or more integrated circuits (ICs). In some embodiments, circuit region 102 includes field-effect transistors (FETs), diodes, memory devices, passive devices, other devices, or combinations thereof. FETs include planar FETs, fin FETs, nanosheet FETs, such as gate all-around (GAA) FETs, and complementary FETs (CFTs). In the disclosed embodiments, circuit region 102 includes active regions and metal gate electrodes designed in a specific configuration.

[0029] The sealing ring region 104 includes a sealing ring structure to provide protection for integrated circuits in the circuit region from various environmental damages, such as moisture and chemicals. The sealing ring structure includes multiple layers extending vertically from the substrate through the interconnect structure and down to the passivation layer. The sealing ring structure can be formed simultaneously with circuit components in the circuit region (or chip region, device region, die) at various manufacturing stages, such as in front-end (FEOL) structures, mid-end (MEOL) structures, and / or back-end (BEOL) structures. As used herein, an FEOL structure includes structural components of transistors or other semiconductor devices fabricated on a semiconductor substrate; a MEOL structure includes source / drain contact vias or gate contact vias; and a BEOL structure includes interconnect structures and a passivation structure above the interconnect structures. In the BEOL process, wires or vias are formed in multiple metal layers stacked above the semiconductor substrate to connect various components in the circuit region. Simultaneously, conductive rings and via rings are formed in the sealing ring region of each metal layer. However, the conductive rings and via rings in the sealing ring region do not provide electrical functionality for the semiconductor structure like the wires and vias in the device region. Conversely, the conductive rings and via rings in the sealing ring region surround and protect the circuit area from moisture, mechanical stress, or other defect formation mechanisms. This functional difference results in the sealing ring region having different characteristics from the circuit area, such as pattern size and / or pattern density. These differences in characteristics can cause processing problems, such as over-etching in etching processes and / or depressions in chemical mechanical planarization (CMP) processes, especially in the area between the sealing ring region and the circuit area.

[0030] The dicing region 106 is designed such that the circuit substrate can be cut through by any suitable technique (such as mechanical sawing, laser cutting, dry etching, blade cutting, plasma cutting, other cutting techniques, or combinations thereof) to form individual circuit dies (chips). In this embodiment, plasma cutting is used, therefore the dicing region is also referred to as plasma dicing (PD) lane 106. During the plasma cutting process, various problems may be introduced into the semiconductor structure 100, such as metal residue, contamination, other problems, or combinations thereof. In this embodiment of the disclosure, PD lane 106 is designed with a suitable structure to eliminate various problems, such as metal residue introduced during etching. PD lane 106 will be described in further detail below.

[0031] The protective ring wall 108 is the region outside the PD channel 106 that has a structure similar to the sealing ring structure in the sealing ring region 104. The boundary region 110 is the region where the various devices for process control monitoring (PCM) are formed during the IC manufacturing process, and is therefore also referred to as the PCM region 110. The protective ring wall 108 is also designed to protect the PCM region 110.

[0032] Semiconductor structure 100 includes a substrate (such as a semiconductor substrate) having a top surface spanning along the x and y directions, and various structures (such as IC devices, interconnect structures, and passivation structures) stacked along the z direction. The x, y, and z directions constitute Cartesian coordinates. In the disclosed embodiments, semiconductor structure 100 includes a suitable shape, such as a square, rectangle, or other suitable shape. In a further embodiment, semiconductor structure 100 includes four corners A, B, C, and D, and four edges AB, BC, CD, and DA.

[0033] The sealing ring structure in sealing ring region 104 is disposed above the substrate and formed in a plurality of metal layers stacked above it and along the z-direction, as discussed in detail below. Sealing ring region 104 has a rectangular or substantially rectangular perimeter that completely surrounds circuit region 102. The four corners A, B, C, and D of the rectangular perimeter are replaced by four sloping corner lines connecting adjacent segments AB, BC, CD, and AD of sealing ring region 104.

[0034] The semiconductor structure 100 includes various component layers extending vertically from the substrate through the interconnect structure and into the passivation layer in the device structure within the circuit region 102 and the sealing ring structure within the sealing ring region 104. The sealing ring structure in the sealing ring region 104 has an annular geometry designed to better protect the circuit devices in the circuit region 102. Specifically, the sealing ring structure in the sealing ring region 104 also includes active regions, gate stacks, and other components designed differently from those in the circuit region 102 for better protection of the circuit devices in the circuit region 102. For example, the active region 112 in the circuit region 102 is longitudinally oriented along the x-direction, while the active region 112 in the sealing ring region 104 is longitudinally oriented along a sealing ring having an annular shape. In another example, the gate stack 114 in the circuit region 102 is longitudinally oriented along the y-direction, while the gate stack 114 in the sealing ring region 104 is longitudinally oriented along a sealing ring having an annular shape. The protective ring wall 108 is configured similarly to the sealing ring structure in the sealing ring region 104.

[0035] Furthermore, PD channel 106 is configured differently from the circuit in circuit region 102 and the sealing ring structure in sealing ring region 104, which will be described further below. Window portion 116 of circuit region 102 and various window portions 118, 120, and 122 of semiconductor structure 100 are further shown in the following figures.

[0036] Figure 2A , Figure 2B , Figure 2C and Figure 2DThese are top views of window portions 116, 118, 120, and 122 of a semiconductor structure 100 constructed according to some embodiments. For simplicity, only the active region 112, gate stack 114, and isolation component 124 are shown. In the disclosed embodiments, the isolation component 124 is a shallow trench isolation (STI) component. The active region 112 protrudes from the substrate such that the top surface of the active region lies above the top surface of the isolation component 124. The active region 112 includes the channel region of a transistor. The transistor may be a FinFET, GAA FET, CFET, other suitable transistors, or combinations thereof. If it is a GAA transistor, the active region will include multiple stacked nanostructures. The isolation component 124 is adjacent to each of the active regions such that the respective active regions are separated and isolated from each other. The gate stack is a conductive component in a field-effect transistor and is designed to be coupled to the channel and allow current to flow from the source to the drain. The gate stack includes a gate dielectric layer, a gate electrode disposed on the gate dielectric layer, and may further include gate spacers disposed on the sidewalls of the gate electrode. The gate dielectric layer includes one or more dielectric materials disposed on a semiconductor channel. For example, the gate dielectric layer includes silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. The gate electrode includes one or more conductive materials, such as copper, aluminum, cobalt, nickel, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, other metals, metal alloys, or combinations thereof. The gate spacers include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof.

[0037] like Figure 2A As shown, the active regions 112 in the circuit region 102 are longitudinally oriented in the same direction (x direction), and the gate stacks 114 in the circuit region 102 are longitudinally oriented in the same direction (y direction).

[0038] The active regions 112 in the sealing ring region 104 within the window portion 118 are longitudinally oriented in different directions, forming a ring shape to provide protection for the circuit devices in the circuit region 102. The segments of the active regions 112 adjacent to segments BC and AD of the sealing ring region 104 are longitudinally oriented along the X direction, as shown... Figure 2C As shown; the active region 112 of segments AB and CD adjacent to the sealing ring region 104 is longitudinally oriented along the Y direction, as shown. Figure 2B As shown; and the segments of the active region 112 in the corner are longitudinally oriented at an angle (e.g., 45° relative to the X direction), such that those segments connect to adjacent segments to form a continuous loop, as shown. Figure 2D As shown in the image.

[0039] The active region 112 in circuit region 102 has a first width W1, and the active region 112 in sealing ring region 104 has a second width W2 different from the first width W1. Specifically, W2 is substantially larger than W1. In some embodiments, the ratio W2 / W1 is in the range of 5 to 15. In some embodiments, W1 is in the range of 0.02 μm to 0.08 μm; and W2 is in the range of 0.1 μm to 0.4 μm.

[0040] The active region 112 in circuit region 102 has a first spacing P1, and the active region 112 in sealing ring region 104 has a second spacing P2 different from the first spacing P1. Specifically, P2 is substantially larger than P1. In some embodiments, the ratio P2 / P1 is in the range of 2 to 6. In some embodiments, P1 is in the range of 0.05 μm to 0.2 μm; and P2 is in the range of 0.2 μm to 0.8 μm.

[0041] Furthermore, dimensional parameters (such as W2 and P2) can be varied depending on manufacturing requirements (such as pattern density uniformity) and device performance factors. For example, those variations can be used to adjust the pattern density to provide an optimal environment to enhance the corresponding process (e.g., CMP or etching) and / or mechanical strength to reduce cracking issues, such as... Figure 2E One example is shown in the top view of window portion 120 according to some embodiments. In this example, the width of the active region 112 varies periodically from Wa to Wb, where Wb is less than Wa. For example, the ratio Wa / Wb is in the range of 1.2 to 1.8. In various embodiments, the variation can be designed randomly or periodically. The variation can be a combination of pitch variation and width variation. The width / pitch variation of the OD in the sealing ring and the gate depends on process requirements (e.g., pattern density uniformity) to provide an optimal environment for etching or CMP processes.

[0042] The active region 112 in the sealing ring region 104 further differs from the active region 112 in the circuit region 102 in terms of continuity. The active region 112 in the circuit region 102 is not continuous and is segmented, depending on the individual circuits and design layout, such as... Figure 2FAs shown in the diagram. However, the active regions 112 in the sealing ring region 104 extend continuously around the circuit region. The active regions 112 in the sealing ring region 104 include a plurality of active regions 112, each extending continuously in a ring shape, such as extending from segment AB, continuously extending to corner B, continuously extending to segment BC, continuously extending to corner C, continuously extending to segment CD, continuously extending to corner D, continuously extending to segment DA, and continuously extending back to corner A. It should be noted that the number of active regions 112 in the sealing ring region 104 is not limited to any particular number and can include any suitable number, such as 4 to 8, depending on the individual circuit and design.

[0043] Furthermore, the gate stacks 114 in circuit region 102 and sealing ring region 104 are configured differently. In the disclosed embodiment, the gate stacks 114 in circuit region 102 are longitudinally oriented in the Y direction, which is orthogonal to the orientation (X direction) of the active region 112 in circuit region 102. Conversely, the gate stacks 114 in sealing ring region 104 are longitudinally oriented parallel to the orientation (Y direction) of the active region 112 in sealing ring region 104. Furthermore, the gate stacks 114 are fully bonded to the respective active regions 112. For example, the gate stacks 114 are bonded to the center of the active region 112 with margins on both sides, such as equal margins on both sides. In this case, the width Wg of the gate stacks 114 is less than the width W2 of the active region 112. In some embodiments, the ratio W2 / Wg is in the range of 1.5 and 2. This configuration of the gate stacks 114 and the active region 112 in sealing ring region 104 makes the sealing structure more robust. The continuity from the active region 112 to the gate stack 114 provides better sealing. In this embodiment, the gate stack 114 is formed simultaneously with the same composition, such as by gate replacement. For example, the gate stack 114 includes a gate dielectric layer (such as an interface layer and a high-k dielectric material layer) and a gate electrode (such as a metal material that also includes a work function metal layer and a fill metal layer).

[0044] The active region 112 and gate stack 114 in the guard ring wall region 108 may have a similar structure in orientation and continuity to the active region 112 and gate stack 114 in the sealing ring region 104. For example, the active region 112 in the guard ring wall region may be oriented to form multiple continuous rings to surround the PD channel 106.

[0045] Referring further to the following figures, the semiconductor structure 100, particularly the structure in the PD channel 106, will be described in further detail below. According to various embodiments, reference will be made first below. Figures 3A to 3F Describe PD channel 106 in window section 118.

[0046] refer to Figure 3A PD channel 106 is located between sealing ring region 104 and guard ring wall region 108. The active region 112 and gate stack 114 in adjacent sealing ring region 104 and guard ring wall region 108 have been described above and will not be repeated here.

[0047] The gate structure and active region in PD channel 106 are dummy components and are designed to differ from those in circuit region 102, sealing ring region 104, and guard ring wall 108. Specifically, the gate stack in PD channel 106 differs in orientation and composition from those in circuit region 102. In some embodiments, the gate stack in PD channel 106 is a dielectric component, also referred to as a dielectric gate stack or simply a dielectric structure. In this case, the gate stack (as a whole) is a dielectric component and does not include a gate electrode or any conductive component. Although the dielectric gate stack is still referred to as gate stack 114, it should be understood that it differs from a functional gate stack that includes a metal gate electrode or a polysilicon gate electrode. In some of the following figures, those dielectric gate stacks are also indicated by different reference numerals, such as reference numeral 242.

[0048] In PD channel 106, the gate stack 114 in PD channel 106 within window portion 118 is longitudinally oriented in the same direction (y direction) as the gate stack 114 in circuit region 102. However, the active region 112 and the gate stack 114 in PD channel 106 are configured differently.

[0049] The PD channel 106 includes two regions: a central region 106A and side regions 106B disposed on both sides of the central region 106A. In the disclosed embodiments, the central region 106A is the cutting region to be cut through, such as by plasma cutting. The side regions 106B are buffer regions between the cutting region and the sealing ring region 104 or between the cutting region and the protective ring wall region 108. The buffer regions will not be cut, but will provide cushioning. The central region 106A spans dimension D1 in the x-direction, and the side regions 106B spans dimension D2 in the x-direction. The PD channel 106 spans dimension D in the x-direction, where D = D1 + 2 * D2. In some embodiments, D is in the range of 2 μm and 10 μm; and D1 is in the range of 0.5 μm to 2.5 μm.

[0050] In the following embodiments, the dummy components in the central region 106A and the side region 106B are designed differently.

[0051] In the central region 106A, the active regions 112 are longitudinally oriented in the same direction (x-direction). In the disclosed embodiment, the active regions 112 extend continuously along the x-direction to the edge of the central region 106A. The gate stacks 114 are longitudinally oriented in the same direction (y-direction). In the disclosed embodiment, the gate stacks 114 extend continuously along the y-direction to the edge of the central region 106A. In the disclosed embodiment, two gate stacks 114 are disposed at both ends of the active regions 112. In a further embodiment, the active regions 112 in the central region 106A are periodically disposed along the y-direction, and the gate stacks 114 in the central region 106A are periodically disposed along the x-direction.

[0052] In some embodiments, the active region 112 in the central region 106A has a third width W3 different from the first width W1 and a third spacing P3 different from the first P1. In particular, W3 is substantially larger than W1. In some embodiments, the ratio W3 / W1 is in the range of 2 to 4. In some embodiments, W3 is in the range of 0.04 μm to 0.15 μm.

[0053] Side region 106B has no active regions 112, but includes gate stacks 114 in different configurations. Specifically, the gate stacks 114 include a first subset of gate stacks 114A longitudinally oriented along the y-direction and a second subset of gate stacks 114B longitudinally oriented along the x-direction. In the disclosed embodiments, the first subset of gate stacks 114A is similar in orientation and size to the gate stacks 114 in the central region 106A. According to the disclosed embodiments, the second subset of gate stacks 114B spans a length less than the length of the first subset of gate stacks 114A. The first subset of gate stacks 114A and the second subset of gate stacks 114B are connected to each other, as shown below. Figure 3A As shown in the diagram. The number N1 of the first subset of gate stacks 114A on each side region 106B and the number N2 of the second subset of gate stacks 114B can be any suitable integer, such as N1 = 2 and N2 = 3, depending on the individual circuitry. In various instances, each of N1 and N2 is in the range between 2 and 10.

[0054] Specifically, the gate stack 114 in PD channel 106 differs from the gate stack 114 in circuit region 102 in composition, size, and formation. According to some embodiments, the gate stack 114 in PD channel 106 is a dielectric component and includes one or more dielectric materials. In the disclosed embodiments, the gate stack 114 in PD channel 106 is made of one or more dielectric materials. In a further embodiment, the gate stack 114 in PD channel 106 is made of silicon nitride (SiN). Furthermore, the gate stack 114 in PD channel 106 extends vertically along the z-direction with a dimension larger than that of the gate stack 114 in circuit region 102. In addition, the gate stack 114 in PD channel 106 is formed by different methods. In some embodiments, the gate stack 114 in PD channel 106 is formed by steps including forming a dummy gate stack and replacing the dummy gate stack with a dielectric material. In some embodiments, the gate stack 114 in PD channel 106 is formed to have gate-cut components by a gate dicing step. The gate dicing process includes: using photolithography and etching to pattern the gate stack to cut the long gate stack into shorter segments, thereby creating a trench; and filling the trench with one or more dielectric materials to form the gate dicing part, and simultaneously forming the gate stack 114 in the PD channel 106 in the present case.

[0055] Figure 3B Another embodiment of the pseudo-structure in PD channel 106 is provided. Figure 3B Similar to Figure 3A For simplicity, similar descriptions will not be repeated herein. However, the gate stacks 114 in side region 106B are configured differently. In the disclosed embodiment, N2 is greater than N1, and N1 = 3 and N2 = 5. As described above, N1 and N2 can be any suitable integer. Furthermore, a second subset of the gate stacks 114B between different pairs of gate stacks 114A is aligned along the x-direction.

[0056] Figure 3C Another embodiment of the pseudo-structure in PD channel 106 is provided. Figure 3C Similar to Figure 3A For simplicity, similar descriptions will not be repeated herein. However, the gate stacks 114 in side region 106B are configured differently. In the disclosed embodiment, N2 is greater than N1, and N1 = 3 and N2 = 6. As described above, N1 and N2 can be any suitable integer. Furthermore, a second subset of the gate stacks 114B between different pairs of gate stacks 114A is offset along the x-direction or configured in an interleaved pattern.

[0057] As described above, metal residues can be introduced into PD lane 106 during the various etching processes. This can cause concerns about plasma cutting, such as cutting efficiency, cutting uniformity, chipping, and cracking. Since PD lane 106 is designed with dielectric gate stacks and contains no metal, the etching process will not introduce metal residues into PD lane 106. This eliminates and significantly reduces those problems.

[0058] In some embodiments, the gate stack 114B in side region 106B is a metal gate stack that is similar in composition to the gate stack 114 in circuit region 102, such as Figures 3D to 3F Those shown.

[0059] Figure 3D The pseudostructure in PD channel 106 is similar to Figure 3A The pseudo-structure. However, the gate stack 114B in side region 106B is a metal gate stack, while the gate stack 114A in central region 106A is a dielectric component, such as a silicon nitride dielectric component. In the disclosed embodiments, the gate stack 114B in side region 106B includes a gate dielectric layer of one or more dielectric materials and a gate electrode of one or more conductive materials (such as metals, metal alloys, or combinations thereof) disposed on the gate dielectric layer, and gate spacers disposed on the sidewalls of the gate electrode; those gate stacks are referred to as metal gate stacks. In this embodiment, the gate stack 114B in side region 106B is formed simultaneously with the gate stack 114 in circuit region 102. For example, both are formed by steps including forming a pseudo gate stack (such as a polysilicon gate stack) and replacing the pseudo gate stack with a metal gate stack. However, the gate stack 114B in side region 106B differs from the gate stack 114 in circuit region 102 in terms of size and configuration.

[0060] As described above, in the PD channel, the central region 106A and the side regions 106B undergo different processes, such as different processes during etching and plasma cutting, and are therefore designed differently to reduce cutting problems (such as metal residue during plasma cutting) and to achieve / maintain other processing properties (such as pattern density and chemical mechanical polishing (CMP) uniformity). This is because metal residue (if any) is only present in the side regions 106B and far from the central region 106A; therefore, the central region 106A, which is the cutting area, is free of metal, thus eliminating problems associated with metal residue.

[0061] Figure 3E The pseudostructure in PD channel 106 is similar to Figure 3BThe pseudo-structure. However, the gate stack 114B in the side region 106B is a metal gate stack, while the gate stack 114A in the central region 106A is a dielectric component, such as a silicon nitride dielectric component.

[0062] Figure 3F The pseudostructure in PD channel 106 is similar to Figure 3C The pseudo-structure. However, the gate stack 114B in the side region 106B is a metal gate stack, while the gate stack 114A in the central region 106A is a dielectric component, such as a silicon nitride dielectric component.

[0063] Now, according to various embodiments, the following references are made. Figures 4A to 4F The PD channel 106 in window portion 120 is described. In this case, the sealing ring region 104 and the protective ring wall region 108 are disposed on both sides of the PD channel 106 along the y-direction. It should be noted that the dummy components in the PD channel 106 in window portion 120 differ in configuration and composition from those in the PD channel 106 in window portion 118. Specifically, all gate stacks 114 in the PD channel 106 within window portion 120 are metal-free and are dielectric components, such as SiN dielectric components. This is because the plasma cutting process will cut through all sub-regions of the PD channel 106. The metal-free gate stacks 114 in the PD channel 106 within window portion 120 effectively eliminate metal residue and enhance plasma cutting performance.

[0064] refer to Figure 4A The PD channel 106 is located between the sealing ring region 104 and the guard ring wall region 108 along the x-direction. The active region 112 and the gate stack 114 in the adjacent sealing ring region 104 and guard ring wall region 108 have been described above and will not be repeated here.

[0065] The gate stack 114 in the PD channel 106 within the window portion 120 is longitudinally oriented in the same direction (y direction) as the gate stack 114 in the circuit region 102. However, the active region 112 and the gate stack 114 in the PD channel 106 are configured differently.

[0066] PD channel 106 includes two regions: a first region 106C and a second region 106D disposed on both sides of the first region 106C. In the following embodiments, the pseudo-components in the first region 106C and the second region 106D are designed differently. The pseudo-components in PD channel 106 are similar to those in the PD channel within window portion 118, but the central region 106A is replaced by the first region 106C, and the side regions 106B are replaced by the second region 106D. For simplicity, similar descriptions will not be repeated herein.

[0067] In the first region 106C, the active regions 112 are longitudinally oriented in the same direction (x-direction). In the disclosed embodiment, the active regions 112 extend continuously along the x-direction to the edge of the first region 106C. The gate stacks 114 are longitudinally oriented in the same direction (y-direction). In the disclosed embodiment, the gate stacks 114 extend continuously along the y-direction to the edge of the first region 106C. In the disclosed embodiment, two gate stacks 114 are disposed at both ends of the active regions 112. In a further embodiment, the active regions 112 in the first region 106C are periodically disposed along the y-direction, and the gate stacks 114 in the first region 106C are periodically disposed along the x-direction.

[0068] In some embodiments, the active region 112 in the first region 106C has a third width W3 different from the first width W1 and a third spacing P3 different from the first P1. In particular, W3 is substantially larger than W1. In some embodiments, the ratio W3 / W1 is in the range of 2 to 4. In some embodiments, W3 is in the range of 0.04 μm to 0.15 μm.

[0069] The second region 106D has no active regions 112, but includes gate stacks 114 in a different configuration. Specifically, the gate stacks 114 include a first subset of gate stacks 114A oriented longitudinally along the y-direction and a second subset of gate stacks 114B oriented longitudinally along the x-direction. In the disclosed embodiments, the first subset of gate stacks 114A is similar in orientation and size to the gate stacks 114 in the first region 106C. According to the disclosed embodiments, the second subset of gate stacks 114B spans a length less than the length of the first subset of gate stacks 114A. The first subset of gate stacks 114A and the second subset of gate stacks 114B are connected to each other, as shown below. Figure 4A As shown in the diagram. The number N1 of the first subset of gate stacks 114A and the number N2 of the second subset of gate stacks 114B on each second region 106D can be any suitable integer, such as N1 = 2 and N2 = 2, depending on the individual circuitry. In various instances, each of N1 and N2 is in the range between 1 and 5.

[0070] Specifically, the gate stack 114 in PD channel 106 differs from the gate stack 114 in circuit region 102 in composition, size, and formation. According to some embodiments, the gate stack 114 in PD channel 106 is a dielectric component and includes one or more dielectric materials. In the disclosed embodiments, the gate stack 114 in PD channel 106 is made of one or more dielectric materials. In a further embodiment, the gate stack 114 in PD channel 106 is made of silicon nitride (SiN). In some embodiments, the gate stack 114 in PD channel 106 is made of silicon nitride (SiN), silicon oxynitride, silicon oxide, other suitable dielectric materials, or combinations thereof. Furthermore, the gate stack 114 in PD channel 106 extends vertically along the z-direction with a dimension larger than that of the gate stack 114 in circuit region 102. In addition, the gate stack 114 in PD channel 106 is formed by different methods. In some embodiments, the gate stack 114 in PD channel 106 is formed by steps including forming a dummy gate stack and replacing the dummy gate stack with a dielectric material. In some embodiments, the gate stack 114 in PD channel 106 is formed to have gate dicing features by a gate dicing step. The gate dicing process includes: using a photolithography process and etching to pattern the gate stack to cut a long gate stack into shorter segments, thereby creating a trench; and filling one or more dielectric materials into the trench to form the gate dicing features, and in the present case, simultaneously forming the gate stack 114 in PD channel 106.

[0071] Figure 4B Another embodiment of the pseudo-structure in PD channel 106 is provided. Figure 4B Similar to Figure 4A For simplicity, similar descriptions will not be repeated herein. However, the gate stacks 114 in the second region 106D are configured differently. In the disclosed embodiment, N2 is greater than N1, and N1 = 3 and N2 = 4. As described above, N1 and N2 can be any suitable integer. In the disclosed embodiment, a second subset of gate stacks 114B between different pairs of gate stacks 114A is aligned along the x-direction. Furthermore, the second subsets of gate stacks 114B on the left side of the second region 106D and on the right side of the second region 106D are aligned along the x-direction.

[0072] Figure 4C Another embodiment of the pseudo-structure in PD channel 106 is provided. Figure 4C Similar to Figure 3CFor simplicity, similar descriptions will not be repeated herein. However, the gate stacks 114 in the second region 106D are configured differently. In the disclosed embodiment, N2 is greater than N1, and N1 = 3 and N2 = 4. As described above, N1 and N2 can be any suitable integer. Furthermore, a second subset of the gate stacks 114B between different pairs of gate stacks 114A is offset along the x-direction or configured in an interleaved pattern.

[0073] As described above, metal residues may be introduced into PD lane 106 during the various etching processes. This will raise concerns about plasma cutting, such as cutting efficiency, cutting uniformity, chipping, and cracking. In PD lane 106, all gate stacks 114 (including 114A and 114B) are designed to have dielectric gate stacks and contain no metal.

[0074] Figure 4D Another embodiment of the pseudo-structure in PD channel 106 is provided. Figure 4D The pseudostructure in PD channel 106 is similar to Figure 4A The pseudo-structure. However, PD channel 106 includes a plurality of first regions 106C and second regions 106D alternately arranged along the x-direction. Each of the first regions 106C is similar to Figure 4A The first region 106C. Each of the second regions 106D is similar to Figure 4A The second region 106D is included. In this embodiment, the pseudo-structures in the PD channels 106 within the window portion 120 include three in the first region 106C and four in the second region 106D. However, those numbers can vary depending on the side and individual design of the window portion 120. In a further implementation of the embodiment, all the first regions 106C are identical, and all the second regions 106D are identical.

[0075] Specifically, the active region 112 is formed only in the first region 106C, and the gate stack 114 in the second region 106D includes a first subset 114A oriented longitudinally along the y direction and a second subset 114B oriented longitudinally along the x direction.

[0076] It should be noted that the gate stacks 114 (including gate stacks 114A and 114B) in the second region 106D are all without metal and are dielectric components, unlike the gate stacks 114 in the side region 106B within the window portion 118.

[0077] Figure 4E The pseudostructure in PD channel 106 is similar to Figure 4DThe pseudo-structure. PD channel 106 includes a plurality of first regions 106C and second regions 106D alternately arranged along the x-direction. Each of the first regions 106C is similar to... Figure 4D The first region 106C, and each of the second regions 106D are similar to Figure 4D The second region 106D is shown. However, the second region 106D is not entirely identical and may have different numbers of gate stacks 114A and different sizes. In this embodiment, the second region 106D includes a first subset having a first size along the x-direction and a second subset having a second size along the x-direction. The second size is larger than the first size.

[0078] Figure 4F The pseudostructure in PD channel 106 is similar to Figure 3E The pseudo-structure. The second region 106D is not exactly the same and may have different numbers of gate stacks 114A and different sizes. In this embodiment, the second region 106D includes a first subset having a first size along the x-direction and a second subset having a second size along the x-direction. The second size is larger than the first size.

[0079] However, the gate stacks 114B in the second subset of the second region 106D are configured to be offset and in an interleaved mode. The gate stacks 114B in the first subset of the second region 106D are configured to be aligned along the x-direction.

[0080] Figure 5A yes Figure 1 A top view of the semiconductor structure 100 in window 116; and Figure 5B It is constructed according to some embodiments. Figure 1 A top view of the semiconductor structure 100 in window 118. Figure 5A Similar to Figure 2A ,and Figure 5B Similar to Figure 2B Furthermore, various dicing components, such as active region dicing component 140 and gate dicing component 142, are also formed and illustrated. Active region dicing component 140 is a dielectric component formed during a dual patterning process or a multi-patterning process to separate the long active region 112. For example, the active region is first formed in a first patterning process, and a second patterning process dices the long active region into short active regions according to a design layout. In this case, the dicing process includes: forming a patterned resist layer by photolithography; etching to form trenches dicing the active regions; depositing dielectric material to fill the trenches, and a CMP process may be further implemented to remove excess dielectric material. Similarly, the gate dicing component has similar functionality to the gate stack and is formed by a similar method.

[0081] Figure 6AIt is along Figure 1 or Figure 5B AA' cut Figure 1 A cross-sectional view of the semiconductor structure 100 in window 118; Figure 6B It is along Figure 1 or Figure 5B BB' cut Figure 1 A cross-sectional view of the semiconductor structure 100 in window 118; Figure 6C It is along Figure 1 or Figure 5A CC' cut Figure 1 A cross-sectional view of the semiconductor structure 100 in window 116; and Figure 6D It is constructed according to some embodiments along Figure 1 or Figure 5A DD' cut Figure 1 A cross-sectional view of the semiconductor structure 100 in window 116. It should be noted that only the substrate, active region, isolation components, and gate stack are shown in those figures. Other components, such as interconnect structures and passivation layers, will be described later. Figure 6A and Figure 6B Regarding the structure in the sealing ring region 104, and Figure 6C and Figure 6D For the structure in circuit region 102.

[0082] exist Figure 6AIn this embodiment, semiconductor stack 226 is formed on substrate 220. In the depicted embodiment, substrate 220 comprises silicon. Additionally or optionally, substrate 220 comprises: another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Optionally, substrate 220 is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using SIMOX, wafer bonding, and / or other suitable methods. Substrate 220 may include various doped regions, depending on the design requirements of semiconductor structure 100. In the depicted embodiments, substrate 220 includes various doped components, such as p-type doped regions (hereinafter referred to as p-wells) that can be configured for n-type gate-all-around (GAA) transistors and n-type doped regions (hereinafter referred to as n-wells) that can be configured for p-type GAA transistors. The n-type doped regions are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped regions are doped with p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, substrate 220 includes doped regions formed with a combination of p-type and n-type dopants. The respective doped regions can be formed directly on and / or in substrate 220, for example, providing p-well structures, n-well structures, double-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be implemented to form the respective doped regions.

[0083] In some embodiments, substrate 220 may be a bulk silicon (Si) substrate. Optionally, substrate 220 may include: elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. In some embodiments, substrate 220 comprises one or more group III-V materials, one or more group II-VI materials, or combinations thereof. In still other examples, substrate 220 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. In some other embodiments, substrate 220 may be a diamond substrate or a sapphire substrate.

[0084] A semiconductor layer stack 226 is formed over a substrate 220. The semiconductor layer stack 226 is patterned to form active regions, such as 112, and a gate stack 114 is formed on the active regions 112. It should be noted that the gate stack 114 within the sealing ring region 104 is different from the gate stack in the circuit region 102 or PD channel 106, and is therefore designated as 224 herein. The semiconductor layer stack 226 includes semiconductor layers 228 and 230 vertically stacked (e.g., along the z-direction) from the surface of the substrate 220 in an alternating or staggered configuration. In some embodiments, semiconductor layers 228 and 230 are epitaxially grown in the depicted alternating and staggered configuration. For example, a first of semiconductor layers 228 is epitaxially grown on a substrate, a first of semiconductor layers 230 is epitaxially grown on the first of semiconductor layers 228, a second of semiconductor layers 228 is epitaxially grown on the first of semiconductor layers 230, and so on, until the semiconductor layer stack 226 has the desired number of semiconductor layers 228 and semiconductor layers 230. In such embodiments, semiconductor layers 228 and 230 may be referred to as epitaxial layers. In some embodiments, the epitaxial growth of semiconductor layers 228 and 230 is achieved by molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), other suitable epitaxial growth processes, or combinations thereof.

[0085] Semiconductor layer 228 has a different composition than semiconductor layer 230 to achieve etch selectivity and / or different oxidation rates during subsequent processing. In some embodiments, semiconductor layer 228 has a first etch rate to an etchant, and semiconductor layer 230 has a second etch rate to an etchant, wherein the second etch rate is less than the first etch rate. In some embodiments, semiconductor layer 228 has a first oxidation rate, and semiconductor layer 230 has a second oxidation rate, wherein the second oxidation rate is less than the first oxidation rate. In the depicted embodiments, semiconductor layers 228 and 230 comprise different materials, atomic percentages of components, weight percentages of components, thicknesses, and / or properties to achieve desired etch selectivity during etching processes, such as etching processes implemented to form a suspended channel layer in a channel region of semiconductor structure 100. For example, in the case where semiconductor layer 228 comprises silicon-germanium and semiconductor layer 230 comprises silicon, in a channel-release etching process, the silicon etch rate of semiconductor layer 230 is less than the silicon-germanium etch rate of semiconductor layer 228. In some embodiments, semiconductor layer 228 and semiconductor layer 230 may comprise the same material but with different atomic percentages to achieve etch selectivity and / or different oxidation rates. For example, semiconductor layer 228 and semiconductor layer 230 may comprise silicon-germanium, wherein semiconductor layer 228 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 230 has a second different silicon atomic percentage and / or a second different germanium atomic percentage. Embodiments of this disclosure contemplate that semiconductor layer 228 and semiconductor layer 230 comprise any combination of semiconductor materials (e.g., materials that maximize current) that can provide desired etch selectivity, desired oxidation rate differences, and / or desired performance characteristics, including any of the semiconductor materials disclosed herein.

[0086] exist Figure 6B In the sealing ring region 104, a gate structure 224, a source, and a drain (collectively referred to as source / drain components) 238 are formed. It should be noted that in... Figure 6B Only one active region 112 is shown, and it is not intended to be limiting. The number of active regions 112 in the sealing ring region 104 can be any suitable number, depending on design considerations, sealing effect, and other factors. In the disclosed structure, the first semiconductor layer 228 is removed while retaining the second semiconductor layer 230 as a channel (also indicated by reference numeral 230), and multiple channels 230 are vertically stacked over the substrate 220 and connected to the source / drain components 238. The gate stack 224 includes one or more gate materials indicated by reference numeral 232. The gate stack 224 may include a gate dielectric layer and a gate electrode. In some embodiments, the gate material 232 includes polysilicon.

[0087] Gate spacer 234 is disposed on the sidewall of gate stack 224. Gate spacer 234 comprises one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Gate stack 224 is disposed on semiconductor layer stack 226. In this case, the structure of the active region 112 and gate stack 224 in sealing ring region 104 differs from that in circuit region 102 because circuit region 102 includes GAA transistors, the first semiconductor layer 228 is removed to release the channel, and the gate stack extends downward to enclose the vertically stacked channel, which will be further described below. The sealing ring structure in sealing ring region 104 may also include various dicing portions formed during dual or multiple patterning processes, such as active region dicing portion 140 and gate dicing portion 142. In some embodiments, active region dicing portion 140 is a dielectric portion or a subset thereof is a dielectric fin (relative to the fin active region) configured to adjust pattern density and pattern uniformity to enhance fabrication (such as CMP process). Source and drain (or source / drain components) 238 are formed on the active region 112, contacting the first semiconductor layer 228 and the second semiconductor layer 230.

[0088] The gate electrode layer may comprise a single-layer or optionally multi-layer structure, such as a metal layer (power function metal layer) having a selected work function to enhance device performance, a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed using ALD, PVD, CVD, electron beam evaporation, or other suitable processes.

[0089] The source / drain components may include silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)) or silicon germanium (SiGe) doped with a p-type dopant (such as boron (B) or boron difluoride (BF2)). The source / drain contacts may include a silicide layer, a metal filler layer disposed above the silicide layer, and a barrier layer separating the metal filler layer from the IMD layer. The barrier layer may include titanium nitride or tantalum nitride and is used to prevent electromigration in the metal filler layer. The silicide layer may include titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide. The silicide layer is disposed at the interface between the metal filler layer and the source / drain components to reduce contact resistance. The metal filler layer may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), or other suitable metallic materials.

[0090] exist Figure 6C and Figure 6DIn this embodiment, circuit region 102 includes a multi-channel device, such as a GAA transistor, formed on substrate 220. The multi-channel device includes a plurality of channels vertically stacked on substrate 220, and a gate stack 114 extends to enclose and couple to each of the vertically stacked channels. It should be noted that the gate stack in circuit region 102 is designated by reference numeral 222 due to different compositions. Sources and drains 238 are disposed on opposite sides of the gate stack 222 and connect to each of the vertically stacked channels 230. In the disclosed embodiment, a first semiconductor layer 228 is removed to release the channels, and a second semiconductor layer 230 serves as the channel for the multi-channel transistor. Gate stack 222 includes a gate dielectric layer and a gate electrode, collectively referred to as the gate material, designated by reference numeral 233. It should be noted that, according to some embodiments, the gate material 233 may differ from the gate material 232. For example, the gate material 233 includes a gate dielectric layer (which also includes a high-k dielectric material) and a gate electrode (which also includes a metal). Gate stack 222 extends to enclose each of channels 230. Source / drain components 238 are isolated from gate stack 222 by internal spacers 236 and gate spacers 234. Internal spacers 236 comprise one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Formation of the disclosed structure includes: forming a dummy gate by deposition (such as polysilicon) and patterning; forming source / drain components by etching to recess the source / drain regions, laterally recessing the first semiconductor layer 228, forming the internal spacers 236 by deposition and anisotropic etching, and epitaxially growing to form the source / drain components 238; forming an interlayer dielectric (ILD) layer; removing the dummy gate by selective etching; selectively removing the first semiconductor layer 228 to release the channel; and forming a metal gate by deposition to enclose the channel. A subset of the above operations forming gate stack 222 is referred to as gate replacement. The replaced gate stack 222 comprises a high-k dielectric material and metal.

[0091] Back Figure 6A and Figure 6B Because gate stack 224 is not formed by gate replacement, the gate material of gate stack 224 is different from the gate material of gate stack 222. For example, gate stack 224 comprises polysilicon. In some embodiments, the gate stack in sealing ring region 104 is partially replaced, such as by replacing only the dummy gate but not removing the first semiconductor layer 228, and the channel is not released in sealing ring region 104. In this case, gate stack 224 has the same composition as gate stack 222, but a different configuration, such as... Figure 6A , Figure 6B , Figure 6C and Figure 6DAs shown in the diagram. In some embodiments, the gate stack 224 in the sealing ring region 104 is formed similarly to the gate stack 222 in the circuit region 102. Specifically, the dummy gate is replaced, and the first semiconductor layer 228 is removed, and a channel is released in the sealing ring region 104, as shown in the diagram. Figure 6E and Figure 6F As shown in the illustration. In some embodiments, the gate dicing member 142 may be formed before, after, or after the dummy gate. In the various embodiments described above, the gate stack 224 may be formed either by gate replacement or optionally without gate replacement, and various parameters of the sealing ring structure (such as the width and spacing of the active regions 112) may vary randomly or periodically, or according to other considerations, such as Figure 2E As shown in the image.

[0092] In other embodiments, the gate dicing member 142 may be configured differently in the circuit region 102, such as Figure 6G As shown in the image. Figure 6G Similar to Figure 6D The difference lies in the configuration of the gate dicing members 142. In the disclosed embodiment, the gate dicing members 142 are formed on each fin dicing member 140. The gate stack 224 is diced into multiple segments.

[0093] In other embodiments, the gate dicing member 142 may be configured differently in the sealing ring region 104, such as Figure 6H and Figure 6I As shown in the image. Figure 6H Similar to Figure 6A The difference lies in the different configuration of the gate cutting component 142. Figure 6I Similar to Figure 6E The difference lies in the different configuration of the gate cutting component 142.

[0094] Now let's return to the structure in PD channel 106. (See reference...) Figure 7 and Figures 8A to 8D as well as Figures 9A to 9D Further description of PD channel 106.

[0095] Figure 7 According to some embodiments Figure 3A AA' cut through Figure 1 or Figure 3A A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 118.

[0096] As described above, the PD channel in window portion 118 includes a central region 106A and a side region 106B. The central region 106A includes an active region 112 and a gate stack 114, while the side region 106B does not have an active region 112 and only includes the gate stack 114 formed on the isolation member 124. However, the gate stack 114 is a dielectric component, such as a SiN component, formed by a suitable method. Therefore, those dielectric gate stacks are referred to as dielectric gate stacks with the designation 242. In the disclosed embodiments, the dielectric gate stacks in the PD channel 106 are formed separately. In some embodiments, the gate stack 114, as a dielectric component, is formed by a gate dicing process (described above) and is formed simultaneously with other gate dicing components 142 in the same gate dicing process. In a further embodiment, the dielectric gate stack 242 extends deeply downward into the substrate 220 and below the bottom surface of the isolation member 124. The structure also includes an interlayer dielectric (ILD) layer 250 formed by appropriate methods, such as steps including deposition and chemical mechanical polishing (CMP). The structure also includes an etch stop layer (ESL) 252 formed beneath the ILD layer 250 to provide etch selectivity. In various embodiments, the ILD layer 250 comprises silicon oxide, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. The ESL 252 comprises one or more dielectric materials different from the ILD layer 250. For example, the ESL 252 comprises SiN, SiON, other dielectric materials, or combinations thereof. It should be noted that the number of gate stacks in the central region 106A and the side regions 106B may not be mismatched. Figure 3A Those mentioned are for illustrative purposes only and are not intended to be restrictive.

[0097] Figure 8A According to some embodiments Figure 3A AA' cut through Figure 1 or Figure 3A A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 118.

[0098] Figure 8A The semiconductor structure 100 in the middle is similar to Figure 7The semiconductor structure 100 is shown. The PD channel 106 in the window portion 118 includes a central region 106A and a side region 106B. The central region 106A includes an active region 112 and a gate stack 114, while the side region 106B lacks an active region 112 and includes only the gate stack 114 formed on the isolation member 124. However, the gate stack 114 is a dielectric component, such as a SiN component, formed by a suitable method. In the disclosed embodiment, the gate stack 114, as a dielectric component, is formed by a separate step and is referred to as the dielectric gate stack 242. In a further embodiment, the dielectric gate stack 242 extends deeply downward into the substrate 220 and below the bottom surface of the isolation member 124. The structure also includes an interlayer dielectric (ILD) layer 250 formed by a suitable method, such as steps including deposition and chemical mechanical polishing (CMP). The structure also includes an etch stop layer (ESL) 252 formed beneath the ILD layer 250 to provide etch selectivity. In various embodiments, ILD layer 250 comprises silicon oxide, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. ESL 252 comprises one or more dielectric materials different from ILD layer 250. For example, ESL 252 comprises SiN, SiON, other dielectric materials, or combinations thereof. It should be noted that the number of gate stacks in the central region 106A and the side regions 106B may not be mismatched. Figure 3A Those mentioned are for illustrative purposes only and are not intended to be restrictive.

[0099] Figure 8B According to some embodiments Figure 3B or Figure 3C AA' cut through Figure 1 A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 118. Figure 8B Similar to Figure 8A Although those structures differ, such as in the top view. For simplicity, this article will not repeat similar descriptions.

[0100] Figure 8C According to some embodiments Figure 3D AA' cut through Figure 1 A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 118. Figure 8D Similar to Figure 8A However, the gate stacks in side region 106B are metal gate stacks similar to those in circuit region 102. Therefore, those gate stacks in side region 106B are referred to as metal gate stacks with the designation 222. For simplicity, a similar description will not be repeated herein.

[0101] Figure 8DAccording to some embodiments Figure 3E or Figure 3F AA' cut through Figure 1 A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 118. Figure 8D Similar to Figure 8B However, the gate stacks in side region 106B are metal gate stacks similar to those in circuit region 102. Therefore, those gate stacks in side region 106B are referred to as metal gate stacks with the designation 222. For simplicity, a similar description will not be repeated herein.

[0102] Figure 9A According to some embodiments Figure 4A AA' cut through Figure 1 or Figure 4A A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 120.

[0103] The PD channel 106 in window portion 120 includes a first region 106C and a second region 106D. The first region 106C includes an active region 112 and a gate stack 114, while the second region 106D lacks an active region 112 and includes only the gate stack 114 formed on the isolation member 124. However, the gate stack 114 in both regions 106C and 106D is a dielectric component, such as a SiN component, formed by a suitable method. In the disclosed embodiments, the gate stack 114, as a dielectric component, is formed by steps including patterning, deposition, and CMP. Therefore, those dielectric gate stacks are referred to as dielectric gate stacks with the designation 242. In a further embodiment, the dielectric gate stack 242 extends deeply downward into the substrate 220 and below the bottom surface of the isolation member 124. The structure also includes an ILD layer 250 formed by a suitable method, such as steps including deposition and CMP. The structure also includes an ESL 252 formed beneath the ILD layer 250 to provide etch selectivity. In various embodiments, the ILD layer 250 comprises silicon oxide, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. The ESL 252 comprises one or more dielectric materials different from the ILD layer 250. For example, the ESL 252 comprises SiN, SiON, other dielectric materials, or combinations thereof.

[0104] Figure 9B According to some embodiments Figure 4B or Figure 4C AA' cut through Figure 1 A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 120. Figure 9B Similar to Figure 9AAlthough those structures differ, such as in the top view. For simplicity, this article will not repeat similar descriptions.

[0105] Figure 9C According to some embodiments Figure 4D AA' cut through Figure 1 A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 120. Figure 9C Similar to Figure 8A However, the PD channels 106 in window portion 120 include multiple channels in the first region 106C and multiple channels in the second region 106D. For simplicity, a similar description will not be repeated here.

[0106] Figure 9D According to some embodiments Figure 4E or Figure 4F AA' cut through Figure 1 A cross-sectional view of the semiconductor structure 100 within the PD channel 106 in the window portion 120. Figure 9D Similar to Figure 9B However, the PD channels 106 in window portion 120 include multiple channels in the first region 106C and multiple channels in the second region 106D. For simplicity, a similar description will not be repeated here.

[0107] The semiconductor structure 100 in the various embodiments can be formed using other techniques, such as system-on-chip (SoC), integrated fan-out (InFO) packaging, stacked package (POP), chip-on-wafer on substrate (CoWoS), and other suitable structures / technologies.

[0108] As previously described, after forming the active regions, channels, source / drain components, and gate stack, interconnect structures and passivation layers are further formed thereon. The components in the sealing ring region 104 are also designed differently from those in the circuit region 102, as described in further detail below.

[0109] refer to Figure 10A The method 600 for forming a semiconductor structure 100 is further described as a flowchart of a method 600 constructed according to some embodiments. Figure 10B This is a flowchart of a method 613 for forming a dielectric gate stack constructed according to some embodiments. Figures 11 to 15 These are cross-sectional views of semiconductor structures 100 constructed at different manufacturing stages according to various embodiments. Specifically, Figure 11 , Figure 12 and Figure 13 Column (A) and Figure 3A The structure is related to; Figure 11 , Figure 12 and Figure 13 Column (B) and Figure 3B or Figure 3C The structure is related to; Figure 11 , Figure 12 and Figure 13 Column (C) and Figure 3D The structure is related to; Figure 11 , Figure 12 and Figure 13 Column (D) and Figure 3E or Figure 3F The structure is related to; and Figure 14 and Figure 15 and Figure 4A , Figure 4B , Figure 4C or Figure 4D The structure is related to this. Lines (1) through (11) are related to the various operations in method 613 and other operations in method 600. (See reference...) Figure 10A , Figure 10B and Figures 11 to 15 Description methods 600 and 613.

[0110] In some embodiments, method 600 fabricates a semiconductor structure having a multi-channel device including p-type GAA transistors and n-type GAA transistors. In block 602, a first semiconductor layer stack and a second semiconductor layer stack are formed over a substrate. Each of the first and second semiconductor layer stacks includes a first semiconductor layer and a second semiconductor layer arranged in an alternating configuration of vertically stacked components. In block 604, a gate structure is formed over a first region of the first semiconductor layer stack and a first region of the second semiconductor layer stack. The gate structure includes a dummy gate stack and a gate spacer. In block 606, portions of the first and second semiconductor layer stacks located in a second region are removed to form source / drain trenches. In block 608, internal spacers are formed along the sidewalls of the first semiconductor layers in the first and second semiconductor layer stacks. In block 610, epitaxial source / drain components are formed in the source / drain trenches. In block 612, an interlayer dielectric (ILD) layer is formed over the epitaxial source / drain components. In block 613, a dielectric gate stack, such as dielectric gate stack 242 in PD channel 106, is formed. Block 613 includes steps including patterning, deposition, and CMP. The process in block 613 will be described in further detail below. In block 614, the dummy gate stack is removed, thereby forming a gate trench that exposes a first semiconductor layer stack in the p-type gate region and a second semiconductor layer stack in the n-type gate region, such as... Figure 12 and Figure 14 As shown in row (6). In block 616, the first semiconductor layer is removed from the first semiconductor layer stack and the second semiconductor layer stack exposed by the gate trench, thereby forming a gap between the second semiconductor layers, as shown. Figure 12 and Figure 15 As shown in row (7). In block 618, various gate materials are deposited into the gate trench to form a gate stack, such as Figure 12 and Figure 15 row(8), Figure 13 and Figure 15 As shown in row (9). The operations in block 618 include deposition and CMP. In block 619, a dielectric gate stack is formed, as shown in the diagram. Figure 13 and Figure 15 As shown in rows (10) and (11). In block 620, an interconnect structure and a passivation layer are formed. In block 622, the semiconductor structure (workpiece) is cut through a dicing track (PD track) using a suitable dicing method (such as plasma cutting). Embodiments of this disclosure contemplate additional processing. Additional steps may be provided before, during, and after method 600, and for additional embodiments of method 600, some of the described steps may be moved, replaced, or eliminated. The following discussion illustrates various embodiments of nanowire-based integrated circuit devices that may be fabricated according to method 600.

[0111] refer to Figure 10B A method 613 for forming a dielectric gate stack in a semiconductor structure 100 is further described as a flowchart constructed according to some embodiments.

[0112] In some embodiments, method 613 includes block 632 to perform a CMP process on the semiconductor structure 100, particularly the ILD layer, to planarize the top surface of the semiconductor structure 100, such as... Figure 11 and Figure 14 As shown in row (1). In box 634, an etch-back process is performed on semiconductor structure 100, as... Figure 11 and Figure 14 As shown in row (2). In box 636, a patterned photoresist layer with openings is formed by photolithography, as shown in... Figure 11 and Figure 14 As shown in line (3). The opening defines a region, such as a cut region in which a gate dicing component will be formed. In some embodiments, a hard mask can be used as an etching mask. In this case, the opening of the patterned photoresist layer is first transferred to the hard mask by an etching process. In 638, an etching process is performed on the semiconductor structure 100 through the opening of the patterned photoresist layer to create trenches, such as in the cut region, as shown in line (3). Figure 11 and Figure 14 As shown in row (4). The trench extends below the bottom surface of the isolation structure 124. In 640, one or more dielectric materials are filled in the trench to form a dielectric gate stack 242, including the dielectric gate stack 242 in the cut region 106, as shown. Figure 12 and Figure 14As shown in line (5). In some embodiments, the dielectric material is silicon nitride. In 642, another CMP process is performed to remove excess dielectric material and planarize the top surface of the semiconductor structure 100, as shown in line (5). Figure 12 and Figure 14 As shown in line (5).

[0113] This disclosure provides embodiments of a dicing channel having active regions and gate stacks configured to reduce metal residue and enhance dicing performance. The active regions and gate stacks in the dicing channel are designed and configured differently in terms of size, orientation, composition, and other parameters from those in the circuit regions and sealing ring regions.

[0114] While not intended to be limiting, embodiments of this disclosure provide one or more of the following advantages. For example, embodiments of this disclosure provide a sealing ring region surrounding a circuit region. The sealing ring region includes a sealing region and a transition region between the sealing region and the circuit region. The transition region includes straight conductors parallel to the edges of the sealing ring region and disposed around the circuit region. The transition region smooths the transition from the circuit region with a higher pattern density to the sealing ring region with a lower pattern density. This reduces over-etching or denting problems during subsequent processes. In some embodiments, all transition lines in the transition region are parallel to the conductors in the circuit region. In some embodiments, each transition line has a width greater than the width of the conductors in the circuit region and less than the width of the conductors in the sealing ring. In some embodiments, a first transition line in the transition region of a first metal layer is substantially perpendicular to a second transition line in the transition region of a second metal layer.

[0115] In one exemplary aspect, embodiments of this disclosure relate to a semiconductor structure, the semiconductor structure comprising: a substrate having a circuit region and a sealing ring region surrounding the circuit region and a cleaving channel surrounding the sealing ring region, wherein the cleaving channel includes a first cleaving region and second cleaving regions disposed on both sides of the first cleaving region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region, the first gate stack including a metal electrode; a second active region formed in the first cleaving region; a dielectric structure formed on the second active region in the first cleaving region; and a second gate stack formed on an isolation member in the second cleaving region.

[0116] In another exemplary aspect, embodiments of this disclosure relate to a semiconductor structure, the semiconductor structure comprising: a substrate having a circuit region and a sealing ring region surrounding the circuit region and a cleaving channel surrounding the sealing ring region, wherein the cleaving channel includes a first cleaving region and second cleaving regions disposed on both sides of the first cleaving region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region; a second active region formed in the first cleaving region; a first dielectric gate stack formed on the second active region in the first cleaving region; and a second dielectric gate stack formed on an isolation member in the second cleaving region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack.

[0117] In another exemplary aspect, embodiments of this disclosure relate to a method of manufacturing a semiconductor structure. The method includes: providing a substrate having a circuit region and a sealing ring region surrounding the circuit region, and a dicing track surrounding the sealing ring region, wherein the dicing track includes a first dicing region and second dicing regions disposed on opposite sides of the first dicing region; forming a first active region in the circuit region and forming a second active region in the first dicing region; forming a first gate stack on the first active region in the circuit region, forming a first dielectric gate stack on the second active region in the first dicing region, and forming a second dielectric gate stack on an isolation member in the second dicing region, wherein the first and second dielectric gate stacks are dielectric members, and the first gate stack is a metal gate stack; and dicing the substrate along the dicing track.

[0118] Some embodiments of this application provide a semiconductor structure including: a substrate having a circuit region and a sealing ring region surrounding the circuit region and a dicing channel surrounding the sealing ring region, wherein the dicing channel includes a first dicing region and second dicing regions disposed on both sides of the first dicing region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region, the first gate stack including a metal electrode; a second active region formed in the first dicing region; a dielectric structure formed on the second active region in the first dicing region; and a second gate stack formed on an isolation member in the second dicing region.

[0119] In some embodiments, the second cut region has no active region. In some embodiments, the first active region and the second active region are longitudinally oriented along a first direction; the first gate stack and the dielectric structure are longitudinally oriented along a second direction orthogonal to the first direction; the second cut region further includes a third gate stack oriented longitudinally along the first direction; and the second gate stack is longitudinally oriented along the second direction. In some embodiments, the third gate stack is connected to the second gate stack. In some embodiments, the second gate stack includes a first gate stack, a second gate stack, and a third gate stack; the third gate stack includes a first subset of the third gate stack distributed between the first gate stack and the second gate stack, and a second subset of the third gate stack distributed between the second gate stack and the third gate stack; and the first subset of the third gate stack spans between the first gate stack and the second gate stack. In some embodiments, the first subset of the third gate stack is aligned with the second subset of the third gate stack along the first direction. In some embodiments, the first subset of the third gate stack and the second subset of the third gate stack are configured in an interleaved pattern along the second direction. In some embodiments, the dicing track further includes a third dicing region and a fourth dicing region cascaded with the first dicing region and the second dicing region; the third dicing region includes a third gate stack oriented longitudinally along the second direction; and the fourth dicing region includes a fourth gate stack oriented longitudinally along the second direction and a fifth gate stack oriented longitudinally along the first direction. In some embodiments, the fourth gate stack is connected to the fifth gate stack. In some embodiments, the first active region includes a first width W1; the second active region includes a second width W2; and the second width is greater than the first width. In some embodiments, the sealing ring region includes a third active region oriented longitudinally along the first direction and a third gate stack oriented longitudinally parallel to the third active region. In some embodiments, the third gate stack is joined to the third active region with a margin, such that the first and second longitudinal edges of each of the third gate stacks are located within the corresponding first and second longitudinal edges of the third active region. In some embodiments, the third gate stack includes polysilicon. In some embodiments, the semiconductor structure further includes an isolation structure surrounding each of the first active region and the second active region, wherein the first active region and the second active region protrude above the top surface of the isolation structure; and the dielectric structure extends vertically below the bottom surface of the isolation structure.

[0120] Other embodiments of this application provide a semiconductor structure including: a substrate having a circuit region and a sealing ring region surrounding the circuit region and a dicing channel surrounding the sealing ring region, wherein the dicing channel includes a first dicing region and second dicing regions disposed on both sides of the first dicing region; a first active region formed in the circuit region; a first gate stack formed on the first active region in the circuit region; a second active region formed in the first dicing region; a first dielectric gate stack formed on the second active region in the first dicing region; and a second dielectric gate stack formed on an isolation member in the second dicing region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack.

[0121] In some embodiments, the second cut region has no active region; the first active region and the second active region are longitudinally oriented along a first direction; the first gate stack and the first dielectric gate stack are longitudinally oriented along a second direction orthogonal to the first direction; the second dielectric gate stack is longitudinally oriented along the second direction; and the second cut region further includes a third dielectric gate stack oriented longitudinally along the first direction. In some embodiments, the second dielectric gate stack includes a first dielectric gate stack, a second dielectric gate stack, and a third dielectric gate stack; the third dielectric gate stack includes a first subset of the third dielectric gate stack spanning between the first dielectric gate stack and the second dielectric gate stack, and a second subset of the third dielectric gate stack spanning between the second dielectric gate stack and the third dielectric gate stack; and the first subset of the third dielectric gate stack spans between the first dielectric gate stack and the second dielectric gate stack. In some embodiments, the first subset of the third dielectric gate stack is aligned with the second subset of the third dielectric gate stack along the first direction. In some embodiments, the first active region includes a first width W1; the second active region includes a second width W2; and the second width is greater than the first width.

[0122] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate having a circuit region and a sealing ring region surrounding the circuit region and a dicing channel surrounding the sealing ring region, wherein the dicing channel includes a first dicing region and second dicing regions disposed on both sides of the first dicing region; forming a first active region in the circuit region and forming a second active region in the first dicing region; forming a first gate stack on the first active region in the circuit region, forming a first dielectric gate stack on the second active region in the first dicing region, and forming a second dielectric gate stack on an isolation member in the second dicing region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack; and dicing the substrate along the dicing channel.

[0123] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: A substrate having a circuit region and a sealing ring region surrounding the circuit region and a cut channel surrounding the sealing ring region, wherein the cut channel includes a first cut region and second cut regions disposed on both sides of the first cut region; A first active region is formed in the circuit region; A first gate stack is formed on the first active region in the circuit region, the first gate stack including a metal electrode; A second active region is formed in the first cut region; A dielectric structure is formed on the second active region within the first diced region; and A second gate stack is formed on an isolation member in the second diced region.

2. The semiconductor structure according to claim 1, wherein, The second cutting region has no active region.

3. The semiconductor structure according to claim 1, wherein, The first active region and the second active region are longitudinally oriented along the first direction; The first gate stack and the dielectric structure are longitudinally oriented along a second direction orthogonal to the first direction; The second dicing region further includes a third gate stack oriented longitudinally along the first direction; and The second gate stack is oriented longitudinally along the second direction.

4. The semiconductor structure according to claim 3, wherein, The third gate stack is connected to the second gate stack.

5. The semiconductor structure according to claim 3, wherein, The second gate stack includes a first gate stack, a second gate stack, and a third gate stack; The third gate stack includes a first subset of the third gate stack distributed between the first gate stack and the second gate stack, and a second subset of the third gate stack distributed between the second gate stack and the third gate stack; and The first subset of the third gate stack spans between the first gate stack and the second gate stack.

6. The semiconductor structure according to claim 5, wherein, The first subset of the third gate stack is aligned with the second subset of the third gate stack along the first direction.

7. The semiconductor structure according to claim 5, wherein, The first subset of the third gate stack and the second subset of the third gate stack are configured in an interleaved pattern along the second direction.

8. The semiconductor structure according to claim 1, wherein, The cutting channel also includes a third cutting area and a fourth cutting area cascaded with the first cutting area and the second cutting area; The third dicing region includes a third gate stack oriented longitudinally along the second direction; and The fourth dicing region includes a fourth gate stack oriented longitudinally along the second direction and a fifth gate stack oriented longitudinally along the first direction.

9. A semiconductor structure, comprising: A substrate having a circuit region and a sealing ring region surrounding the circuit region and a cut channel surrounding the sealing ring region, wherein the cut channel includes a first cut region and second cut regions disposed on both sides of the first cut region; A first active region is formed in the circuit region; A first gate stack is formed on the first active region in the circuit region; A second active region is formed in the first cut region; A first dielectric gate stack is formed on the second active region of the first diced region; and A second dielectric gate stack is formed on an isolation member in the second diced region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack.

10. A method for forming a semiconductor structure, comprising: A substrate is provided having a circuit region and a sealing ring region surrounding the circuit region and a cleavage channel surrounding the sealing ring region, wherein the cleavage channel includes a first cleavage region and second cleavage regions disposed on both sides of the first cleavage region; A first active region is formed in the circuit region, and a second active region is formed in the first cut region; A first gate stack is formed on the first active region in the circuit region, a first dielectric gate stack is formed on the second active region in the first diced region, and a second dielectric gate stack is formed on an isolation member in the second diced region, wherein the first dielectric gate stack and the second dielectric gate stack are dielectric members, and the first gate stack is a metal gate stack; and The substrate is cut along the cutting path.

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