Hybrid bonding structure, method of manufacturing the same, hybrid bonding process and bonding apparatus

Abstract

The application belongs to the technical field of semiconductor manufacturing, and provides a hybrid bonding structure, a manufacturing method thereof, a hybrid bonding process and a bonding device. The first wafer to be bonded in the hybrid bonding structure comprises a dielectric layer with a filling groove, wherein a first metal block is arranged; and further comprises a first dielectric layer with an opening groove capable of exposing the first metal block, and the first dielectric layer forms a first inclined side surface in the opening groove. The second wafer to be bonded in the hybrid bonding structure comprises a second metal block protrudingly arranged on a second dielectric layer; the second metal block has a second inclined side surface matched with the first inclined side surface; during bonding, the opening groove accommodates the second metal block, and the cooperation of the first inclined side surface and the second inclined side surface avoids bonding errors caused by mechanical movement, vibration and other factors, thereby keeping a lower offset and effectively improving the precision problem of bonding alignment. The hybrid bonding process and the bonding device provided by the application are used for performing bonding of the hybrid bonding structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor processing and manufacturing technology, and relates to a hybrid bonding structure, its manufacturing method, hybrid bonding process and bonding equipment. Background Technology

[0002] Hybrid bonding typically refers to simultaneously achieving dielectric bonding between dielectric layers and direct metal connections between metal pads during wafer-to-wafer or die-to-wafer integration, thereby constructing a vertical interconnect structure. This technology is widely used in image sensors, memory stacking, heterogeneous integration of logic chips, and MEMS device packaging, significantly improving signal transmission rates, reducing parasitic capacitance and power consumption, and enabling more compact device layouts.

[0003] Currently, conventional processes often require wafer-to-wafer pattern alignment within the bonding equipment before bonding. This can be achieved through methods such as infrared or laser-based marking alignment, and some advanced equipment incorporates electron beam-assisted or diffraction optical calibration techniques to improve alignment resolution. After alignment, bonding is performed, followed by high-temperature processing and hybrid bonding.

[0004] However, after actual bonding, testing revealed that the actual alignment deviation of the metal interconnect structure often increased significantly, generally exceeding 200 nm, and in extreme cases even exceeding 500 nm, severely deviating from the design expectations. This significant degradation in post-bonding accuracy has become a major obstacle restricting the widespread application of hybrid bonding technology in submicron and smaller interconnect pitches. Summary of the Invention

[0005] In view of the problems existing in the prior art, the purpose of the present invention is to provide a hybrid bonding structure, its manufacturing method, hybrid bonding process and bonding equipment, so as to mainly solve the problem of decreased accuracy after bonding caused by alignment errors due to the superposition of factors such as mechanical motion and vibration in the existing hybrid bonding process.

[0006] To achieve this objective, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a hybrid bonding structure, the hybrid bonding structure comprising a first wafer to be bonded and a second wafer to be bonded;

[0008] The first wafer to be bonded includes a first raw wafer, and a dielectric layer and a first dielectric layer stacked on the side to be bonded thereon; the dielectric layer has a filling groove, and a first metal block in contact with the first raw wafer is disposed in the filling groove; the first dielectric layer has an opening groove corresponding to the position of the filling groove, exposing the first metal block; a first inclined side surface is formed in the first dielectric layer in the opening groove.

[0009] The second wafer to be bonded includes a second original wafer and a second dielectric layer disposed on one side of the surface to be bonded; a protruding second metal block is disposed on the surface of the second dielectric layer away from the second original wafer;

[0010] The opening slot and the second metal block are configured such that the second metal block has a second inclined side that matches the first inclined side, and the opening slot accommodates the second metal block when the first dielectric layer and the second dielectric layer are in contact during bonding.

[0011] This invention effectively improves bonding alignment accuracy by creating a specific structure on the surface of the wafers to be bonded, specifically by constructing matching first and second inclined side surfaces within the opening slot and the second metal block. During bonding, the designed inclined side surfaces can be fully utilized, correcting the alignment and bonding positions of the two wafers to be bonded, avoiding errors caused by mechanical movement, vibration, and other factors, thus maintaining a lower offset.

[0012] The following are preferred technical solutions of the present invention, but are not intended to limit the technical solutions provided by the present invention. The technical objectives and beneficial effects of the present invention can be better achieved and realized through the following technical solutions.

[0013] As a preferred embodiment of the present invention, the first inclined side surface and the second inclined side surface satisfy at least one of the following conditions:

[0014] (a1) The angle between the first inclined side and the thickness direction of the first dielectric layer is the first inclined angle θ1, 0° < θ1 < 90°; preferably (a2) 25° < θ1 < 65°, and more preferably (a3) ​​40° < θ1 < 50°.

[0015] (a4) The angle between the second inclined side and the thickness direction of the second metal block is the second inclined angle θ2, θ2=θ1.

[0016] As a preferred embodiment of the present invention, the first metal block and the second metal block satisfy at least one of the following conditions:

[0017] (b1) The thickness of the first metal block is equal to the thickness of the dielectric layer.

[0018] (b2) When the first dielectric layer and the second dielectric layer are bonded and in contact, the opening groove accommodates the second metal block, and an expansion gap is maintained between the second metal block and the first metal block.

[0019] By setting and retaining an appropriate expansion gap, this invention can serve as a reserve for the thermal expansion and extension of copper during the heat treatment of the bonding wafer. This not only helps to ensure the quality of the metal interconnect after bonding, but also effectively controls the stress of the bonding material.

[0020] (b3) The thickness of the second metal block is less than or equal to the thickness of the first dielectric layer.

[0021] (b4) The thickness of the first metal block is H1, the thickness of the second metal block is H2, and the size of the expansion gap is L. Then L = ((H1 + H2) × α × (T - T0))β, where α is the linear thermal expansion coefficient of the metal, in units of 10. -6 / ℃; T is the maximum processing temperature during bonding; T0 is the initial ambient temperature before bonding; β is an empirical coefficient, β is taken from 0.7 to 1.3.

[0022] (b5) The metal composition of the first metal block includes copper and / or gold.

[0023] (b6) The metal composition of the second metal block includes copper and / or gold.

[0024] As a preferred embodiment of the present invention, the hybrid bonding structure further satisfies at least one of the following conditions:

[0025] (c1) Both the first original wafer and the second original wafer comprise at least one of silicon, glass, SiC, SiN or LiTaO3.

[0026] (c2) A first isolation layer is provided in the filling groove, and the first isolation layer is disposed between the first original wafer and the first metal block.

[0027] (c3) The second wafer to be bonded further includes a second isolation layer, which is disposed between the second dielectric layer and the second metal block.

[0028] (c4) The first isolation layer includes at least one of Ti, Ta or TaN.

[0029] (c5) Both the first dielectric layer and the second dielectric layer comprise silicon nitride and / or silicon carbonitride.

[0030] (c6) The dielectric layer comprises silicon oxide.

[0031] In a second aspect, the present invention provides a method for manufacturing the hybrid bonding structure described in the first aspect, the method comprising:

[0032] Fabricating a first wafer to be bonded: providing a first raw wafer, forming a dielectric layer on the side of the first raw wafer to be bonded; forming a filling trench in the dielectric layer, and then forming a first metal block in the filling trench; forming a first dielectric layer to cover the dielectric layer and the first metal layer, and then forming an opening trench in the first dielectric layer corresponding to the position of the filling trench, to obtain the first wafer to be bonded;

[0033] Manufacturing a second wafer to be bonded: A first raw wafer is provided, a second dielectric layer is formed on the side of the second raw wafer to be bonded, and then a second metal block is formed on the second dielectric layer to obtain a second wafer to be bonded.

[0034] As a preferred embodiment of the present invention, the first wafer to be bonded satisfies at least one of the following conditions:

[0035] (d1) Methods for forming a dielectric layer include thermal oxidation and / or chemical vapor deposition.

[0036] (d2) Methods for forming filling grooves include etching.

[0037] (d3) A method for forming a first metal block in a filling trench includes: depositing a first metal layer on one side of a dielectric layer having the filling trench, removing excess first metal layer to retain the formation of a first metal block within the filling trench.

[0038] (d4) The method of forming a first metal block in a filling tank further includes: before depositing a first metal layer, depositing a first isolation layer on the side of the dielectric layer having the filling tank, depositing a first metal layer on the first isolation layer, removing excess first isolation layer and first metal layer, so as to retain a portion of the first isolation layer and the first metal block in the filling tank.

[0039] (d5) Methods for depositing the first isolation layer include physical vapor deposition.

[0040] (d6) The method for forming the first dielectric layer includes chemical vapor deposition.

[0041] (d7) Methods for forming openings include etching.

[0042] (d8) The metal composition of the first metal layer includes copper and / or gold.

[0043] As a preferred embodiment of the present invention, the method for forming the second metal block includes any one of the following methods:

[0044] Method 1: A second metal layer and a dielectric auxiliary layer are sequentially deposited on the second dielectric layer. A chamfered groove is etched on the dielectric auxiliary layer, and the outline shape of the chamfered groove is the same as that of the second metal block. Then, a third metal layer is deposited on the side of the dielectric auxiliary layer with the chamfered groove to fill the chamfered groove with copper. Then, the excess third metal layer outside the chamfered groove is removed, followed by the removal of the dielectric auxiliary layer, and then the excess second metal layer is removed, so that the part of the third metal layer remaining in the chamfered groove and the part of the second metal layer remaining below it constitute the second metal block.

[0045] Method 2 involves depositing a fourth metal layer on the second dielectric layer, and then etching the fourth metal layer to form the second metal block.

[0046] As a preferred embodiment of the present invention, the second wafer to be bonded satisfies at least one of the following conditions:

[0047] (e1) Methods for forming the second dielectric layer include chemical vapor deposition.

[0048] (e2) In Method 1, the methods for depositing the second, third and fourth metal layers all include physical vapor deposition.

[0049] (e3) In Method 1, the method for depositing the dielectric auxiliary layer includes chemical vapor deposition.

[0050] (e4) In Method 1, the method of etching to form the chamfer groove includes etching.

[0051] (e5) In Method 1, the method of depositing to form the second metal layer includes electroplating.

[0052] (e6) In Method 1, the method for removing the excess third metal layer other than the chamfer groove includes chemical mechanical polishing.

[0053] (e7) In Method 1, the method for removing the dielectric auxiliary layer includes dry etching.

[0054] (e8) In Method 1, the method for removing the second metal layer includes etching.

[0055] (e9) Method 1 further includes depositing a second isolation layer on the second dielectric layer before depositing the second metal layer, and then depositing the second metal layer on the second isolation layer; when removing the excess second metal layer, the excess second isolation layer is also removed so as to retain a portion of the second isolation layer below the second metal block.

[0056] (e10) Method 2 further includes depositing a second isolation layer on the second dielectric layer before depositing the fourth metal layer, and then depositing the fourth metal layer on the second isolation layer; when etching the fourth metal layer, the excess second isolation layer is simultaneously etched away to retain a portion of the second isolation layer below the second metal block.

[0057] (e11) The metal composition of the second metal layer, the third metal layer and the fourth metal layer all includes copper and / or gold.

[0058] (e12) The material of the dielectric auxiliary layer includes silicon oxide.

[0059] Thirdly, the present invention provides a wafer-level hybrid bonding process, the hybrid bonding process comprising:

[0060] The hybrid bonding structure described in the first aspect is provided, wherein one of the first wafer to be bonded or the second wafer to be bonded is used as the upper wafer, and the other wafer to be bonded is used as the lower wafer:

[0061] The upper and lower wafers are pre-aligned so that the second metal block in the upper wafer is aligned with the slot in the lower wafer.

[0062] A point pressing process is performed to bring the first dielectric layer and the second dielectric layer into contact. During this process, the second inclined side of the second metal block cooperates with the first inclined side of the opening slot, so that the second metal block is embedded in the opening slot, thereby achieving precise alignment between the upper wafer and the lower wafer.

[0063] A surface pressing process is performed. After the surface pressing process is completed, the first dielectric layer and the second dielectric layer are connected, and the first metal block and the second metal block are connected.

[0064] As a preferred embodiment of the present invention, the wafer-level hybrid bonding process satisfies at least one of the following conditions:

[0065] (f1) The pressure of the point pressure treatment is 1N~10N.

[0066] (f2) The duration of the point pressure treatment is 5s~15s.

[0067] (f3) The pressure of the surface pressure treatment is 100N~300N.

[0068] (f4) The duration of the surface pressing treatment is 1 min to 10 min.

[0069] (f5) Annealing is performed after the surface pressing process is completed.

[0070] (f6) The annealing temperature is 250℃~1000℃.

[0071] (f7) The annealing process includes a first annealing at 250℃~500℃ for 1h~3h, followed by a second annealing at 500℃~1000℃ for 1h~3h.

[0072] (f8) The upper wafer is gripped by vacuum adsorption using a chuck, with a vacuum value of -500mbar to -300mbar. After the point pressure treatment is completed and before the surface pressure treatment begins, the upper wafer vacuum adsorbed by the chuck is vacuum released in sections.

[0073] Fourthly, the present invention provides a bonding apparatus for performing the bonding process described in the third aspect, the bonding apparatus comprising an upper stage and a lower stage arranged opposite to each other for fixing the upper wafer and the lower wafer, respectively;

[0074] A movable slide is used to carry the loading stage and / or the downloading stage, and to adjust the relative position between the upper wafer and the lower wafer.

[0075] A force output unit, connected to the upper stage or the lower stage, is used to perform point pressure and / or surface pressure between the upper wafer and the lower wafer.

[0076] Compared with existing technical solutions, the present invention has at least the following beneficial effects:

[0077] This invention effectively improves bonding alignment accuracy by creating a specific structure on the surface of the wafers to be bonded, specifically by constructing matching first and second inclined side surfaces within the opening slot and the second metal block. During bonding, the designed inclined side surfaces can be fully utilized, correcting the alignment and bonding positions of the two wafers to be bonded, avoiding errors caused by mechanical movement, vibration, and other factors, thus maintaining a lower offset.

[0078] In this invention, spot pressing is performed first during the bonding process. The spot pressing pressure is small, which allows the first metal block and the second metal block to cooperate and adjust their positions under low pressure. This avoids the direct surface pressing pressure, which would cause the first and second metal blocks to be compacted before their positions are adjusted, and voids are easily generated at the contact point.

[0079] By setting and retaining an appropriate expansion gap, this invention can serve as a reserve for the thermal expansion and extension of copper during the heat treatment of the bonding wafer. This not only helps to ensure the quality of the metal interconnect after bonding, but also effectively controls the stress of the bonding material. Attached Figure Description

[0080] Figure 1 This is a schematic diagram of the structure of the first wafer to be bonded in the hybrid bonding structure provided in one or more embodiments of the present invention.

[0081] Figure 2 yes Figure 1 Enlarged view of the area circled by the red dotted line.

[0082] Figure 3 This is a schematic diagram of the structure of the first wafer to be bonded in the hybrid bonding structure provided in one or more embodiments of the present invention.

[0083] Figure 4 yes Figure 3 Enlarged view of the area circled by the red dotted line.

[0084] Figures 5 to 9 These are schematic diagrams of the corresponding steps in the manufacturing method of the hybrid bonding structure provided by one or more embodiments of the present invention, specifically the structural diagrams corresponding to the steps in manufacturing the first wafer to be bonded.

[0085] Figures 10 to 17 These are schematic diagrams of the corresponding steps in the manufacturing method of the hybrid bonding structure provided by one or more embodiments of the present invention, specifically the manufacturing steps of the second wafer to be bonded.

[0086] Figures 18 to 20 These are schematic diagrams of the corresponding steps in the wafer-level hybrid bonding process provided by one or more embodiments of the present invention.

[0087] Figure 21 This is a schematic diagram of the nested mark formed after the hybrid bonding structure completes the hybrid bonding process in one or more embodiments of the present invention.

[0088] In the above figure: 10 - first wafer to be bonded, 11 - first raw wafer, 12 - dielectric layer, 13 - filling trench, 14 - first metal block, 15 - first dielectric layer, 16 - opening trench, 17 - first inclined side, 20 - second wafer to be bonded, 21 - second raw wafer, 22 - second dielectric layer, 23 - second metal layer, 24 - dielectric auxiliary layer, 25 - chamfer trench, 26 - part of the third metal layer retained in the chamfer trench, 27 - second metal block, 28 - second inclined side, 29 - fourth metal layer. Detailed Implementation

[0089] The embodiments of the present invention are described in detail below. The term "embodiment" as used herein means that a specific feature, structure, or characteristic described in connection with an embodiment can be included in one or more embodiments or implementations of the present invention. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. The term "implementation" as used herein has a similar understanding. Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions, and all technical features and optional technical features of the present invention can be combined with each other to form new technical solutions.

[0090] In the description of this invention, open-ended technical features or solutions described with terms such as "containing," "comprising," "including," and "having" include the content specified in this invention. Unless otherwise stated, other content besides the specified content is not excluded, and it can be regarded as providing both closed-ended features or solutions consisting of the specified content and open-ended features or solutions that include additional content beyond the specified content.

[0091] In the description of this invention, "X and / or Y" may optionally include the case of X alone, the case of Y alone, or the case of X and Y, wherein X and Y are merely examples and may be any technical feature connected by "and / or" in this invention.

[0092] The "scope" disclosed in this invention is defined in the form of a lower limit and an upper limit. A given scope is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific scope. The scope defined in this way can include or exclude end values, and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a scope.

[0093] In the description of this invention, unless otherwise specified, "multiple" or "a variety" refers to a quantity greater than or equal to 2. For example, "one or more" means one or more types.

[0094] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. "First feature" and "second feature" may optionally include one or more of the indicated feature.

[0095] In the description of this invention, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The detailed execution order of each step should be determined by its function and possible internal logic.

[0096] In the description of this invention, the technical terms "length", "width", "thickness", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", "upper", "lower", etc., indicating the orientation or positional relationship, can be understood as based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this invention and simplifying the description, and are not intended to indicate or imply that the structure referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this invention.

[0097] Embodiments of the present invention are described in detail below. Examples of one or more embodiments are shown in the accompanying drawings, but unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of practically identical structures may be omitted. Furthermore, the drawings and the following description are provided to enable those skilled in the art to fully understand the invention and are not intended to limit the subject matter of the claims. Rather, these embodiments are provided to make the disclosure of the invention more thorough and complete.

[0098] In hybrid bonding processes, while initial alignment accuracy can be high, uneven advancement of the contact front between wafers often occurs during the application of mechanical pressure, especially in the edge regions of large wafers. Uneven pressure distribution, differences in surface curvature, or localized particle contamination can easily trigger relative slippage or rotation between wafers, causing misalignment of the aligned pattern. Existing technologies lack mechanisms to control the dynamic bonding process and cannot correct misalignment in real time during pressure application, resulting in the inability to effectively maintain the initial alignment. Furthermore, the quality of the bonded metal interconnects is significantly affected by the process. During high-temperature annealing, residual stress arises in metals such as copper due to the mismatch between their thermal expansion coefficients and the surrounding medium, potentially leading to wire breakage, void formation, or interface delamination, affecting the reliability of the electrical connection.

[0099] Therefore, how to effectively suppress dynamic offset during the bonding process, improve the actual alignment accuracy after bonding, and improve the integrity of metal interconnects and stress distribution at the bonding interface while achieving high-density electrical interconnects has become a core problem that urgently needs to be solved in the development of current wafer-level hybrid bonding technology.

[0100] Therefore, in one or more embodiments of the present invention, a hybrid bonding structure is provided, the hybrid bonding structure comprising a first wafer to be bonded and a second wafer to be bonded;

[0101] like Figure 1 As shown, the first wafer to be bonded 10 includes a first raw wafer 11, and a dielectric layer 12 and a first dielectric layer 15 stacked on the side to be bonded thereon; the dielectric layer 12 has a filling groove 13, and a first metal block 14 in contact with the first raw wafer 11 is disposed in the filling groove 13; the first dielectric layer 15 has an opening groove 16 corresponding to the position of the filling groove 13, exposing the first metal block 14; in the opening groove 16, a first inclined side surface 17 is formed in the first dielectric layer 15.

[0102] like Figure 3As shown, the second wafer to be bonded 20 includes a second original wafer 21 and a second dielectric layer 22 disposed on one side of the surface to be bonded; a protruding second metal block 27 is disposed on the surface of the second dielectric layer 22 away from the second original wafer 21.

[0103] The opening slot 16 and the second metal block 27 are configured such that the second metal block 27 has a second inclined side 28 that matches the first inclined side 17, and when the first dielectric layer 15 and the second dielectric layer 22 are in contact during bonding, the opening slot 16 accommodates the second metal block 27, such as... Figure 19 As shown.

[0104] This invention effectively improves bonding alignment accuracy by creating a specific structure on the surface of the wafers to be bonded, namely, by constructing a first inclined side surface 17 and a second inclined side surface 28 that match each other in the opening slot 16 and the second metal block 27. Specifically, after spot pressing during the bonding process, there will be a certain offset between the upper and lower wafers. The inclined side surface provides friction to the upper wafer, allowing it to support the center of gravity of the upper wafer. During subsequent surface pressing, the pressure of the surface pressing is much greater than the friction between the inclined side surface and the upper wafer, causing the center of gravity of the upper wafer to move towards the center of the supporting surface, thus achieving stability. In other words, when bonding is performed in an integrated spot pressing and surface pressing device, the designed inclined side surface is fully utilized to correct the alignment and bonding positions of the two wafers to be bonded, avoiding errors caused by mechanical movement, vibration, and other factors, thereby maintaining a lower offset.

[0105] In some embodiments, the opening groove 16 has a first platform shape; the top surface of the first platform faces the first metal block 14, and the bottom surface of the first platform forms an opening on the surface of the first dielectric layer 15 away from the dielectric layer 12, thereby exposing the first metal block 14; in the opening groove 16, the side surface of the first platform forms the first inclined side surface 17 in the first dielectric layer 15. Alternatively, it can be understood that, on a cross-section parallel to the thickness of the first wafer to be bonded 10, the outline shape of the cross-section of the opening groove 16 is an inverted first trapezoid, the long base of the first trapezoid forms the opening, and the two waists of the first trapezoid form the first inclined side surface 17. In this case, the bonding surface of the first wafer to be bonded 10 includes the surface of the first dielectric layer 15 exposed outside the opening groove 16, the first inclined side surface 17 in the opening groove 16, and the surface of the first metal block 14 exposed at the bottom of the opening groove 16.

[0106] In some embodiments, the outline shape of the second metal block 27 is a second platform; the bottom surface of the second platform is in contact with the second dielectric layer 22, and the top surface of the second platform is disposed away from the surface of the second dielectric layer 22; the side surface of the second platform forms a second inclined side surface 28 on the side surface of the second metal block 27. Alternatively, it can be understood that, on a cross-section parallel to the wafer thickness, the outline shape of the cross-section of the second metal block 27 is an upright second trapezoid, the long base of the second trapezoid is in contact with the second dielectric layer 22, and the two waists of the second trapezoid form the second inclined side surface 28. In this case, the bonding surface of the second wafer to be bonded 20 includes the surface of the second metal block 27 away from the second dielectric layer 22, the second inclined side surface 28 on the second metal block 27, and the surface of the second dielectric layer 22 exposed outside the second metal block 27.

[0107] In some implementations, such as Figure 2 As shown, the angle between the first inclined side 17 and the thickness direction of the first dielectric layer 15 is a first inclined angle θ1, where 0° < θ1 < 90°. For example, θ1 can be 5°, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, or 85°, further preferably 25° < θ1 < 65°, and even further preferably 40° < θ1 < 50°.

[0108] In some implementations, such as Figure 4 As shown, the angle between the second inclined side surface 28 and the thickness direction of the second metal block 27 is the second inclined angle θ2, where θ2 = θ1. This allows the second inclined side surface 28 to better cooperate with the first inclined side surface 17, so that the second metal block 27 is completely embedded in the opening groove 16.

[0109] The tilt angle of the first tilted side 17 is related to the friction force of the inclined surface and the gravity of the upper wafer (e.g., the second wafer to be bonded 20) when the first tilted side 17 and the second tilted side 28 are in contact and rub together. Adjustment is made according to the actual situation. When 40° < θ1 = θ2 < 50°, it is beneficial to obtain better constraint and correction effect.

[0110] As a further example, when the second wafer to be bonded 20 is used as the upper wafer (i.e., the upper wafer), the frictional force experienced by the second metal block 27 when it is in contact with the first inclined side 17 and the second inclined side 28 is denoted as F1, the elastic force experienced is denoted as F2, and the gravity of the second wafer to be bonded 20 itself is denoted as G; if there are n second metal blocks 27 on the second wafer to be bonded 20 (i.e., there are n corresponding first metal blocks 14 on the first wafer to be bonded 10), then θ2 (or θ1) satisfies: n×F2×sinθ2+n×F1×cosθ2=G.

[0111] In some implementations, such as Figure 2 As shown, the thickness of the first metal block 14 is H1, and the thickness of the dielectric layer 12 is H4, so H1 = H4. Since the filling groove 13 penetrates the dielectric layer 12, the thickness of the first metal block 14 is equal to the thickness of the dielectric layer 12, that is, the first metal block 14 completely fills the filling groove 13.

[0112] In some implementations, such as Figure 2 As shown and Figure 19 As shown, the thickness of the second metal block 27 is H2 and the thickness of the first dielectric layer 15 is H3, then H3+H4≥H1+H2; that is, when the first dielectric layer 15 and the second dielectric layer 22 are bonded together, the opening groove 16 accommodates the second metal block 27, and an expansion gap is maintained between the second metal block 27 and the first metal block 14; or, the size of the expansion gap is L, then H3+H4=H1+H2+L, L>0.

[0113] In some embodiments, the thickness of the second metal block 27 is less than or equal to the thickness of the first dielectric layer 15, i.e., H2 ≤ H3.

[0114] If the thickness of the second metal block 27 is too small, although it is beneficial for embedding in the slot 16, the gap between it and the first metal block 14 may be too large. After the bonding process is completed, the copper interconnects in the two wafers may not be fully connected, thus affecting electrical transmission. If the thickness of the second metal block 27 is too large, resulting in a gap between it and the first metal block 14 that is too small or even nonexistent and in direct contact, the thermal expansion of copper will cause compression at the copper contact point during heat treatment after bonding, leading to stress inside the bonded wafer and potentially causing internal cracks. Therefore, setting an appropriate expansion gap means that the thickness of the first dielectric layer 15, the thickness of the second metal block 27, and other layer thicknesses are properly matched. This provides sufficient margin for the thermal expansion of copper during heat treatment of the bonded wafer, thereby avoiding problems such as internal cracks caused by excessive stress.

[0115] In some implementations, L = ((H1 + H2) × α × (T - T0))β, where α is the linear thermal expansion coefficient of the metal, in units of 10. -6 / ℃; T is the maximum processing temperature during bonding; T0 is the initial ambient temperature before bonding; β is an empirical coefficient, β is taken from 0.7 to 1.3.

[0116] In some embodiments, the metal composition of the first metal block 14 includes copper and / or gold.

[0117] In some embodiments, the metal composition of the second metal block 27 includes copper and / or gold.

[0118] Furthermore, considering the bonding and subsequent heat treatment temperatures, when the metal composition is entirely copper, α is taken from 18.91 × 10⁻⁶. -6 / ℃~19.53×10 -6 / ℃; for example, α can be 18.91×10 -6 / ℃, 19×10 -6 / ℃, 19.1×10 -6 / ℃, 19.15×10 -6 / ℃, 19.2×10 -6 / ℃, 19.25×10 -6 / ℃, 19.3×10 -6 / ℃, 19.35×10 -6 / ℃, 19.4×10 -6 / ℃, 19.45×10 -6 / ℃, 19.5×10 -6 / ℃ or 19.53×10 -6 / ℃, etc.; β can be 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, 1.05, 1.1, 1.15, 1.2, 1.25, or 1.3, etc. Furthermore, when the metal compositions of the first metal block 14 and the second metal block 27 are different, L=((α1H1+α2H2)×(T-T0))β, where α1 is the linear thermal expansion coefficient of the first metal and α2 is the linear thermal expansion coefficient of the second metal.

[0119] In some embodiments, both the first original wafer 11 and the second original wafer 21 comprise at least one of silicon, glass, SiC, SiN, or LiTaO3.

[0120] In some embodiments, the size of the first original wafer 11 and the second original wafer 21 is any one of 4 inches, 6 inches, 8 inches or 12 inches.

[0121] It is understood that the surfaces of the first original wafer 11 and the second original wafer 21 should be clean before further forming the relevant layer structures. For example, in some embodiments, the surface roughness Ra of the first original wafer 11 and the second original wafer 21 is ≤0.5nm (0.5μm×0.5μm area), the Bow value is -40μm~40μm, and the total thickness deviation (TTV) value is ≤25μm. Exemplarily, Ra can be 0.5nm, 0.4nm, 0.3nm, 0.2nm, 0.1nm, or 0.05nm, etc.; the Bow value can be -40μm, -30μm, -20μm, -10μm, 0μm, 10μm, 20μm, 30μm, or 40μm, etc.; and the TTV value can be 25μm, 22μm, 20μm, 18μm, 15μm, 12μm, 10μm, 8μm, or 5μm, etc.

[0122] In some embodiments, a first isolation layer is provided in the filling groove 13, and the first isolation layer is disposed between the first original wafer 11 and the first metal block 14.

[0123] In some embodiments, the second wafer to be bonded 20 further includes a second isolation layer disposed between the second dielectric layer 22 and the second metal block 27.

[0124] Before depositing copper, an isolation layer can be deposited first to facilitate the diffusion of metals such as copper in the metal block (metal layer), as copper diffuses relatively easily to layers such as dielectric layer 12, thus preventing its diffusion from reducing the insulation of dielectric layer 12. It is understood that after forming the isolation layer, the isolation layer and the corresponding metal block (metal layer) should be considered as a single unit to facilitate the calculation and setting of layer thicknesses and the thickness relationships between different layers. For example, when the above-mentioned first and second isolation layers are provided, the thickness of the first metal block 14 is H1, the thickness of the dielectric layer 12 is H4, the thickness of the second metal block 27 is H2, the thickness of the first dielectric layer 15 is H3, the thickness of the first isolation layer is H5, the thickness of the second isolation layer is H6, and the size of the expansion gap is L. Then, H1 + H5 = H4, H3 ≥ H2 + H6, that is, H3 + H4 ≥ H1 + H5 + H2 + H6, or H3 + H4 = H1 + H5 + H2 + H6 + L.

[0125] In some implementations, the first isolation layer includes at least one of Ti, Ta, or TaN.

[0126] In some embodiments, both the first dielectric layer 15 and the second dielectric layer 22 comprise silicon nitride and / or silicon carbonitride.

[0127] In some embodiments, the dielectric layer 12 comprises silicon oxide.

[0128] Selecting a silicon nitride / silicon carbonitride layer can serve as a pre-reserved film material for subsequent copper back-side interconnection, acting as a stop layer and preventing short circuits caused by direct copper-silicon bonding during mixed bonding.

[0129] In one or more embodiments of the present invention, a method for manufacturing the hybrid bonding structure described in the above embodiments is provided, the method comprising:

[0130] like Figures 5 to 9 as well as Figure 1 As shown, the first wafer to be bonded 10 is manufactured as follows: a first raw wafer 11 is provided, and a dielectric layer 12 is formed on the side of the first raw wafer 11 to be bonded; a filling trench 13 is formed in the dielectric layer 12, and then a first metal block 14 is formed in the filling trench 13; a first dielectric layer 15 is formed to cover the dielectric layer 12 and the first metal block, and then an opening trench 16 corresponding to the position of the filling trench 13 is formed in the first dielectric layer 15 to obtain the first wafer to be bonded 10;

[0131] like Figures 10 to 17 as well as Figure 3 As shown, the second wafer to be bonded 20 is manufactured by providing a second original wafer 21, forming a second dielectric layer 22 on the bonding side of the first original wafer 11, and then forming a second metal block 27 on the second dielectric layer 22 to obtain the second wafer to be bonded 20.

[0132] In some embodiments, the method of forming dielectric layer 12 includes thermal oxidation and / or chemical vapor deposition.

[0133] In some embodiments, the method of forming the filling groove 13 includes etching.

[0134] Exemplarily, the etching described in embodiments of the present invention may optionally include applying a suitable etchant (e.g., on dielectric layer 12), exposure, development, and then performing a suitable etching method, such as dry etching and / or wet etching, in the developed area to form an etched pattern (e.g., forming a filling groove 13 in dielectric layer 12), followed by etchant removal. Further, the etchant application method includes at least one of spin coating, printhead coating, or screen printing.

[0135] In some embodiments, the method of forming the first metal block 14 in the filler 13 includes: depositing a first metal layer on one side of the dielectric layer 12 having the filler 13, and removing excess first metal layer to retain the first metal block 14 within the filler 13. When removing the first metal layer from the surface of the dielectric layer 12, some of the dielectric layer 12 may be removed incidentally, or the surface of the first metal block 14 retained within the filler 13 may be treated to improve the smoothness and flatness of this surface when subsequently used as a bonding surface to form a metal connection, thereby improving the bonding quality.

[0136] In some embodiments, the method of forming the first metal block 14 in the filling tank 13 further includes: depositing a first isolation layer on the side of the dielectric layer 12 having the filling tank 13 before depositing the first metal layer, depositing the first metal layer on the first isolation layer, removing excess first isolation layer and first metal layer, so as to retain a portion of the first isolation layer and the first metal block 14 in the filling tank 13.

[0137] In some implementations, the method of depositing to form the first isolation layer includes physical vapor deposition.

[0138] In some embodiments, the method of forming the first dielectric layer 15 includes chemical vapor deposition.

[0139] In some embodiments, the method of forming the opening groove 16 includes etching.

[0140] During the etching process of the opening groove 16, the formation of the first inclined side surface 17 and the inclination angle of the first inclined side surface 17 can be adjusted by etching process parameters. For example, when using dry etching (such as plasma-assisted etching), the beveled surface can be formed and the angle of the beveled surface controlled by adjusting the power value of the RF bias power and the gas type. For wet etching, this can be achieved by adjusting the machine's revolution speed and the wafer's rotation speed.

[0141] In some embodiments, the metal composition of the first metal layer includes copper and / or gold.

[0142] In some embodiments, the method of forming the second metal block 27 includes either method one or method two:

[0143] Method 1, such as Figures 10 to 16 as well as Figure 3As shown, a second metal layer 23 and a dielectric auxiliary layer 24 are sequentially deposited on the second dielectric layer 22. A chamfered groove 25 is etched on the dielectric auxiliary layer 24, and the outline shape of the chamfered groove 25 is the same as that of the second metal block 27. Then, a third metal layer is deposited on the side of the dielectric auxiliary layer 24 with the chamfered groove 25 to fill the chamfered groove 25 with copper. Then, the excess third metal layer outside the chamfered groove 25 is removed, followed by the removal of the dielectric auxiliary layer 24, and then the removal of the excess second metal layer 23, so that the portion of the third metal layer 26 remaining in the chamfered groove and the portion of the second metal layer 23 remaining below it constitute the second metal block 27.

[0144] Method 2, such as Figure 10 , Figure 11 , Figure 17 as well as Figure 3 As shown, a fourth metal layer 29 is deposited on the second dielectric layer 22, and the fourth metal layer 29 is etched to form the second metal block 27.

[0145] In some embodiments, the method of forming the second dielectric layer 22 includes chemical vapor deposition.

[0146] In some embodiments, in Method 1, the method for depositing the second metal layer 23, the third metal layer, and the fourth metal layer 29 all include physical vapor deposition.

[0147] In some embodiments, in Method 1, the method of depositing to form the dielectric auxiliary layer 24 includes chemical vapor deposition.

[0148] In some embodiments, in Method 1, the method of etching to form the chamfered groove 25 includes etching.

[0149] In some embodiments, in Method 1, the method of depositing to form the second metal layer 23 includes electroplating.

[0150] In some embodiments, in Method 1, the method for removing the excess third metal layer other than the chamfered groove 25 includes chemical mechanical polishing.

[0151] In some embodiments, in Method 1, the method for removing the dielectric auxiliary layer 24 includes dry etching.

[0152] In some embodiments, in Method 1, the method for removing the second metal layer 23 includes etching.

[0153] In some embodiments, Method 1 further includes depositing a second isolation layer on the second dielectric layer 22 before depositing the second metal layer 23, and then depositing the second metal layer 23 on the second isolation layer; when removing the excess second metal layer 23, the excess second isolation layer is also removed to retain a portion of the second isolation layer below the second metal block 27.

[0154] In some embodiments, Method 2 further includes depositing a second isolation layer on the second dielectric layer 22 before depositing the fourth metal layer 29, and then depositing the fourth metal layer 29 on the second isolation layer; when etching the fourth metal layer 29, the excess second isolation layer is also etched away to retain a portion of the second isolation layer below the second metal block 27.

[0155] In some embodiments, the metal components of the second, third, and fourth metal layers all include copper and / or gold.

[0156] In some embodiments, the dielectric auxiliary layer 24 is made of silicon oxide.

[0157] In one or more embodiments of the present invention, a wafer-level hybrid bonding process is provided, the hybrid bonding process comprising:

[0158] like Figure 18 As shown, a hybrid bonding structure as described in the above embodiments is provided, wherein one of the first wafer to be bonded 10, the second wafer to be bonded 20, or the second wafer to be bonded is used as the upper wafer, and the other wafer to be bonded is used as the lower wafer.

[0159] Pre-align the upper and lower wafers to make the second metal block 27 initially aligned with the opening slot 16.

[0160] like Figure 19 As shown, a point pressing process is performed to make the first dielectric layer 15 and the second dielectric layer 22 adhere and contact. During this process, the second inclined side 28 of the second metal block 27 cooperates with the first inclined side 17 of the opening slot 16, so that the second metal block 27 is embedded in the opening slot 16, thereby achieving precise alignment between the upper wafer and the lower wafer.

[0161] like Figure 20 As shown, surface pressing is performed. After the surface pressing is completed, the first dielectric layer 15 and the second dielectric layer 22 are connected, and the first metal block 14 and the second metal block 27 are connected.

[0162] In some embodiments, the pressure of the point pressure treatment is 1N to 10N. For example, it can be 1N, 2N, 3N, 4N, 5N, 6N, 7N, 8N, 9N, or 10N, etc.

[0163] In some implementations, the duration of the point pressure treatment is 5s to 15s. For example, it can be 5s, 6s, 7s, 8s, 9s, 10s, 11s, 12s, 13s, 14s, or 15s, etc.

[0164] In some embodiments, the pressure of the surface pressure treatment is 100N to 300N. For example, it can be 100N, 130N, 150N, 180N, 200N, 220N, 240N, 260N, 280N or 300N, etc.

[0165] In some embodiments, the duration of the surface pressing treatment is 1 min to 10 min. For example, it can be 1 min, 3 min, 5 min, 7 min, 10 min, etc.

[0166] In some embodiments, annealing is performed after the surface pressing process.

[0167] In some embodiments, the annealing temperature is 250°C to 1000°C. Exemplarily, it can be 250°C, 300°C, 350°C, 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, or 1000°C, etc.

[0168] In some embodiments, the annealing process includes a first annealing at 250°C to 500°C for 1 hour to 3 hours, followed by a second annealing at 500°C to 1000°C for 1 hour to 3 hours.

[0169] In some embodiments, the upper wafer is gripped by vacuum adsorption using a suction cup, with a vacuum value of -500 mbar to -300 mbar. Exemplarily, it can be -500 mbar, -480 mbar, -460 mbar, -440 mbar, -420 mbar, -400 mbar, -380 mbar, -360 mbar, -340 mbar, -320 mbar, or -300 mbar, etc.

[0170] Furthermore, in some embodiments, after the point pressing process is completed and before the surface pressing process begins, the upper wafer vacuum-adsorbed by the chuck is subjected to partitioned vacuum release.

[0171] As a further example, the bonding accuracy can be observed using an infrared camera. Utilizing the principle that infrared light can penetrate silicon material, the nested marks on the wafer can be located to measure the bonding accuracy. For instance, a first alignment mark can be set on the first wafer 10 to be bonded, and a second alignment mark can be set on the second wafer 20 to be bonded. After achieving precise bonding using the hybrid bonding structure and hybrid bonding process described above, the second alignment mark is nested within the first alignment mark, forming concentric nested marks, such as... Figure 21 As shown.

[0172] In one or more embodiments of the present invention, a bonding apparatus is provided for performing the bonding process described in the above embodiments, the bonding apparatus including an upper stage and a lower stage arranged opposite to each other for fixing the upper wafer and the lower wafer, respectively;

[0173] A movable slide is used to carry the loading stage and / or the downloading stage, and to adjust the relative position between the upper wafer and the lower wafer.

[0174] A force output unit, connected to the upper stage or the lower stage, is used to perform point pressure and / or surface pressure between the upper wafer and the lower wafer.

[0175] Example 1

[0176] This embodiment provides a hybrid bonding structure as described in the above embodiments, such as... Figures 1 to 2 as well as Figures 3 to 4 As shown, the first wafer to be bonded, 10, and the second wafer to be bonded, 20, are both 12-inch wafers.

[0177] The first wafer to be bonded 10 includes a first raw silicon wafer 11, and a 300nm thick dielectric layer 12 and a 200nm thick first dielectric layer 15 of silicon nitride stacked on its bonding side; the dielectric layer 12 has a filling groove 13, and a first metal block 14 in contact with the first raw wafer 11 is disposed in the filling groove 13; a 10nm thick first isolation layer of titanium is also disposed between the first raw wafer 11 and the first metal block 14; the first dielectric layer 15 has an opening groove 16 corresponding to the position of the filling groove 13, exposing the first metal block 14 with a diameter of 1μm; a first inclined side surface 17 is formed in the first dielectric layer 15 in the opening groove 16; the first inclined side surface 17 has a first inclined angle θ1 of 45°; the first wafer to be bonded 10 also has a first alignment mark; the metal composition of the first metal block 14 is copper; the dielectric layer 12 is silicon oxide.

[0178] The second wafer to be bonded 20 includes a second original wafer 21 (silicon) and a second dielectric layer 22 (silicon carbonitride) with a thickness of 200 nm disposed on one side of its bonding surface; a second metal block 27 with a diameter of 1 μm is disposed on the surface of the second dielectric layer 22 away from the second original wafer 21; and a second isolation layer (titanium layer) with a thickness of 10 nm is disposed between the second original wafer 21 and the second metal block 27; the second metal block 27 has a second inclined side surface 28 that matches the first inclined side surface 17, and the angle between the second inclined side surface 28 and the thickness direction of the second metal block 27 is a second inclined angle θ2, and θ2 = θ1; the second wafer to be bonded 20 also has a second alignment mark; the metal composition of the second metal block 27 is copper;

[0179] The thickness of the first metal block 14 is H1 = 290 nm, the thickness of the dielectric layer is H4 = 300 nm, the thickness of the second metal block 27 is H2 = 188 nm, and the thickness of the first dielectric layer 15 is H3 = 200 nm. Figure 19 As shown, when the first dielectric layer 15 and the second dielectric layer 22 are bonded together, the opening groove 16 accommodates the second metal block 27, and an expansion gap L=2nm is maintained between the second metal block 27 and the first metal block 14.

[0180] This embodiment also provides a method for manufacturing the hybrid bonding structure, including:

[0181] S10. Provide a first raw wafer 11 and a second raw wafer 21. Before further setting the relevant layer structure, the first raw wafer 11 and the second raw wafer 21 are cleaned by a cleaning process to make the surface roughness Ra≤0.5nm (0.5μm×0.5μm area), the bending Bow value is -40μm~40μm, and the total thickness deviation TTV value is ≤5μm.

[0182] S20. For example Figures 5 to 9 by Figure 1 and Figure 2 As shown, the first wafer to be bonded, 10, is manufactured:

[0183] S21. Take the first original wafer 11 and thermally oxidize the side of the first original wafer 11 to be bonded to form a dielectric layer 12;

[0184] S22. A filling trench 13 is formed in the dielectric layer 12 by etching. Specifically, a coating is applied to the dielectric layer 12 by spin coating, and after exposure and development, wet etching is performed in the developed area to form the filling trench 13.

[0185] S23. A first isolation layer is formed on the side of the dielectric layer 12 with the filling trench 13 by physical vapor deposition, and a first metal layer, which is a copper layer, is formed on the first isolation layer by physical vapor deposition. The excess first isolation layer and the first metal layer are removed so that a portion of the first isolation layer and the first metal block 14 are retained in the filling trench 13.

[0186] S24. A first dielectric layer 15 is formed by chemical vapor deposition to cover the dielectric layer 12 and the first metal layer. Then, an opening trench 16 corresponding to the position of the filling trench 13 is etched in the first dielectric layer 15 to obtain the first wafer to be bonded 10. That is, a photoresist is applied to the first dielectric layer 15 by a nozzle coating. After exposure and development, dry etching is performed in the development area. The dry etching is plasma-assisted etching. By controlling the power value of the radio frequency bias power and the etching gas, the first tilt angle of the first tilted side 17 is controlled while forming the filling trench 13; thus, the first wafer to be bonded 10 is obtained.

[0187] S30. For example Figures 10 to 16 by Figure 3 and Figure 4 As shown, the second wafer 20 to be bonded is manufactured:

[0188] S31. Take the second original wafer 21 and form the second dielectric layer 22 on the side of the first original wafer 11 to be bonded by chemical vapor deposition;

[0189] S32. A second isolation layer is deposited on the second dielectric layer 22, and a second metal layer 23, which is a copper layer, is formed on the second isolation layer by electroplating. Then, a dielectric auxiliary layer 24 is formed by chemical vapor deposition; the dielectric auxiliary layer 24 is silicon oxide.

[0190] S33. A chamfered groove 25 is formed on the dielectric auxiliary layer 24 by etching. That is, the dielectric auxiliary layer 24 is coated with adhesive by screen printing, and after exposure and development, dry etching is performed in the developed area. The outline shape of the chamfered groove 25 is the same as that of the second metal block 27. That is, the tilt angle of the tilted side in the chamfered groove 25 is controlled by dry etching, so that the second tilted sidewall in the second metal block 27 reaches the target second tilt angle.

[0191] S34. Then, a third metal layer, which is a copper layer, is deposited on one side of the dielectric auxiliary layer 24 with the chamfered groove 25 to fill the chamfered groove 25 with copper. Then, the excess third metal layer outside the chamfered groove 25 is removed, followed by the removal of the dielectric auxiliary layer 24, and then the excess second metal layer 23 and the excess second isolation layer are removed, so that the portion of the third metal layer 26 retained in the chamfered groove and the portion of the second metal layer 23 retained below it constitute the second metal block 27, and the portion of the second isolation layer below the second metal block 27 is retained; thus, the second wafer to be bonded 20 is obtained.

[0192] Example 2

[0193] This embodiment provides a hybrid bonding structure as described in the above embodiments, differing from Embodiment 1 in the following aspects: both the first wafer to be bonded 10 and the second wafer to be bonded 20 are 8-inch wafers; in the first wafer to be bonded 10, the first original wafer 11 is silicon carbide, the first isolation layer is Ta / TaN, and the first tilt angle θ1 of the first tilted side 17 in the first dielectric layer 15 is 60°; the metal composition of the first metal block 14 and the second metal block 27 is gold; and the manufacturing process of the second wafer to be bonded 20 is different. Specifically, in the manufacturing method of the hybrid bonding structure, such as... Figure 10 , Figure 11 , Figure 17 as well as Figure 3 and Figure 4 As shown, steps S30 to S34 are replaced with the following steps:

[0194] S40. Fabrication of the second wafer to be bonded 20:

[0195] S41. Take the second original wafer 21 and form the second dielectric layer 22 on the side of the first original wafer 11 to be bonded by chemical vapor deposition;

[0196] S42. A second isolation layer is deposited on the second dielectric layer 22, and a fourth metal layer 29 is formed on the second isolation layer by electroplating;

[0197] S43. The fourth metal layer 29 is etched to form the second metal block 27; that is, a photoresist is applied to the fourth metal layer 29 by spin coating, and after exposure and development, dry etching and wet etching are performed in the developed area to remove excess second metal layer 23 and excess second isolation layer, forming the second metal block 27 and retaining part of the second isolation layer below the second metal block 27; thus obtaining the second wafer to be bonded 20.

[0198] Application Example 1

[0199] This application example provides a hybrid bonding process using the hybrid bonding structure of Example 1 or Example 2, performed using the bonding equipment provided in the aforementioned embodiments, such as... Figures 18 to 20 As shown, the hybrid bonding process includes:

[0200] Step 1) Using the hybrid bonding structure described in the first aspect, the first wafer to be bonded 10 is used as the lower wafer, and the second wafer to be bonded 20 is used as the upper wafer. The upper wafer is picked up by vacuum adsorption using a suction cup, and the vacuum value of the vacuum adsorption is -400mbar. The upper wafer and the lower wafer are pre-aligned so that the second metal block 27 in the upper wafer is initially aligned with the opening slot 16 in the lower wafer.

[0201] Step 2) Perform a point pressure treatment to bring the first dielectric layer 15 in the lower wafer into contact with the second dielectric layer 22 in the upper wafer. During this process, the second inclined side 28 of the second metal block 27 in the upper wafer mates with the first inclined side 17 of the opening slot 16 in the lower wafer, so that the second metal block 27 is embedded in the opening slot 16, achieving precise alignment between the upper and lower wafers. The pressure of the point pressure treatment is set to 2N, and the point pressure treatment lasts for 10s. After point pressure treatment, the vacuum of the upper suction cup is released sequentially from the center to the edge.

[0202] Step 3) Perform surface pressing treatment. The surface pressing treatment pressure is set to 300N. After the surface pressing treatment is completed, the first dielectric layer 15 and the second dielectric layer 22 are connected, and the first metal block 14 and the second metal block 27 are connected. After 5 minutes of surface pressing treatment, annealing is performed. The annealing temperature is set to 300℃ and lasts for 2 hours.

[0203] After achieving precise hybrid bonding, the second alignment mark is nested within the first alignment mark, forming concentric nested marks, such as... Figure 21 As shown, the high precision of the hybrid bonding process is demonstrated.

[0204] Comparative Example 1

[0205] This comparative example provides a hybrid bonding structure in the above embodiments. The difference from Embodiment 1 is that the first tilt angle θ1 of the first tilted side 17 in the first wafer to be bonded 10 is 0°, that is, no tilting is performed, and the second tilt angle θ2 of the second tilted side 28 in the second wafer to be bonded 20 is also 0°, that is, no tilting is performed. Apart from the above, the other conditions are exactly the same as in Embodiment 1.

[0206] When the first tilt angle θ1 of the first tilted side surface 17 in the first wafer to be bonded 10 is 0°, if the roughness of the tilted side surface is sufficient, the first wafer can achieve force balance, but Figure 19The space between the two copper blocks at a height L is filled with air, and the air cannot be expelled during the annealing process, ultimately preventing the formation of a metal interconnect.

[0207] Comparing Application Example 1 with Comparative Example 1, it was found that in the hybrid bonding process of Application Example 1, spot pressing is performed first. The spot pressing pressure is small, and pressure is applied to the center of the wafer first, causing the wafer center to bulge and contact the surface first. Then, the bonding spreads like a wave, which can eliminate the gas between the two bonding surfaces. On the other hand, since the hybrid bonding structures in Examples 1 and 2 are provided with inclined sides, they can be moved with the cooperation of the inclined sides during bonding. This allows the first metal block and the second metal block to cooperate and adjust their alignment position under small pressure, thereby improving the bonding accuracy. This helps to avoid the first and second metal blocks being compacted before their positions are adjusted due to the large direct surface pressure, which can easily create voids at the contact point. The gap between the first metal block and the second metal block will be sealed after the material thermally expands. The trace gas can be removed by microscopic reaction during high-temperature annealing, or remain uniformly on the interface, without agglomerating to form large voids. In Comparative Example 1, since no inclined side is provided, mechanical vibration and other factors during the bonding process make it impossible to achieve high-precision direct alignment. There will be interference between the bump and the sidewall of the groove, making it impossible to make slight adjustments to the position. If the width of the groove is increased excessively at this time, although the bump can be inserted smoothly, there will be gaps between the bump and the sidewall of the groove, which is not conducive to improving the bonding accuracy.

[0208] As can be seen from the above, this invention effectively improves the bonding alignment accuracy by creating a specific structure on the surface of the wafers to be bonded, namely, by constructing matching first and second inclined side surfaces in the opening slot and the second metal block. During bonding, the designed inclined side surfaces can be fully utilized, correcting the alignment and bonding positions of the two wafers to be bonded, avoiding errors caused by mechanical movement, vibration, and other factors, thus maintaining a lower offset. Furthermore, this invention, by setting and retaining a suitable expansion gap, can provide a margin for the thermal expansion of copper during the heat treatment of the bonded wafers, which is beneficial for ensuring the quality of the metal interconnects after bonding and effectively controlling the stress of the bonding material.

[0209] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0210] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0211] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A hybrid bonding process, characterized by, The process comprises: providing a hybrid bonding structure comprising a first to-be-bonded wafer and a second to-be-bonded wafer; the first to-be-bonded wafer comprises a first original wafer, a dielectric layer and a first dielectric layer which are stacked on a side to be bonded; a filling groove is arranged in the dielectric layer, and a first metal block in contact with the first original wafer is arranged in the filling groove; an opening groove corresponding to the position of the filling groove is arranged in the first dielectric layer, so as to expose the first metal block; a first inclined side surface is formed in the first dielectric layer in the opening groove; the second to-be-bonded wafer comprises a second original wafer and a second dielectric layer arranged on a side to be bonded; a protruding second metal block is arranged on a surface of the second dielectric layer away from the second original wafer; the opening groove and the second metal block are configured such that the second metal block has a second inclined side surface matched with the first inclined side surface, and the opening groove accommodates the second metal block when the first dielectric layer and the second dielectric layer are in contact during bonding; one of the first to-be-bonded wafer or the second to-be-bonded wafer is taken as an upper wafer, and the other to-be-bonded wafer is taken as a lower wafer; pre-alignment is performed on the upper wafer and the lower wafer, so as to align the second metal block with the opening groove; point pressing treatment is performed, so as to make the first dielectric layer and the second dielectric layer in contact; in this process, the second inclined side surface of the second metal block cooperates with the first inclined side surface of the opening groove, so as to embed the second metal block into the opening groove, and realize fine alignment of the upper wafer and the lower wafer; surface pressing treatment is performed, and after the surface pressing treatment is completed, the first dielectric layer and the second dielectric layer are connected, and the first metal block and the second metal block are connected.

2. The hybrid bonded process of claim 1, wherein, In the hybrid bonding structure, the first inclined side surface and the second inclined side surface satisfy at least one of the following conditions: (a1) the first inclined side surface and the thickness direction of the first dielectric layer form a first inclined angle θ1, 0°< θ1< 90°; (a2) 25°< θ1< 65°; (a3) 40°< θ1< 50°; (a4) the second inclined side surface and the thickness direction of the second metal block form a second inclined angle θ2, θ2= θ1.

3. The hybrid bonded process of claim 1, wherein, In the hybrid bonding structure, the first metal block and the second metal block satisfy at least one of the following conditions: (b1) the thickness of the first metal block is equal to the thickness of the dielectric layer; (b2) when the first dielectric layer and the second dielectric layer are in contact during bonding, the opening groove accommodates the second metal block, and an expansion gap is reserved between the second metal block and the first metal block; (b3) the thickness of the second metal block is less than or equal to the thickness of the first dielectric layer; (b4) the thickness of the first metal block is H1, the thickness of the second metal block is H2, and the size of the expansion gap is L, then L = ((H1+H2) x a x (T-T0))β, wherein a is the linear thermal expansion coefficient of the metal, 10 -6 / ℃; T is the maximum value of the processing temperature at the time of bonding; T0 is the initial temperature of the environment before bonding; and β is an empirical coefficient, β is taken from 0.7 to 1.

3. (b5) the metal composition of the first metal block comprises copper and / or gold; (b6) the metal composition of the second metal block comprises copper and / or gold.

4. The process for hybrid bonding according to claim 1, wherein, The hybrid bonding structure further satisfies at least one of the following conditions: (c1) the first original wafer and the second original wafer each comprise at least one of silicon, glass, SiC, SiN or LiTaO3. (c2) the first isolation layer is arranged between the first original wafer and the first metal block; (c3) the second wafer to be bonded further comprises a second isolation layer, which is arranged between the second dielectric layer and the second metal block; (c4) the first isolation layer comprises at least one of Ti, Ta or TaN; (c5) the first dielectric layer and the second dielectric layer each comprise silicon nitride and / or silicon carbon nitride; (c6) the dielectric layer comprises silicon oxide.

5. The hybrid bonded process of claim 1, wherein, The manufacturing method of the hybrid bonding structure comprises: manufacturing a first wafer to be bonded: providing a first original wafer, forming a dielectric layer on the side of the first original wafer to be bonded, forming a filling slot in the dielectric layer, then forming a first metal block in the filling slot, forming a first dielectric layer to cover the dielectric layer and the first metal block, then forming an opening slot in the first dielectric layer corresponding to the position of the filling slot, to obtain the first wafer to be bonded; manufacturing a second wafer to be bonded: providing a first original wafer, forming a second dielectric layer on the side of the second original wafer to be bonded, then forming a second metal block on the second dielectric layer, to obtain the second wafer to be bonded.

6. The process for hybrid bonding according to claim 5, wherein, In the manufacturing method of the hybrid bonding structure, the first wafer to be bonded satisfies at least one of the following conditions: (d1) the method of forming the dielectric layer comprises thermal oxidation and / or chemical vapor deposition; (d2) the method of forming the filling slot comprises etching; (d3) the method of forming the first metal block in the filling slot comprises: depositing a first metal layer on the side of the dielectric layer having the filling slot, removing the excess first metal layer to retain the first metal block in the filling slot; (d4) the method of forming the first metal block in the filling slot further comprises: before depositing the first metal layer, first depositing a first isolation layer on the side of the dielectric layer having the filling slot, then depositing the first metal layer on the first isolation layer, removing the excess first isolation layer and the first metal layer to retain the first metal block and part of the first isolation layer in the filling slot; (d5) the method of depositing the first isolation layer comprises physical vapor deposition; (d6) the method of forming the first dielectric layer comprises chemical vapor deposition; (d7) the method of forming the opening slot comprises etching; (d8) the metal composition of the first metal layer comprises copper and / or gold.

7. The process for hybrid bonding according to claim 5, wherein In the manufacturing method of the hybrid bonding structure, the method of forming the second metal block comprises any one of the following mode one or mode two: mode one, sequentially depositing a second metal layer and a dielectric auxiliary layer on the second dielectric layer, etching a chamfer slot on the dielectric auxiliary layer, the chamfer slot having the same profile shape as the second metal block; then depositing a third metal layer on the side of the dielectric auxiliary layer having the chamfer slot to fill the chamfer slot with metal, then removing the excess third metal layer outside the chamfer slot, then removing the dielectric auxiliary layer, and then removing the excess second metal layer, so that the part of the third metal layer remaining in the chamfer slot and the part of the second metal layer remaining below it constitute the second metal block; In the second mode, a fourth metal layer is deposited on the second dielectric layer, and the fourth metal layer is etched to form the second metal block.

8. The process of hybrid bonding according to claim 7, wherein, In the manufacturing method of the hybrid bonding structure, the second wafer to be bonded satisfies at least one of the following conditions: (e1) the method of forming the second dielectric layer comprises chemical vapor deposition; (e2) in the first mode, the method of depositing the second metal layer, the third metal layer and the fourth metal layer all comprises physical vapor deposition; (e3) in the first mode, the method of depositing the dielectric auxiliary layer comprises chemical vapor deposition; (e4) in the first mode, the method of etching to form the chamfered groove comprises etching; (e5) in the first mode, the method of depositing the second metal layer comprises electroplating; (e6) in the first mode, the method of removing the excess third metal layer except the chamfered groove comprises chemical mechanical polishing; (e7) in the first mode, the method of removing the dielectric auxiliary layer comprises dry etching; (e8) in the first mode, the method of removing the second metal layer comprises etching; (e9) in the first mode, before depositing the second metal layer, a second isolation layer is first deposited on the second dielectric layer, and then the second metal layer is deposited on the second isolation layer; when the excess second metal layer is removed, the excess second isolation layer is also removed to retain part of the second isolation layer below the second metal block; (e10) in the second mode, before depositing the fourth metal layer, a second isolation layer is first deposited on the second dielectric layer, and then the fourth metal layer is deposited on the second isolation layer; when the fourth metal layer is etched, the excess second isolation layer is also etched to retain part of the second isolation layer below the second metal block; (e11) the metal components of the second metal layer, the third metal layer and the fourth metal layer all comprise copper and / or gold; (e12) the material of the dielectric auxiliary layer comprises silicon oxide.

9. The process for hybrid bonding as claimed in claim 1, wherein, In the hybrid bonding process, at least one of the following conditions is satisfied: (f1) the pressure of the point pressing process is 1N-10N; (f2) the duration of the point pressing process is 5s-15s; (f3) the pressure of the surface pressing process is 100N-300N; (f4) the duration of the surface pressing process is 1min-10min; (f5) annealing is performed after the surface pressing process; (f6) the temperature of the annealing is 250℃-1000℃; (f7) the annealing process comprises a first annealing at 250℃-500℃ for 1h-3h, and then a second annealing at 500℃-1000℃ for 1h-3h; (f8) the upper wafer is grasped by vacuum suction of a suction chuck, and the vacuum value of the vacuum suction is -500mbar--300mbar; after the point pressing process is completed, the upper wafer is released in a partitioned manner before the surface pressing process is started.

10. A bonding apparatus for performing the process of hybrid bonding according to any one of claims 1-9, characterized in that, The device comprises a relatively arranged upper loading platform and a lower loading platform for fixing the upper wafer and the lower wafer respectively; a moving slide platform is used to carry the upper loading platform and / or the lower loading platform, and is used to adjust the relative position between the upper wafer and the lower wafer; A force output part is connected to the upper loading platform or the lower loading platform, and is used to perform point pressure and / or surface pressure between the upper wafer and the lower wafer.

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