Self-driven peak detection switching circuit and power generation system
By using a self-driven peak detection switching circuit, diodes and capacitors are used to control the switching state of the synchronous switch during the input voltage change phase. This solves the problem of high energy consumption in the prior art and achieves efficient generator energy output and switching control.
Patent Information
- Application Number
- CN202511033818.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-25
- Publication Date
- 2025-11-18
AI Technical Summary
Existing peak detection type electronic synchronous switch circuits require a large amount of generator power to operate, resulting in a significant reduction in energy output. Furthermore, existing transistor drive circuits are complex and consume a lot of energy.
Design a self-driven peak detection switch circuit. Utilize a first diode and a first capacitor to turn off the synchronous switch circuit during the rising phase of the input voltage and drive it to close during the falling phase. Self-drive is achieved through positive feedback loop, reducing energy consumption of the generator.
This technology enables efficient detection of generator output peak value and switching on without relying on external power supply, thereby improving energy utilization efficiency, reducing switch closing losses, and enhancing generator output performance.
Smart Images
Figure CN120979402A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of synchronous switch, in particular to a self-driven peak detection switch circuit and a power generation system. BACKGROUND
[0002] As an effective electrostatic energy extraction device, the synchronous switch can convert the continuous alternating voltage output by the generator into pulsed high voltage, thereby reducing the output impedance of the generator. At the same time, the synchronous switch can also improve the electromechanical coupling mode of the generator and enhance the output of the generator.
[0003] The existing peak detection type electronic synchronous switch controls the closing of the transistor switch by designing a peak detection module and using the output voltage signal, so as to achieve the closing at the accurate voltage peak and realize the optimal energy output.
[0004] However, due to the complexity of the existing peak detection and transistor driving circuit, a large amount of energy from the generator is consumed to work, and sometimes the external power supply is needed, which greatly reduces the available energy under the action of the switch. SUMMARY
[0005] Therefore, it is necessary to provide a self-driven peak detection switch circuit capable of reducing the energy consumption of the generator.
[0006] In a first aspect, the embodiments of the present application provide a self-driven peak detection switch circuit, which comprises a first diode, a first capacitor and a synchronous switch circuit, the synchronous switch circuit comprising an NMOS transistor, a PMOS transistor and a first resistor, the gate of the NMOS transistor being connected to the drain of the PMOS transistor and one end of the first resistor, the anode of the first diode being connected to the gate of the PMOS transistor, the drain of the NMOS transistor and the input end of the circuit, the cathode of the first diode being connected to one end of the first capacitor and the source of the PMOS transistor, the other end of the first capacitor being connected to the source of the NMOS transistor, the other end of the first resistor and the output end of the circuit.
[0007] The first diode is used to turn off the synchronous switch circuit in the input voltage rising stage.
[0008] The first capacitor is used to charge in the input voltage rising stage and discharge in the input voltage falling stage, so as to drive the synchronous switch circuit to close.
[0009] In one of the embodiments, the self-driven peak detection switch circuit further comprises a second capacitor, which is arranged on the path of the first diode and the first capacitor and is connected in series with the first capacitor.
[0010] In one embodiment, a second capacitor is disposed between the first diode and the NMOS transistor. One end of the second capacitor is connected to the drain of the NMOS transistor and the circuit input terminal, and the other end of the second capacitor is connected to the anode of the first diode and the gate of the PMOS transistor.
[0011] In one embodiment, the self-driven peak detection switch circuit further includes a second diode and a third diode. The anode of the second diode is connected to the cathode of the third diode and the other end of the first capacitor. The cathode of the second diode is connected to the anode of the first diode and the other end of the second capacitor. The anode of the third diode is grounded.
[0012] In one embodiment, the self-driven peak detection switch circuit further includes a fourth diode, which is disposed at any point in the path between the circuit input terminal, the NMOS transistor, and the circuit output terminal, so that when the NMOS transistor is turned on, electrical energy flows from the circuit input terminal to the circuit output terminal.
[0013] In one embodiment, the self-driven peak detection switch circuit further includes a fifth diode. The anode of the fifth diode is connected to the source of the PMOS transistor, or to any point on the path between the drain of the PMOS transistor and the gate of the NMOS transistor. The cathode of the fifth diode is connected to any point on the path between the circuit input terminal, the NMOS transistor, and the circuit output terminal. The fifth diode is used to release the charge in the first capacitor so that the NMOS transistor enters the cutoff state when the input voltage is lower than the voltage across the first capacitor.
[0014] In one embodiment, the self-driven peak detection switch circuit further includes a second resistor, one end of which is connected to the drain of the PMOS transistor, and the other end of which is connected to both the gate of the NMOS transistor and one end of the first resistor; or,
[0015] The self-driven peak detection switch circuit also includes a third resistor, one end of which is connected to both the drain of the PMOS transistor and one end of the first resistor, and the other end of which is connected to the gate of the NMOS transistor; or,
[0016] The self-driven peak detection switch circuit also includes a fourth resistor and a fifth resistor. One end of the fourth resistor is connected to the drain of the PMOS transistor, and the other end of the fourth resistor is connected to one end of the fifth resistor and one end of the first resistor. The other end of the fifth resistor is connected to the gate of the NMOS transistor.
[0017] Secondly, this application provides a power generation system, which includes an electrostatic generator, a load, and at least one self-driven peak detection switch circuit as described in any of the first aspects above; the electrostatic generator is connected to the circuit input terminal of the self-driven peak detection switch circuit, and the circuit output terminal of the self-driven peak detection switch circuit is connected to the load.
[0018] In one embodiment, the generator of the electrostatic generator includes an electrostatic generator or a piezoelectric generator; the electrostatic generator is a device that realizes the conversion of mechanical energy to electrical energy through electrostatic induction, and the electrostatic generator includes an electret generator or a triboelectric nanogenerator.
[0019] In one embodiment, the positive terminal of the generator is connected to the circuit input terminal of a self-driven peak detection switch circuit, the negative terminal of the generator is connected to the circuit input terminal of another self-driven peak detection switch circuit, and the circuit output terminal of each self-driven peak detection switch circuit is connected to the load.
[0020] The aforementioned self-driven peak detection switch circuit includes a first diode, a first capacitor, and a synchronous switch circuit. The synchronous switch circuit includes an NMOS transistor, a PMOS transistor, and a first resistor. The gate of the NMOS transistor is connected to the drain of the PMOS transistor and one end of the first resistor. The anode of the first diode is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode is connected to one end of the first capacitor and the source of the PMOS transistor. The other end of the first capacitor is connected to the source of the NMOS transistor, the other end of the first resistor, and the circuit output terminal. The first diode is used to turn off the synchronous switch circuit during the input voltage rise phase. The first capacitor is used to charge during the input voltage rise phase and discharge during the input voltage fall phase to drive the synchronous switch circuit to close. Thus, during the voltage rise phase before the input voltage reaches its peak, the circuit input terminal, the first diode, and the first capacitor are connected to the circuit output terminal, charging the first capacitor. The first diode generates a stable voltage drop, causing the PMOS transistor to turn off stably, and consequently the NMOS transistor also turns off. When the input voltage begins to decrease after reaching its peak, the first diode is reverse-biased, and the voltage across the first capacitor remains constant. As the input voltage decreases, the gate voltage of the PMOS transistor is lower than the source voltage, causing the PMOS transistor to turn on. This releases the charge stored in the first capacitor to the gate of the NMOS transistor, driving the NMOS transistor to turn on. This causes the energy / charge in the generator capacitor to flow to the load side, resulting in a rapid decrease in the input voltage, which in turn promotes the PMOS transistor to turn on. The PMOS transistor, in turn, further promotes the NMOS transistor to turn on, thus forming a positive feedback loop. The synchronous switching circuit will remain on until the voltage / energy on the first capacitor can no longer drive the NMOS transistor to turn on. The self-driven peak detection switch circuit described above can effectively detect the peak value of the generator output and achieve self-driven closing at the peak value by relying solely on the generator output. Since the NMOS has a low driving charge, the first capacitor only needs to store a small amount of charge to effectively drive the NMOS, thereby reducing the energy consumption of the generator and improving the energy utilization efficiency. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 A schematic diagram of a power generation system provided for one embodiment;
[0023] Figure 2 A schematic diagram of a self-driven peak detection switch circuit provided in one embodiment;
[0024] Figure 3 This is a schematic diagram of the working logic of a self-driven peak detection switch circuit during the input voltage rise phase in one embodiment.
[0025] Figure 4 This is a schematic diagram of the working logic of a self-driven peak detection switch circuit during the input voltage drop phase in one embodiment.
[0026] Figure 5 A schematic diagram of a self-driven peak detection switch circuit is provided for another embodiment;
[0027] Figure 6 A schematic diagram of a self-driven peak detection switch circuit is provided for another embodiment;
[0028] Figures 7A-7C A schematic diagram of a self-driven peak detection switch circuit is provided for another embodiment;
[0029] Figures 8A-8D A schematic diagram of a self-driven peak detection switch circuit is provided for another embodiment;
[0030] Figure 9 A schematic diagram of a power generation system provided for another embodiment. Detailed Implementation
[0031] To facilitate understanding of this application, a more complete description of the application will be provided below with reference to the accompanying drawings. Embodiments of the application are shown in the drawings. However, the application may be implemented in many different forms and is not limited to the embodiments described herein (rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete).
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0033] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0034] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0035] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.
[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0037] Electrostatic generators have shown great potential in low-frequency and irregular kinetic energy harvesting, offering a green and sustainable solution to the energy supply challenges of distributed sensing nodes such as those in the Internet of Things (IoT). However, due to the inherent capacitive characteristics of these generators, their output internal resistance typically reaches megaohms or even gigohms, significantly reducing their output under low-resistivity loads. Synchronous switches, as effective electrostatic energy extraction devices, can convert the continuous AC voltage output from the generator into pulsed high voltage, reducing the generator's output impedance. Simultaneously, synchronous switches improve the generator's electromechanical coupling mode, enhancing its output. Because the generator's output capacitance is extremely small (~pF to ~nF) while its output voltage is extremely high (~hundredsV to kiloV), the design parameters of the synchronous switch greatly influence its impedance matching with the generator, affecting the final achievable electrical output. Furthermore, to achieve optimal energy output, the switch must close at the peak of the generator's output voltage; closing it at other points may fail to enhance the output or even have a negative effect.
[0038] Currently, the development of synchronous switching technology can be roughly divided into three categories: mechanical synchronous switches, threshold-type electronic synchronous switches, and peak-detection electronic synchronous switches. Specifically: 1) Mechanical synchronous switches achieve closure by designing a decarrier switch structure that precisely closes at the physical position corresponding to the peak output voltage of the generator (e.g., precisely generating contact between moving electrodes). Although simple in structure, it requires customized design for different generator structures. Slight positional deviations may lead to unstable switch operation or performance degradation, resulting in poor robustness. Simultaneously, mechanical switches introduce additional frictional resistance and unexpected discharges at high voltages, reducing electromechanical conversion efficiency and affecting long-term operational stability. 2) Threshold-type electronic synchronous switches utilize electronic threshold switches, including commercially available gas discharge tubing (GDT), air breakdown threshold switches, or silicon controlled rectifiers (SCRs) combined with voltage regulation circuits. The closure of these switches depends on a voltage threshold; when the generator reaches the set threshold, the switch closes. Therefore, the switch threshold is typically set near the peak output voltage of the generator. However, since the peak output voltage of a generator may vary with its operating conditions, the threshold voltage often needs to be set based on the generator's lowest peak voltage to ensure that the threshold switch can still operate under these conditions. Otherwise, all electrical energy output below the threshold voltage must be abandoned, which makes this type of switch less practical. 3) Peak-detection electronic synchronous switches use a peak detection module to control the transistor switch to close accurately at the voltage peak by using the output voltage signal. However, due to the complexity of existing peak detection and transistor drive circuits, which consume excessive energy, these switches often require a large amount of electrical energy from the generator to operate, and sometimes even need to rely on external power supply. This greatly reduces the final electrical energy obtainable under the operation of this type of switch.
[0039] In view of this, embodiments of this application provide a self-driven peak detection switching circuit that can reduce energy consumption of the generator.
[0040] In one exemplary embodiment, such as Figure 1 As shown in the figure, this application embodiment provides a power generation system 10, which includes a generator 100, a self-driven peak detection switch circuit 200 and a load 300. The self-driven peak detection switch is disposed between the generator 100 and the load 300. The generator 100 is connected to the circuit input terminal of the self-driven peak detection switch circuit 200, and the circuit output terminal of the self-driven peak detection switch circuit 200 is connected to the load 300.
[0041] The circuit structure of the self-driven peak detection switch is described below, such as... Figure 2The diagram shown is a possible self-driven peak detection switch circuit. The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOS One end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end is connected to both the circuit output terminal.
[0042] The first diode D1 is used to turn off the synchronous switching circuit during the input voltage rise phase; the first capacitor C... Drive It is used to charge during the rising phase of the input voltage and discharge during the falling phase of the input voltage to drive the synchronous switching circuit to close.
[0043] like Figure 3 and Figure 4 The diagram shows the working logic of the self-driven peak detection switch circuit 200. A complete switch closure consists of two stages: the input voltage rise stage, and the input voltage rise stage. Figure 3 As shown, and during the input voltage drop phase, as Figure 4 As shown. The input voltage of the self-driven peak detection switch circuit 200 is the output voltage of the electrostatic generator.
[0044] Please refer to Figure 3 At the generator output voltage V in During the voltage rise phase before reaching the peak value, the generator, first diode D1, and first capacitor C... Drive With the "load" path connected, due to the presence of capacitor displacement current, the first capacitor C... Drive It will accumulate charge during charging, and at the same time, during the input voltage rise phase, there is current in this path, and the first diode D1 generates a stable voltage drop V. D Since the anode of the first diode D1 is connected to the gate of the PMOS transistor and the cathode of the first diode D1 is connected to the source of the PMOS transistor, the voltage drop V D This causes the gate voltage of the PMOS transistor to be greater than the source voltage, resulting in a gate-source voltage (V) of the PMOS transistor. GS The value remains positive throughout, maintaining the stable shutdown of the PMOS transistor. During this phase, the NMOS transistor also remains stable.
[0045] Please refer to Figure 4At the generator output voltage V in During the decline phase after reaching the peak value, the first diode D1 is reverse-biased and the first capacitor C... Drive With the voltage across both terminals remaining constant, at this time, as the generator output voltage V... in The decrease in voltage (V) of the PMOS transistor leads to a decrease in the gate voltage (V) of the PMOS transistor. G,P = V in The source voltage (V) also decreases. S,P = V Drive The gate voltage of the PMOS transistor remains constant, gradually decreasing below the source voltage, driving the PMOS transistor to conduct. After the PMOS transistor is turned on, the first capacitor C... Drive PMOS transistor and first resistor R NMOS The path 1 between them is open, and the energy stored in the first capacitor C is... Drive The charge is released to the gate of the NMOS transistor, in the first resistor R NMOS A gate-source voltage is formed between the gate and source of the NMOS transistor, driving it to turn on. After the NMOS transistor turns on, path 2 between the NMOS, the generator, and the load is open. Energy / charge in the generator capacitor flows to the load side through path 2, causing the generator output voltage V to increase. in The voltage drops rapidly, which in turn promotes the conduction of the PMOS transistor, and the PMOS transistor further promotes the conduction of the NMOS transistor, thus forming a positive feedback loop. The synchronous switching circuit will continue to conduct until the voltage / energy on the first capacitor can no longer drive the NMOS transistor to conduct.
[0046] Among them, the synchronous switching structure of positive feedback loop also enables the improvement of peak detection sensitivity and greatly improves the switching closing speed, reducing the switching closing speed to the tens of ns level, reducing switching closing losses, and improving the final generator output.
[0047] Optionally, an NMOS transistor can be used as the main switch, and a low-Q transistor can be employed. GS By using NMOS transistors that meet the conduction requirements, the drive charge required by the synchronous switching circuit can be further reduced, thereby further reducing the energy demand on the generator and increasing the generator's output energy to the load.
[0048] In one exemplary embodiment, such as Figure 5 The diagram shown is a schematic of another possible self-driven peak detection switch circuit. Please refer to it. Figure 5 The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOSOne end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end and the circuit output are both connected. The self-driven peak detection switch circuit also includes a second capacitor C. Div The second capacitor C Div The first diode D1 and the first capacitor C are set Drive On the path where it is located, it is connected to the first capacitor C. Drive Series connection.
[0049] Optional, such as Figure 5 As shown, the second capacitor C in The second capacitor C is positioned between the first diode D1 and the NMOS transistor. in One end is connected to the drain of the NMOS transistor and the circuit input terminal, and the second capacitor C in The other end is connected to both the anode of the first diode D1 and the gate of the PMOS transistor.
[0050] Due to limitations in current semiconductor technology, PMOS transistors can only withstand voltages of a few hundred volts, and the driving voltage they can withstand is even lower than tens of volts. In this case, self-driven peak detection switching circuits are usually difficult to apply to the output voltage of electrostatic generators that can reach thousands of volts, resulting in them being unable to work or having extremely low efficiency with most generators.
[0051] Optionally, through the first capacitor C Drive Second capacitor C Div In series, the input voltage V of the self-driven peak detection switch circuit can be controlled. in Voltage division is performed, first capacitor C Drive voltage V Drive = V in ×C Drive / (C Div +C Drive This effectively reduces the first capacitor C. Drive The voltage.
[0052] By selecting an appropriate voltage division ratio, low-voltage PMOS transistors and low-drive-voltage NMOS transistors can still be used when the input voltage is high. Furthermore, the maximum withstand voltage of the self-driven peak detection switch circuit depends entirely on the withstand voltage of the main switch NMOS transistor, which greatly improves the applicability of the switch to high-output-voltage electrostatic generators.
[0053] Furthermore, since the capacitor voltage divider structure only divides the voltage, it does not affect the first capacitor C.Drive The amount of charge obtained (Q) Drive = V max ×C 总电容 Taking advantage of the generator's high output voltage, even the second capacitor C Div Even with a capacitance value in the pF range, the circuit can obtain sufficient charge to effectively drive the synchronous switching circuit. This can be achieved by adjusting the first capacitor C. Drive This allows the first capacitor C to... Drive The voltage range is matched with the drive voltage range of the NMOS transistor, and the voltage stored in the first capacitor C Drive All the charge is used to drive the NNMOS transistor, improving energy utilization efficiency. Meanwhile, the second capacitor C... Div It can also improve the matching between the self-driven peak detection switch circuit and the generator, thereby increasing the total output power of the generator.
[0054] In such Figure 5 The self-driven peak detection switch circuit shown also consists of two stages in a complete switch closure, which will not be described in detail here.
[0055] It is understandable that the self-driven peak detection switch circuit includes a second capacitor C. Div At that time, when the generator output voltage V in During the decline phase after reaching the peak value, the first diode D1 is reverse-biased and the first capacitor C... Drive With the voltage across both terminals remaining constant, at this time, as the generator output voltage V... in The decrease in voltage (V) of the PMOS transistor leads to a decrease in the gate voltage (V) of the PMOS transistor. G,P = V in -V Div (It also decreased.)
[0056] In one exemplary embodiment, such as Figure 6 The diagram shown is a schematic of another possible self-driven peak detection switch circuit. Please refer to it. Figure 6 The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOS One end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOSThe other end and the circuit output are both connected. The self-driven peak detection switch circuit also includes a second capacitor C. Div Second diode D2, third diode D3, second capacitor C Div The first diode D1 and the first capacitor C are set Drive On the path where it is located, it is connected to the first capacitor C. Drive Series connection; the anode of the second diode D2 is connected to the cathode of the third diode D3 and the first capacitor C. Drive The other ends are connected, with the cathode of the second diode D2 connected to the anode of the first diode D1 and the second capacitor C. Div The other end of each diode is connected, and the anode of the third diode D3 is grounded.
[0057] Optional, such as Figure 6 As shown, after the NMOS transistor, when the input voltage Vin is lower than the voltage of the second capacitor C... Div At voltage, Figure 6 The "second diode D2, third diode D3, second capacitor C" Div The path containing the NMOS transistor and the load is turned on, which causes the second capacitor C to conduct. Div The charge can be completely released to the load, increasing output and improving switching efficiency, while also initializing the second capacitor C. Div This state is crucial for the next correct and reliable peak detection and switching triggering.
[0058] In one exemplary embodiment, such as Figures 2-6 As shown, the self-driven peak detection switch circuit also includes a fourth diode D4. The fourth diode D4 is located at any point in the path where the circuit input terminal, the NMOS transistor, and the circuit output terminal are located, so that when the NMOS transistor is turned on, the charge flows from the circuit input terminal to the circuit output terminal.
[0059] The fourth diode, D4, can prevent reverse current surges and avoid damage to the synchronous switching circuit.
[0060] In one possible embodiment, such as Figures 2-6 As shown, the anode of the fourth diode D4 is connected to the source of the NMOS transistor, and the first resistor R... NMOS The other end and the other end C of the first capacitor Drive All are connected, with the cathode of the fourth diode D4 connected to the circuit output terminal.
[0061] In another possible embodiment, the anode of the fourth diode D4 is connected to the source of the NMOS transistor, and the cathode of the fourth diode D4 is connected to the first resistor R. NMOS The other end and the other end C of the first capacitor Drive All are connected.
[0062] In another possible embodiment, the anode of the fourth diode D4 can also be connected to the circuit input terminal, and the cathode of the fourth diode D4 can be connected to the drain of the NMOS transistor.
[0063] It is understood that the connection method of the fourth diode D4 is not limited in the embodiments of this application.
[0064] In one exemplary embodiment, such as Figure 7A or Figure 7B The diagram shows two possible self-driven peak detection switch circuits. Please refer to them. Figure 7A or Figure 7B The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOS One end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end of the circuit is connected to both the circuit output terminal and the self-driven peak detection switch circuit. The self-driven peak detection switch circuit also includes a fifth diode D5. The anode of the fifth diode D5 is connected to the source of the PMOS transistor, or to any point on the path between the drain of the PMOS transistor and the gate of the NMOS transistor. The cathode of the fifth diode D5 is connected to any point on the path between the circuit input terminal, the NMOS transistor and the circuit output terminal. The fifth diode D5 is used to release the charge in the first capacitor so that the NMOS transistor enters the cut-off state when the input voltage is lower than the voltage across the first capacitor.
[0065] For example, such as Figure 7A As shown, the anode of the fifth diode D5 is connected to the drain of the PMOS transistor, and the cathode of the fifth diode D5 is connected to the drain of the NMOS transistor. Figure 7B As shown, the anode of the fifth diode D5 is connected to the source of the PMOS transistor, and the cathode of the fifth diode D5 is connected to the drain of the NMOS transistor.
[0066] By placing a fifth diode D5 between the PMOS and NMOS transistors, the first capacitor C can be de-energized when the input voltage drops below the voltage across the first capacitor. DriveThe charge on the transistor is released rapidly, allowing the main switch NMOS transistor to enter the cutoff state in a timely manner. This shortens the switch's on-time while ensuring sufficient energy transfer, reducing unnecessary on-time and avoiding energy leakage caused by generator asynchrony during high-frequency operation due to excessively long switch on-time. This improves the switch's adaptability to high-frequency generator operation.
[0067] It is understood that the fifth diode D5 can be placed in any of the self-driven peak detection switch circuits in the above embodiments to release the charge in the first capacitor when the input voltage is lower than the voltage across the first capacitor, thereby causing the NMOS transistor to enter the cutoff state. Figures 2-6 In any of the circuits shown, the anode of the fifth diode D5 is connected to the source of the PMOS transistor, or to any point in the path between the drain of the PMOS transistor and the gate of the NMOS transistor, and the cathode of the fifth diode D5 is connected to any point in the path containing the circuit input, the NMOS transistor, and the circuit output. For example, as... Figure 7C The diagram shown is a schematic of another possible self-driven peak detection switch circuit. Please refer to it. Figure 7C The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOS One end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end and the circuit output are both connected; the self-driven peak detection switch circuit also includes a second capacitor C. Div The second capacitor C Div The first diode D1 and the first capacitor C are set Drive On the path where it is located, it is connected to the first capacitor C. Drive The self-driven peak detection switch circuit is connected in series and also includes a fifth diode D5. The anode of the fifth diode D5 is connected to the drain of the PMOS transistor, and the cathode of the fifth diode D5 is connected to the drain of the NMOS transistor.
[0068] It is understood that the types of the diodes described above are not limited in the embodiments of this application.
[0069] In one exemplary embodiment, such as Figures 8A-8DThe diagram shown is a possible self-driven peak detection switch circuit. The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOS One end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end and the circuit output are both connected; for example Figure 8A As shown, the self-driven peak detection switch circuit also includes a second resistor R. NMOS1 The second resistor R NMOS1 One end is connected to the drain of the PMOS transistor, and the second resistor R NMOS1 The other end is connected to the gate of the NMOS transistor and the first resistor R. NMOS One end is connected; or, as Figure 8B As shown, the self-driven peak detection switch circuit also includes a third resistor R. NMOS2 The third resistor R NMOS2 One end is connected to the drain of the PMOS transistor and the first resistor R. NMOS One end of each resistor is connected to the third resistor R. NMOS2 The other end is connected to the gate of the NMOS transistor; or, as... Figure 8C As shown, the self-driven peak detection switch circuit also includes a fourth resistor R. NMOS1 and the fifth resistor R NMOS2 The fourth resistor R NMOS1 One end is connected to the drain of the PMOS transistor, and the fourth resistor R NMOS1 The other end is connected to the fifth resistor R NMOS2 one end and the first resistor R NMOS One end of each resistor is connected to the fifth resistor R. NMOS2 The other end is connected to the gate of the NMOS transistor.
[0070] Optionally, by adding a resistor between the drain of the PMOS transistor and the gate of the NMOS transistor to perform voltage division, the first capacitor C can be reduced. Drive The voltage can be higher without damaging the NMOS transistor, thus broadening the selection range of components for synchronous switching circuits.
[0071] Optionally, in the embodiments of this application, the second resistor, the third resistor, the fourth resistor, and the fifth resistor can be a single resistor or a combination of multiple resistors connected in series.
[0072] It is understandable that the above Figures 8A-8C Adding at least one resistor between the drain of the PMOS transistor and the gate of the NMOS transistor is applicable to any of the self-driven peak detection switching circuits in the above embodiments, that is, applicable to... Figures 2-7A , Figure 7B or Figure 7C In any of the circuits shown. This application's embodiments will not elaborate further.
[0073] For example, such as Figure 8D The diagram shown is a schematic of another possible self-driven peak detection switch circuit. Please refer to it. Figure 8D The self-driven peak detection switch circuit 200 includes a first diode D1 and a first capacitor C. Drive And a synchronous switching circuit, which includes an NMOS transistor, a PMOS transistor, and a first resistor R. NMOS The gate of the NMOS transistor, the drain of the PMOS transistor, and the first resistor R NMOS One end of each diode is connected to the circuit. The anode of the first diode D1 is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode D1 is connected to the first capacitor C. Drive One end of the capacitor is connected to the source of the PMOS transistor, and the first capacitor C is connected to the source of the PMOS transistor. Drive The other end is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end is connected to both the circuit output terminal; it also includes a second capacitor C. Div、 The second diode D2, the third diode D3, the fourth diode D4, and the fourth resistor R NMOS1 and the fifth resistor R NMOS2 The second capacitor C Div One end is connected to the drain of the NMOS transistor and the circuit input terminal, and the second capacitor C Div The other end is connected to both the anode of the first diode D1 and the gate of the PMOS transistor; the anode of the second diode D2 is connected to the cathode of the third diode D3 and the first capacitor C. Drive The other ends are connected, with the cathode of the second diode D2 connected to the anode of the first diode D1 and the second capacitor C. Div The other ends are all connected, with the anode of the third diode D3 grounded; the anode of the fourth diode D4 is connected to the source of the NMOS transistor and the first resistor R. NMOS The other end and the first capacitor C Drive The other ends are connected, and the cathode of the fourth diode D4 is connected to the output terminal; the fourth resistor R NMOS1 One end is connected to the drain of the PMOS transistor, and the fourth resistor R NMOS1 The other end is connected to the fifth resistor R NMOS2 one end and the first resistor R NMOSOne end of each resistor is connected to the fifth resistor R. NMOS2 The other end is connected to the gate of the NMOS transistor.
[0074] Understandably, in Figure 8D The circuit shown may also include a fifth diode D5. The anode of the fifth diode D5 can be connected to the source of the PMOS transistor, or it can be connected to the drain of the PMOS transistor and the second resistor R. NMOS1 One end of the resistor is connected, or it can be connected to the second resistor R. NMOS1 The other end and the second resistor R NMOS2 One end of each resistor is connected, and it can also be connected to a second resistor R. NMOS2 The other end of the diode is connected to the gate of the NMOS transistor; the cathode of the fifth diode D5 can be connected to the drain of the NMOS transistor, or it can be connected to both the source of the NMOS transistor and the anode of the fourth diode D4. This application does not limit this.
[0075] In one embodiment, this application also provides a power generation system 10, such as... Figure 9 As shown, the power generation system includes a generator 100, a load 300, and at least one self-driven peak detection switch circuit 200 as described in any of the above-mentioned embodiments; the generator 100 is connected to the circuit input terminal of the self-driven peak detection switch circuit 200, and the circuit output terminal of the self-driven peak detection switch circuit 200 is connected to the load 300.
[0076] Optionally, the generator 100 may include an electrostatic generator or a piezoelectric generator; the electrostatic generator is a device that realizes the conversion of mechanical energy to electrical energy through electrostatic induction, and may include an electret generator or a triboelectric nanogenerator, etc.
[0077] In an optional embodiment, the power generation system 10 includes a self-driven peak detection switch circuit 200, which is a unipolar positive peak detection switch. Its circuit input is connected to the positive terminal of the generator 100, and its circuit output is connected to the load 300.
[0078] In another alternative embodiment, such as Figure 9 As shown, the power generation system 10 includes two self-driven peak detection switch circuits 200. The positive terminal of the generator 100 is connected to the circuit input terminal of one self-driven peak detection switch circuit 200, and the negative terminal of the generator 100 is connected to the circuit input terminal of the other self-driven peak detection switch circuit 200. The circuit output terminal of each self-driven peak detection switch circuit 200 is connected to the load.
[0079] It is understood that the circuit output of the self-driven peak detection switch circuit 200 can be connected to the same load or to different loads respectively, and this application embodiment does not limit this.
[0080] By setting two self-driven peak detection switch circuits 200, a bipolar switch circuit capable of detecting positive and negative peak values can be obtained.
[0081] Understandable, Figure 9 The self-driven peak detection switch circuit 200 in the above embodiments can be any one of them, and the embodiments of this application do not limit it.
[0082] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A self-driven peak detection switching circuit, characterized in that, The self-driven peak detection switch circuit includes a first diode, a first capacitor, and a synchronous switch circuit. The synchronous switch circuit includes an NMOS transistor, a PMOS transistor, and a first resistor. The gate of the NMOS transistor is connected to the drain of the PMOS transistor and one end of the first resistor. The anode of the first diode is connected to the gate of the PMOS transistor, the drain of the NMOS transistor, and the circuit input terminal. The cathode of the first diode is connected to one end of the first capacitor and the source of the PMOS transistor. The other end of the first capacitor is connected to the source of the NMOS transistor, the other end of the first resistor, and the circuit output terminal. The first diode is used to turn off the synchronous switching circuit during the input voltage rise phase; The first capacitor is used to charge during the input voltage rise phase and discharge during the input voltage fall phase to drive the synchronous switching circuit to close.
2. The circuit according to claim 1, characterized in that, The self-driven peak detection switch circuit also includes a second capacitor, which is disposed in the path between the first diode and the first capacitor and is connected in series with the first capacitor.
3. The circuit according to claim 2, characterized in that, The second capacitor is disposed between the first diode and the NMOS transistor. One end of the second capacitor is connected to the drain of the NMOS transistor and the circuit input terminal, and the other end of the second capacitor is connected to the anode of the first diode and the gate of the PMOS transistor.
4. The circuit according to claim 3, characterized in that, The self-driven peak detection switch circuit further includes a second diode and a third diode. The anode of the second diode is connected to the cathode of the third diode and the other end of the first capacitor. The cathode of the second diode is connected to the anode of the first diode and the other end of the second capacitor. The anode of the third diode is grounded.
5. The circuit according to any one of claims 1 to 4, characterized in that, The self-driven peak detection switch circuit also includes a fourth diode, which is disposed at any point in the path where the circuit input terminal, the NMOS transistor, and the circuit output terminal are located, so that when the NMOS transistor is turned on, charge flows from the circuit input terminal to the circuit output terminal.
6. The circuit according to any one of claims 1 to 5, characterized in that, The self-driven peak detection switch circuit further includes a fifth diode. The anode of the fifth diode is connected to the source of the PMOS transistor, or to any point on the path between the drain of the PMOS transistor and the gate of the NMOS transistor. The cathode of the fifth diode is connected to any point on the path between the circuit input terminal, the NMOS transistor, and the circuit output terminal. The fifth diode is used to release the charge in the first capacitor so that the NMOS transistor enters the cutoff state when the input voltage is lower than the voltage across the first capacitor.
7. The circuit according to any one of claims 1 to 6, characterized in that, The self-driven peak detection switch circuit further includes a second resistor, one end of which is connected to the drain of the PMOS transistor, and the other end of which is connected to both the gate of the NMOS transistor and one end of the first resistor; or, The self-driven peak detection switch circuit further includes a third resistor, one end of which is connected to both the drain of the PMOS transistor and one end of the first resistor, and the other end of which is connected to the gate of the NMOS transistor; or, The self-driven peak detection switch circuit further includes a fourth resistor and a fifth resistor. One end of the fourth resistor is connected to the drain of the PMOS transistor, and the other end of the fourth resistor is connected to one end of the fifth resistor and one end of the first resistor. The other end of the fifth resistor is connected to the gate of the NMOS transistor.
8. A power generation system, characterized in that, The power generation system includes a generator, a load, and a self-driven peak detection switching circuit as described in any one of claims 1 to 7; The generator is connected to the input terminal of the self-driven peak detection switch circuit, and the output terminal of the self-driven peak detection switch circuit is connected to the load.
9. The power generation system according to claim 8, characterized in that, The generator includes an electrostatic generator or a piezoelectric generator; the electrostatic generator is a device that realizes the conversion of mechanical energy to electrical energy through electrostatic induction, and the electrostatic generator includes an electret generator or a triboelectric nanogenerator.
10. The power generation system according to claim 8, characterized in that, The power generation system includes two self-driven peak detection switch circuits. The positive terminal of the generator is connected to the circuit input terminal of one of the self-driven peak detection switch circuits, and the negative terminal of the generator is connected to the circuit input terminal of the other self-driven peak detection switch circuit. The circuit output terminal of each self-driven peak detection switch circuit is connected to the load.