Zero-delay CT SDM excessive loop delay compensation method

Abstract

According to the zero-delay CT SDM excessive loop delay compensation method, the feedback coefficient of loop delay compensation can be adjusted by changing the specific value of different sampling capacitors in a switched capacitor network, the reference level of an embedded quantizer is used for adjusting the gain of the quantizer, the number of ports, connected to the reference level, of a comparator in the Flash quantizer is reduced, and meanwhile the power consumption of the Flash quantizer is reduced. The power consumption of the comparator can be effectively reduced, and the whole circuit is simple in structure and has zero delay.

Description

Technical Field

[0001] This invention relates to a technology in the field of analog-to-digital conversion, specifically a method for compensating for excessive loop delay in a zero-delay continuous-time Σ-Δ modulator (CT SDM) based on a switched-capacitor network. Background Technology

[0002] In practical CT SDM circuits, the operating delay of the quantizer and feedback DAC alters the modulator coefficients and affects loop stability. Therefore, CT SDM circuits require Excess Loop Delay Compensation (ELDC) to ensure circuit performance and stability. Classical ELDC technology utilizes an additional DAC module to directly feed the quantizer output back to the quantizer input. The introduction of the DAC module and summing circuit increases overall circuit power consumption and reduces energy efficiency. Since Σ-Δ modulators have lower requirements for quantizer conversion accuracy, flash analog-to-digital converters (Flash ADCs) are often chosen as the quantizer structure due to their high conversion speed. In differential flash quantizers, the comparator is typically a multi-input structure, consuming more power compared to a two-input comparator. Summary of the Invention

[0003] This invention addresses the problem of excessive loop delay inherent in continuous-time modulators (CT SDMs) which cannot be solved with high energy efficiency by existing technologies. It proposes a zero-delay CT SDM excessive loop delay compensation method, which directly achieves zero-delay compensation during the sampling stage through a switched-capacitor network. This simplifies the circuit structure and significantly reduces the comparator complexity and power consumption.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a zero-delay CT SDM excessive loop delay compensation method, which connects a loop filter circuit, a switched capacitor network array with embedded reference voltage and a quantizer in series between the input and output terminals, and connects a feedback DAC circuit between the output and input terminals. By changing the ratio of different sampling capacitors in the switched capacitor network, the feedback coefficient of loop delay compensation is adjusted, thereby achieving zero-delay compensation.

[0006] The switched capacitor network uses a sampling capacitor based on a ping-pong buffer mechanism to perform the difference operation of the input voltage sampling of two adjacent cycles in the charge domain, and uses the embedded quantizer reference level to synchronously adjust the reference level and gain of the flash quantizer.

[0007] The quantizer described herein may be, but is not limited to, a flash quantizer, which utilizes a switched capacitor network to embed a reference voltage and adjust the quantizer gain.

[0008] Technical effect

[0009] This invention achieves zero-delay ELD compensation by applying a switched-capacitor sampling circuit architecture to the CTDSM design, while simultaneously implementing the difference function between the input signal and the reference signal. Compared with existing technologies, this invention directly achieves zero-delay ELD compensation during the sampling stage, eliminating the need for an additional DAC module. This significantly simplifies the circuit and shortens the quantization delay. Furthermore, it integrates the difference function between the input signal and the reference voltage into the sampling capacitor network, requiring only two input terminals for the subsequent comparator, significantly reducing comparator complexity and power consumption. By adjusting the capacitor ratio in the switched-capacitor network, the ELDC compensation coefficient can be dynamically adjusted to adapt to different loop delay scenarios. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the basic architecture of the CT SDM of the present invention;

[0011] Figure 2 This is a schematic diagram of a switched capacitor network;

[0012] Figure 3 This is the timing diagram of the switched capacitor network;

[0013] Figure 4 This is a schematic diagram of a CT SDM single-ended circuit used for simulation verification of the invention's effectiveness in the embodiment.

[0014] Figure 5 This is a schematic diagram comparing simulation results of an example. Detailed Implementation

[0015] like Figure 1 As shown, this embodiment relates to a zero-delay CT SDM excessive loop delay compensation circuit, including: a loop filter, a switched capacitor network array, a flash quantizer, and a feedback DAC disposed between the output and input terminals, connected in series. The switched capacitor network calculates the difference between the input voltages sampled in two adjacent cycles in the charge domain using a sampling capacitor operating based on a ping-pong buffer mechanism, while simultaneously adjusting the reference level and quantizer gain of the flash quantizer through an embedded quantizer reference level. The flash quantizer outputs a digital signal sequence to the feedback DAC. The feedback DAC feeds the quantization result back to the input terminal of the loop filter.

[0016] like Figure 2 As shown, the switched capacitor network includes three parallel branches, wherein: the first sampling capacitor Second sampling capacitor With a third sampling capacitor The input buffers are respectively set in a parallel branch, and the first sampling capacitor The input and output terminals are each equipped with a first switch. and the fifth switch Second sampling capacitor The input and output terminals are each equipped with a second switch. and the sixth switch The input and output terminals of the third sampling capacitor are each equipped with a seventh switch. and the tenth switch First sampling capacitor Second sampling capacitor The output terminals are connected to the reference voltage Vref.

[0017] The reference voltage Vref and the first sampling capacitor Second sampling capacitor A third switch is provided between each of the output terminals. and the fourth switch .

[0018] The third sampling capacitor An eighth switch is further provided between the input and output terminals and the ground potential. and the ninth switch .

[0019] like Figure 3 As shown, the first switch, the second switch, and the seventh to tenth switches are controlled by the first control signal. Control; the third and sixth switches are controlled by the second control signal. Control; the fourth and fifth switches are controlled by the third control signal. Control. When the control signal is high, the switch is on; when the control signal is low, the switch is off.

[0020] The frequency of the first control signal is twice that of the second and third control signals, and the second and third control signals have a phase difference of 180°, which makes the first and second sampling capacitors and The system operates alternately between two cycles. Specifically, during the quantizer sampling phase, when the second control signal is high and the third control signal is low, the first sampling capacitor... The two ends are connected to the input level respectively. and reference level In the sampling phase of the next cycle, when the second control signal is low and the third control signal is high, the first sampling capacitor... The two ends are connected to the input level respectively. and output level The output signal is obtained from the law of conservation of charge. ,in: This represents the input level of the switched capacitor network. This is the output level of the switched capacitor network. As a reference level, and The capacitance values ​​of the first and third sampling capacitors.

[0021] The output signal is represented in the discrete domain as follows: That is, zero-delay excessive loop delay compensation is achieved through a switched capacitor network during the quantizer sampling stage. Different compensation coefficients can be obtained from... and Different proportions are achieved between them.

[0022] like Figure 4 As shown, this embodiment illustrates a CT SDM system based on the aforementioned circuit, comprising: a first-order low-pass filter, a switched-capacitor network array, a 4-bit flash quantizer, and a feedback DAC disposed between the output and input terminals, connected in series. The switched-capacitor network array consists of 15 switched-capacitor networks, with the output signal of each network directly connected to a comparator in the 4-bit flash quantizer. The gain of the flash quantizer is adjusted by changing the reference level in the switched-capacitor network. The feedback DAC circuit is used to feed the quantizer output back to the SDM input terminal.

[0023] Based on specific simulation experiments, with a CT DSM bandwidth of 625kHz and an oversampling rate of 16, the CT DSM output spectrum is as follows. Figure 5 As shown, in the spectrum of the CT SDM output signal without excessive loop delay compensation, a significant spike appears near the 7MHz frequency. In contrast, the spike near the 7MHz frequency of this invention is reduced by approximately 50dB, demonstrating the effectiveness of the ELDC zero-delay excessive loop delay compensation method based on a switched capacitor network.

[0024] Compared to existing technologies, this invention achieves zero-delay ELD compensation directly during the sampling stage, eliminating the need for an additional DAC module, significantly simplifying the circuit and shortening the quantization delay. By integrating the reference voltage embedded in the switched-capacitor network, the difference function between the input signal and the reference voltage is integrated into the sampling capacitor network, requiring only two input terminals for the subsequent comparator, significantly reducing comparator complexity and power consumption. By adjusting the capacitor ratio in the switched-capacitor network, the ELDC compensation coefficient can be dynamically adjusted to adapt to different loop delay scenarios.

[0025] The specific implementations described herein may be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of this invention. The scope of protection of this invention is defined by the claims and is not limited by the specific implementations described herein. All implementation schemes within the scope thereof are subject to the constraints of this invention.

Claims

1. A zero-latency CT SDM excess loop delay compensation circuit, characterized by, The application relates to a sigma-delta modulator (SDM) comprising a loop filter, a switched capacitor network array, a flash quantizer and a feedback DAC connected in series, wherein the switched capacitor network array adjusts the reference level and the quantizer gain of the flash quantizer by simultaneously calculating the difference between the input voltages of two adjacent periods in the charge domain through a sampling capacitor pair working based on a ping-pong buffer mechanism and through an embedded quantizer reference level, the flash quantizer outputs a digital signal sequence to the feedback DAC, and the feedback DAC feeds back the quantization result to the input end of the loop filter. The switched capacitor network comprises three parallel branches, wherein a first sampling capacitor, a second sampling capacitor and an input buffer with a third sampling capacitor are arranged in one parallel branch, the input end and the output end of the first sampling capacitor are respectively provided with a first switch and a second switch, the input end and the output end of the second sampling capacitor are respectively provided with a first switch and a third switch, the input end and the output end of the third sampling capacitor are respectively provided with a first switch and a fourth switch, and the output ends of the first sampling capacitor and the second sampling capacitor are respectively connected with a reference voltage.

2. The zero-latency CT SDM excess loop delay compensation circuit of claim 1, wherein, The reference voltage and the output ends of the first sampling capacitor and the second sampling capacitor are respectively provided with a third switch and a second switch. The input end and the output end of the third sampling capacitor are further provided with a fourth switch and a first switch. The first to third switches are respectively turned on when the first to third control signals are high and are turned off when the first to third control signals are low, and the fourth switch is turned on when the fourth control signal is low and is turned off when the fourth control signal is high.

3. The zero-latency CT SDM excess loop delay compensation circuit of claim 2, wherein, The application relates to a sigma-delta modulator (SDM) comprising a loop filter, a switched capacitor network array, a flash quantizer and a feedback DAC connected in series, wherein the switched capacitor network array adjusts the reference level and the quantizer gain of the flash quantizer by simultaneously calculating the difference between the input voltages of two adjacent periods in the charge domain through a sampling capacitor pair working based on a ping-pong buffer mechanism and through an embedded quantizer reference level, the flash quantizer outputs a digital signal sequence to the feedback DAC, and the feedback DAC feeds back the quantization result to the input end of the loop filter. The frequency of the first control signal is twice that of the second and third control signals, and the second and third control signals are 180° out of phase, so that the first and second sampling capacitors work alternately in two cycles, specifically: in the quantizer sampling stage, when the second control signal is high and the third control signal is low, the two ends of the first sampling capacitor are connected to the voltage and respectively; in the sampling stage of the next cycle, when the second control signal is low and the third control signal is high, the two ends of the first sampling capacitor are connected to the voltage and respectively, and the output signal is obtained according to the law of conservation of charge, which is expressed in the discrete domain as ; that is, zero-delay excess loop delay compensation is achieved through the switched-capacitor network in the quantizer sampling stage, and different compensation coefficients can be realized by different proportions between and .

4. A CTSDM system based on the excess loop delay compensation circuit of any of claims 1-3, comprising: The switched capacitor network array comprises 15 switched capacitor networks, the output signal of each switched capacitor network is directly connected to a comparator in the 4-bit flash quantizer, the gain of the flash quantizer is adjusted by changing the size of the reference level in the switched capacitor network, and the feedback DAC circuit is used for feeding back the quantizer output result to the input end of the SDM.

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