Error feedback noise shaping successive approximation analog-to-digital converter circuit and conversion method thereof

Abstract

The invention discloses an error feedback noise shaping successive approximation analog-to-digital converter circuit, which comprises a successive approximation analog-to-digital converter, and a conversion residual voltage extraction amplification circuit and a switched capacitor infinite impulse response circuit which are electrically connected with the successive approximation analog-to-digital converter, one end of the conversion residual voltage extraction and amplification circuit is connected with the capacitor array digital-to-analog converter and is used for acquiring a conversion residual voltage signal, and the other end of the conversion residual voltage extraction and amplification circuit is connected with one end of the switched capacitor infinite impulse response circuit; and the amplified conversion residual voltage signal is fed back to the switched capacitor infinite impulse response circuit, and noise shaping is carried out through the noise shaping circuit. The invention discloses an error feedback noise shaping successive approximation analog-to-digital converter circuit with a simple structure and a conversion method thereof, which can realize error feedback noise shaping by utilizing a charge sharing summation mode, avoid the use of an operational amplifier and reduce power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor circuit technology, specifically to an error feedback noise shaping successive approximation analog-to-digital converter circuit and its conversion method. Background Technology

[0002] Currently, converting signals from the analog domain and processing them in the digital domain has become a common method in the field of signal processing technology. This processing method requires the participation of an analog-to-digital converter (ADC) to convert analog signals into digital signals.

[0003] Common types of analog-to-digital converters (ADCs) include flash memory ADCs, successive approximation register ADCs, pipelined ADCs, and Σ-Δ ADCs. However, existing ADC technologies still exhibit the following characteristics: Flash-based analog-to-digital converters (ADCs) are the fastest and simplest in structure, but their application is limited to high-speed, low-precision applications because the number of components required increases exponentially with the number of bits. Successive approximation register-based ADCs use successive approximation algorithms for conversion, have a relatively simple architecture, and low power consumption, but their application in high-precision fields faces challenges due to component mismatch issues. Pipeline-based ADCs utilize pipelined principles to increase throughput, thus improving operating speed. Σ-Δ ADCs utilize oversampling and noise shaping techniques to achieve very high accuracy, but their high power consumption and limited speed are due to the large number of active components and high oversampling rate.

[0004] Therefore, in order to reduce the power consumption of products, it is urgent to develop a successive approximation analog-to-digital converter with a highly digital architecture. Summary of the Invention

[0005] This invention overcomes the shortcomings of the prior art and provides a simple error feedback noise shaping successive approximation analog-to-digital converter circuit and its conversion method. It can achieve error feedback noise shaping by using charge sharing summation, avoiding the use of operational amplifiers and reducing power consumption.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: an error feedback noise shaping successive approximation analog-to-digital converter circuit, comprising: a successive approximation analog-to-digital converter, and a noise shaping circuit electrically connected to the successive approximation analog-to-digital converter, wherein the noise shaping circuit comprises a conversion residual voltage extraction amplification circuit and a switched capacitor infinite impulse response circuit. The successive approximation analog-to-digital converter includes a capacitor array digital-to-analog converter, which is used for analog-to-digital conversion; One end of the conversion residual voltage extraction and amplification circuit is connected to the capacitor array digital-to-analog converter to acquire the conversion residual voltage signal. The other end of the conversion residual voltage extraction and amplification circuit is connected to one end of the switched capacitor infinite impulse response circuit to feed the amplified conversion residual voltage signal back to the switched capacitor infinite impulse response circuit for noise shaping.

[0007] In a preferred embodiment of the present invention, the successive approximation analog-to-digital converter includes: a comparator, the output of which is connected to the input of the successive approximation logic module; the non-inverting input of the comparator is connected to the upper plate of the positive capacitor bank of the capacitor array digital-to-analog converter, and the lower plate of the positive capacitor bank is connected to the reference power supply vref or gnd via a selection switch group one; The inverting input of the comparator is connected to the upper plate of the negative capacitor bank of the capacitor array digital-to-analog converter, and the lower plate of the negative capacitor bank is connected to the reference power supply vref or gnd through the second selection switch group. The upper plates of the positive capacitor bank and the negative capacitor bank are respectively connected to the conversion residual voltage extraction and amplification circuit through sampling switch one and sampling switch two.

[0008] In a preferred embodiment of the present invention, the positive terminal capacitor bank includes capacitor C. 1p ,capacitance C 2p Capacitor C 3p ,capacitance C 4p Capacitor C 5p ,capacitance C 6p ,capacitance C 7p ,capacitance C 8p Capacitor C 9p Capacitor C 10p Furthermore, the upper plates of the capacitors in the positive capacitor bank are all connected to the non-inverting input of the comparator, and the lower plates are connected to the reference power supply vref or gnd via the selection switch group one. The negative terminal capacitor bank includes capacitor C. 1n Capacitor C 2n ,capacitance C 3n ,capacitance C 4n Capacitor C 5n Capacitor C 6n Capacitor C 7n ,capacitance C 8n Capacitor C 9n ,capacitance C 10nFurthermore, the upper plates of the capacitors in the negative capacitor bank are all connected to the inverting input of the comparator, and the lower plates are connected to the reference power supply vref or gnd through the second selection switch group.

[0009] In a preferred embodiment of the present invention, capacitor C 1p Including capacitor C 1pa and capacitor C 1pb Capacitor C 2p Including capacitor C 2pa and capacitor C 2pb ,capacitance C 3p Including capacitor C 3pa and capacitor C 3pb ,capacitance C 4p Including capacitor C 4pa and capacitor C 4pb Capacitor C 5p Including capacitor C 5pa and capacitor C 5pb Capacitor C 6p Including capacitor C 6pa and capacitor C 6pb Capacitor C 7p Including capacitor C 7pa and capacitor C 7pb ,capacitance C 8p Including capacitor C 8pa and capacitor C 8pb Capacitor C 9p Including capacitor C 9pa and capacitor C 9pb ,capacitance C 10p Including capacitor C 10pa and capacitor C 10pb ; Capacitor C 1pa and capacitor C 1pb Capacitor C 2pa and capacitor C 2pb Capacitor C 3pa and capacitor C 3pb Capacitor C 4pa and capacitor C 4pb Capacitor C 5pa and capacitor C 5pb Capacitor C 6pa and capacitor C 6pb Capacitor C 7pa and capacitor C 7pb Capacitor C 8pa and capacitor C 8pb Capacitor C 9pa and capacitor C 9pb Capacitor C10pa and capacitor C 10pb The upper plates of both capacitors are connected to the non-inverting input of the comparator; capacitor C 1pa and capacitor C 1pb Capacitor C 2pa and capacitor C 2pb Capacitor C 3pa and capacitor C 3pb Capacitor C 4pa and capacitor C 4pb Capacitor C 5pa and capacitor C 5pb Capacitor C 6pa and capacitor C 6pb Capacitor C 7pa and capacitor C 7pb Capacitor C 8pa and capacitor C 8pb Capacitor C 9pa and capacitor C 9pb Capacitor C 10pa and capacitor C 10pb The lower plates are all connected to the reference power supply vref or gnd via a selector switch group one.

[0010] In a preferred embodiment of the present invention, capacitor C 1n Including capacitor C 1na and capacitor C 1nb Capacitor C 2n Including capacitor C 2na and capacitor C 2nb ,capacitance C 3n Including capacitor C 3na and capacitor C 3nb ,capacitance C 4n Including capacitor C 4na and capacitor C 4nb Capacitor C 5n Including capacitor C 5na and capacitor C 5nb Capacitor C 6n Including capacitor C 6na and capacitor C 6nb Capacitor C 7n Including capacitor C 7na and capacitor C 7nb ,capacitance C 8n Including capacitor C 8na and capacitor C 8nb Capacitor C 9n Including capacitor C 9na and capacitor C 9nb ,capacitance C 10n Including capacitor C10na and capacitor C 10nb ; Capacitor C 1na and capacitor C 1nb Capacitor C 2na and capacitor C 2nb Capacitor C 3na and capacitor C 3nb Capacitor C 4na and capacitor C 4nb Capacitor C 5na and capacitor C 5nb Capacitor C 6na and capacitor C 6nb Capacitor C 7na and capacitor C 7nb Capacitor C 8na and capacitor C 8nb Capacitor C 9na and capacitor C 9nb Capacitor C 10na and capacitor C 10nb The upper plates of both capacitors are connected to the inverting input of the comparator; capacitor C 1na and capacitor C 1nb Capacitor C 2na and capacitor C 2nb Capacitor C 3na and capacitor C 3nb Capacitor C 4na and capacitor C 4nb Capacitor C 5na and capacitor C 5nb Capacitor C 6na and capacitor C 6nb Capacitor C 7na and capacitor C 7nb Capacitor C 8na and capacitor C 8nb Capacitor C 9na and capacitor C 9nb Capacitor C 10na and capacitor C 10nb The lower plates are all connected to the reference power supply vref or gnd via selector switch group two.

[0011] In a preferred embodiment of the present invention, the VIP terminal of sampling switch one and the VIN terminal of sampling switch two of the capacitor array digital-to-analog converter are respectively connected to the switched capacitor infinite impulse response circuit through switch S6 and switch S4. The switched-capacitor infinite impulse response circuit includes a gain amplifier. The output of the gain amplifier is connected to switch S6, and the input of the gain amplifier is grounded through switch S5. The input of the gain amplifier is also connected to a capacitor C. d Connect to GND; The output of the switched capacitor infinite impulse response circuit is connected to switch S4 through switch S1, and the connection point between switch S1 and switch S4 is connected to gnd through capacitor C1. The output of the switched capacitor infinite impulse response circuit is also connected to the input of the gain amplifier through switches S2 and S3 connected in series, and the connection node of switches S2 and S3 is grounded through capacitor C2.

[0012] In a preferred embodiment of the present invention, capacitors C1, C2, and C3 are... d The capacitance values ​​are equal, and each is 1 / 30 of the total capacitance value of the single-ended capacitor array digital-to-analog converter.

[0013] In a preferred embodiment of the present invention, the gain of the gain amplifier is set to 60, and the noise transfer function is: NTF(z) = 1 - 15 / 8z -1 +15 / 16z -2 .

[0014] In a preferred embodiment of the present invention, a conversion method for an error feedback noise-shaping successive approximation analog-to-digital converter circuit is implemented using an error feedback noise-shaping successive approximation analog-to-digital converter circuit. The conversion method includes: The timing sequence of the successive approximation analog-to-digital converter includes the Φs sampling phase and the Φc conversion phase; When sampling phase Φs, sampling switch one and sampling switch two are closed and connected to the input signal for sampling; When the phase of Φc is changed, the switching switch of the capacitor array digital-to-analog converter is switched sequentially according to the comparator output; When the comparator output is 1 for the first time, capacitor C 1pa The lower plate is switched to gnd, capacitor C 1pb The lower plate remains connected to gnd, and capacitor C 1nb The lower plate is switched to vref, capacitor C 1na The lower electrode plate remains connected to vref; When the first comparator output is 0, capacitor C 1pa The lower plate remains connected to vref, and capacitor C 1pb The lower plate is switched to vref, capacitor C 1nb The lower plate remains connected to gnd, and capacitor C 1na The lower electrode plate is switched to GND; When the second comparator output is 1, capacitor C 2pa The lower plate is switched to gnd, capacitor C 2pb The lower plate remains connected to gnd, and capacitor C 2nb The lower plate is switched to vref, capacitor C 2naThe lower electrode plate remains connected to vref; When the second comparator output is 0, capacitor C 2pa The lower plate remains connected to vref, and capacitor C 2pb The lower plate is switched to vref, capacitor C 2nb3 The lower plate remains connected to gnd, and capacitor C 2na The lower electrode plate is switched to GND; When the third comparator outputs 1, capacitor C 3pa The lower plate is switched to gnd, capacitor C 3pb The lower plate remains connected to gnd, and capacitor C 3nb The lower plate is switched to vref, capacitor C 3na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 3pa The lower plate remains connected to vref, and capacitor C 3pb The lower plate is switched to vref, capacitor C 3nb The lower plate remains connected to gnd, and capacitor C 3na The lower electrode plate is switched to GND; When the fourth comparator output is 1, capacitor C 4pa The lower plate is switched to gnd, capacitor C 4pb The lower plate remains connected to gnd, and capacitor C 4nb The lower plate is switched to vref, capacitor C 4na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 4pa The lower plate remains connected to vref, and capacitor C 4pb The lower plate is switched to vref, capacitor C 4nb The lower plate remains connected to gnd, and capacitor C 4na The lower electrode plate is switched to GND; When the fifth comparator output is 1, capacitor C 5pa The lower plate is switched to gnd, capacitor C 5pb The lower plate remains connected to gnd, and capacitor C 5nb The lower plate is switched to vref, capacitor C 5na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 5pa The lower plate remains connected to vref, and capacitor C 5pb The lower plate is switched to vref, capacitor C 5nb The lower plate remains connected to gnd, and capacitor C 5na The lower electrode plate is switched to GND; When the sixth comparator outputs 1, capacitor C 6p The lower plate is switched to gnd, capacitor C 6n The lower electrode plate remains connected to vref; When the output of the sixth comparator is 0, capacitor C 6p The lower plate remains connected to vref, and capacitor C 6n The lower electrode plate is switched to GND; When the seventh comparator outputs 1, capacitor C 7p The lower plate is switched to gnd, capacitor C 7n The lower electrode plate remains connected to vref; When the output of the seventh comparator is 0, capacitor C 7p The lower plate remains connected to vref, and capacitor C 7n The lower electrode plate is switched to GND; When the eighth comparator output is 1, capacitor C 8p The lower plate is switched to gnd, capacitor C 8n The lower electrode plate remains connected to vref; When the output of the eighth comparator is 0, capacitor C 8p The lower plate remains connected to vref, and capacitor C 8n The lower electrode plate is switched to GND; When the ninth comparator output is 1, capacitor C 9p The lower plate is switched to gnd, capacitor C 9n The lower electrode plate remains connected to vref; When the ninth comparator output is 0, capacitor C 9p The lower plate remains connected to vref, and capacitor C 9n The lower electrode plate is switched to GND; When the tenth comparator output is 1, capacitor C 10p The lower plate is switched to gnd, capacitor C 10n The lower electrode plate remains connected to vref; When the tenth comparator output is 0, capacitor C 10p The lower plate remains connected to vref, and capacitor C 10n The lower electrode plate is switched to GND.

[0015] In a preferred embodiment of the present invention, during the reset phase, capacitor C d The upper plate is connected to gnd via a switch, which connects capacitor C. dThe stored charge is cleared; in the residual extraction amplification phase, the upper plates of capacitors C1 and C2 are connected to the output of the dynamic amplifier via a switch to obtain the residual voltage from the previous successive approximation conversion and store it in the form of charge; in the delayed phase, the upper plate of capacitor C2 and capacitor C... d The upper plates are connected to each other, and the residual voltage delay of one cycle is achieved through charge sharing; During the error feedback phase, the upper plate of capacitor C1 and capacitor C d The upper plates are connected to the upper plates of the capacitor array digital-to-analog converter, and voltage summation is achieved through charge sharing, thereby realizing the noise shaping function.

[0016] This invention addresses the deficiencies in the technical background, and the beneficial technical effects of this invention are: A simple error feedback noise shaping successive approximation analog-to-digital converter circuit and its conversion method are disclosed. The circuit can achieve error feedback noise shaping by using charge sharing summation, avoiding the use of operational amplifiers and reducing power consumption. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Figure 1 This is a schematic diagram of the circuit structure of a successive approximation analog-to-digital converter according to a preferred embodiment of the present invention. Figure 2 A schematic diagram of the circuit structure of the switched capacitor infinite impulse response circuit according to a preferred embodiment of the present invention; Figure 3 FFT simulation, a preferred embodiment of the present invention Figure 1 ; Figure 4 FFT simulation, a preferred embodiment of the present invention Figure 2 ; Figure 5 This is a parameter performance table for solutions in the prior art. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention and therefore only show the components relevant to the present invention.

[0020] Example 1, as Figures 1-3As shown, an error feedback noise shaping successive approximation analog-to-digital converter (ADC) circuit includes: a successive approximation ADC, a conversion residual voltage extraction and amplification circuit and a switched-capacitor infinite impulse response circuit electrically connected to the successive approximation ADC; the successive approximation ADC includes a capacitor array digital-to-analog converter (DAC) for analog-to-digital conversion; one end of the conversion residual voltage extraction and amplification circuit is connected to the capacitor array DAC to acquire the conversion residual voltage signal, and the other end of the conversion residual voltage extraction and amplification circuit is connected to one end of the switched-capacitor infinite impulse response circuit to feed back the amplified conversion residual voltage signal to the switched-capacitor infinite impulse response circuit for noise shaping by the noise shaping circuit.

[0021] Specifically, the successive approximation analog-to-digital converter includes: a comparator, the output of which is connected to the input of the successive approximation logic module; the non-inverting input of the comparator is connected to the upper plate of the positive capacitor bank of the capacitor array digital-to-analog converter, and the lower plate of the positive capacitor bank is connected to the reference power supply vref or gnd via a selection switch group one; the inverting input of the comparator is connected to the upper plate of the negative capacitor bank of the capacitor array digital-to-analog converter, and the lower plate of the negative capacitor bank is connected to the reference power supply vref or gnd via a selection switch group two; the upper plates of the positive and negative capacitor banks are respectively connected to the conversion residual voltage extraction amplification circuit via sampling switch one and sampling switch two. Further, the successive approximation logic circuit employing a binary search algorithm is specifically implemented as follows: the successive approximation logic records and outputs CTRLLP and CTRLN control signals to switch the circuit based on the comparator's result. If the comparator output is 0, the corresponding switch of the upper half of the capacitor array is switched to VREF, and the corresponding switch of the lower half of the capacitor array is switched to GND, and DOUT=0 is recorded. If the comparator output is 1, the corresponding switch of the upper half of the capacitor array is switched to GND, and the corresponding switch of the lower half of the capacitor array is switched to VREF, and DOUT=1 is recorded. DOUT is the output code value, i.e., the digital output of the analog-to-digital converter, and does not participate in the closed loop. CTRLP of the "successive approximation logic" is a control signal. CTRLP and CTRLN control the switches of the upper and lower half of the capacitor array, respectively.

[0022] Specifically, the capacitor array digital-to-analog converter is connected to the switched-capacitor infinite impulse response circuit via switches S6 and S4; the switched-capacitor infinite impulse response circuit includes a gain amplifier, the output of which is connected to switch S6, the input of which is grounded via switch S5, and the input of which is also connected to a capacitor C. dThe output of the switched capacitor infinite impulse response circuit is connected to gnd through switch S1 and switch S4, and the connection node of switch S1 and switch S4 is connected to gnd through capacitor C1; the output of the switched capacitor infinite impulse response circuit is also connected to the input of the gain amplifier through switches S2 and S3 connected in series, and the connection node of switches S2 and S3 is grounded through capacitor C2.

[0023] Example 2, based on Example 1, such as Figures 1-3 As shown, in the error feedback noise shaping successive approximation analog-to-digital converter circuit, the positive terminal capacitor bank includes capacitor C. 1p ,capacitance C 2p Capacitor C 3p ,capacitance C 4p Capacitor C 5p ,capacitance C 6p ,capacitance C 7p ,capacitance C 8p Capacitor C 9p Capacitor C 10p Furthermore, the upper plates of all capacitors in the positive capacitor bank are connected to the non-inverting input of the comparator, and the lower plates are connected to the reference power supply vref or gnd via a selector switch group. More specifically, capacitor C... 1p Including capacitor C 1pa and capacitor C 1pb Capacitor C 2p Including capacitor C 2pa and capacitor C 2pb ,capacitance C 3p Including capacitor C 3pa and capacitor C 3pb ,capacitance C 4p Including capacitor C 4pa and capacitor C 4pb Capacitor C 5p Including capacitor C 5pa and capacitor C 5pb Capacitor C 6p Including capacitor C 6pa and capacitor C 6pb Capacitor C 7p Including capacitor C 7pa and capacitor C 7pb ,capacitance C 8p Including capacitor C 8pa and capacitor C 8pb Capacitor C 9p Including capacitor C 9paand capacitor C 9pb ,capacitance C 10p Including capacitor C 10pa and capacitor C 10pb Capacitor C 1pa and capacitor C 1pb Capacitor C 2pa and capacitor C 2pb Capacitor C 3pa and capacitor C 3pb Capacitor C 4pa and capacitor C 4pb Capacitor C 5pa and capacitor C 5pb Capacitor C 6pa and capacitor C 6pb Capacitor C 7pa and capacitor C 7pb Capacitor C 8pa and capacitor C 8pb Capacitor C 9pa and capacitor C 9pb Capacitor C 10pa and capacitor C 10pb The upper plates of both capacitors are connected to the non-inverting input of the comparator; capacitor C 1pa and capacitor C 1pb Capacitor C 2pa and capacitor C 2pb Capacitor C 3pa and capacitor C 3pb Capacitor C 4pa and capacitor C 4pb Capacitor C 5pa and capacitor C 5pb Capacitor C 6pa and capacitor C 6pb Capacitor C 7pa and capacitor C 7pb Capacitor C 8pa and capacitor C 8pb Capacitor C 9pa and capacitor C 9pb Capacitor C 10pa and capacitor C 10pb The lower plates are all connected to the reference power supply vref or gnd via a selector switch group one.

[0024] Specifically, the negative terminal capacitor bank includes capacitor C. 1n Capacitor C 2n ,capacitance C 3n ,capacitance C 4n Capacitor C 5n Capacitor C 6n Capacitor C 7n ,capacitance C 8n Capacitor C 9n ,capacitance C 10n Furthermore, the upper plates of all capacitors in the negative capacitor bank are connected to the inverting input of the comparator, and the lower plates are connected to the reference power supply vref or gnd via selection switch group two. More specifically, capacitor C 1n Including capacitor C 1na and capacitor C 1nb Capacitor C 2n Including capacitor C 2na and capacitor C 2nb ,capacitance C 3n Including capacitor C 3na and capacitor C 3nb ,capacitance C 4n Including capacitor C 4na and capacitor C 4nb Capacitor C 5n Including capacitor C 5na and capacitor C 5nb Capacitor C 6n Including capacitor C 6na and capacitor C 6nb Capacitor C 7n Including capacitor C 7na and capacitor C 7nb ,capacitance C 8n Including capacitor C 8na and capacitor C 8nb Capacitor C 9n Including capacitor C 9na and capacitor C 9nb ,capacitance C 10n Including capacitor C 10na and capacitor C 10nb Capacitor C 1na and capacitor C 1nb Capacitor C 2na and capacitor C 2nb Capacitor C 3na and capacitor C 3nb Capacitor C 4na and capacitor C 4nb Capacitor C 5na and capacitor C 5nb Capacitor C 6na and capacitor C 6nb Capacitor C 7na and capacitor C 7nb Capacitor C 8na and capacitor C 8nb Capacitor C 9na and capacitor C9nb Capacitor C 10na and capacitor C 10nb The upper plates of both capacitors are connected to the inverting input of the comparator; capacitor C 1na and capacitor C 1nb Capacitor C 2na and capacitor C 2nb Capacitor C 3na and capacitor C 3nb Capacitor C 4na and capacitor C 4nb Capacitor C 5na and capacitor C 5nb Capacitor C 6na and capacitor C 6nb Capacitor C 7na and capacitor C 7nb Capacitor C 8na and capacitor C 8nb Capacitor C 9na and capacitor C 9nb Capacitor C 10na and capacitor C 10nb The lower plates are all connected to the reference power supply vref or gnd via selector switch group two.

[0025] like Figure 2 As shown, the present invention relates to a finite impulse response filter constructed using a switched capacitor circuit. The passive switched capacitor finite impulse response filter consists of capacitors C1, C2, and C... d It consists of switches S1, S2, S3, S4, and S5. The upper plates of capacitors C1 and C2 are connected to one end of switches S1 and S2, respectively, and the lower plates of capacitors C1 and C2 are connected to gnd. The other ends of switches S1 and S2 are connected to the output of the gain amplifier. One end of switch S3 is connected to the upper plate of capacitor C2, and the other end is connected to capacitor C... d The upper plate is connected. Capacitor C d The lower electrode plate is connected to gnd. One end of switch S5 is connected to C. d One end is connected to the upper plate, and the other end is connected to gnd. One end of switch S6 is connected to C. d One end of switch S4 is connected to the upper plate of capacitor C1, and the other end is connected to the upper plate of the capacitor array of the capacitor array digital-to-analog converter.

[0026] Example 3, based on Example 2, such as Figure 2As shown, the noise shaping circuit is presented in single-ended form, but the actual circuit is differential. The noise shaping process consists of a reset phase, a residual extraction and amplification phase, a delay phase, and an error feedback phase, with each phase performing a specific task sequentially. The capacitors C1, C2, and C3 in the switched-capacitor infinite impulse response circuit are shown in the diagram. d The capacitance values ​​are equal, and each is 1 / 30 of the total capacitance of the single-ended capacitor array digital-to-analog converter. To compensate for the voltage attenuation caused by charge sharing during the filtering process of the switched-capacitor finite impulse response filter, a dynamic amplifier is needed to achieve gain attenuation compensation. Furthermore, the gain of the gain amplifier is set to 60; the noise transfer function is: NTF(z) = 1 - 15 / 8z -1 +15 / 16z -2 z is the field transfer function, z -1 Represents a one-cycle delay, z -2 This represents a two-cycle delay.

[0027] Specifically, in one alternative example, the dynamic amplifier can be multiplexed with a comparator in a successive approximation analog-to-digital converter and have its gain calibrated using a digital back-end calibration method, thereby further reducing power consumption.

[0028] Example 4: A conversion method for an error feedback noise-shaping successive approximation analog-to-digital converter circuit, implemented using an error feedback noise-shaping successive approximation analog-to-digital converter circuit from any of Examples 1 to 3. The conversion method includes: The timing sequence of the successive approximation analog-to-digital converter includes the Φs sampling phase and the Φc conversion phase; When sampling phase Φs, sampling switch one and sampling switch two are closed and connected to the input signal for sampling; When the phase of Φc is changed, the switching switch of the capacitor array digital-to-analog converter is switched sequentially according to the comparator output; When the comparator output is 1 for the first time, capacitor C 1pa The lower plate is switched to gnd, capacitor C 1pb The lower plate remains connected to gnd, and capacitor C 1nb The lower plate is switched to vref, capacitor C 1na The lower electrode plate remains connected to vref; When the first comparator output is 0, capacitor C 1pa The lower plate remains connected to vref, and capacitor C 1pb The lower plate is switched to vref, capacitor C 1nb The lower plate remains connected to gnd, and capacitor C 1na The lower electrode plate is switched to GND; When the second comparator output is 1, capacitor C 2paThe lower plate is switched to gnd, capacitor C 2pb The lower plate remains connected to gnd, and capacitor C 2nb The lower plate is switched to vref, capacitor C 2na The lower electrode plate remains connected to vref; When the second comparator output is 0, capacitor C 2pa The lower plate remains connected to vref, and capacitor C 2pb The lower plate is switched to vref, capacitor C 2nb3 The lower plate remains connected to gnd, and capacitor C 2na The lower electrode plate is switched to GND; When the third comparator outputs 1, capacitor C 3pa The lower plate is switched to gnd, capacitor C 3pb The lower plate remains connected to gnd, and capacitor C 3nb The lower plate is switched to vref, capacitor C 3na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 3pa The lower plate remains connected to vref, and capacitor C 3pb The lower plate is switched to vref, capacitor C 3nb The lower plate remains connected to gnd, and capacitor C 3na The lower electrode plate is switched to GND; When the fourth comparator output is 1, capacitor C 4pa The lower plate is switched to gnd, capacitor C 4pb The lower plate remains connected to gnd, and capacitor C 4nb The lower plate is switched to vref, capacitor C 4na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 4pa The lower plate remains connected to vref, and capacitor C 4pb The lower plate is switched to vref, capacitor C 4nb The lower plate remains connected to gnd, and capacitor C 4na The lower electrode plate is switched to GND; When the fifth comparator output is 1, capacitor C 5pa The lower plate is switched to gnd, capacitor C 5pb The lower plate remains connected to gnd, and capacitor C 5nb The lower plate is switched to vref, capacitor C 5na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 5pa The lower plate remains connected to vref, and capacitor C5pb The lower plate is switched to vref, capacitor C 5nb The lower plate remains connected to gnd, and capacitor C 5na The lower electrode plate is switched to GND; When the sixth comparator outputs 1, capacitor C 6p The lower plate is switched to gnd, capacitor C 6n The lower electrode plate remains connected to vref; When the output of the sixth comparator is 0, capacitor C 6p The lower plate remains connected to vref, and capacitor C 6n The lower electrode plate is switched to GND; When the seventh comparator outputs 1, capacitor C 7p The lower plate is switched to gnd, capacitor C 7n The lower electrode plate remains connected to vref; When the output of the seventh comparator is 0, capacitor C 7p The lower plate remains connected to vref, and capacitor C 7n The lower electrode plate is switched to GND; When the eighth comparator output is 1, capacitor C 8p The lower plate is switched to gnd, capacitor C 8n The lower electrode plate remains connected to vref; When the output of the eighth comparator is 0, capacitor C 8p The lower plate remains connected to vref, and capacitor C 8n The lower electrode plate is switched to GND; When the ninth comparator output is 1, capacitor C 9p The lower plate is switched to gnd, capacitor C 9n The lower electrode plate remains connected to vref; When the ninth comparator output is 0, capacitor C 9p The lower plate remains connected to vref, and capacitor C 9n The lower electrode plate is switched to GND; When the tenth comparator output is 1, capacitor C 10p The lower plate is switched to gnd, capacitor C 10n The lower electrode plate remains connected to vref; When the tenth comparator output is 0, capacitor C 10p The lower plate remains connected to vref, and capacitor C 10n The lower electrode plate is switched to GND.

[0029] Specifically, the first five capacitor switching operations can ensure that the output common-mode voltage of the capacitor array digital-to-analog converter remains constant, thereby reducing the design difficulty of the dynamic comparator and also reducing the overall power consumption of the capacitor array digital-to-analog converter.

[0030] Example 5, based on Example 4, in a conversion method for an error feedback noise shaping successive approximation analog-to-digital converter circuit, such as... Figure 2 As shown, capacitor C d The upper plate is connected to gnd via a switch, which connects capacitor C. d The stored charge is cleared; in the residual extraction amplification phase, the upper plates of capacitors C1 and C2 are connected to the output of the dynamic amplifier through a switch to obtain the residual voltage of the previous successive approximation conversion and store it in the form of charge. During the delayed phase, the upper plate of capacitor C2 is parallel to that of capacitor C. d The upper plates are connected to each other, and the residual voltage delay of one cycle is achieved through charge sharing; During the error feedback phase, the upper plate of capacitor C1 and capacitor C d The upper plates are connected to the upper plates of the capacitor array digital-to-analog converter, and voltage summation is achieved through charge sharing, thereby realizing the noise shaping function.

[0031] Working principle: This invention provides an error feedback noise shaping successive approximation analog-to-digital converter circuit and its conversion method. The switched-capacitor infinite impulse response filter noise shaping circuit of this invention has a simple structure, requiring only MOS switches and capacitors. By connecting it to the upper plate of the capacitor array in a capacitor array digital-to-analog converter, error feedback noise shaping is achieved through charge-sharing summation. Simultaneously, the use of a dynamic amplifier to amplify the conversion residual avoids the need for an operational amplifier, thereby significantly reducing power consumption.

[0032] like Figure 3 The image shown is a simulation example of an FFT. This noise-shaping successive approximation analog-to-digital converter (ADC) has an OSR of 8 and a 10-bit precision, achieving an SNR of 83.24 dB, an SFDR of 88.14 dB, and an ENOB of 13.53 bits. Compared to existing technologies such as... Figure 5 As shown, the present invention provides a simple error feedback noise shaping successive approximation analog-to-digital converter circuit and its conversion method, which can achieve error feedback noise shaping by using charge sharing summation, avoiding the use of operational amplifiers and reducing power consumption.

[0033] The above specific embodiments are specific support for the concept proposed in this invention, and should not be used to limit the scope of protection of this invention. Any equivalent changes or modifications made on the basis of this technical solution in accordance with the technical concept proposed in this invention shall still fall within the scope of protection of this invention.

Claims

1. An error feedback noise shaping successive approximation analog-to-digital converter circuit, characterized in that, include: A successive approximation analog-to-digital converter, and a noise shaping circuit electrically connected to the successive approximation analog-to-digital converter, the noise shaping circuit including a conversion residual voltage extraction amplification circuit and a switched capacitor infinite impulse response circuit; The successive approximation analog-to-digital converter includes a capacitor array digital-to-analog converter, which is used for analog-to-digital conversion; One end of the conversion residual voltage extraction and amplification circuit is connected to the capacitor array digital-to-analog converter to acquire the conversion residual voltage signal. The other end of the conversion residual voltage extraction and amplification circuit is connected to one end of the switched capacitor infinite impulse response circuit to feed the amplified conversion residual voltage signal back to the switched capacitor infinite impulse response circuit for noise shaping.

2. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 1, characterized in that: The successive approximation analog-to-digital converter includes: a comparator, the output of which is connected to the input of the successive approximation logic module; the non-inverting input of the comparator is connected to the upper plate of the positive capacitor bank of the capacitor array digital-to-analog converter, and the lower plate of the positive capacitor bank is connected to the reference power supply vref or gnd through a selection switch group one. The inverting input of the comparator is connected to the upper plate of the negative capacitor bank of the capacitor array digital-to-analog converter, and the lower plate of the negative capacitor bank is connected to the reference power supply vref or gnd through the second selection switch group. The upper plates of the positive capacitor bank and the negative capacitor bank are respectively connected to the conversion residual voltage extraction and amplification circuit through sampling switch one and sampling switch two.

3. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 2, characterized in that: The positive terminal capacitor bank includes capacitor C 1p Capacitor C 2p Capacitor C 3p Capacitor C 4p Capacitor C 5p Capacitor C 6p Capacitor C 7p Capacitor C 8p Capacitor C 9p Capacitor C 10p Furthermore, the upper plates of the capacitors in the positive capacitor bank are all connected to the non-inverting input of the comparator, and the lower plates are connected to the reference power supply vref or gnd via the selection switch group one. The negative terminal capacitor bank includes capacitor C. 1n Capacitor C 2n Capacitor C 3n Capacitor C 4n Capacitor C 5n Capacitor C 6n Capacitor C 7n Capacitor C 8n Capacitor C 9n Capacitor C 10n Furthermore, the upper plates of the capacitors in the negative capacitor bank are all connected to the inverting input of the comparator, and the lower plates are connected to the reference power supply vref or gnd via the second selection switch.

4. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 3, characterized in that: Capacitor C 1p Including capacitor C 1pa and capacitor C 1pb Capacitor C 2p Including capacitor C 2pa and capacitor C 2pb Capacitor C 3p Including capacitor C 3pa and capacitor C 3pb Capacitor C 4p Including capacitor C 4pa and capacitor C 4pb Capacitor C 5p Including capacitor C 5pa and capacitor C 5pb Capacitor C 6p Including capacitor C 6pa and capacitor C 6pb Capacitor C 7p Including capacitor C 7pa and capacitor C 7pb Capacitor C 8p Including capacitor C 8pa and capacitor C 8pb Capacitor C 9p Including capacitor C 9pa and capacitor C 9pb Capacitor C 10p Including capacitor C 10pa and capacitor C 10pb ; Capacitor C 1pa and capacitor C 1pb Capacitor C 2pa and capacitor C 2pb Capacitor C 3pa and capacitor C 3pb Capacitor C 4pa and capacitor C 4pb Capacitor C 5pa and capacitor C 5pb Capacitor C 6pa and capacitor C 6pb Capacitor C 7pa and capacitor C 7pb Capacitor C 8pa and capacitor C 8pb Capacitor C 9pa and capacitor C 9pb Capacitor C 10pa and capacitor C 10pb The upper plates of both capacitors are connected to the non-inverting input of the comparator; capacitor C 1pa and capacitor C 1pb Capacitor C 2pa and capacitor C 2pb Capacitor C 3pa and capacitor C 3pb Capacitor C 4pa and capacitor C 4pb Capacitor C 5pa and capacitor C 5pb Capacitor C 6pa and capacitor C 6pb Capacitor C 7pa and capacitor C 7pb Capacitor C 8pa and capacitor C 8pb Capacitor C 9pa and capacitor C 9pb Capacitor C 10pa and capacitor C 10pb The lower plates are all connected to the reference power supply vref or gnd via a selector switch group one.

5. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 4, characterized in that: Capacitor C 1n Including capacitor C 1na and capacitor C 1nb Capacitor C 2n Including capacitor C 2na and capacitor C 2nb Capacitor C 3n Including capacitor C 3na and capacitor C 3nb Capacitor C 4n Including capacitor C 4na and capacitor C 4nb Capacitor C 5n Including capacitor C 5na and capacitor C 5nb Capacitor C 6n Including capacitor C 6na and capacitor C 6nb Capacitor C 7n Including capacitor C 7na and capacitor C 7nb Capacitor C 8n Including capacitor C 8na and capacitor C 8nb Capacitor C 9n Including capacitor C 9na and capacitor C 9nb Capacitor C 10n Including capacitor C 10na and capacitor C 10nb ; Capacitor C 1na and capacitor C 1nb Capacitor C 2na and capacitor C 2nb Capacitor C 3na and capacitor C 3nb Capacitor C 4na and capacitor C 4nb Capacitor C 5na and capacitor C 5nb Capacitor C 6na and capacitor C 6nb Capacitor C 7na and capacitor C 7nb Capacitor C 8na and capacitor C 8nb Capacitor C 9na and capacitor C 9nb Capacitor C 10na and capacitor C 10nb The upper plates of both capacitors are connected to the inverting input of the comparator; capacitor C 1na and capacitor C 1nb Capacitor C 2na and capacitor C 2nb Capacitor C 3na and capacitor C 3nb Capacitor C 4na and capacitor C 4nb Capacitor C 5na and capacitor C 5nb Capacitor C 6na and capacitor C 6nb Capacitor C 7na and capacitor C 7nb Capacitor C 8na and capacitor C 8nb Capacitor C 9na and capacitor C 9nb Capacitor C 10na and capacitor C 10nb The lower plates are all connected to the reference power supply vref or gnd via selector switch group two.

6. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 5, characterized in that: The VIP terminal of sampling switch one and the VIN terminal of sampling switch two of the capacitor array digital-to-analog converter are connected to the switched capacitor infinite impulse response circuit through switch S6 and switch S4 respectively. The switched-capacitor infinite impulse response circuit includes a gain amplifier. The output of the gain amplifier is connected to switch S6, and the input of the gain amplifier is grounded through switch S5. The input of the gain amplifier is also connected to a capacitor C. d Connect to GND; The output of the switched capacitor infinite impulse response circuit is connected to switch S4 through switch S1, and the connection point between switch S1 and switch S4 is connected to gnd through capacitor C1. The output of the switched capacitor infinite impulse response circuit is also connected to the input of the gain amplifier through switches S2 and S3 connected in series, and the connection node of switches S2 and S3 is grounded through capacitor C2.

7. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 6, characterized in that: Capacitor C1, capacitor C2, capacitor C d The capacitance values ​​are equal, and each is 1 / 30 of the total capacitance value of the single-ended capacitor array digital-to-analog converter.

8. The error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 6, characterized in that: The gain of the gain amplifier is set to 60, and the noise transfer function is: NTF(z)=1-15 / 8z -1 +15 / 16z -2 。 9. A conversion method for an error feedback noise-shaping successive approximation analog-to-digital converter circuit, characterized in that: The conversion is implemented using the error feedback noise shaping successive approximation analog-to-digital converter circuit described in any one of claims 1-8, and the conversion method includes: The timing sequence of the successive approximation analog-to-digital converter includes the Φs sampling phase and the Φc conversion phase; When sampling phase Φs, sampling switch one and sampling switch two are closed and connected to the input signal for sampling; When the phase of Φc is changed, the switching switch of the capacitor array digital-to-analog converter is switched sequentially according to the comparator output; When the comparator output is 1 for the first time, capacitor C 1pa The lower plate is switched to gnd, capacitor C 1pb The lower plate remains connected to gnd, and capacitor C 1nb The lower plate is switched to vref, capacitor C 1na The lower electrode plate remains connected to vref; When the first comparator output is 0, capacitor C 1pa The lower plate remains connected to vref, and capacitor C 1pb The lower plate is switched to vref, capacitor C 1nb The lower plate remains connected to gnd, and capacitor C 1na The lower electrode plate is switched to GND; When the second comparator output is 1, capacitor C 2pa The lower plate is switched to gnd, capacitor C 2pb The lower plate remains connected to gnd, and capacitor C 2nb The lower plate is switched to vref, capacitor C 2na The lower electrode plate remains connected to vref; When the second comparator output is 0, capacitor C 2pa The lower plate remains connected to vref, and capacitor C 2pb The lower plate is switched to vref, capacitor C 2nb3 The lower plate remains connected to gnd, and capacitor C 2na The lower electrode plate is switched to GND; When the third comparator outputs 1, capacitor C 3pa The lower plate is switched to gnd, capacitor C 3pb The lower plate remains connected to gnd, and capacitor C 3nb The lower plate is switched to vref, capacitor C 3na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 3pa The lower plate remains connected to vref, and capacitor C 3pb The lower plate is switched to vref, capacitor C 3nb The lower plate remains connected to gnd, and capacitor C 3na The lower electrode plate is switched to GND; When the fourth comparator output is 1, capacitor C 4pa The lower plate is switched to gnd, capacitor C 4pb The lower plate remains connected to gnd, and capacitor C 4nb The lower plate is switched to vref, capacitor C 4na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 4pa The lower plate remains connected to vref, and capacitor C 4pb The lower plate is switched to vref, capacitor C 4nb The lower plate remains connected to gnd, and capacitor C 4na The lower electrode plate is switched to GND; When the fifth comparator output is 1, capacitor C 5pa The lower plate is switched to gnd, capacitor C 5pb The lower plate remains connected to gnd, and capacitor C 5nb The lower plate is switched to vref, capacitor C 5na The lower electrode plate remains connected to vref; When the fourth comparator output is 0, capacitor C 5pa The lower plate remains connected to vref, and capacitor C 5pb The lower plate is switched to vref, capacitor C 5nb The lower plate remains connected to gnd, and capacitor C 5na The lower electrode plate is switched to GND; When the sixth comparator outputs 1, capacitor C 6p The lower plate is switched to gnd, capacitor C 6n The lower electrode plate remains connected to vref; When the output of the sixth comparator is 0, capacitor C 6p The lower plate remains connected to vref, and capacitor C 6n The lower electrode plate is switched to GND; When the seventh comparator outputs 1, capacitor C 7p The lower plate is switched to gnd, capacitor C 7n The lower electrode plate remains connected to vref; When the output of the seventh comparator is 0, capacitor C 7p The lower plate remains connected to vref, and capacitor C 7n The lower electrode plate is switched to GND; When the eighth comparator output is 1, capacitor C 8p The lower plate is switched to gnd, capacitor C 8n The lower electrode plate remains connected to vref; When the output of the eighth comparator is 0, capacitor C 8p The lower plate remains connected to vref, and capacitor C 8n The lower electrode plate is switched to GND; When the ninth comparator output is 1, capacitor C 9p The lower plate is switched to gnd, capacitor C 9n The lower electrode plate remains connected to vref; When the ninth comparator output is 0, capacitor C 9p The lower plate remains connected to vref, and capacitor C 9n The lower electrode plate is switched to GND; When the tenth comparator output is 1, capacitor C 10p The lower plate is switched to gnd, capacitor C 10n The lower electrode plate remains connected to vref; When the tenth comparator output is 0, capacitor C 10p The lower plate remains connected to vref, and capacitor C 10n The lower electrode plate is switched to GND.

10. The conversion method of the error feedback noise shaping successive approximation analog-to-digital converter circuit according to claim 9, characterized in that: During the reset phase, capacitor C d The upper plate is connected to gnd via a switch, which connects capacitor C. d The stored charge is cleared; in the residual extraction amplification phase, the upper plates of capacitors C1 and C2 are connected to the output of the dynamic amplifier via a switch to obtain the residual voltage from the previous successive approximation conversion and store it in the form of charge; in the delayed phase, the upper plate of capacitor C2 and capacitor C... d The upper plates are connected to each other, and the residual voltage delay of one cycle is achieved through charge sharing; During the error feedback phase, the upper plate of capacitor C1 and capacitor C d The upper plates are connected to the upper plates of the capacitor array digital-to-analog converter, and voltage summation is achieved through charge sharing, thereby realizing the noise shaping function.

Images