Low-offset high-speed reference buffer

Abstract

The invention relates to a low-offset high-speed reference buffer. A reference buffer is disclosed herein. The reference buffer includes an amplifier configured to amplify a difference between a reference output voltage and a reference input voltage during a closed loop phase of the reference buffer. The reference buffer also includes a sampling circuit configured to sample the amplifier output voltage during the closed loop phase. The reference buffer also includes a buffer circuit having a buffer input coupled to the sampling circuit and a buffer output configured to provide a reference output voltage. The reference buffer also includes a first switching circuit and a second switching circuit. The first switching circuit is configured to isolate the sampling circuit from the output stage of the amplifier during an open loop phase of the reference buffer. The second switching circuit is configured to isolate the input stage from the output of the reference buffer during the open loop phase.

Description

Technical Field

[0001] This disclosure generally relates to circuits, and more specifically to a high-speed, low-offset reference buffer. Background Technology

[0002] An analog-to-digital converter (ADC) is a circuit that converts an analog input signal into a digital signal representing the value of the analog signal. One type of ADC is the successive approximation register (SAR) ADC. A reference buffer can be used to provide a reference voltage to the ADC (such as a SAR ADC). The inventors of the embodiments of this disclosure have recognized that reference buffers used for ADCs (such as SAR ADCs) may require fast transient response times but with minimal power consumption. The inventors of the embodiments of this disclosure have also recognized that any systematic or random offset from the reference buffer can be translated into gain error in the ADC. The embodiments of this disclosure address one or more of these challenges. Attached Figure Description

[0003] A more complete understanding of embodiments of the invention can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0004] Figure 1 A schematic diagram of an ADC according to an embodiment of the present disclosure is illustrated.

[0005] Figure 2 A schematic diagram of a reference buffer according to an embodiment of the present disclosure is illustrated.

[0006] Figure 3 A transistor-level schematic diagram of a reference buffer according to an embodiment of the present disclosure is illustrated.

[0007] Figure 4 A transistor-level schematic diagram of a reference buffer according to an embodiment of the present disclosure is illustrated.

[0008] Figure 5 A graph illustrating the waveform within a reference buffer according to an embodiment of the present disclosure is shown.

[0009] Figure 6 A method for buffering a reference voltage according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0010] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the specification, drawings, and claims.

[0011] Figure 1A schematic diagram of an ADC 100 according to an embodiment of the present disclosure is illustrated. The ADC 100 may be implemented in any suitable manner according to the operation described in the present disclosure. In some embodiments, the ADC 100 may include a digital-to-analog converter (DAC) 120, a comparator 130, a successive approximation register (SAR) 140, and a reference buffer 110.

[0012] Reference buffer 110 can receive a reference input voltage VREF_IN. Reference buffer 110 can buffer VREF_IN and provide a reference output voltage VREF_OUT. In some embodiments, VREF_OUT can be equal to the reference input voltage VREF_IN. Reference buffer 110 can be configured to provide a stable reference output voltage VREF_OUT, regardless of varying loads from DAC 120 during the continuous sampling and conversion phases of the conversion process.

[0013] DAC 120 can be configured to receive an input voltage VIN, a buffered reference output voltage VREF_OUT from reference buffer 110, and an N-bit digital feedback signal from SAR 140. DAC 120 can be a capacitive digital-to-analog converter (capacitive DAC) that uses switched-capacitor circuitry to sample the input voltage VIN. For example, DAC 120 may include N switched-capacitor circuits, each corresponding to one of the N bits of SAR 140. Each of the N switched-capacitor circuits may include a capacitor whose capacitance is scaled to its corresponding bit position.

[0014] To generate an N-bit digital output, the ADC 100 can perform a sampling phase and N consecutive conversion steps during the conversion phase. During the sampling phase, the DAC 120 can sample VIN. Subsequently, during each of the N conversion steps, the ADC 100 can determine one bit of the N-bit digital output (and the N-bit digital feedback signal), starting with the most significant bit and ending with the least significant bit. For example, a 4-bit implementation of the ADC 100 can start by setting the 4-bit midpoint value 0111 in the SAR 140. For each bit position with a "1", the capacitor of the corresponding switched capacitor circuit in the DAC 120 can be charged to the value VREF_OUT. For each bit position with a "0", the capacitor of the corresponding switched capacitor circuit in the DAC 120 can be discharged to a negative reference value (such as ground GND). The charge can then be redistributed on the total DAC capacitance, and the DAC 120 can output a differential signal to the comparator 130. Based on the differential output from the DAC 120, the comparator 130 can generate a comparison signal. If the differential output of DAC 120 is positive, the comparator outputs logic -1. And if the differential output of DAC 120 is negative, the comparator outputs logic -0. SAR 140 can be coupled to receive the comparison signal from comparator 130 and provide an N-bit digital feedback signal to DAC 120. For example, SAR 140 can store the output of comparator 130 in the most significant bit position. After determining the most significant bit, SAR 140 can move to the next consecutive bit, thus setting the remaining three bits to the midpoint value 011. The above conversion steps can be repeated until each of the four bits has been determined consecutively, thus completing the conversion phase. After completing the N-bit conversion steps during the conversion phase, the N-bit output signal from SAR 140 can provide a digital representation of the analog VIN signal.

[0015] Although the above example has been described in the context of a 4-bit SAR ADC, the ADC 100 can be implemented using more or fewer bits than 4. The ADC 100 can be implemented as an ADC with, for example, 4 bits, 6 bits, 8 bits, 10 bits, 12 bits, 14 bits or more.

[0016] Figure 2 A schematic diagram of a reference buffer 110 according to an embodiment of the present disclosure is illustrated. The reference buffer 110 may be implemented in any suitable manner according to the operation described in the present disclosure. In some embodiments, the reference buffer 110 may include an amplifier 111, a buffer circuit 112 and a sampling circuit 113, as well as a first switching circuit 116 and a second switching circuit 117.

[0017] Amplifier 111 may be an operational amplifier. Amplifier 111 may have a first input 121 and a second input 122. In some embodiments, the first input 121 may be a negative input of amplifier 111, and the second input 122 may be a positive input of amplifier 111. Amplifier 111 may amplify the difference between its first input 121 and its second input 122 and provide an amplifier output voltage at its amplifier output 123.

[0018] like Figure 2 As shown, the reference buffer 110 may further include a first switching circuit 116 and a second switching circuit 117. In some embodiments, the first switching circuit 116 may include a first switch 126, and the second switching circuit 117 may include a second switch 127. The first switching circuit 116 may be coupled between the amplifier output 123 and the sampling circuit 113, and the buffer circuit 112 may also be coupled to the sampling circuit. The second switching circuit 117 may be coupled between the output of the reference buffer 110 and the first input 121 of the amplifier 111. As described in further detail below, the first switching circuit 116 and the second switching circuit 117 may each be in an open state during the open-loop phase of the reference buffer 110, and may each be in a closed state during the closed-loop phase of the reference buffer 110.

[0019] In some embodiments, sampling circuit 113 may be coupled to first switching circuit 116 at node 118. Sampling circuit 113 may be configured to sample the amplifier output voltage from amplifier 111 during the closed-loop phase of reference buffer 110 and to maintain the sampled voltage level during the open-loop phase of reference buffer 110. For example, sampling circuit 113 may include capacitor 114 coupled between node 118 and ground GND, and may therefore be configured to sample the amplifier output voltage from amplifier 310 during the closed-loop phase of reference buffer 110 and to maintain the sampled voltage level during the open-loop phase of reference buffer 110.

[0020] The buffer circuit 112 may have a buffer input coupled to the sampling circuit 113 at node 118, and a buffer output coupled to drive the output of the reference buffer 110. For example, the buffer circuit 112 may provide a reference output voltage VREF_OUT at its output corresponding to the voltage at its buffer input.

[0021] Reference buffer 110 is capable of operating in alternating first and second phases. The first phase of reference buffer 110 may correspond to the reference described above. Figure 1The sampling phase of the described ADC 100. During the first phase, the "sample" signal can drive the first switching circuit 116 and the second switching circuit 117 to a closed state. When the first switching circuit 116 and the second switching circuit 117 are in the closed state, the reference buffer 110 can operate in a closed loop. Therefore, for the purposes of this disclosure, the first phase of the reference buffer 110 can also be referred to as the closed-loop phase. During the closed-loop phase, the amplifier 111 can amplify the difference between the reference output voltage VREF_OUT and the reference input voltage VREF_IN, and can provide the amplifier output voltage to the sampling circuit 113 and the buffer circuit 112 at node 118. The closed-loop configuration can cause the amplifier 111 and the buffer circuit 112 to bring VREF_OUT to a voltage level equal to VREF_IN (although any difference may exist due to amplifier offset or the non-infinite gain of the amplifier 111).

[0022] The second stage of reference buffer 110 can correspond to the reference above. Figure 1 The conversion phase of the ADC 100 is described. During the second phase, the "sample" signal can be deasserted, and the first switching circuit 116 and the second switching circuit 117 can be driven to the off state. Therefore, the second phase of the reference buffer 110 can also be referred to as the open-loop phase.

[0023] During the open-loop phase, amplifier 111 can be isolated from sampling circuit 113 and buffer circuit 112. For example, second switching circuit 117 can be in the off state and thus isolate the first input 121 of amplifier 111 from the output of reference buffer 110. Therefore, any noise or voltage spikes that may occur during the conversion phase of ADC 100 due to the changing capacitive load at the output of reference buffer 110 can be blocked from entering amplifier 111. Furthermore, first switching circuit 116 can be in the off state and thus isolate sampling circuit 113 at node 118 from amplifier output 123 during the open-loop phase.

[0024] As described above, sampling circuit 113 may include capacitor 114. Capacitor 114 may sample the amplifier output voltage during the closed-loop phase and may maintain the sampled voltage level of the amplifier output voltage during the open-loop phase. Therefore, buffer circuit 112 may continue to output VREF_OUT at a voltage level equal to the voltage level of VREF_IN based on the sampled voltage at node 118 during the open-loop phase.

[0025] In some implementations, the reference buffer 110 may alternate between closed-loop and open-loop phases. For example, the repeated closed-loop phase of the reference buffer 110 may correspond to the repeated sampling phase of the ADC 100, and the repeated open-loop phase of the reference buffer 110 may correspond to the repeated conversion phase of the ADC 100. By alternating between closed-loop operation during the closed-loop phase and open-loop operation during the open-loop phase, the reference buffer 110 can benefit from the accuracy of the closed-loop operation and the high bandwidth of the open-loop operation. For example, during the sampling phase of the ADC 100, the reference buffer 110 will not experience the switched-capacitive load of the DAC 120 incurred during the conversion step of the conversion phase of the ADC 100. Therefore, the closed-loop operation of the reference buffer 110 allows VREF_OUT to stabilize to the correct value at low bandwidth during the sampling phase of the ADC 100. Subsequently, the open-loop operation of the reference buffer 110 provides a high-bandwidth output that can quickly stabilize any transient spikes caused by the switched-capacitive load that occurs during the conversion phase of the ADC 100.

[0026] Figure 3 A transistor-level schematic diagram of a reference buffer 300 according to an embodiment of the present disclosure is illustrated. In some embodiments, the reference buffer 300 may serve as a reference buffer 110 for a SAR ADC (such as the ADC 100 described above). The reference buffer 300 may be implemented in any suitable manner according to the operation described in this disclosure. In some embodiments, the reference buffer 300 may include an amplifier 310, a first switching circuit 350, a second switching circuit 351, a sampling circuit 355, and a buffer circuit 380.

[0027] Amplifier 310 may be an operational amplifier. Amplifier 310 may be implemented in any suitable manner according to the operation described in this disclosure. Amplifier 310 may include an input stage 311 and an output stage 312. Although input stage 311 and output stage 312 are described below as separate stages of amplifier 310, in some embodiments, input stage 311 and output stage 312 may both be formed from a single amplification stage of a single-stage amplifier.

[0028] The input stage 311 of amplifier 310 may include transistors 315 and 316, and current sources 317, 318, and 319. A first input 301 of amplifier 310 may be coupled to the gate of transistor 315, and a second input 302 of amplifier 310 may be coupled to the gate of transistor 316. In some embodiments, the first input 301 may be the negative input of amplifier 310, and the second input 302 may be the positive input of amplifier 310. In some embodiments, transistors 315 and 316 may each be an N-type metal-oxide-semiconductor field-effect transistor (“N-type MOSFET” or “NMOS transistor”). Transistors 315 and 316 may form a differential pair, wherein their respective sources are coupled together at node 303. Transistors 315 and 316 may be biased by current source 317, which may be coupled between node 303 and ground (GND). Furthermore, transistor 315 may have a drain coupled to current source 318 at node 304, and transistor 316 may have a drain coupled to current source 319 at node 305. Current sources 318 and 319 may be configured to supply the same amount of current to each other. For example, in some embodiments, current sources 318 and 319 may be two matched branches of a current mirror circuit configured to output matched currents. The differential pair formed by transistors 315 and 316 may draw different amounts of current from nodes 304 and 305 respectively based on the difference in voltage levels received at the first input 301 and the second input 302. Therefore, different amounts of current can be provided to the output stage 312 of amplifier 310. Specifically, different amounts of current can be provided to transistors 320 and 321 of output stage 312 based on the difference in voltage levels received at the first input 301 and the second input 302.

[0029] Output stage 312 may include transistors 320 and 321, as well as transistors 322 and 323. Transistors 320 and 321 may be configured as cas-source, cas-gate transistors, wherein their respective gates are both driven by a bias voltage VBIAS. In some embodiments, transistors 320 and 321 may each be a P-type metal-oxide-semiconductor field-effect transistor (“P-type MOSFET” or “PMOS transistor”). Transistor 320 may have a source coupled to the drain of transistor 316 at node 305. Similarly, transistor 321 may have a source coupled to the drain of transistor 315 at node 304.

[0030] In some embodiments, transistors 322 and 323 of output stage 312 may be NMOS transistors. Transistors 322 and 323 may be configured as current mirrors. Transistor 322 may have a drain coupled to the drain of transistor 320 at node 306 and a source coupled to ground (GND). Transistor 323 may have a drain coupled to the drain of transistor 321 at node 309 and a source coupled to ground (GND). The gates of transistors 322 and 323 may be coupled together and further coupled to the drain of transistor 322 at node 306. Therefore, output stage 312 of amplifier 310 may provide an amplifier output voltage (which may also be referred to as amplifier output 309 for the purposes of this disclosure) at node 309 based on the difference between the voltage levels received at the first input 301 and the second input 302 of amplifier 310.

[0031] like Figure 3 As shown, the reference buffer 300 may further include a first switching circuit 350 and a second switching circuit 351. The first switching circuit 350 may be coupled to the output stage 312 of the amplifier 310 and to the sampling circuit 355, to which the buffer circuit 380 may also be coupled. The second switching circuit 351 may be coupled to the output of the reference buffer 300 and to the input stage 311 of the amplifier 310. As described in further detail below, the first switching circuit 350 and the second switching circuit 351 may each be in an open state during the open-loop phase of the reference buffer 300 and may each be in a closed state during the closed-loop phase of the reference buffer 300.

[0032] like Figure 3 As shown, sampling circuit 355 may be coupled to first switching circuit 350 at node 352. Sampling circuit 355 may be configured to sample the amplifier output voltage from amplifier 310 during the closed-loop phase of reference buffer 300 and to maintain the sampled voltage level during the open-loop phase of reference buffer 300. For example, sampling circuit 355 may include capacitor 356, which may be coupled between node 352 and ground GND, and thus may sample the amplifier output voltage from amplifier 310 during the closed-loop phase of reference buffer 300 and maintain the sampled voltage level during the open-loop phase of reference buffer 300.

[0033] Buffer circuit 380 may have a buffer input 381 coupled to sampling circuit 355 at node 352, and a buffer output 382 coupled to provide VREF_OUT. Buffer circuit 380 may be implemented in any suitable manner according to the operation described in this disclosure. Buffer circuit 380 may generate and provide a voltage reference output VREF_OUT, the voltage level of which corresponds to the voltage received at its buffer input 381. For example, buffer circuit 380 may generate and provide VREF_OUT at a voltage level that has a constant offset from the sampled voltage received at its buffer input 381. In some embodiments, buffer circuit 380 may include a flip-flop voltage follower. For example, buffer circuit 380 may include transistor 383, transistor 384, and current source 385. Transistors 383 and 384 may be PMOS transistors. Transistor 383 may have a drain coupled to current source 385 at node 388. Current source 385 may be coupled between node 388 and ground GND and may bias transistor 383. Transistor 383 may also have a gate coupled to buffer input 381 and a source coupled to buffer output 382. Furthermore, transistor 384 may include a gate coupled to node 388, a source coupled to VDD, and a drain coupled to the source of transistor 383 at buffer output 382 of buffer circuit 380. Therefore, as... Figure 3 As shown, the transistor 383 of the buffer circuit 380 can operate as a flip-flop voltage follower biased by transistor 384 and current source 385. This flip-flop voltage follower is configured to provide a constant offset from buffer input 381 to buffer output 382 based on the gate-to-source voltage of transistor 383 under the bias of current source 385 and transistor 384.

[0034] The reference buffer 300 can operate in a first stage and a second stage. The first stage of the reference buffer 300 can correspond to the reference described above. Figure 1 The sampling phase of the described ADC 100. During the first phase, the "sample" signal can drive each of the first switching circuit 350 and the second switching circuit 351 into a closed state. When the first switching circuit 350 and the second switching circuit 351 are in the closed state, the reference buffer 300 can operate in a closed loop. Therefore, for the purposes of this disclosure, the first phase of the reference buffer 300 may also be referred to as the closed-loop phase.

[0035] During the closed-loop phase, amplifier 310 can amplify any difference between the reference input voltage VREF_IN and the reference output voltage VREF_OUT received from the output of reference buffer 300 via second switching circuit 351. Amplifier 310 can therefore provide the amplifier output voltage to sampling circuit 355 and buffer circuit 380 at node 352. The output amplifier output voltage can cause buffer circuit 380 to bring VREF_OUT to a voltage equal to VREF_IN (despite any differences due to amplifier offset or the non-infinite gain of amplifier 310).

[0036] The second stage of reference buffer 300 can correspond to the reference above. Figure 1 The conversion phase of the ADC 100 is described. During the second phase, the "sample" signal can be deasserted, and the first switching circuit 350 and the second switching circuit 351 can each be driven to the off state. Therefore, the second phase of the reference buffer 300 can also be referred to as the open-loop phase.

[0037] During the open-loop phase, amplifier 310 can be isolated from sampling circuit 355 and buffer circuit 380. For example, second switch circuit 351 can be in the off state and thus isolate the input stage 311 of amplifier 310 from VREF_OUT at the output of reference buffer 300. Therefore, any noise or voltage spikes that occur during the conversion phase of ADC 100 due to the changing capacitive load at the output of reference buffer 300 can be blocked from entering the negative input 301 of amplifier 310. Furthermore, first switch circuit 350 can also be in the off state during the open-loop phase and thus isolate the buffer input 381 of sampling circuit 355 and buffer circuit 380 from the output stage 312 of amplifier 310.

[0038] As described above, sampling circuit 355 may include capacitor 356. Capacitor 356 may sample the amplifier output voltage from amplifier 310 during the closed-loop phase and may maintain the sampled voltage level of the amplifier output voltage at node 352 during the open-loop phase. Therefore, buffer circuit 380 may continue to output VREF_OUT at a voltage level equal to the voltage level of VREF_IN based on the sampled voltage at node 352 during the open-loop phase.

[0039] In some implementations, the reference buffer 300 may alternate between closed-loop and open-loop phases. The repeated closed-loop phase of the reference buffer 300 may correspond to the repeated sampling phase of the ADC 100, and the repeated open-loop phase of the reference buffer 300 may correspond to the repeated conversion phase of the ADC 100. By alternating between closed-loop operation during the closed-loop phase and open-loop operation during the open-loop phase, the reference buffer 300 benefits from the accuracy of the closed-loop operation and the high bandwidth of the open-loop operation. For example, during the sampling phase of the ADC 100, the reference buffer 300 will not experience the switched-capacitive load of the capacitive DAC incurred during the conversion step of the ADC 100's conversion phase. Therefore, the closed-loop operation of the reference buffer 300 allows VREF_OUT to stabilize to the correct value at low bandwidth during the sampling phase of the ADC 100. Subsequently, the open-loop operation of the reference buffer 300 provides a high-bandwidth output that can quickly stabilize any transient spikes caused by the switched-capacitive load that occurs during the conversion phase of the ADC 100.

[0040] Using different stages for the reference buffer 300 offers several advantages. The open-loop stage of the reference buffer 300 can correspond to a SAR ADC (such as the one mentioned above). Figure 1 The conversion phase of the ADC 100 is described. During this phase, the output of the reference buffer 300 can withstand the switched-capacitive load of a capacitive DAC (such as DAC 120). The open-loop configuration of the reference buffer 300 during this phase provides a high-bandwidth, low-impedance output capable of driving the switched load of the capacitive DAC. For example, the flip-flop voltage follower configuration of the buffer circuit 380 provides a low-impedance output that can quickly respond to the switched-capacitive load at its output. Furthermore, the buffer circuit 380 requires only a small bias current, such as 10 μA, 1 μA, or less, to bias the gate of transistor 384 and the flip-flop voltage follower configuration of transistor 383. Compared to a conventional voltage follower biased only by a current source, the flip-flop voltage follower configuration can require less current to achieve the same bandwidth. The bias current consumed by the reference buffer 300 as a whole can therefore be much less than the bias current originally required to achieve similar high bandwidth using a continuous closed-loop system.

[0041] The closed-loop phase of the reference buffer 300 may correspond to the sampling phase of a SAR ADC (such as ADC 100 described above). During this phase, the output of the reference buffer 300 may not have the same switched-capacitive load as during the conversion phase of the SAR ADC. However, any offset at the input of the amplifier 310 can be translated into a gain error in the SAR ADC in which the reference buffer 300 is implemented. Therefore, the reference buffer 300 may be configured to support low offset rather than high bandwidth during this closed-loop phase. In some embodiments, transistors 315 and 316 may be configured to have large channel width and channel length dimensions to ensure good matching with each other, thereby minimizing the input offset of the amplifier 310. Similarly, transistors 322 and 323 may be configured to have large channel width and channel length dimensions to ensure good matching with each other, thereby minimizing the input offset of the amplifier 310. Additionally, as described above, in some embodiments, current sources 318 and 319 may be two matching branches of a current mirror circuit configured to output matching currents. In some implementations, the transistors forming the matching branches of the current mirror to form current source 318 and current source 319 may have the same large channel width and channel length dimensions to ensure good matching between them.

[0042] Figure 4 A transistor-level schematic diagram of a reference buffer 400 according to an embodiment of the present disclosure is illustrated. Certain components of the reference buffer 400 and amplifier 410 may be similar in some respects to... Figure 3 The corresponding components in the reference buffer 300 and amplifier 310. Therefore, unless otherwise described or illustrated herein, Figure 4 Elements with similar reference numerals in the accompanying drawings can be compared with those described above. Figure 3 The operation is similar to the method described.

[0043] In some embodiments, reference buffer 400 may serve as reference buffer 110 for a SAR ADC (such as ADC 100 described above). Reference buffer 400 may be implemented in any suitable manner according to the operation described in this disclosure. In some embodiments, reference buffer 400 may include amplifier 410, sampling circuitry 440, and buffer circuitry 380.

[0044] Amplifier 410 may be a chopper operational amplifier. Therefore, for the purposes of this disclosure, amplifier 410 may also be referred to as a chopper amplifier. As described in further detail below, amplifier 410 may have a first chopper stage and a second chopper stage that are alternately aligned with the repetitive closed-loop stages of reference buffer 400. During these closed-loop stages, amplifier 410 may amplify the difference between the reference output voltage VREF_OUT and the reference input voltage VREF_IN, and may provide the amplifier output voltage to sampling circuit 440.

[0045] Amplifier 410 may be implemented in any suitable manner according to the operation described in this disclosure. Amplifier 410 may include an input stage 406 and an output stage 407. Although input stage 406 and output stage 407 are described below as separate stages of amplifier 410, in some embodiments, input stage 406 and output stage 407 may both be formed from a single amplification stage of a single-stage amplifier.

[0046] Input stage 406 may include transistors 315 and 316, and current sources 317, 318, and 319. A first input node 401 of amplifier 410 may be coupled to the gate of transistor 315, and a second input node 402 of amplifier 410 may be coupled to the gate of transistor 316. Transistors 315 and 316 may form a differential pair, with their respective sources coupled together at node 403. Transistors 315 and 316 may be biased by current source 317, which may be coupled between node 403 and ground (GND). Furthermore, transistor 315 may have a drain coupled to current source 318 at node 404, and transistor 316 may have a drain coupled to current source 319 at node 405. Current sources 318 and 319 may be configured to supply the same amount of current to each other. For example, in some embodiments, current sources 318 and 319 may be two matched branches of a current mirror circuit configured to output matched currents. The differential pair formed by transistors 315 and 316 can draw different amounts of current from nodes 404 and 405 respectively based on the difference in voltage levels received at the first input node 401 and the second input node 402. Therefore, different amounts of current can be provided to the output stage 407 of amplifier 410. Specifically, different amounts of current can be provided to transistors 320 and 321 of output stage 407 based on the difference in voltage levels received at the first input node 401 and the second input node 402.

[0047] Output stage 407 may include transistors 320 and 321, and transistors 322 and 323. Transistors 320 and 321 may be configured as cascode, with their respective gates driven by a bias voltage VBIAS. Transistor 320 may have a source coupled to the drain of transistor 316 at node 405. Transistor 321 may similarly have a source coupled to the drain of transistor 315 at node 404. Transistor 322 may have a drain coupled to the drain of transistor 320 and a source coupled to ground (GND). Transistor 323 may have a drain coupled to the drain of transistor 321 and a source coupled to ground (GND). As described in further detail below, the output polarity of output stage 407 may be alternated using a first switching circuit 425 formed by switches 420, 421, 422, and 423. During a chopping phase, the gates of transistors 322 and 323 can be coupled to the drain of one of transistors 322 and 323 to form a current mirror, and the drain of the other of transistors 322 and 323 can be coupled to the amplifier output 409. Therefore, the output stage 407 of amplifier 410 can provide an amplifier output voltage at amplifier output 409 based on the difference between the voltage levels received at the first input node 401 and the second input node 402 of amplifier 410.

[0048] In addition to the transistors and current sources mentioned above, amplifier 410 may also include various switching circuits and switches to provide a chopping function that alternates the polarity of the internal circuitry of amplifier 410. For example, such as Figure 4 As shown, amplifier 410 may include a first switching circuit 425 and a second switching circuit 415.

[0049] In some embodiments, the first switching circuit 425 may have a first plurality of switches, including switches 420, 421, 422, and 423, which may be coupled to the output stage 407 of the amplifier 410 and may be configured to alternate the output polarity of the output stage 407 based on a first chopping phase and a second chopping phase. For example, switches 420 and 421 may be driven by a first chopping signal S1 during the first chopping phase. When S1 is asserted to drive switches 420 and 421 to a closed state during the first chopping phase, switch 420 may couple the gate of transistors 322 and 323 to the drain of transistor 322, and switch 421 may couple the drain of transistor 323 to the amplifier output 409. Conversely, switches 422 and 423 may be driven by a second chopping signal S2 during the second chopping phase. When S2 is asserted to drive switches 422 and 423 to a closed state during the second chopping phase, switch 422 can couple the gates of transistors 322 and 323 to the drain of transistor 323, and switch 423 can couple the drain of transistor 322 to amplifier output 409. Therefore, the output polarity of output stage 407 (and particularly the polarity of the current mirror formed by transistors 322 and 323) can be alternated by alternating the first chopping signal S1 and the second chopping signal S2 during the corresponding first and second chopping phases.

[0050] To ensure that the input polarity of the input stage 406 of amplifier 410 matches the alternating output polarity of the output stage 407, amplifier 410 may further include a second switching circuit 415 coupled to the input stage 406 of amplifier 410. For example, the second switching circuit 415 may have a second plurality of switches, including switches 411, 412, 413, and 414, which are coupled to the input stage 406 of amplifier 410 and configured to alternate the input polarity of the input stage 406 based on a first chopping stage and a second chopping stage.

[0051] In some implementations, switches 411 and 412 may be driven by a first chopping signal S1 during a first chopping phase. When S1 is asserted to drive switches 411 and 412 to a closed state during the first chopping phase, switch 411 may couple a first input 301 to the gate of transistor 315 at a first input node 401, and switch 412 may couple a second input 302 to the gate of transistor 316 at a second input node 402. Conversely, switches 413 and 414 may be driven by a second chopping signal S2 during a second chopping phase. When S2 is asserted to drive switches 413 and 414 to a closed state during the second chopping phase, switch 413 may couple a first input 301 to the gate of transistor 316 at a second input node 402, and switch 414 may couple a second input 302 to the gate of transistor 315 at a first input node 401. Therefore, the polarity of the differential pair formed by transistors 315 and 316 can be alternated by alternating the first chopping signal S1 and the second chopping signal S2 during the corresponding first chopping phase and second chopping phase.

[0052] In summary, amplifier 410 may have a first chopping stage and a second chopping stage that can be alternately aligned with the repetitive closed-loop stages of reference buffer 400. When one of S1 and S2 is asserted, the input stage 406 of amplifier 410 may be coupled by the second switching circuit 415 to receive VREF_OUT and VREF_IN. Similarly, the output stage 407 of amplifier 410 may be coupled to sampling circuit 440 by the first switching circuit 425. Therefore, reference buffer 400 can operate in the closed loop when one of S1 and S2 is asserted. Furthermore, when one of S1 and S2 is asserted during the closed-loop stage, amplifier 410 may amplify the difference between the reference output voltage VREF_OUT and the reference input voltage VREF_IN, and may further provide the amplifier output voltage to sampling circuit 440.

[0053] By alternating the polarities of input stage 406 and output stage 407 during the first and second chopping phases, any offset present in amplifier 410 due to defects in the semiconductor manufacturing process may have a first value during the first chopping phase and a second value during the second chopping phase, wherein the second value has the same magnitude but opposite polarity as the first value. For example, if an offset of +10mV exists in amplifier 410 during the first chopping phase, the alternating polarity of the internal circuitry of amplifier 410 will therefore produce an offset of -10mV during the second chopping phase. As described in further detail below, the output of amplifier 410 may be filtered such that any offset generated during the first chopping phase can be canceled out by an equal and opposite offset generated during the second chopping phase.

[0054] like Figure 4 As shown, sampling circuit 440 may have an input 450 coupled to amplifier output 409 of amplifier 410. Sampling circuit 440 may be implemented in any suitable manner according to the operation described in this disclosure. As described in further detail below, sampling circuit 440 may be configured to sample the amplifier output voltage from amplifier 410 during the closed-loop phase of reference buffer 400, and may provide the sampled voltage level to buffer circuit 380.

[0055] In some implementations, the sampling circuit 440 may be implemented as a switched notch filter comprising multiple switches and multiple capacitors. For example, as Figure 4 As shown, the sampling circuit 440 may include switches 441, 442, 443, and 444, and capacitors 446 and 447. Capacitor 446 may be coupled between node 454 and ground GND. Capacitor 447 may be coupled between node 455 and ground GND. Switches 441 and 442 may be driven by a first sampling signal SN. When SN drives switches 441 and 442 to a closed state, switch 441 may couple input 450 to capacitor 446 at node 454, and switch 442 may couple capacitor 447 to output 451 of sampling circuit 440 at node 455. Conversely, switches 443 and 444 may be driven by a second sampling signal SNN. The second sampling signal SNN may be the inverse of the first sampling signal SN. For example, when SN is at a logic high level, SNN may be at a logic low level. Similarly, when SN is at a logic low level, SNN may be at a logic high level. When the SNN drives switches 443 and 444 to the closed state, switch 443 can couple input 450 to capacitor 447 at node 455, and switch 444 can couple capacitor 446 to output 451 of sampling circuit 440 at node 454. See below for further details. Figure 5 As further described in the timing diagram, capacitors 446 and 447 of sampling circuit 440 can alternate between the following operations: sampling the amplifier output voltage during consecutive first and second chopping phases, and providing the filtered sampled voltage to buffer input 381 of buffer circuit 380.

[0056] like Figure 4As shown, the reference buffer 400 may include a buffer circuit 380. The buffer circuit 380 may have a buffer input 381 coupled to the output 451 of the sampling circuit 355, and a buffer output 382 coupled to provide VREF_OUT. The buffer circuit 380 may be implemented in any suitable manner according to the operation described in this disclosure. The buffer circuit 380 may generate and provide a voltage reference output VREF_OUT, the voltage level of which corresponds to the voltage received at its buffer input 381. For example, the buffer circuit 380 may generate and provide VREF_OUT at a voltage level that has a constant offset from the sampled voltage received at its buffer input 381. In some embodiments, the buffer circuit 380 may include a flip-flop voltage follower. For example, the buffer circuit 380 may include transistor 383, transistor 384, and current source 385. Transistors 383 and 384 may be PMOS transistors. Transistor 383 may have a drain coupled to the current source 385 at node 388. Current source 385 can be coupled between node 388 and ground GND and can bias transistor 383. Transistor 383 may also have a gate coupled to buffer input 381 and a source coupled to buffer output 382. Furthermore, transistor 384 may include a gate coupled to node 388, a source coupled to VDD, and a drain coupled to the source of transistor 383 at buffer output 382 of buffer circuit 380. Therefore, as... Figure 3 As shown, the transistor 383 of the buffer circuit 380 can operate as a flip-flop voltage follower biased by transistor 384 and current source 385. This flip-flop voltage follower is configured to provide a constant offset from buffer input 381 to buffer output 382 based on the gate-to-source voltage of transistor 383 under the bias of current source 385 and transistor 384.

[0057] Figure 5 A graph illustrating the waveform of the reference buffer 400 according to an embodiment of the present disclosure is shown. A logic high level of the "sample" signal may correspond to the sampling phase of the SAR ADC, and a logic low level of the "sample" signal may correspond to the conversion phase of the SAR ADC.

[0058] like Figure 5As shown, the first and second chopping phases can be interleaved with the separate sampling and conversion phases of the SAR ADC in which the reference buffer 400 can be implemented. For example, during the first sampling phase of the SAR ADC, the first chopping signal S1 corresponding to the first chopping phase can be asserted between times t1 and t2. Subsequently, during the second sampling phase of the SAR ADC, the second chopping signal S2 corresponding to the second chopping phase can be asserted between times t3 and t4. This sequence can be repeated. For example, the first chopping signal S1 can be asserted again between times t5 and t6 during the third sampling phase of the SAR ADC, and the second chopping signal S2 can be asserted again between times t7 and t8 during the fourth sampling phase of the SAR ADC.

[0059] As mentioned above Figure 4 As described, the reference buffer 400 can operate in a closed loop when one of S1 and S2 is asserted. For example, when one of S1 and S2 is asserted, the input stage 406 of the amplifier 410 can be coupled by the second switching circuit 415 to receive VREF_OUT and VREF_IN. Similarly, the output stage 407 of the amplifier 410 can be coupled to the sampling circuit 440 by the first switching circuit 425. Thus, when one of S1 and S2 is asserted, the amplifier 410 can amplify the difference between the reference output voltage VREF_OUT and the reference input voltage VREF_IN, and can further provide the amplifier output voltage to the sampling circuit 440. Therefore, the repetitive chopping phase of the reference buffer 400 during which one of S1 and S2 is asserted can correspond to the repetitive continuous sampling phase of the SAR ADC.

[0060] like Figure 5 As shown, during the conversion phase of the SAR ADC in which the reference buffer 400 can be implemented, neither the first chopper signal S1 nor the second chopper signal S2 may be asserted. For example, during the conversion phase, neither the first chopper signal S1 nor the second chopper signal S2 may be asserted between times t2 and t3, between times t4 and t5, between times t6 and t7, and between times t8 and t9.

[0061] As mentioned above Figure 4As described, the reference buffer 400 can operate in an open-loop manner when neither S1 nor S2 is asserted. For example, when neither S1 nor S2 is asserted, the first switching circuit 425 can isolate the sampling circuit 440 from the output stage 407 of the amplifier 410. Furthermore, when neither S1 nor S2 is asserted, the second switching circuit 415 can isolate the input stage 406 of the amplifier 410 from VREF_OUT at the output of the reference buffer 400. During this open-loop phase of the reference buffer 400, the buffer circuit 380 can continue to provide the reference output voltage VREF_OUT based on the sampled voltage held by the sampling circuit 440. Therefore, the repeated open-loop phase of the reference buffer 400 during which neither S1 nor S2 is asserted can correspond to the repeated continuous conversion phase of the SAR ADC.

[0062] Similarly, Figure 5 As shown, the sampling signals SN and SNN of the switch driving the sampling circuit 440 can be asserted in an alternating manner. In some embodiments, the sampling signals SN and SNN of the switch driving the sampling circuit 440 can be asserted in an alternating manner at a frequency that is one-quarter of the frequency of the "sampling" signal driving the SAR ADC.

[0063] For example, such as Figure 5 As illustrated, the assertion of SN can span from time t1 to time t5, and therefore can cover instances of asserting the first chopping stage of S1 during this period as well as instances of asserting the second chopping stage of S2 during this period. At time t5, SN can be deasserted and SNN can be asserted. The assertion of SNN can span from time t5 to time t9, and therefore can also cover instances of asserting the first chopping stage of S1 during this period as well as instances of asserting the second chopping stage of S2 during this period.

[0064] Return to reference Figure 4 The sampling circuit 440 may include a switched notch filter that samples and filters the amplifier output voltage during the periods of the first and second chopping phases. For example, when asserting SN from time t1 to time t5, capacitor 446 of the sampling circuit 440 may sample the amplifier output voltage during both the first and second chopping phases. (Refer to the above...) Figure 4 As described, in relation to any offset present in amplifier 410 during the first chopping phase when chopping signal S1 is asserted, amplifier 410 may have an equal and opposite offset during the second chopping phase when chopping signal S2 is asserted. Therefore, by sampling the amplifier output voltage from time t1 to time t5, capacitor 446 can filter out the equal and opposite offset of amplifier 410 from both the first and second chopping phases.

[0065] At time t5, SN can be deasserted and SNN can be asserted. The filtered voltage sampled by capacitor 446 can therefore be provided to the buffer input 381 of buffer circuit 380 at time t5. And as described above, buffer circuit 380 can generate and provide a voltage reference output VREF_OUT, the voltage level of which corresponds to the voltage received at its buffer input 381. Furthermore, as with capacitor 446 from time t1 to time t5, when asserting SNN from time t5 to time t9, capacitor 447 of sampling circuit 440 can sample the amplifier output voltage in both the first chopping stage and the second chopping stage. Therefore, when sampling the amplifier output voltage from time t5 to time t9, capacitor 447 can filter out equal and opposite offsets from the first chopping stage and the second chopping stage.

[0066] At time t9, SNN can be deasserted and SN can be asserted again. The filtered voltage sampled by capacitor 447 can therefore be provided to buffer input 381 of buffer circuit 380 at time t9. And as described above, buffer circuit 380 can continue to generate and provide voltage reference output VREF_OUT, the voltage level of which corresponds to the voltage received at its buffer input 381. After time t9, the alternating assertions of SN and SNN can be repeated, and capacitors 446 and 447 of sampling circuit 440 can continue to alternately sample the amplifier output voltage and provide the filtered sampled voltage to buffer circuit 380.

[0067] The interleaving of the chopping phase with the open-loop and closed-loop phases of the reference buffer 400 offers several advantages. The open-loop phase of the reference buffer 400 can correspond to a SAR ADC (such as the one mentioned above). Figure 1 The conversion stages of the ADC 100 are described. During these stages, the output of the reference buffer 400 can withstand the switched-capacitive load of a capacitive DAC (such as DAC 120). The open-loop configuration of the reference buffer 400 during these stages provides a high-bandwidth, low-impedance output capable of driving the switched load of the capacitive DAC. For example, the flip-flop voltage follower configuration of the buffer circuit 380 provides a low-impedance output that can quickly respond to the switched-capacitive load at its output. Furthermore, the buffer circuit 380 requires only a small bias current, such as 10 μA, 1 μA, or less, to bias the gate of transistor 384 and the flip-flop voltage follower configuration of transistor 383. Compared to a conventional voltage follower biased only by a current source, the flip-flop voltage follower configuration can require less current to achieve the same bandwidth. The bias current consumed by the reference buffer 300 as a whole can therefore be much less than the bias current originally required to achieve similar high bandwidth using a continuous closed-loop system.

[0068] The closed-loop phase of the reference buffer 400 may correspond to the sampling phase of a SAR ADC (such as ADC 100 described above). During these phases, the output of the reference buffer 400 may not have the same switched-capacitive load as during the conversion phase of the SAR ADC. However, any offset in the closed loop due to amplifier 410 will translate into a gain error in the SAR ADC in which the reference buffer 400 is implemented. Therefore, the reference buffer 400 may be configured to support low offset rather than high bandwidth during this closed-loop phase. For example, as described above, the reference buffer 400 may utilize alternating chopping phases to eliminate any offset that might otherwise be present in amplifier 410 during the closed-loop phase. Thus, the reference buffer 400 can minimize any gain error to the SAR ADC in which it is implemented.

[0069] Although the reference buffers disclosed herein have been described in the context of SAR ADCs, reference buffers 110, 300, and 400 can also be used in other applications. The advantages of the reference buffers disclosed herein are equally applicable to any system in which a reference signal or other signal can drive a load that may have alternating characteristics (e.g., a load that is stable during a first phase and may vary during a second phase).

[0070] Figure 6 A method for buffering a reference voltage according to an embodiment of this disclosure is illustrated. Method 600 can be performed by any suitable mechanism, such as amplifier 310, sampling circuit 355, and buffer circuit 380 of reference buffer 300, or amplifier 410, sampling circuit 440, and buffer circuit 380 of reference buffer 400, or any suitable combination thereof. Method 600 can be used with... Figure 6 The method can be executed in fewer or more steps. Furthermore, steps in method 600 can be omitted, repeated, executed in parallel, or combined with... Figure 6 The steps shown may be executed in different sequences or recursively. Although one or more steps of method 600 are shown in sequence, they may be executed simultaneously or in a reordered manner.

[0071] At step 602, the difference between the reference input voltage and the reference output voltage of the reference buffer can be amplified during the closed-loop phase of the reference buffer. For example, when S1 is asserted during the first chopping phase or S2 is asserted during the second chopping phase, the input stage 406 of amplifier 410 can be coupled by the second switching circuit 415 to receive VREF_OUT and VREF_IN. Similarly, the output stage 407 of amplifier 410 can be coupled to sampling circuit 440 by the first switching circuit 425. Therefore, the reference buffer 400 can operate in the closed loop when one of S1 and S2 is asserted. Furthermore, when one of S1 and S2 is asserted during the closed-loop phase, amplifier 410 can amplify the difference between the reference output voltage VREF_OUT and the reference input voltage VREF_IN, and can provide the amplifier output voltage to sampling circuit 440.

[0072] At step 604, the amplifier output can be sampled using a sampling circuit during the closed-loop phase. For example, sampling circuit 440 may have an input 450 coupled to amplifier output 409 of amplifier 410. Sampling circuit 440 may sample the amplifier output voltage at amplifier output 409 of amplifier 410 during the first chopping phase and the second chopping phase.

[0073] At step 606, the sampled voltage can be buffered to generate a reference output voltage. For example, the amplifier output voltage sampled and filtered by sampling circuit 440 can be provided to buffer input 381 of buffer circuit 380. Buffer circuit 380 can generate and provide a reference output voltage VREF_OUT, the voltage level of which corresponds to the voltage received at its buffer input 381.

[0074] At step 608, the sampling circuit can be isolated from the amplifier's output stage during the open-loop phase of the reference buffer. For example, as described above... Figure 4 As described, the sampling circuit 440 can be isolated from the output stage 407 of the amplifier 410 during the open-loop phase of the reference buffer 400. For example, the reference buffer can operate in open loop when neither S1 nor S2 is asserted. When neither S1 nor S2 is asserted, each of the switches 420, 421, 422, and 423 of the first switching circuit 425 can be in the off state. Therefore, the first switching circuit 425 can isolate the sampling circuit 440 from the output stage 407 of the amplifier 410 during the open-loop phase of the reference buffer 400.

[0075] At step 610, the input stage of the amplifier can be isolated from the reference output voltage of the reference buffer during the open-loop phase. For example, as described above... Figure 4As described, the input stage 406 of amplifier 410 can be isolated from the reference output voltage VREF_OUT at the output of reference buffer 400 during the open-loop phase. For example, the reference buffer can operate in open loop when neither S1 nor S2 is asserted. When neither S1 nor S2 is asserted, each of switches 411, 412, 413, and 414 of the second switching circuit 415 can be in the off state. Therefore, the second switching circuit 415 can isolate the input stage 406 of amplifier 410 from the reference output voltage VREF_OUT at the output of reference buffer 400 during the open-loop phase.

[0076] At step 612, the amplifier may alternate between a first chopping phase and a second chopping phase. For example, amplifier 410 may be a chopper amplifier having a first chopping phase and a second chopping phase. The first chopping signal S1 may be asserted during the first chopping phase, and the second chopping signal S2 may be asserted during the second chopping phase. Figure 5 As shown, amplifier 410 can alternate between a first chopping stage asserted in S1 and a second chopping stage asserted in S2 during each successive closed-loop phase of reference buffer 400. Therefore, after reference buffer 400 cycles through closed-loop phases and corresponding open-loop phases, amplifier 410 can alternate from one of the first chopping stage and the second chopping stage to the other. Method 600 can then return to step 602, and the cycle of closed-loop and open-loop phases of reference buffer 400 can be repeated.

[0077] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The above description of various embodiments exemplifies the principles of the invention. Based on the foregoing disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to cover all such variations and modifications.

Claims

1. A reference buffer, the reference buffer comprising: An amplifier configured to amplify the difference between a reference output voltage and a reference input voltage during the closed-loop phase of the reference buffer; A sampling circuit configured to sample the amplifier output voltage during the closed-loop phase; A buffer circuit having a buffer input and a buffer output, the buffer input being coupled to the sampling circuit, and the buffer output being configured to provide the reference output voltage to the output of the reference buffer; A first switching circuit, coupled to the output stage of the amplifier and the sampling circuit, is configured to isolate the sampling circuit from the output stage of the amplifier during the open-loop phase of the reference buffer. and A second switching circuit, coupled to the output of the reference buffer and the input stage of the amplifier, is configured to isolate the input stage from the output of the reference buffer during the open-loop phase.

2. The reference buffer of claim 1, wherein the reference buffer is configured to repeatedly alternate between the closed-loop phase and the open-loop phase.

3. The reference buffer of claim 2, wherein the amplifier is a chopper amplifier having a first chopper stage and a second chopper stage, the first chopper stage and the second chopper stage being alternately aligned with a repeating closed-loop stage of the reference buffer.

4. The reference buffer according to claim 3, wherein: The first switching circuit includes a first plurality of switches coupled to the output stage of the amplifier and configured to alternate the output polarity of the output stage of the amplifier based on the first chopping stage and the second chopping stage; and The second switching circuit includes a second plurality of switches coupled to the input stage of the amplifier and configured to alternate the input polarity of the input stage of the amplifier based on the first chopping stage and the second chopping stage.

5. The reference buffer of claim 3, wherein the sampling circuit includes a switched notch filter, the switched notch filter including a plurality of capacitors.

6. The reference buffer of claim 1, wherein the sampling circuit includes a capacitor configured to sample the amplifier output voltage during the closed-loop phase and maintain the sampled voltage level during the open-loop phase.

7. The reference buffer of claim 1, wherein the buffer circuitry includes a flip-flop voltage follower.

8. An analog-to-digital converter (ADC), the ADC comprising: A capacitive digital-to-analog converter (DAC) configured to receive an input voltage and a digital feedback signal; A comparator, coupled to the DAC and configured to generate a comparison signal based on the DAC output; A successive approximation register (SAR) is coupled to receive the comparison signal and provide the digital feedback signal to the capacitive DAC. and A reference buffer, configured to receive a reference input voltage and provide a reference output voltage to the capacitive DAC, the reference buffer comprising: An amplifier configured to amplify the difference between the reference output voltage and the reference input voltage during the closed-loop phase of the reference buffer; A sampling circuit configured to sample the amplifier output voltage during the closed-loop phase; A buffer circuit having a buffer input and a buffer output, the buffer input being coupled to the sampling circuit, and the buffer output being configured to provide the reference output voltage to the output of the reference buffer; A first switching circuit, coupled to the output stage of the amplifier and the sampling circuit, is configured to isolate the sampling circuit from the output stage of the amplifier during the open-loop phase of the reference buffer; and A second switching circuit, coupled to the output of the reference buffer and the input stage of the amplifier, is configured to isolate the input stage from the output of the reference buffer during the open-loop phase.

9. The ADC of claim 8, wherein the reference buffer is configured to repeatedly alternate between the closed-loop phase and the open-loop phase, wherein the repeated closed-loop phase corresponds to a repeated sampling phase of the ADC, and the repeated open-loop phase corresponds to a repeated conversion phase of the ADC.

10. The ADC of claim 9, wherein the amplifier is a chopper amplifier having a first chopper stage and a second chopper stage, the first chopper stage and the second chopper stage being alternately aligned with a repetitive closed-loop stage of the reference buffer.

11. The ADC of claim 10, wherein: The first switching circuit includes a first plurality of switches coupled to the output stage of the amplifier and configured to alternate the output polarity of the output stage of the amplifier based on the first chopping stage and the second chopping stage; and The second switching circuit includes a second plurality of switches coupled to the input stage of the amplifier and configured to alternate the input polarity of the input stage of the amplifier based on the first chopping stage and the second chopping stage.

12. The ADC of claim 10, wherein the sampling circuit includes a switched notch filter, the switched notch filter including a plurality of capacitors.

13. The ADC of claim 8, wherein the sampling circuitry includes a capacitor configured to sample the amplifier output voltage during the closed-loop phase and maintain the sampled voltage level during the open-loop phase.

14. The ADC of claim 8, wherein the buffer circuit includes a flip-flop voltage follower.

15. A method for buffering a reference voltage, the method comprising: The difference between the reference input voltage and the reference output voltage of the reference buffer is amplified during the closed-loop phase of the reference buffer. During the closed-loop phase, the amplifier output is sampled using a sampling circuit; The sampled voltage is buffered to generate the reference output voltage; The sampling circuit is isolated from the output stage of the amplifier during the open-loop phase of the reference buffer; as well as During the open-loop phase, the input stage of the amplifier is isolated from the reference output voltage of the reference buffer.

16. The method of claim 15, further comprising alternating between repeated closed-loop phases and repeated open-loop phases.

17. The method of claim 15, further comprising alternating the amplifier between a first chopping stage and a second chopping stage.

18. The method of claim 17, wherein the first chopping stage and the second chopping stage are aligned alternately with the repeating closed-loop stage of the reference buffer.

19. The method of claim 17, further comprising: The input polarity of the input stage of the amplifier is alternated based on the first chopping stage and the second chopping stage; as well as The output polarity of the amplifier's output stage is alternated based on the first chopping stage and the second chopping stage.

20. The method of claim 17, further comprising filtering the output of the amplifier using a switched notch filter.

Images