Memory devices, systems and methods of forming the same

Abstract

A memory device includes: a stack structure including staggered conductive layers and dielectric layers extending in a first direction; a semiconductor layer including a first semiconductor layer in contact with the stacked structure and a second semiconductor layer on the first semiconductor layer; and a channel structure extending in the stack structure along a second direction and in contact with the first semiconductor layer. The semiconductor layer includes a first semiconductor portion extending along the first direction and a second semiconductor portion extending into the channel structure along the second direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor technology, and more specifically, to semiconductor devices and methods of forming semiconductor devices. BACKGROUND

[0002] Planar memory cells have been scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and a peripheral circuit for facilitating operation of the memory array. SUMMARY

[0004] Embodiments of memory devices and methods of forming the same are disclosed herein.

[0005] In one aspect, a memory device is disclosed. The memory device includes a stack structure including interleaved conductive layers and dielectric layers extending in a first direction; a semiconductor layer including a first semiconductor layer in contact with the stack structure and a second semiconductor layer on the first semiconductor layer; and a channel structure extending in the stack structure along a second direction orthogonal to the first direction and in contact with the first semiconductor layer. The semiconductor layer includes a first semiconductor portion extending along the first direction and a second semiconductor portion extending along the second direction into the channel structure.

[0006] In some embodiments, the conductive layers include at least one source select gate line, and the second semiconductor portion overlaps the at least one source select gate line in the first direction.

[0007] In some embodiments, the channel structure includes a blocking layer, a storage layer, a tunnel layer, a semiconductor channel layer, and a cap layer stacked along the first direction, and the second semiconductor portion is surrounded by at least the blocking layer, the storage layer, and the tunnel layer.

[0008] In some embodiments, the first semiconductor layer is in contact with the semiconductor channel layer and the cap layer.

[0009] In some embodiments, the channel structure further includes a core layer filled in the cap layer, and the first semiconductor layer and the core layer include a same material and are formed in a same process.

[0010] In some embodiments, the second semiconductor portion, the blocking layer, the storage layer, the tunneling layer, and the at least one source select gate line overlap in the first direction.

[0011] In some embodiments, the second semiconductor layer has a first doping concentration at a first end of the second semiconductor portion and a second doping concentration at a second end of the second semiconductor portion opposite the first end in the second direction, and a ratio of the first doping concentration to the second doping concentration is less than 10.

[0012] In some embodiments, the first semiconductor layer has a doping concentration less than 1 x 1010atoms / cm2and the second semiconductor layer has a doping concentration between 1 x 1010atoms / cm2and 1 x 1011atoms / cm2. 18 3 19 3 23 3

[0013] In some embodiments, the semiconductor layer is configured to generate a gate induced drain leakage (GIDL) assisted body bias when performing an erase operation.

[0014] In another aspect, a method of manufacturing a semiconductor device is disclosed. A stack structure extending in a first direction is formed on a substrate, the stack structure including alternating conductive layers and dielectric layers. A channel structure is formed, the channel structure extending in the stack structure along a second direction orthogonal to the first direction. The channel structure includes a blocking layer, a storage layer, a tunneling layer, a semiconductor channel layer, and a cap layer stacked along the first direction. The substrate is removed. Portions of the channel structure are removed to form a recess extending in the second direction in the channel structure. A semiconductor layer is formed, the semiconductor layer including a first semiconductor portion extending along the first direction on the stack structure and a second semiconductor portion extending along the second direction in the recess. A first end of the second semiconductor portion has a first doping concentration and a second end of the second semiconductor portion opposite the first end in the second direction has a second doping concentration, and a ratio of the first doping concentration to the second doping concentration is less than 10.

[0015] In some embodiments, the blocking layer, the storage layer, and the tunneling layer are removed. The semiconductor channel layer and the cap layer are removed, and the channel structure is coplanar with the stack structure. Portions of the cap layer are removed to form the recess extending in the second direction in the channel structure.

[0016] ​​​​​​In some embodiments, a first semiconductor layer is formed in the recess and on a surface of the stack structure, the first semiconductor layer being in contact with the semiconductor channel layer and the cap layer in the recess. A second semiconductor layer is formed on the first semiconductor layer.

[0017] In some embodiments, the first semiconductor layer has a doping concentration less than 1 x 10 18 atoms / cm 3 , and the second semiconductor layer has a doping concentration between 1 x 10 19 atoms / cm 3 and 1 x 10 23 atoms / cm 3 .

[0018] In some embodiments, the first semiconductor layer and the second semiconductor layer have different doping concentrations, and the doping concentration of the second semiconductor layer is higher than the doping concentration of the first semiconductor layer.

[0019] In some embodiments, an activation operation is performed on the second semiconductor layer.

[0020] In some embodiments, a core layer is formed filled in the cap layer, wherein the first semiconductor layer and the core layer comprise a same material and are formed in a same process.

[0021] In some embodiments, a cap dielectric layer is formed on the second semiconductor layer, and a pad-out layer is formed on the cap dielectric layer.

[0022] In some embodiments, the semiconductor layer surrounded by the blocking layer, the storage layer, and the tunnel layer is formed in the recess.

[0023] In some embodiments, the semiconductor layer overlapping the at least one source select gate line in the first direction is formed in the recess.

[0024] In some embodiments, the substrate is removed from the stack structure, and a sacrificial layer of the stack structure is removed.

[0025] In one aspect, a system is disclosed. The system includes a memory device and a memory controller. The memory device includes a stack structure including interleaved conductive layers and dielectric layers extending in a first direction; a semiconductor layer including a first semiconductor layer in contact with the stack structure and a second semiconductor layer on the first semiconductor layer; and a channel structure extending in the stack structure along a second direction orthogonal to the first direction and in contact with the first semiconductor layer. The semiconductor layer includes a first semiconductor portion extending along the first direction and a second semiconductor portion extending along the second direction into the channel structure. The memory controller is coupled to the memory device and configured to control operation of the channel structure. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0027] Figure 1 A schematic view of a cross-section of a memory device is shown in accordance with some embodiments of the present disclosure.

[0028] Figure 2 A schematic circuit diagram of a memory device including a peripheral circuit is shown in accordance with some embodiments of the present disclosure.

[0029] Figure 3 A block diagram of a memory device including an array of memory cells and a peripheral circuit is shown in accordance with some embodiments of the present disclosure.

[0030] Figure 4 A cross-sectional view of an exemplary memory device is shown in accordance with some embodiments of the present disclosure.

[0031] Figure 5 A cross-sectional view of an exemplary memory device is shown in accordance with some embodiments of the present disclosure.

[0032] Figures 6-13 Cross-sectional views of an exemplary memory device at various stages of a fabrication process are shown in accordance with some embodiments of the present disclosure.

[0033] Figure 14 A flowchart of a method for forming an exemplary memory device is shown in accordance with some embodiments of the present disclosure.

[0034] Figure 15 A block diagram of an exemplary system having a memory device is shown in accordance with some embodiments of the present disclosure.

[0035] Figure 16AA diagram illustrating an exemplary memory card having a memory device according to some embodiments of the present disclosure is shown.

[0036] Figure 16B A diagram illustrating an exemplary solid state drive (SSD) having a memory device according to some embodiments of the present disclosure is shown.

[0037] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0038] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of the present disclosure. Moreover, the present disclosure can also be implemented in various other applications, including other microarchitectures and architectures. The functional and structural features described in the present disclosure can be combined, adjusted, and modified with respect to each other and can be combined, adjusted, and modified in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0039] In general, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures, or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, can be understood, at least in part, depending at least in part upon context, either to refer to a singular feature or otherwise to refer to both a singular and plural sense, as appropriate. Additionally, the term “based on” can be understood as not necessarily intended to convey an exclusive set of factors, and instead can allow for existence of additional factors not necessarily expressly described, again, at least in part, depending at least in part on context.

[0040] It should be readily understood that the terms “on,” “over,” and “above,” in the present disclosure are to be interpreted in the broadest possible way, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” not only means the meaning of “over something” or “above something,” but also can include the meaning of “over something” or “above something” without intervening features or layers therebetween (i.e., directly over something).

[0041] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0042] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure, the region having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between and including the top surface and the bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect via contact are formed) and one or more dielectric layers.

[0043] As the demand for higher storage continues to increase, 3D NAND memory devices are employed with an increasing number of tiers (e.g., storage tiers). Memory strings are formed, extending through the storage tiers, creating an array of memory cells. To perform an erase operation on the memory cells, typically holes are injected into the semiconductor channel of the memory string to maintain a positive potential in the memory string. The holes can be generated from a P-well below the memory string. However, the increasing number of tiers in 3D NAND memory devices makes it more difficult to timely and efficiently transfer the holes from the bottom to the top of the semiconductor channel. As a result, fluctuations can occur in the erase operation, and some memory cells cannot be effectively erased. As a remedial measure, a gate-induced-drain-leakage (GIDL) assisted body bias (or GIDL erase operation) has been used to improve erase efficiency and effectiveness. In a typical GIDL erase operation, a bit line and / or a source line electrically connected to the memory string are each applied with a high positive voltage, such that holes are generated from an end of the memory string (e.g., from outside of a drain-select gate (DSG) and / or a source-select gate (SSG)) and injected into the semiconductor channel. However, the doped layer of the plug structure (e.g., n+ poly plug) above or below the word line requires a deeper implant depth, and the holes generated in the erase operation are limited to the thickness of the n+ poly plug.

[0044] To address the above concerns, the present disclosure introduces a plug structure and erase operation scheme for a memory device, particularly a 3D NAND memory device, with improved erase efficiency and effectiveness. By forming an undoped poly layer between the poly plug and the channel poly, the injection direction of band-to-band-tunneling (BTBT) current in the erase operation can include not only a vertical direction, but also a lateral direction that can generate more holes. Furthermore, an activation operation, such as a laser activation operation, is performed to activate the n+ poly plug, which can further prevent the undoped poly layer from being doped. The erase efficiency of the 3D NAND memory device can be improved.

[0045] Figure 1A schematic view of a cross-section of a 3D memory device 100 is shown in accordance with some aspects of the present disclosure. The 3D memory device 100 represents an example of a periphery under cell (PUC) structure. In some implementations, a peripheral circuit 104 can be formed first on a substrate 102, and then a memory cell array 106 can be formed on the peripheral circuit 104. In some implementations, the peripheral circuit 104 can be formed over the substrate 102, and a semiconductor layer, such as a polysilicon layer, can be formed over the peripheral circuit 104. The memory cell array 106 can be formed over the semiconductor layer.

[0046] It should be noted that Figure 1 structures such as periphery over cell, multi-layer stack, or substrateless structures can also be applied to the present application. It should also be noted that in Figure 1 X, Y, and Z axes are added in FIG. 1 to further illustrate the spatial relationship of components of the semiconductor device. The substrate 102 of the 3D memory device 100 includes two lateral surfaces (e.g., top and bottom surfaces) that extend laterally in the X direction and / or the Y direction (lateral direction and / or width direction). As used herein, whether a component (e.g., layer or device) of the semiconductor device is “on,” “over,” or “under” another component (e.g., layer or device) is determined with respect to the substrate 102 of the 3D memory device 100 in the Z direction (vertical direction or thickness direction). The same concept for describing spatial relationship applies throughout the present disclosure.

[0047] In some implementations, the memory cell array 106 includes an array of NAND flash memory cells. For ease of description, an array of NAND flash memory cells can be used as an example to describe the memory cell array 106 in the present disclosure. However, it should be understood that the memory cell array 106 is not limited to an array of NAND flash memory cells, and can include any other suitable type of memory cell array, such as an array of NOR flash memory cells, an array of phase change memory (PCM) cells, an array of resistive memory cells, an array of magnetic memory cells, an array of spin transfer torque (STT) memory cells, etc.

[0048] The array of storage cells 106 can be a NAND flash memory device in which storage cells are provided in the form of an array of 3D NAND storage strings and / or an array of two-dimensional (2D) NAND storage cells. The NAND storage cells can be organized into pages or fingers, which are then organized into blocks, with each NAND storage cell being coupled to a separate line called a bit line (BL). All cells in a NAND storage cell that have the same vertical position can be coupled through a control gate by a word line (WL). In some embodiments, a storage plane contains a certain number of blocks that are coupled by the same bit line. The array of storage cells 106 can include one or more storage planes, and the peripheral circuitry required to perform all read / program (write) / erase operations can be included in the peripheral circuitry 104.

[0049] In some embodiments, the array of NAND storage cells is an array of 2D NAND storage cells, in which each storage cell includes a floating gate transistor. According to some embodiments, the array of 2D NAND storage cells includes a plurality of 2D NAND storage strings, each 2D NAND storage string including a plurality of storage cells connected in series (similar to a NAND gate) and two select transistors. According to some embodiments, each 2D NAND storage string is arranged in the same plane (e.g., referred to herein as a flat two-dimensional (2D) surface, as distinguished from the term “storage plane” in the present disclosure) on a substrate. In some embodiments, the array of NAND storage cells is an array of 3D NAND storage strings, in which each storage string extends vertically (in 3D) above a substrate through a stacked structure (e.g., a storage stack). Depending on the 3D NAND technology (e.g., the number of layers / tiers in the storage stack), a 3D NAND storage string typically includes a certain number of NAND storage cells, each NAND storage cell including a floating gate transistor or a charge-trapping transistor.

[0050] As Figure 1As shown, the 3D memory device 100 may include peripheral circuitry 104 of a memory cell array 106. Peripheral circuitry 104 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry to facilitate the operation of the memory cell array 106. For example, peripheral circuitry 104 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 104 may be implemented using CMOS technology, which can be implemented using logic processes at any suitable technology node.

[0051] Figure 2 A schematic circuit diagram of a memory device 200 including peripheral circuitry according to some aspects of the present disclosure is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. A 3D memory device 100 may be an example of the memory device 200, wherein the memory cell array 201 and at least the peripheral circuitry 202 may be included in peripheral circuitry 104.

[0052] The memory cell array 201 may be a NAND flash memory cell array, wherein the memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 on a substrate ( Figure 2 (Not shown in the image) Extending vertically above. In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 that are series-coupled and vertically stacked. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0053] In some implementations, each storage cell 206 is a single-level cell (SLC) with two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range and a second storage state "1" can correspond to a second voltage range. In some implementations, each storage cell 206 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to assume one of three possible program levels by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0054] As shown in Figure 2 each NAND storage string 208 can include a source select gate (SSG) transistor 210 at its source end and a drain select gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and the DSG transistor 212 can be configured to activate a selected NAND storage string 208 (column of the array) during read and program operations. In some implementations, the SSG transistors 210 of the NAND storage strings 208 in the same block 204 are coupled to ground by the same source line (SL) 214 (e.g., a common SL). According to some implementations, the DSG transistor 212 of each NAND storage string 208 is coupled to a respective bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND storage string 208 is configured to be selected or deselected by applying a select voltage (e.g., above a threshold voltage of the DSG transistor 212) or a deselect voltage (e.g., 0 V) to the respective DSG transistor 212 via one or more DSG lines 213 and / or by applying a select voltage (e.g., above a threshold voltage of the SSG transistor 210) or a deselect voltage (e.g., 0 V) to the respective SSG transistor 210 via one or more SSG lines 215.

[0055] As shown in Figure 2As shown, the NAND memory strings 208 can be organized into a plurality of blocks 204, each of which can have a common source line 214. In some embodiments, each block 204 is a basic unit of data for erase operations, e.g., all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 of adjacent NAND memory strings 208 can be coupled by a word line 218, which selects which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is a basic unit of data for program and read operations. The size of one page 220 in bits can correspond to the number of NAND memory strings 208 coupled by a word line 218 in one block 204. Each word line 218 can include a plurality of control gates (gate electrodes) at each memory cell 206 in the corresponding page 220 as well as a gate line that couples the control gates.

[0056] The peripheral circuitry 202 can be coupled to the memory cell array 201 by the bit lines 216, the word lines 218, the source lines 214, the SSG lines 215, and the DSG lines 213. As described above, the peripheral circuitry 202 can include any suitable circuitry for facilitating operation of the memory cell array 201 by applying voltage signals to and sensing voltage signals from each target memory cell 206 via the word lines 218, the source lines 214, the SSG lines 215, and the DSG lines 213 and / or current signals to and from each target memory cell 206 via the bit lines 216. The peripheral circuitry 202 can include various types of peripheral circuitry formed using CMOS technology. For example, Figure 3 Some example peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface (I / F) 316, and a data bus 318. It should be understood that additional peripheral circuitry 202 can also be included in some examples.

[0057] The page buffer 304 can be configured to buffer data read from or programmed to the memory cell array 201 according to control signals of the control logic 312. In one example, the page buffer 304 can store a page of program data (write data) to be programmed into a page 220 of the memory cell array 201. In another example, the page buffer 304 also performs a program verify operation to ensure that the data has been properly programmed into the memory cells 206 coupled to the selected word line 218.

[0058] Row decoders / word line drivers 308 can be configured to be controlled by control logic 312 and select blocks 204 of memory cell array 201 and word lines 218 of select blocks 204. Row decoders / word line drivers 308 can also be configured to drive memory cell array 201. For example, row decoders / word line drivers 308 can use word line voltages generated from voltage generator 310 to drive memory cells 206 coupled to a selected word line 218.

[0059] Column decoders / bit line drivers 306 can be configured to be controlled by control logic 312 and select one or more 3D NAND memory strings 208 by applying bit line voltages generated from voltage generator 310. For example, column decoders / bit line drivers 306 can apply column signals for selecting a set of N bits of data from page buffer 304 to be output in a read operation.

[0060] Control logic 312 can be coupled to each peripheral circuit 202 and configured to control the operation of peripheral circuit 202. Registers 314 can be coupled to control logic 312 and include state registers, command registers, and address registers for storing state information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202.

[0061] Interface 316 can be coupled to control logic 312 and configured to interface memory cell array 201 with a memory controller (not shown). In some embodiments, interface 316 acts as a control buffer to buffer and relay control commands received from a memory controller and / or a host (not shown) to control logic 312 and to buffer and relay state information received from control logic 312 to the memory controller and / or host. Interface 316 can also be coupled to page buffer 304 and column decoders / bit line drivers 306 via data bus 318 and act as an I / O interface and data buffer to buffer and relay program data received from the memory controller and / or host to page buffer 304 and to buffer and relay read data from page buffer 304 to the memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuit 202.

[0062] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) and bit line voltages to be supplied to memory cell array 201. In some embodiments, voltage generator 310 is part of a voltage source that provides various voltage levels to different peripheral circuits 202, as described in detail below. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 310 to, for example, row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than certain levels sufficient to perform memory operations. For example, the voltage supplied to the page buffer circuitry in page buffer 304 and / or the logic circuitry in control logic 312 may be between 1.3V and 5V, such as 3.3V, and the voltage supplied to the drive circuitry in row decoder / word line driver 308 and / or column decoder / bit line driver 306 may be between 5V and 30V.

[0063] Figure 4 A cross-sectional view of an exemplary storage device 400 according to some embodiments of the present disclosure is shown. For example... Figure 4 As shown, the memory device 400 includes a stacked structure comprising interleaved conductive layers 410 and dielectric layers 408 extending in the X direction. In some embodiments, the conductive layer 410 may be a word line, and the dielectric layer 408 may be a silicon oxide layer. In some embodiments, the conductive layer 410 may be a gate structure comprising a gate dielectric layer and a gate conductive layer on the gate dielectric layer. In some embodiments, the gate dielectric layer may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric layer comprises silicon oxide, which is in the form of a gate oxide. The gate conductive layer may comprise any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. In some embodiments, the gate conductive layer may comprise doped polysilicon, which is in the form of a gate polycrystalline layer.

[0064] like Figure 4As shown, the memory device 400 also includes a semiconductor layer including a first semiconductor layer 406 in contact with the stack structure and a second semiconductor layer 404 on the first semiconductor layer 406. In some embodiments, a dielectric layer 402 is formed on the second semiconductor layer 404. In some embodiments, the first semiconductor layer 406 is an undoped polysilicon layer, the second semiconductor layer 404 is an n+ doped polysilicon layer, and the dielectric layer 402 is a silicon oxide layer. A channel structure 460 is formed in the memory device 400, extending in the stack structure along a Z direction orthogonal to the X direction. In some embodiments, the channel structure 460 is in contact with the first semiconductor layer 406.

[0065] The semiconductor layer includes a first semiconductor portion extending along the X direction, including a first portion 406A of the first semiconductor layer 406 and a first portion 404A of the second semiconductor layer 404. The semiconductor layer also includes a second semiconductor portion extending along the Z direction, including a second portion 406B of the first semiconductor layer 406 and a second portion 404B of the second semiconductor layer 404. In some embodiments, the second portion 404B of the second semiconductor layer 404 has a first doping concentration at a first end A of the second portion 404B of the second semiconductor layer 404 and a second doping concentration at a second end B of the second portion 404B of the second semiconductor layer 404 opposite the first end A in the Z direction. In some embodiments, a ratio of the first doping concentration at the first end A to the second doping concentration at the second end B is less than 20. In other words, an n+ doping concentration at the first end A is less than 20 times an n+ doping concentration at the second end B. In some embodiments, a ratio of the first doping concentration at the first end A to the second doping concentration at the second end B is less than 10. In other words, an n+ doping concentration at the first end A is less than 10 times an n+ doping concentration at the second end B. In some embodiments, a ratio of the first doping concentration at the first end A to the second doping concentration at the second end B is less than 5. In other words, an n+ doping concentration at the first end A is less than 5 times an n+ doping concentration at the second end B.

[0066] In some embodiments, a topmost layer or a bottommost layer of the conductive layer 410 is formed as a source select gate line 462, as shown. Figure 4 In some embodiments, a plurality of topmost layers or a plurality of bottommost layers of the conductive layer 410 are formed as the source select gate line 462. It is noted that a number of layers of the source select gate line 462 is not limited in the present application. In the present application, the number of layers of the source select gate line 462 is at least greater than 1. As shown, Figure 4 The second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 overlap with at least one of the source select gate lines 462 in the X direction.

[0067] like Figure 4 As shown, the channel structure 460 includes a barrier layer 412, a storage layer 414, a tunnel layer 416, a semiconductor channel layer 418, and a cap layer 420 stacked along the X direction. In some embodiments, the channel structure includes a barrier layer 412, a storage layer 414, a tunnel layer 416, a semiconductor channel layer 418, and a cap layer 420 stacked along the radial direction of the channel structure. In some embodiments, the channel structure further includes a core layer 422 filled in the cap layer 420. In some embodiments, the barrier layer 412, the storage layer 414, and the tunnel layer 416 are also referred to as a storage film. In some embodiments, the barrier layer 412 may include silicon oxide, silicon oxynitride, a high-k dielectric material, or any combination thereof. In some embodiments, the storage layer 414 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunnel layer 416 may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage film may be a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0068] In some embodiments, a tunnel layer 416 is located between a semiconductor channel layer 418 and a storage layer 414. The storage layer 414 is also referred to as a charge trapping layer, and the storage or removal of charge in the charge trapping layer determines the switching state of the semiconductor channel. Charge moves between the storage layer 414 and the semiconductor channel layer 418 through the tunneling effect of the tunnel layer 416 to enable / disable the semiconductor channel layer 418, and is then stored and erased via programming. The storage layer 414 can store charge, and the charge can be stored in the storage layer 414 when the memory device is powered off. A barrier layer 412 is located between the storage layer 414 and the gate layer for isolation. When the memory device is powered off, the charge in the storage layer 414 is blocked from moving to the gate layer, thereby preventing data loss.

[0069] like Figure 4As shown, the second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 extend into the channel structure 460. In some embodiments, the second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 are at least surrounded by the blocking layer 412, the storage layer 414, and the tunnel layer 416. In some embodiments, the first semiconductor layer 406 and the semiconductor channel layer 418 are formed of the same material. In some embodiments, the first semiconductor layer 406 and the semiconductor channel layer 418 are formed of polysilicon. In some embodiments, the first semiconductor layer 406 and the core layer 422 are formed of the same material. In some embodiments, the first semiconductor layer 406 and the core layer 422 are formed of polysilicon.

[0070] In some embodiments, the first semiconductor layer 406 is an undoped polysilicon layer, and the second semiconductor layer 404 is an n+ doped polysilicon layer. With two semiconductor layers (one of which is undoped and the other of which is doped), the process of doping the second semiconductor layer 404 can be precisely controlled. In some embodiments, the process of forming the second semiconductor layer 404 (e.g., an n+ doped polysilicon layer) can include using a laser activation operation. In some embodiments, the first semiconductor layer 406 can be an undoped polysilicon layer. In some embodiments, the first semiconductor layer 406 can be a lightly doped polysilicon layer. In some embodiments, the first semiconductor layer 406 can have a doping concentration less than 1 x 1014atoms / cm2, and the second semiconductor layer 404 can have a doping concentration between 1 x 1014atoms / cm2and 1 x 1016atoms / cm2. In some embodiments, the semiconductor layers including the first semiconductor layer 406 and the second semiconductor layer 404 are configured to generate a gate-induced drain leakage (GIDL) assisted body bias when performing an erase operation. 18 3 19 3 23 3 In some embodiments, the semiconductor layers including the first semiconductor layer 406 and the second semiconductor layer 404 are configured to generate a gate-induced drain leakage (GIDL) assisted body bias when performing an erase operation.

[0071] Figure 5 An enlarged cross-sectional view of the memory device 400 is shown, in accordance with some embodiments of the present disclosure. As shown, the second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 extend into the channel structure 460. In some embodiments, the second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 are at least surrounded by the blocking layer 412, the storage layer 414, and the tunnel layer 416. In some embodiments, the first semiconductor layer 406 and the semiconductor channel layer 418 are formed of the same material. In some embodiments, the first semiconductor layer 406 and the semiconductor channel layer 418 are formed of polysilicon. In some embodiments, the first semiconductor layer 406 and the core layer 422 are formed of the same material. In some embodiments, the first semiconductor layer 406 and the core layer 422 are formed of polysilicon. Figure 5 ​​​​​As shown, in some embodiments, the second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 overlap with at least one layer of the source select gate line 462 in the X direction along the line CC’. In some embodiments, the second portion 406B of the first semiconductor layer 406, the second portion 404B of the second semiconductor layer 404, the blocking layer 412, the storage layer 414, the tunnel layer 416, and the semiconductor channel layer 418 together overlap with at least one layer of the source select gate line 462 in the X direction along the line CC’. In other words, when the memory device 400 is cut along the line CC’, the second portion 406B of the first semiconductor layer 406, the second portion 404B of the second semiconductor layer 404, the blocking layer 412, the storage layer 414, the tunnel layer 416, and the semiconductor channel layer 418 all overlap with at least one layer of the source select gate line 462 in the X direction.

[0072] During the erase operation, the injection direction of the BTBT current can include not only the vertical direction D, but also the lateral direction E, as Figure 5 As shown, this can generate more holes. In other words, by forming an undoped poly layer (e.g., the first semiconductor layer 406) between a poly plug (e.g., the second semiconductor layer 404) and a channel poly (e.g., the semiconductor channel layer 418), the injection direction of the BTBT current in the erase operation can include not only the vertical direction D, but also the lateral direction E, which can generate more holes. Furthermore, an activation operation, such as a laser activation operation, is performed to activate the n+ poly plug, such as the second semiconductor layer 404, which can further prevent the undoped poly layer (e.g., the first semiconductor layer 406) from being doped. The erase efficiency of the 3D NAND memory device can be improved.

[0073] Figures 6-13 Cross-sectional views of the memory device 400 at various stages of a fabrication process are shown in accordance with some embodiments of the present disclosure. Figure 14 A flowchart of a method 1400 for forming the memory device 400 in accordance with some embodiments of the present disclosure is shown. For a better appreciation of the present disclosure, the cross-section of the memory device 400 in Figures 6-13 and the method 1400 in Figure 14 will be described together. It should be appreciated that the operations shown in the method 1400 are not exhaustive and that other operations can also be performed before, after, or between any of the operations shown. Furthermore, some operations can be performed concurrently, or in a different order than shown in Figures 6-13 and Figure 14 .

[0074] As shown in Figure 6 and Figure 14As shown in operation 1402, a stacked structure is formed. The stacked structure includes an interlaced conductive layer 410 and a dielectric layer 408 extending in the X direction on a substrate 450. In some embodiments, a sacrificial layer 452 may be formed between the stacked structure and the substrate 450. Figure 6 The structure shown is a flipped structure after a stacked structure has been formed on the substrate 450. Therefore, the substrate 450 is located on... Figure 6 Above the stacked structure. In some embodiments, conductive layer 410 may be a word line, and dielectric layer 408 may be a silicon oxide layer. In some embodiments, conductive layer 410 may be a gate structure including a gate dielectric layer and a gate conductive layer on the gate dielectric layer. In some embodiments, the gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric layer includes silicon oxide, which is in the form of a gate oxide. The gate conductive layer may include any suitable conductive material, such as polysilicon, metal (e.g., W, Cu, Al, etc.), metal compound (e.g., TiN, TaN, etc.), or silicide. In some embodiments, the gate conductive layer may include doped polysilicon, which is in the form of a gate polycrystalline material.

[0075] like Figure 6 and Figure 14 As shown in operation 1404, a channel structure 460 is formed in a stacked structure extending along a Z direction orthogonal to the X direction. In some embodiments, the channel structure 460 includes a barrier layer 412, a storage layer 414, a tunnel layer 416, a semiconductor channel layer 418, and a cap layer 420 stacked along the X direction. In some embodiments, the channel structure includes a barrier layer 412, a storage layer 414, a tunnel layer 416, a semiconductor channel layer 418, and a cap layer 420 stacked along the radial direction of the channel structure. In some embodiments, the barrier layer 412, the storage layer 414, and the tunnel layer 416 are also referred to as a storage film. In some embodiments, the barrier layer 412 may include silicon oxide, silicon oxynitride, a high-k dielectric material, or any combination thereof. In some embodiments, the storage layer 414 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunnel layer 416 may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the storage film may be a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0076] like Figure 7 and Figure 14 As shown in operation 1406, the substrate 450 and sacrificial layer 452 are removed. In some embodiments, the substrate 450 and sacrificial layer 452 can be removed using a wet etching process, a dry etching process, a chemical mechanical polishing (CMP) process, or any suitable removal process. Figure 7As shown, after removing the substrate 450 and the sacrificial layer 452, one end of the channel structure 460 is exposed, for example, the top.

[0077] like Figures 8-10 and Figure 14 As shown in operation 1408, a portion of the channel structure 460 is removed, forming a recess extending in the Z direction within the channel structure 460. For example... Figure 8 As shown, the portion of the storage film (ONO layer) above the stacked structure, including the barrier layer 412, storage layer 414, and tunnel layer 416, can be removed first. In some embodiments, portions of the barrier layer 412, storage layer 414, and tunnel layer 416 can be removed using a wet etching process, a dry etching process, or any suitable removal process.

[0078] Then, as Figure 9 As shown, the semiconductor channel layer 418 and cap layer 420 above the stacked structure are removed. In some embodiments, the semiconductor channel layer 418 and cap layer 420 above the stacked structure can be removed using a CMP process. Figure 10 As shown, a portion of the capping layer 420 is removed to form a recess 454 extending in the Z direction. It should be noted that after forming the recess 454, the top surface of the capping layer 420 is below at least one layer of the source-select gate line 462. In some embodiments, after forming the recess 454, the top surface of the capping layer 420 is below multiple layers of the source-select gate line 462.

[0079] like Figures 11-12 and Figure 14 As shown in operation 1410, a first semiconductor layer 406 and a second semiconductor layer 404 are formed on the stacked structure. Figure 11 As shown, a first semiconductor layer 406 is first formed on the stacked structure and in the recess 454. In some embodiments, the first semiconductor layer 406 is formed in the recess 454, in contact with the semiconductor channel layer 418 and the cap layer 420, and is formed on the surface of the stacked structure. In some embodiments, the first semiconductor layer 406 may also fill the gaps in the cap layer 420. By forming the first semiconductor layer 406 in the recess 454, a portion 406B of the first semiconductor layer extends into the recess 454 along the Z direction, and another portion 406A of the first semiconductor layer 406 extends along the X direction on the stacked structure. In some embodiments, the first semiconductor layer 406 is an undoped polysilicon layer. Then, as... Figure 12As shown, a second semiconductor layer 404 is formed on the first semiconductor layer 406 and fills the recess 454. By forming the second semiconductor layer 404 in the recess 454, a portion 404B of the second semiconductor layer 404 extends into the recess 454 along the Z direction, and another portion 404A of the second semiconductor layer 404 extends along the X direction on the stacked structure.

[0080] Then, a doping operation is performed on the second semiconductor layer 404. In some embodiments, an activation operation is performed on the second semiconductor layer 404 to form an n+ doped polysilicon layer. The semiconductor layer includes a first semiconductor portion extending along the X direction, the first semiconductor portion including a first portion 406A of the first semiconductor layer 406 and a first portion 404A of the second semiconductor layer 404. The semiconductor layer also includes a second semiconductor portion extending along the Z direction, the second semiconductor portion including a second portion 406B of the first semiconductor layer 406 and a second portion 404B of the second semiconductor layer 404. In some embodiments, the second portion 404B of the second semiconductor layer 404 has a first doping concentration at a first end A of the second portion 404B of the second semiconductor layer 404, and a second doping concentration at a second end B of the second portion 404B of the second semiconductor layer 404, opposite to the first end A in the Z direction. In some embodiments, the ratio of the first doping concentration at the first end A to the second doping concentration at the second end B is less than 20. In other words, the n+ doping concentration at the first end A is less than 20 times the n+ doping concentration at the second end B. In some embodiments, the ratio of the first doping concentration at the first terminal A to the second doping concentration at the second terminal B is less than 10. In other words, the n+ doping concentration at the first terminal A is less than 10 times the n+ doping concentration at the second terminal B. In some embodiments, the ratio of the first doping concentration at the first terminal A to the second doping concentration at the second terminal B is less than 5. In other words, the n+ doping concentration at the first terminal A is less than 5 times the n+ doping concentration at the second terminal B.

[0081] In some embodiments, the top or bottom layer of conductive layer 410 is formed as a source-select gate line 462. In some embodiments, multiple top or bottom layers of conductive layer 410 are formed as source-select gate lines 462. It should be noted that the number of source-select gate lines 462 is not limited in this application. In this application, the number of source-select gate lines 462 is at least greater than one. Figure 12 As shown, the second portion 406B of the first semiconductor layer 406 and the second portion 404B of the second semiconductor layer 404 overlap with at least one layer of the source-select gate line 462 in the X direction. Figure 13As shown, a cap dielectric layer, such as the dielectric layer 402, is formed on the second semiconductor layer 404. In some embodiments, a pad-out layer (not shown) can be formed on the cap dielectric layer.

[0082] During the erase operation, the injection direction of the BTBT current can include not only the vertical direction D, but also the lateral direction E, as Figure 5 As shown, this can generate more holes. In other words, by forming an undoped poly layer (e.g., the first semiconductor layer 406) between the poly plug (e.g., the second semiconductor layer 404) and the channel poly (e.g., the semiconductor channel layer 418), the injection direction of the BTBT current in the erase operation can include not only the vertical direction D, but also the lateral direction E, which can generate more holes. Further, an activation operation (e.g., a laser activation operation) is performed to activate the n+ poly plug (e.g., the second semiconductor layer 404), which can further prevent the undoped poly layer (e.g., the first semiconductor layer 406) from being doped. The erase efficiency of the 3D NAND memory device can be improved.

[0083] Figure 15 A block diagram of a system 1500 having a memory device according to some aspects of the present disclosure is shown. The system 1500 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having storage. As Figure 15 As shown, the system 1500 can include a host 1508 and a storage system 1502 having one or more memory devices 1504 and a memory controller 1506. The host 1508 can be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 1508 can be configured to send data to or receive data from the memory device 1504.

[0084] The memory device 1504 can be any memory device disclosed herein, such as the memory device 400. The transistors in the peripheral circuit of the memory device 1504 can include a gate stack having a staircase shape, which can enhance the control of the well region (channel region) of the transistors to improve the body effect of the transistors. As a result, the operating speed of the transistors in the peripheral circuit of the 3D memory device can be further improved.

[0085] According to some embodiments, a memory controller 1506 is coupled to the memory device 1504 and the host 1508 and is configured to control the memory device 1504. The memory controller 1506 can manage data stored in the memory device 1504 and communicate with the host 1508. In some embodiments, the memory controller 1506 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 1506 is designed for operation in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 1506 can be configured to control operations of the memory device 1504, such as read, erase, and program operations. In some embodiments, the memory controller 1506 is configured to control the array of memory cells through the first and second peripheral circuits. The memory controller 1506 can also be configured to manage various functions related to data stored or to be stored in the memory device 1504, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 1506 is also configured to process error correction codes (ECC) related to data read from or written to the memory device 1504. The memory controller 1506 can also perform any other suitable functions, e.g., formatting the memory device 1504. The memory controller 1506 can communicate with external devices (e.g., the host 1508) according to a particular communication protocol.For example, the memory controller 1506 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, and / or the like.

[0086] The memory controller 1506 and the one or more memory devices 1504 can be integrated into various types of storage devices, for example, included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the storage system 1502 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 15A, the memory controller 1506 and a single memory device 1504 can be integrated into a memory card 1602. The memory card 1602 can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and / or the like. The memory card 1602 can also include a memory card connector 1604 that couples the memory card 1602 with a host (e.g., the host 1508 in FIG. 15B). In another example as shown in FIG. 15B, the memory controller 1506 and a plurality of memory devices 1504 can be integrated into an SSD 1606. The SSD 1606 can also include an SSD connector 1608 that couples the SSD 1606 with a host (e.g., the host 1508 in FIG. 15B). In some embodiments, the storage capacity and / or operating speed of the SSD 1606 is greater than that of the memory card 1602. Figure 16A Figure 15 Figure 16B Figure 15

[0087] ​​​​The foregoing description of a specific implementation can be readily modified and / or adapted by those skilled in the art, and therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0088] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A storage device, comprising: A stacked structure comprising interleaved conductive and dielectric layers extending in a first direction; The semiconductor layer includes a first semiconductor layer in contact with the stacked structure and a second semiconductor layer on the first semiconductor layer; as well as The channel structure extends in the stacked structure along a second direction orthogonal to the first direction and contacts the first semiconductor layer. The semiconductor layer includes a first semiconductor portion extending along the first direction and a second semiconductor portion extending along the second direction into the channel structure.

2. The storage device according to claim 1, wherein, The conductive layer includes at least one source-select gate line, and the second semiconductor portion overlaps with the at least one source-select gate line in the first direction.

3. The storage device according to claim 2, wherein, The channel structure includes a barrier layer, a storage layer, a tunnel layer, a semiconductor channel layer, and a cap layer stacked along the first direction, and the second semiconductor portion is at least surrounded by the barrier layer, the storage layer, and the tunnel layer.

4. The storage device according to claim 3, wherein, The first semiconductor layer is in contact with the semiconductor channel layer and the cap layer.

5. The storage device according to claim 3, wherein, The channel structure further includes a core layer filled in the cap layer, and the first semiconductor layer and the core layer comprise the same material and are formed in the same process.

6. The storage device according to claim 3, wherein, The second semiconductor portion, the barrier layer, the storage layer, the tunnel layer, and the at least one source-select gate line overlap in the first direction.

7. The storage device according to claim 1, wherein, The second semiconductor layer has a first doping concentration at a first end of the second semiconductor portion and a second doping concentration at a second end of the second semiconductor portion opposite to the first end in the second direction, and the ratio of the first doping concentration to the second doping concentration is less than 10.

8. The storage device according to claim 7, wherein, The first semiconductor layer has a density of less than 1×10 18 atoms / cm 3 The doping concentration is such that the second semiconductor layer has a doping concentration of 1×10⁻⁶. 19 atoms / cm 3 and 1×10 23 atoms / cm 3 The doping concentration between them.

9. The storage device according to claim 1, wherein, The semiconductor layer is configured to generate a gate-induced drain leakage (GIDL) auxiliary bias when an erase operation is performed.

10. A method for manufacturing a semiconductor device, comprising: A stacked structure is formed on a substrate, the stacked structure comprising interleaved conductive layers and dielectric layers extending in a first direction; A channel structure is formed, the channel structure extending in the stacked structure along a second direction orthogonal to the first direction, the channel structure including a barrier layer, a storage layer, a tunnel layer, a semiconductor channel layer and a cap layer stacked along the first direction; Remove the substrate; Remove a portion of the channel structure to form a recess extending in the second direction within the channel structure; as well as A semiconductor layer is formed, the semiconductor layer comprising a first semiconductor portion extending along the first direction on the stacked structure and a second semiconductor portion extending along the second direction in the recess. Wherein, the first end of the second semiconductor portion has a first doping concentration, and the second end of the second semiconductor portion opposite to the first end in the second direction has a second doping concentration, and the ratio of the first doping concentration to the second doping concentration is less than 10.

11. The method according to claim 10, wherein, Removing the portion of the channel structure to form the recess extending in the second direction in the channel structure includes: Remove the blocking layer, the storage layer, and the tunnel layer; Remove the semiconductor channel layer and the capping layer, wherein the channel structure is coplanar with the stacked structure; and A portion of the cap layer is removed to form the recess extending in the second direction within the channel structure.

12. The method according to claim 10, wherein, Forming the semiconductor layer includes: A first semiconductor layer formed in the recess and on the surface of the stacked structure, the first semiconductor layer contacting the semiconductor channel layer and the capping layer in the recess; and A second semiconductor layer is formed on the first semiconductor layer.

13. The method according to claim 12, wherein, The first semiconductor layer has a density of less than 1×10 18 atoms / cm 3 The doping concentration is such that the second semiconductor layer has a doping concentration of 1×10⁻⁶. 19 atoms / cm 3 and 1×10 23 atoms / cm 3 The doping concentration between them.

14. The method according to claim 12, wherein, The first semiconductor layer and the second semiconductor layer have different doping concentrations, and the doping concentration of the second semiconductor layer is higher than that of the first semiconductor layer.

15. The method of claim 12, further comprising: An activation operation is performed on the second semiconductor layer.

16. The method of claim 12, further comprising: A core layer is formed to fill the cap layer, wherein the first semiconductor layer and the core layer comprise the same material and are formed in the same process.

17. The method of claim 12, further comprising: A cap dielectric layer is formed on the second semiconductor layer; as well as A pad lead-out layer is formed on the cap dielectric layer.

18. The method according to claim 10, wherein, Forming the semiconductor layer in the recess includes: The semiconductor layer, surrounded by the barrier layer, the storage layer, and the tunnel layer, is formed in the recess.

19. The method according to claim 10, wherein, The stacked structure includes at least one source-select gate line extending in the first direction, and forming the semiconductor layer in the recess includes: The semiconductor layer is formed in the recess, overlapping the at least one source-select gate line in the first direction.

20. The method of claim 10, wherein, Removing the substrate includes: Remove the substrate from the stacked structure; and Remove the sacrificial layer from the stacked structure.

21. A system comprising: Storage devices, including: A stacked structure comprising interleaved conductive and dielectric layers extending in a first direction; The semiconductor layer includes a first semiconductor layer in contact with the stacked structure and a second semiconductor layer on the first semiconductor layer; and The channel structure extends in the stacked structure along a second direction orthogonal to the first direction and contacts the first semiconductor layer. Wherein, the semiconductor layer includes a first semiconductor portion extending along the first direction and a second semiconductor portion extending along the second direction into the channel structure; and A memory controller, coupled to the memory device and configured to control the operation of the channel structure.

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