Silicon carbide semiconductor device, power conversion device, and method for manufacturing silicon carbide semiconductor device

Abstract

The purpose of the present invention is, in a silicon carbide semiconductor device, to suppress variations in threshold voltage and to suppress the occurrence of cracks in a barrier metal. A silicon carbide semiconductor device (101) is provided with: a silicon carbide substrate (11); a semiconductor layer (12) formed on the silicon carbide substrate (11); a gate electrode (18) facing the semiconductor layer (12) via a gate insulating film (26); an interlayer insulating film (19) that covers the gate electrode (18); a barrier metal formed on the interlayer insulating film (19); and an upper surface electrode covering a barrier metal, the barrier metal having a two-layer structure comprising a barrier metal (21) and a barrier metal (22), the barrier metal (21) on the interlayer insulating film (19) side comprising the same metal as the barrier metal (22), and having a thickness smaller than that of the barrier metal (22).

Description

[0001] This application is a divisional application of Chinese National Application No. 202111305821.2 (Silicon Carbide Semiconductor Device, Power Conversion Device and Method for Manufacturing Silicon Carbide Semiconductor Device) filed on November 5, 2021, the contents of which are quoted below. Technical Field

[0002] This invention relates to silicon carbide semiconductor devices. Background Technology

[0003] Currently, in silicon carbide semiconductor devices, barrier metals are provided for purposes such as preventing the diffusion of metal materials in the electrodes (e.g., Patent Document 1). From the viewpoint of suppressing changes in the threshold voltage, the thicker the single-layer barrier metal is, the better (e.g., paragraph 0021 of Patent Document 2), and preferably the thickness of the single-layer barrier metal is greater than or equal to 100 nm.

[0004] However, the following problem exists: the thicker the single-layer barrier metal, the more prone it is to cracking in the barrier metal or interlayer insulating film during post-forming processing or electrostatic screening due to the internal stress of the barrier metal. Furthermore, if cracks occur, localized areas become unprotected by the barrier metal, leading to fluctuations in the threshold voltage.

[0005] Furthermore, in Embodiment 5 of Patent Document 2, a two-layer structure consisting of a TiSi layer and a Ti layer is described. However, if the barrier metal is a two-layer structure consisting of different materials, a problem arises: thermal stress caused by the difference in thermal expansion coefficients may be applied between the first and second layers, resulting in cracks.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-182032

[0007] Patent Document 2: Japanese Patent Application Publication No. 2012-129503 Summary of the Invention

[0008] The purpose of this invention is to suppress fluctuations in the threshold voltage and suppress the formation of cracks at the blocking metal in a silicon carbide semiconductor device.

[0009] The silicon carbide semiconductor device of the present invention comprises: a silicon carbide substrate; a semiconductor layer formed on the silicon carbide substrate; a gate electrode facing the semiconductor layer across a gate insulating film; an interlayer insulating film covering the gate electrode; a barrier metal formed on the interlayer insulating film; and an upper surface electrode covering the barrier metal, wherein the barrier metal is a two-layer structure composed of a first barrier metal and a second barrier metal, and the barrier metal on the interlayer insulating film side, namely the first barrier metal, is composed of the same metal as the second barrier metal but has a smaller thickness than the second barrier metal.

[0010] The effects of the invention

[0011] According to the technology of the present invention, in a silicon carbide semiconductor device, it is possible to suppress fluctuations in the threshold voltage and suppress the generation of cracks at the blocking metal. Attached Figure Description

[0012] Figure 1 This is a top view of the silicon carbide semiconductor device according to Embodiment 1.

[0013] Figure 2 This is a cross-sectional view of a unit region of the silicon carbide semiconductor device according to Embodiment 1.

[0014] Figure 3 This is a cross-sectional view of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1.

[0015] Figure 4 This is a flowchart illustrating the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0016] Figure 5 This is a cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0017] Figure 6 This is a cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0018] Figure 7 This is a cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0019] Figure 8 This is a cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0020] Figure 9 This is a cross-sectional view of a silicon carbide semiconductor device.

[0021] Figure 10 This is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 2.

[0022] Figure 11This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device of Embodiment 2.

[0023] Figure 12 This is a cross-sectional view of the silicon carbide semiconductor device of Embodiment 3.

[0024] Figure 13 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device of Embodiment 3.

[0025] Figure 14 This is a flowchart showing the manufacturing process of the silicon carbide semiconductor device of Embodiment 4.

[0026] Figure 15 This is a block diagram showing the structure of the power conversion system of Embodiment 5. Detailed Embodiments

[0027] In this specification, the first conductivity type of the semiconductor is set to n-type, and the second conductivity type is set to p-type. However, the first conductivity type can also be set to p-type, and the second conductivity type can be set to n-type. In addition, notations such as n - type and n-type indicate that the n-type impurity concentration increases in the order of the description. That is, compared with n - type, the n-type impurity concentration of n-type is higher. For notations such as p - type and p-type, this relationship of impurity concentration also applies to the p-type impurity concentration.

[0028] <A. Embodiment 1>

[0029] <A-1. Structure>

[0030] <A-1-1. Planar Structure>

[0031] Figure 1 This is a top view of the silicon carbide semiconductor device 101 of Embodiment 1. As Figure 1 shown, the silicon carbide semiconductor device 101 is configured to include a cell region 1, an end region 2, and a pad region 3. In addition, Figure 1 the top view shown is applicable not only to the silicon carbide semiconductor device 101 of Embodiment 1 but also to the semiconductor devices of other embodiments and the semiconductor devices of the comparative examples described later.

[0032] In the following description, the silicon carbide semiconductor device 101 is described as a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0033] The cell region 1 is an area where a semiconductor element structure is formed and operates as a semiconductor element. In the case where the silicon carbide semiconductor device 101 is a MOSFET, a MOSFET structure is formed in the cell region 1 and operates as a MOSFET.

[0034] The terminal region 2 is provided to surround the cell region 1 and the pad region 3 and is responsible for maintaining the breakdown voltage of the silicon carbide semiconductor device 101.

[0035] The pad region 3 is an area where the control pad 4 for controlling the silicon carbide semiconductor device 101 is provided and is adjacent to the cell region 1. In addition, the combination of the cell region 1 and the pad region 3 is also referred to as the element region.

[0036] The control pad 4 is, for example, a current sensing pad 4a or a gate pad 4b. The current sensing pad 4a is a control pad for detecting the current flowing in the cell region 1. The current sensing pad 4a is electrically connected to a part of the cell region 1, so that when a current flows in the cell region 1, a current of one fraction to one ten-thousandth of the current flowing through the entire cell region 1 flows through the current sensing pad 4a. The current sensing pad 4a can be provided with multiple ones as shown in Figure 1 or can be provided with only one. The current sensing pad 4a is also referred to as a sensing cell region. On the other hand, the gate pad 4b is connected to the gate electrode of the cell region 1 and controls the current flowing in the cell region 1. The region where the gate pad 4b is formed is also referred to as the gate pad region.

[0037] <A-1-2. Cross-sectional structure>

[0038] Figure 2 and Figure 3 are cross-sectional views of the silicon carbide semiconductor device 101. Figure 2 is Figure 1 a cross-sectional view of the cell region 1 at the A-A line of. In addition, Figure 1 the cross-sectional view of the current sensing pad 4a at the B-B line of is also the same as that shown in Figure 2 That is, the cell region 1 and the current sensing pad 4a have the same cross-sectional structure. Figure 3 is Figure 1 a cross-sectional view of the gate pad region at the C-C line of.

[0039] As shown in Figure 2 the silicon carbide semiconductor device 101 is configured to have a silicon carbide substrate 11, a semiconductor layer 12, a gate insulating film 26, a gate electrode 18, barrier metals 21, 22, a source electrode 23, and a drain electrode 24 in the cell region 1.

[0040] The silicon carbide substrate 11 is n -The type has a first substrate main surface S111 and a second substrate main surface S112 opposite to the first substrate main surface S111.

[0041] A semiconductor layer 12 is disposed on the first substrate main surface S111 of the silicon carbide substrate 11, and has a first semiconductor layer main surface S121 and a second semiconductor layer main surface S122 opposite to the first semiconductor layer main surface S121. The second semiconductor layer main surface S122 is in contact with the first substrate main surface S111 of the silicon carbide substrate 11. The semiconductor layer 12 has n - The epitaxial layer 14, multiple p-type well regions 15, multiple n-type source regions 16, and multiple p+ type contact regions 17.

[0042] The epitaxial layer 14 is disposed on the first substrate main surface S111 of the silicon carbide substrate 11.

[0043] Multiple well regions 15 are selectively formed on the surface of the first semiconductor layer main surface S121 of the epitaxial layer 14.

[0044] Each source region 16 is selectively formed on the surface layer of the first semiconductor layer main surface S121 of each well region 15.

[0045] Each contact region 17 is selectively formed adjacent to each source region 16 on the surface layer of the first semiconductor layer main surface S121 of each well region 15. Alternatively, the contact region 17 may not be present in the silicon carbide semiconductor device 101.

[0046] The surface of the well region 15 is sandwiched between the source region 16 and the epitaxial layer 14, functioning as a channel region. A gate insulating film 26 is formed over this channel region.

[0047] A gate electrode 18 is formed on the gate insulating film 26. The gate electrode 18 is opposite to the channel region of the well region 15 across the gate insulating film 26.

[0048] The interlayer insulating film 19 is formed in a manner that covers the gate electrode 18. The interlayer insulating film 19 is a thermally oxidized film. Contact holes 19h are formed in the interlayer insulating film 19 to expose the source region 16 and the contact region 17.

[0049] A barrier metal 21 is formed within the contact hole 19h and on the interlayer insulating film 19. The barrier metal 21 contacts the source region 16 and the contact region 17 in the contact hole 19h.

[0050] A barrier metal 22 is formed on the barrier metal 21. That is, the silicon carbide semiconductor device 101 has two layers of barrier metals, namely, a lower barrier metal 21 and an upper barrier metal 22. The barrier metal 21 is also referred to as the first barrier metal, and the barrier metal 22 is also referred to as the second barrier metal. The barrier metals 21 and 22 are made of the same metal material. For the barrier metal 21, in order to suppress the variation of the threshold voltage and suppress cracks, the thickness is preferably less than or equal to 100 nm. For the barrier metal 22, in order to suppress the variation of the threshold voltage and suppress cracks, the thickness is preferably larger than the thickness of the barrier metal 21 and less than or equal to 100 nm. The total thickness of the barrier metals 21 and 22 is greater than or equal to 100 nm and less than or equal to 200 nm.

[0051] A source electrode 23 is formed on the barrier metal 22 and is in contact with the source region 16 and the contact region 17 via the barrier metals 21 and 22. The source electrode 23 is an example of an upper surface electrode.

[0052] A drain electrode 24 is formed on the second substrate main surface S112 of the silicon carbide substrate 11. The drain electrode 24 is an example of a lower surface electrode.

[0053] On the other hand, in the gate pad region, as Figure 3 shown, a field oxide film 27 is formed on the upper surface of the well region 15, and the gate electrode 18 extends on the field oxide film 27. In addition, in the gate pad region, the interlayer insulating film 19 is removed to expose the gate electrode 18. On the upper surface of the exposed gate electrode 18, the above-mentioned barrier metals 21 and 22 are formed, and a gate pad 4b is formed thereon. In addition, the source electrode 23 and the gate pad 4b are formed by the same process, but are electrically separated by patterning together with the barrier metals 21 and 22.

[0054] <A-2. Manufacturing process>

[0055] Figure 4 is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 101. In addition, Figures 5 to 8 is a cross-sectional view showing the manufacturing process of the silicon carbide semiconductor device 101. Below, according to Figure 4 the flowchart, refer to Figures 5 to 8 to describe the manufacturing process of the silicon carbide semiconductor device 101. In addition, Figures 5 to 8 is along Figure 1The cross-sectional view corresponding to the AA or BB line is not shown; the gate pad region and end region 2 are not illustrated. The barrier metals 21 and 22 of the gate pad region are formed using the same method as the barrier metals 21 and 22 of the cell region 1 and the current sensing pad 4a. The structure other than the barrier metals 21 and 22 of the gate pad region is manufactured using a known manufacturing method. Furthermore, end region 2 is also fabricated using a known manufacturing method.

[0056] First, prepare the silicon carbide substrate 11 (step S101).

[0057] Next, epitaxial growth is performed on the first substrate main surface S111 of the silicon carbide substrate 11 to form an epitaxial layer 14 (step S102). Here, the concentration of n-type impurities contained in the silicon carbide substrate 11 and the epitaxial layer 14 is appropriately selected according to the breakdown voltage of the semiconductor device being fabricated. Thus, a semiconductor device is obtained... Figure 5 The structure shown.

[0058] Next, ions of p-type and n-type impurities are implanted from the upper surface of the epitaxial layer 14, and the implanted ions are diffused in the epitaxial layer 14 by heat treatment or the like, thereby forming a well region 15, a source region 16, and a contact region 17 in the cell region 1 and the current sensing pad 4a (step S103).

[0059] Specifically, a masking process is performed on the upper surface of the epitaxial layer 14. The masking process involves applying a photoresist and forming openings in designated areas of the photoresist using photolithography. P-type impurities such as boron (B) are implanted into the epitaxial layer 14 through these openings. The p-type impurities are diffused through heat treatment, thereby forming multiple well regions 15. These multiple well regions 15 are selectively formed on the upper surface side of the epitaxial layer 14.

[0060] The formation depth and p-type impurity concentration of the multiple well regions 15 can also be the same. In this case, since the formation of the multiple well regions 15 only requires one ion implantation, the productivity of the silicon carbide semiconductor device 101 is improved. In addition, since the depth of the multiple well regions 15 is the same, the electric field concentration can be mitigated, thereby suppressing the decrease in breakdown voltage. Furthermore, the formation depth and p-type impurity concentration of the multiple well regions 15 can also be different by performing multiple ion implantations.

[0061] Next, a masking process is applied to the upper surface of the epitaxial layer 14 and the well region 15, and an n-type impurity is implanted into the well region 15 through the openings in the resist. The implanted n-type impurity is, for example, arsenic (As) or phosphorus (P). Then, the n-type impurity is diffused within the well region 15 by heat treatment, thereby forming the source region 16. The source region 16 is selectively formed on the surface of the well region 15.

[0062] Next, a masking process is performed on the upper surface of the epitaxial layer 14, and p-type impurities such as boron are implanted into the well region 15 through the openings in the resist. Then, the p-type impurities are diffused through heat treatment, thereby forming a p+ type contact region 17. The contact region 17 is selectively formed on the surface layer of the well region 15 adjacent to the source region 16. Thus, a semiconductor layer 12 comprising the epitaxial layer 14, the well region 15, the source region 16, and the contact region 17 is formed, resulting in... Figure 6 The structure shown.

[0063] Next, a gate insulating film 26, a gate electrode 18, and an interlayer insulating film 19 are formed in cell region 1 and current sensing pad 4a (step S104). Specifically, firstly, a gate insulating film 26 made of SiO2 is formed on the upper surface of semiconductor layer 12 by heating the wafer in an oxygen-containing environment. Then, a gate electrode 18 is formed on the gate insulating film 26 by depositing polysilicon doped with n-type or p-type impurities using CVD (Chemical Vapor Deposition) or the like.

[0064] Next, an interlayer insulating film 19 is formed on the gate electrode 18. The interlayer insulating film 19 is, for example, SiO2 or TEOS (Tetraethyl Orthosilicate). Then, by applying a mask to the upper surface of the interlayer insulating film 19, a portion of the interlayer insulating film 19 is etched through openings in the resist, thereby... Figure 7 As shown, a contact hole 19h is formed in the interlayer insulating film 19. The contact hole 19h is formed on the trap region 15 and the contact region 17.

[0065] Next, in unit region 1, a barrier metal 21 is formed within the contact hole 19h of the interlayer insulating film 19 and on the interlayer insulating film 19 (step S105). The barrier metal 21 is formed by forming a titanium (Ti) film using PVD (Physical Vapor Deposition) or CVD.

[0066] After the barrier metal 21 is formed, titanium (Ti) is continuously deposited using PVD (Physical Vapor Deposition) or CVD without exposing the wafer to the atmosphere. Thus, in cell region 1, barrier metal 22 is formed on top of barrier metal 21 (step S106). Here, barrier metal 22 is formed to be thicker than barrier metal 21. This yields... Figure 8 The structure shown.

[0067] Next, a source electrode 23 is formed over the barrier metal 22 (step S107). The source electrode 23 is formed, for example, by depositing an aluminum-silicon alloy (Al-Si based alloy) over the barrier metal 22 by PVD such as sputtering or evaporation. Alternatively, a nickel alloy (Ni alloy) may be further formed over the aluminum-silicon alloy by electroless plating or electroplating, and the aluminum-silicon alloy and the nickel alloy are combined as the source electrode 23. According to the plating process, a thick metal film can be easily formed as the source electrode 23. Therefore, the heat capacity of the source electrode 23 increases and the heat resistance improves. The formation of the nickel alloy by the above plating process may also be performed after forming a drain electrode 24 described later.

[0068] Next, a drain electrode 24 is formed over the second substrate main surface S112 of the silicon carbide substrate 11. The drain electrode 24 is formed to straddle the cell region 1 and the terminal region 2. The drain electrode 24 is formed, for example, by depositing an aluminum-silicon alloy or titanium by PVD such as sputtering or evaporation. Alternatively, the drain electrode 24 may be formed by laminating a plurality of metals such as an aluminum-silicon alloy, titanium, nickel, or gold. Alternatively, a metal film may be further formed by electroless plating or electroplating over the metal film formed by PVD, and the metal film formed by PVD and the metal film formed by the plating process are combined as the drain electrode 24. Thereby, the Figure 2 structure shown is obtained.

[0069] The silicon carbide semiconductor device 101 is manufactured in a matrix form on one n-type wafer. Therefore, one wafer is diced into individual silicon carbide semiconductor devices 101 by laser dicing or blade dicing, thereby completing the silicon carbide semiconductor device 101.

[0070] <A-3. Modified Example>

[0071] In the above, the metal materials of the barrier metals 21 and 22 are described as Ti. However, as long as the metal materials of the barrier metals 21 and 22 are the same, it is not limited to Ti, and the same effect can be obtained even with TiN or TiSi. When the metal materials of the barrier metals 21 and 22 are TiN, the barrier metal 21 is formed by heat treatment in an N2 environment after forming a film of titanium (Ti) by PVD (Physical Vapor Deposition) or CVD. The annealing temperature is 500 to 1100 °C and the time is about 1 hour. A natural oxide film may also be formed over the TiN. Thereafter, the barrier metal 22 is formed in the same manner as the barrier metal 21.

[0072] [[ID=??]]<A-4. Effects>

[0073] Figure 9 It seems there is a formatting issue with the tag [[ID=??]] which should probably be as per the original text's structure. If this is a mistake in the original text, please correct it for a more accurate translation.This is a cross-sectional view of a silicon carbide semiconductor device 100 having a single layer of barrier metal 20. Regarding the silicon carbide semiconductor device 100, by making the thickness of the barrier metal 20 large, fluctuations in the threshold voltage can be suppressed. However, there is a problem: the thicker the barrier metal 20, the more easily cracks are generated in the barrier metal 20 or the interlayer insulating film 19 due to the influence of internal stress in the barrier metal 20. The causes of cracks in the barrier metal 20 include heat generated during processing steps such as dicing cuts to cut chips from semiconductor wafers, and thermal stress caused by the application of current during screening tests with poor electrical characteristics. Furthermore, if cracks occur, localized areas are created that cannot be protected by the barrier metal 20, thus causing fluctuations in the threshold voltage.

[0074] In contrast, the silicon carbide semiconductor device 101 of Embodiment 1 has two layers of barrier metals 21 and 22. Furthermore, the lower barrier metal 21 is thinner than the upper barrier metal 22. That is, when viewed from above, the silicon carbide semiconductor device 101 is divided into a unit region 1 and a sensing unit region adjacent to the unit region 1. The silicon carbide semiconductor device 101 has: a silicon carbide substrate 11; a semiconductor layer 12 formed on the silicon carbide substrate 11; a gate electrode 18 facing the semiconductor layer 12 across a gate insulating film 26; an interlayer insulating film 19 covering the gate electrode 18; barrier metals formed on the interlayer insulating film 19; and an upper surface electrode covering the barrier metals. The barrier metals are a two-layer structure consisting of barrier metal 21 and barrier metal 22. The barrier metal on the interlayer insulating film 19 side, i.e., barrier metal 21, is made of the same metal as barrier metal 22 and is thinner than barrier metal 22.

[0075] In the manufacturing method of the silicon carbide semiconductor device 101 in Embodiment 1, a silicon carbide substrate 11 is prepared, a semiconductor layer 12 is formed on the silicon carbide substrate 11, a gate electrode 18 is formed opposite to the semiconductor layer 12 through a gate insulating film 26, an interlayer insulating film 19 is formed covering the gate electrode 18, a barrier metal 21 is formed on the interlayer insulating film 19, a barrier metal 22 made of the same metal as the barrier metal 21 but thicker than the barrier metal 21 is formed on the barrier metal 21, and an upper surface electrode covering the barrier metal 22 is formed.

[0076] Therefore, even if a crack occurs in the upper barrier metal 22, the likelihood of a crack occurring in the thinner lower barrier metal 21 is lower than that in the upper barrier metal 22. Thus, even if a crack occurs in the upper barrier metal 22, the lower barrier metal 21 will suppress the crack, inhibiting its propagation into the interlayer insulating film 19, thereby suppressing fluctuations in the threshold voltage.

[0077] In addition, since the metal materials of the barrier metals 21 and 22 are the same, the interatomic bonding of the barrier metals 21 and 22 is stronger than in different cases. Therefore, even if the barrier metal 21 in the first layer is thin, due to its strong bonding with the barrier metal 22 in the second layer, the intrusion of hydrogen ions, which is the cause of threshold voltage variation, into the gate insulating film 26 is further suppressed. In addition, when the metal materials of the barrier metals 21 and 22 are different, the thermal expansion rates between the barrier metals 21 and 22 are different, and thermal stress caused by the difference in thermal expansion coefficients is generated. However, by making the metal materials of the barrier metals 21 and 22 the same, the thermal stress is suppressed.

[0078] As described above, according to the silicon carbide semiconductor device 101, the variation of the threshold voltage and the generation of cracks can be suppressed, and the productivity is improved.

[0079] <B. Embodiment 2>

[0080] <B-1. Structure>

[0081] Figure 10 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device 102 of Embodiment 2. Figure 9 It is a cross-sectional view along Figure 1 the A-A line. The silicon carbide semiconductor device 102 has an oxide film 25 between the lower barrier metal 21 and the upper barrier metal 22 in addition to the structure of the silicon carbide semiconductor device 101 of Embodiment 1. The thickness of the oxide film 25 is extremely small, about around.

[0082] <B-2. Manufacturing Process>

[0083] Figure 11 It is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 102 of Embodiment 2. The manufacturing process of the silicon carbide semiconductor device 102 of Embodiment 2 will be described.

[0084] The processes (steps S101 to step S105) up to the formation of the lower barrier metal 21 are the same as those in Embodiment 1.

[0085] After the lower barrier metal 21 is formed, the wafer is taken out, and an oxide film 25 with a thickness of about is formed by naturally oxidizing the surface of the barrier metal 21 made of Ti (step S105A).

[0086] The subsequent steps S106 and step S107 are the same as those in Embodiment 1.

[0087] <B-3. Effects>

[0088] In addition to the structure of the silicon carbide semiconductor device 101 of Embodiment 1, the silicon carbide semiconductor device 102 has an oxide film 25 between the barrier metals 21 and 22. In the manufacturing method of the silicon carbide semiconductor device 102, the oxide film 25 is formed over the barrier metal 21, and the barrier metal 22 is formed over the barrier metal 21 with the oxide film 25 interposed therebetween. The oxide film 25 prevents cracks generated in the upper barrier metal 22 from reaching the lower barrier metal 21, and suppresses the intrusion of hydrogen ions, which cause threshold voltage variations, into the gate insulating film 26. Therefore, according to the silicon carbide semiconductor device 102 of Embodiment 2, compared with the silicon carbide semiconductor device 101 of Embodiment 1, the variation of the threshold voltage can be further suppressed.

[0089] <C. Embodiment 3>

[0090] <C-1. Structure>

[0091] Figure 12 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device 103 of Embodiment 3. Figure 12 It is a cross-sectional view along Figure 1 the line A-A. In the case of the silicon carbide semiconductor device 101 of Embodiment 1, the lower barrier metal 21 and the upper barrier metal 22 are formed over the entire region of the interlayer insulating film 19. In contrast, the silicon carbide semiconductor device 103 of Embodiment 3 is characterized in that the lower barrier metal 21 is not formed but the upper barrier metal 22 is formed over a partial region of the interlayer insulating film 19, thereby creating a step in the upper barrier metal 22.

[0092] <C-2. Manufacturing Process>

[0093] Figure 13 It is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 103 of Embodiment 3. The manufacturing process of the silicon carbide semiconductor device 103 of Embodiment 3 will be described.

[0094] The processes up to the formation of the lower barrier metal 21 (Steps S101 to Step S105) are the same as those in Embodiment 1. After the lower barrier metal 21 is formed, the barrier metal 21 over a partial region of the interlayer insulating film 19 is removed (Step S105B).

[0095] The removal of the barrier metal 21 is performed, for example, by the following method. That is, a resist pattern is formed over the barrier metal 21 through a photolithography process, and the barrier metal 21 is locally etched. Thereafter, the resist is removed to complete the patterning of the barrier metal 21.

[0096] The subsequent Steps S106 and Step S107 are the same as those in Embodiment 1.

[0097] Further, similar to Embodiment 2, in the case of the silicon carbide semiconductor device 103 of Embodiment 3, an oxide film 25 may be formed between the barrier metals 21 and 22. In this case, step S105A described in Embodiment 2 is performed between step S105B and step S106.

[0098] In Figure 12 a structure is shown in which the lower barrier metal 21 is not formed over a part of the interlayer insulating film 19, but instead of the lower barrier metal 21, the upper barrier metal 22 may not be formed over a part of the interlayer insulating film 19. In this case, the above step S105B is not performed. After forming the upper barrier metal 22 in the same manner as in Embodiment 1, photolithography is performed on the barrier metal 22, and local etching of the barrier metal 22 is performed.

[0099] Above, removal of a part of the barrier metal 21 by photolithography has been described. However, in the case where foreign matter adheres to the lower barrier metal 21 in the manufacturing process, a water washing process may be performed after forming the barrier metal 21 and before forming the barrier metal 22. Since the foreign matter and the barrier metal 21 formed thereon are peeled off from the interlayer insulating film 19 by the water washing process, a part of the barrier metal 21 can be removed without using photolithography.

[0100] <C-3. Effects>

[0101] In the case of the silicon carbide semiconductor device 103 of Embodiment 3, there is a part where the barrier metal 21 is not formed between the interlayer insulating film 19 and the source electrode 23. On the surface of the barrier metal 22, there is a step in the part where the barrier metal 21 is not formed. Thus, by having a step on the surface of the barrier metal 22, stress can be relaxed, and generation of cracks after heat treatment of the barrier metal 22 can be suppressed.

[0102] <D. Embodiment 4>

[0103] <D-1. Structure>

[0104] A top view of the silicon carbide semiconductor device 104 of Embodiment 4 is as Figure 1 shown. In the case of the silicon carbide semiconductor device 104 of Embodiment 4, in the sense unit region, that is, the current sense pad 4a, two-layer barrier metals 21 and 22 similar to those in the unit region 1 are also provided.

[0105] <D-2. Manufacturing Process>

[0106] Figure 14It is a flowchart showing the manufacturing process of the silicon carbide semiconductor device 104 of Embodiment 4. The manufacturing process of the silicon carbide semiconductor device 104 of Embodiment 4 will be described.

[0107] The processes from step S101 to step S106 until the barrier metal 22 on the upper layer of the cell region 1 are the same as those in Embodiment 1. After forming the barrier metal 22 on the upper layer of the cell region 1, in the sense cell region, the lower barrier metal 21 is also formed on the interlayer insulating film 19 and within the contact hole 19h in the same manner as in the cell region 1 (step S106A). Next, the upper barrier metal 22 is formed on the barrier metal 21 in the sense cell region (step S106B). The subsequent step S107 is the same as that in Embodiment 1.

[0108] <D-3. Effects>

[0109] If the threshold voltage is different between the cell region 1 and the sense cell region, accurate current detection cannot be performed in the sense cell region, and thus appropriate overcurrent protection cannot be achieved. However, for the silicon carbide semiconductor device 104 of Embodiment 4, the sense cell region also has two layers of barrier metals 21 and 22 made of the same metal. That is, for the silicon carbide semiconductor device 104 of Embodiment 4, the barrier metals 21 and 22 are formed between the interlayer insulating film 19 and the source electrode 23 in the sense cell region. Thereby, the threshold voltage can be made consistent between the sense cell region and the cell region 1, and accurate current detection can be performed.

[0110] The film thickness and material of the barrier metals 21 and 22 may also be different between the sense cell region and the cell region 1. However, if the film thickness and material of the barrier metals 21 and 22 are the same between the sense cell region and the cell region 1, the barrier metals of the sense cell region and the cell region 1 can be formed simultaneously, and thus the productivity is improved.

[0111] In addition, in the above embodiment, a MOSFET is used as an example of the semiconductor device. However, it is not limited to MOSFET. Even for other semiconductor devices, as long as they have an element structure on the silicon carbide layer, the structure of the above embodiment can be applied and the same effect can be obtained.

[0112] Several embodiments of the present invention have been described, but these embodiments are only presented as examples. Various omissions, substitutions, and changes can be made without departing from the gist thereof. In addition, the embodiments can be combined.

[0113] <E. Embodiment 5>

[0114] This embodiment applies the silicon carbide semiconductor devices 101-104 of the above embodiments to a power conversion device. The application of silicon carbide semiconductor devices 101-104 is not limited to a specific power conversion device, but below, as embodiment 5, the application of silicon carbide semiconductor devices 101-104 to a three-phase inverter will be described.

[0115] Figure 15 This is a block diagram showing the structure of a power conversion system, in which the power conversion device according to this embodiment is applied.

[0116] Figure 15 The power conversion system shown consists of a power source 150, a power conversion device 200, and a load 300. The power source 150 is a DC power source that supplies DC power to the power conversion device 200. The power source 150 can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit or an AC / DC converter connected to an AC system. Alternatively, the power source 150 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0117] The power conversion device 200 is a three-phase inverter connected between the power source 150 and the load 300, which converts the DC power supplied from the power source 150 into AC power and supplies the AC power to the load 300. For example... Figure 15 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power for output; a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203 that outputs control signals to control the drive circuit 202.

[0118] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0119] The details of the power conversion device 200 are described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements on and off, it converts the DC power supplied from the power source 150 into AC power, which is then supplied to the load 300. The specific circuit structure of the main conversion circuit 201 varies, but the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. Each switching element of the main conversion circuit 201 uses any of the silicon carbide semiconductor devices 101-104 described in embodiments 1-4 above. The six switching elements are connected in series in pairs to form upper and lower bridge arms, and each upper and lower bridge arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower bridge arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0120] The drive circuit 202 generates drive signals to drive the switching elements of the main converter circuit 201 and supplies them to the control electrodes of the switching elements of the main converter circuit 201. Specifically, according to the control signals from the control circuit 203 (described later), drive signals that turn the switching elements on and drive signals that turn the switching elements off are output to the control electrodes of each switching element. When the switching element is kept on, the drive signal is a voltage signal greater than or equal to the threshold voltage of the switching element (on signal); when the switching element is kept off, the drive signal is a voltage signal less than or equal to the threshold voltage of the switching element (off signal).

[0121] Control circuit 203 controls the switching elements of main converter circuit 201 to supply the desired power to load 300. Specifically, it calculates the time (on-time) during which each switching element of main converter circuit 201 should be in the on state based on the power to be supplied to load 300. For example, main converter circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements in accordance with the voltage to be output. Moreover, control command (control signal) is output to drive circuit 202 in such a way that an on signal is output to the switching element that should be in the on state at each time, and an off signal is output to the switching element that should be in the off state. Drive circuit 202 outputs the on signal or off signal as a drive signal to the control electrode of each switching element according to the control signal.

[0122] In the case of the power conversion device according to this embodiment, since the silicon carbide semiconductor device 101-104 of any of the embodiments 1-4 is used as the switching element of the main conversion circuit 201, the reliability can be improved.

[0123] In this embodiment, an example of applying the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 to a 2-level three-phase inverter has been described. However, the application of the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 is not limited to this, and they can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is provided, but it can also be a 3-level or multi-level power conversion device. When supplying power to a single-phase load, the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 can also be applied to a single-phase inverter. In addition, when supplying power to DC loads, the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 can also be applied to a DC / DC converter or an AC / DC converter.

[0124] Furthermore, the power conversion device using the silicon carbide semiconductor devices 101-104 of Embodiments 1-4 is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing, induction heating cooker, or contactless power supply system, and can also be used as a power regulator for solar power generation system or energy storage system.

[0125] Explanation of the label

[0126] 1. Cell region, 2. End region, 3. Pad region, 4. Control pad, 4a. Current sensing pad, 4b. Gate pad, 11. Silicon carbide substrate, 12. Semiconductor layer, 14. Epitaxial layer, 15. Well region, 16. Source region, 17. Contact region, 18. Gate electrode, 19. Interlayer insulating film, 19h. Contact hole, 20, 21, 22. Barrier metal, 23. Source electrode, 24. Drain electrode, 25. Oxide film, 26. Gate oxide film, 27. Field insulating film, 100, 101, 102, 103, 104. Semiconductor device, 150. Power supply, 200. Power conversion device, 201. Main conversion circuit, 202. Drive circuit, 203. Control circuit, 300. Load.

Claims

1. A silicon carbide semiconductor device, comprising: Silicon carbide substrate; A semiconductor layer is formed on the silicon carbide substrate; A gate electrode, which is opposite to the semiconductor layer through a gate insulating film; An interlayer insulating film covers the gate electrode; A barrier metal, which is formed on the interlayer insulating film; as well as The upper surface electrode covers the barrier metal. The barrier metal is a two-layer structure consisting of a first barrier metal and a second barrier metal. The first barrier metal on the interlayer insulating film side is made of the same Ti metal as the second barrier metal, but has a smaller thickness than the second barrier metal.

2. The silicon carbide semiconductor device according to claim 1, wherein, The combined thickness of the first blocking metal and the second blocking metal is greater than or equal to 100 nm and less than or equal to 200 nm.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein, An oxide film is also present between the first barrier metal and the second barrier metal.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein, There is a portion between the interlayer insulating film and the upper surface electrode where the first blocking metal is not formed. In the portion where the first blocking metal is not formed, the surface of the second blocking metal has a step.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The blocking metal is formed in the sensing unit region between the interlayer insulating film and the upper surface electrode.

6. A power conversion device, comprising: A main conversion circuit having a silicon carbide semiconductor device as described in any one of claims 1 to 5, the main conversion circuit converting the input power to an output; A driving circuit that outputs a driving signal to the silicon carbide semiconductor device. as well as The control circuit outputs control signals to the drive circuit to control the drive circuit.

7. A method for manufacturing a silicon carbide semiconductor device, wherein, Prepare a silicon carbide substrate. A semiconductor layer is formed on the silicon carbide substrate. A gate electrode is formed that is opposite to the semiconductor layer through a gate insulating film. An interlayer insulating film is formed to cover the gate electrode. A first barrier metal is formed on the interlayer insulating film. A second barrier metal, composed of the same Ti metal as the first barrier metal but thicker than the first barrier metal, is formed on top of the first barrier metal. An upper surface electrode is formed that covers the second barrier metal.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein, The combined thickness of the first blocking metal and the second blocking metal is greater than or equal to 100 nm and less than or equal to 200 nm.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 7 or 8, wherein, An oxide film is further formed on the first barrier metal. The second barrier metal is formed on top of the first barrier metal, with the oxide film in between.

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