Tunneling passivation back contact crystalline silicon cell and preparation method thereof

Abstract

The invention belongs to the field of photovoltaic technology, and discloses a tunneling passivation back contact crystalline silicon cell and a preparation method thereof, and the preparation method comprises the steps: carrying out the texturing and polishing of an N-type substrate silicon wafer; sequentially depositing a first tunneling oxide layer, a first amorphous silicon layer and a first oxide layer; performing laser scanning for the first time to form a patterned first electrode area, and removing the area scanned by laser through chemical corrosion; sequentially depositing a second tunneling oxide layer, a second amorphous silicon layer and a second oxide layer in the chemically corroded region; performing second laser scanning to form a doped region and an undoped region; and forming a passivation layer and an antireflection film, and metallizing the first electrode region and the second electrode region to obtain the back contact crystalline silicon cell. According to the preparation method, on the premise that the photoelectric conversion efficiency of the cell is not reduced, the cell structure is optimized, a traditional GAP layer is removed, damage of laser to the silicon wafer is further reduced, the alkali corrosion time is shortened, and the technological process is shortened.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic technology, and specifically relates to a tunneling passivated back contact crystalline silicon solar cell and its preparation method. Background Technology

[0002] Back-contact crystalline silicon solar cells are a type of high-efficiency solar cell technology that designs all the electrodes (positive and negative) of the cell on the back, thereby eliminating the shading of the front grid lines and maximizing the light absorption area. Its core advantage lies in improving conversion efficiency through structural innovation, while also taking into account aesthetics and the convenience of module packaging.

[0003] N-type interdigitated back contact (IBC) solar modules offer numerous advantages, including low temperature coefficient, low power degradation, low NOCT, virtually no hot spots, and an aesthetically pleasing, grid-free front surface. PERC cells are crystalline silicon solar cells that improve efficiency through back-side passivation technology. The core of this technology involves adding a passivation layer and localized contact structures to the back of the cell to reduce carrier recombination, thereby significantly improving photoelectric conversion efficiency. N-type IBC modules have a temperature coefficient of -0.3% / ℃, lower than the -0.39% / ℃ of P-type PERC modules; their first-year power degradation is 0.5%, and the annual power degradation is 0.25%, significantly lower than the 2% first-year power degradation and 0.5% annual power degradation of P-type PERC modules. For photovoltaic power plants with the same initial installed capacity, N-type IBC modules can generate approximately 10% more electricity over a 25-year power generation cycle. In addition, during hot spot reliability testing, the surface temperature of N-type IBC battery modules was around 100°C, which is much lower than the 200°C of PERC battery modules. This greatly reduces the risk of modules burning out or even damaging the power generation system due to partial shading during outdoor use.

[0004] With the development of electronic pastes and laser technology, the efficiency of N-type IBC cells has approached its limit. TOPCon technology involves fabricating an ultrathin silicon oxide layer (SiOx) and a doped polycrystalline silicon layer (poly-Si) on the back side of an N-type silicon substrate to form a passivated contact structure. This structure utilizes the quantum confinement effect of the tunneling oxide layer and the selective carrier transport of the doped polycrystalline silicon layer to improve the open-circuit voltage and conversion efficiency of the cell. HJT technology deposits an intrinsic amorphous silicon layer (ia-Si) on the back side of an N-type silicon substrate to achieve surface passivation, then covers it with a P / N-type doped amorphous silicon layer. Finally, current is collected through a TCO (transparent conductive oxide) film and metal electrodes. This structure can isolate the metal contact, significantly reducing carrier recombination loss, thereby improving the open-circuit voltage of the cell. TBC technology is a composite high-efficiency solar cell technology that integrates TOPCon passivated contacts and back contact (BC) electrodes. Its core lies in improving optical utilization through a full back-side electrode design while retaining the passivation advantages of TOPCon. HBC (Heterojunction Back Contact) technology is a high-efficiency solar cell technology that combines heterojunction passivation (HJT) with back contact electrode (BC). It achieves a breakthrough in photoelectric conversion efficiency through a front-side gridless design and a double-sided passivation structure.

[0005] However, both TBC and HBC technologies require a gap area to isolate the P-region and N-region from contact, reducing recombination and leakage at the contact area. The formation of the gap area requires multiple steps involving laser equipment and wet processing, indirectly increasing equipment investment and process steps.

[0006] Therefore, it is necessary to provide a new type of battery that optimizes the battery structure without reducing the battery's photoelectric conversion efficiency, eliminates the traditional GAP layer, further reduces laser damage to the silicon wafer, reduces alkaline etching time and process flow, thereby increasing the silicon wafer thickness and increasing the product qualification rate from silicon wafer to battery cell. Summary of the Invention

[0007] To address the above problems, this application discloses a method for fabricating a tunneling passivated back-contact crystalline silicon solar cell, comprising: The N-type substrate silicon wafer is texturized and polished to obtain a pretreated silicon wafer; A first tunneling oxide layer, a first amorphous silicon layer, and a first oxide layer are sequentially deposited on the back side of the pretreated silicon wafer; A first laser scan is performed on the back side of the pretreated silicon wafer after the first oxide layer is deposited to remove part of the first oxide layer and form a patterned first electrode area. The area scanned by the laser is removed by chemical etching until the N-type substrate silicon wafer is exposed. A second tunneling oxide layer, a second amorphous silicon layer, and a second oxide layer are sequentially deposited in the chemically etched area of ​​the pretreated silicon wafer. A second laser scan is performed on the back side of the pretreated silicon wafer after the second oxide layer is deposited to form doped and undoped regions. The undoped regions form patterned second electrode regions, and the doped regions form doped polysilicon with a preset doping concentration. After the second laser scan, a passivation layer and an anti-reflection film are formed sequentially on the front and back sides of the pre-treated silicon wafer. Metallization is then performed in the first electrode region and the second electrode region to obtain a back-contact crystalline silicon solar cell.

[0008] Further, the N-type substrate silicon wafer is texturized and polished, including: Texturing is performed on the front and back sides of the N-type substrate silicon wafer to obtain a pyramid-shaped textured surface, with a reflectivity of 9%-13% on the front side; A mask is formed on the front side of the texturized N-type substrate silicon wafer; The back side of the N-type substrate silicon wafer with a mask is polished to form a polished substrate. The base of the remaining pyramid structure on the back side has a side length of 7-30 micrometers and a reflectivity of 35-45%.

[0009] Furthermore, the thickness of the first tunneling oxide layer is 0.5 nm to 5 nm.

[0010] Furthermore, when the first amorphous silicon layer is a boron-doped amorphous silicon layer, its thickness is 200-400 nm, the boron doping surface concentration is 5E18-1E20, the first oxide layer is a boron-doped oxide layer with a thickness of 3-30 nm and a boron content of 20-50% by mass, and the second oxide layer is a PSG oxide layer with a thickness of 1-10 nm and a phosphorus content of 10%-50% by mass. When the first amorphous silicon layer is a phosphorus-doped amorphous silicon layer, its thickness is 200-400 nm and the phosphorus doping surface concentration is 5E18-1E20. The first oxide layer is a phosphorus-doped oxide layer with a thickness of 3-30 nm and a phosphorus content of 20-50% by mass. The second oxide layer is a BSG oxide layer with a thickness of 1-10 nm and a boron content of 10%-50% by mass.

[0011] Furthermore, the frequency of the first laser scan is 200-500kHz, the power is 30-100w, the spot size is 100-200μm×100-200μm, and the patterned linewidth is 200-400μm.

[0012] Furthermore, chemical corrosion is carried out using an alkaline solution, which is one or more of KOH, NaOH, and LiOH, with a mass concentration of 20%-40% and a temperature of 60-80℃.

[0013] Further, a second tunneling oxide layer, a second amorphous silicon layer, and a second oxide layer are sequentially deposited in the chemically etched region of the pretreated silicon wafer, including: The deposition temperature of the second tunneling oxide layer was controlled at 580-630℃, the deposition time at 1800s-3600s, and the deposition thickness at 1-3nm. The deposition temperature of the second amorphous silicon layer was controlled at 580-630℃, the deposition time at 900s-3600s, and the deposition thickness at 70-150nm. The deposition temperature of the second oxide layer is controlled at 800-900℃, and the surface concentration of doped into the second amorphous silicon layer is 1E17-5E18.

[0014] Furthermore, the second laser scan has a frequency of 200-500kHz, a power of 30-100w, and a spot size of 100-200 micrometers × 100-200 micrometers.

[0015] Furthermore, before sequentially forming the passivation layer and antireflection film on the front and back sides of the pre-treated silicon wafer after deposition, the process includes: The mask, the first oxide layer, and the second oxide layer are removed using an HF solution with a mass concentration of 3-20% and a temperature of 20-40℃.

[0016] Furthermore, the passivation layer on the front side is aluminum oxide with a thickness of 3-10 nm; The front antireflective coating is SiN X or SiON X The thickness is 60-100nm; The back passivation layer is aluminum oxide with a thickness of 3-10 nm; The anti-reflective coating on the back is SiN X or SiON X The thickness is 80-120nm.

[0017] This application also discloses a back-contact crystalline silicon solar cell prepared by the above method, wherein the GAP region of the back-contact crystalline silicon solar cell is doped polycrystalline silicon with a preset doping concentration.

[0018] The technical effects and advantages of this application are as follows: 1. The tunnel-back contact crystalline silicon solar cell of this application eliminates the traditional GAP region and uses the difference between high and low doping concentration to reduce leakage and recombination, further reducing laser damage to the substrate silicon wafer, reducing chemical etching time and process flow, thereby increasing the thickness of the substrate silicon wafer and increasing the yield of the solar cell.

[0019] 2. The preparation method of this application involves texturing on a substrate silicon wafer. Compared with the texturing process in the traditional TBC process, the texturing surface is easier to control, is not affected by traditional diffusion, and the uniformity and density of the textured surface are significantly improved.

[0020] 3. This application adopts a process of texturing first and then polishing with alkaline solution, which can avoid the impact of heavy line marks in the original silicon wafer on electrical performance.

[0021] 4. This application adopts a process of texturing first and then making the emitter, which can avoid the use of chemicals such as HNO3 that cause serious environmental pollution.

[0022] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating a method for manufacturing a tunneling passivated back-contact crystalline silicon solar cell according to an embodiment of this application. Figure 2 This is a schematic diagram of the structure of a tunnel passivated back contact crystalline silicon solar cell according to an embodiment of this application; Figure 3 This is a schematic diagram of the back surface morphology of the polished N-type substrate silicon wafer in Embodiment 1 of this application; Figure 4 This is a schematic diagram of the back surface morphology of the polished N-type substrate silicon wafer in the comparative example of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] To further reduce laser damage to silicon wafers, shorten alkaline etching time and process flow, thereby increasing silicon wafer thickness and improving the product yield from silicon wafers to solar cells, such as... Figure 1 As shown, this application discloses a method for manufacturing a tunneling passivated back-contact crystalline silicon solar cell, comprising: Step 1: Texturing and polishing the N-type substrate silicon wafer. Texturing is performed on both the front and back sides of the N-type substrate silicon wafer to obtain a pyramidal textured surface, controlling the reflectivity of the textured surface to be 9%-13%. A mask is formed on the front side of the texturized N-type substrate silicon wafer. The mask is one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 30-80 nm. The back side of the N-type substrate silicon wafer with the mask is polished to form a polished substrate. After polishing, the remaining pyramidal structure base on the back side has a side length of 7-30 micrometers, and the reflectivity of the back side is 35-45%, resulting in a pre-treated silicon wafer.

[0027] Step 2: Sequentially deposit a first tunneling oxide layer, a first amorphous silicon layer, and a first oxide layer on the back side of the pretreated silicon wafer. The thickness of the first tunneling oxide layer is 0.5 nm-5 nm. When the first amorphous silicon layer is a boron-doped amorphous silicon layer, its thickness is 200-400 nm, and the boron doping concentration is 5E18-1E20. The first oxide layer is a boron-doped oxide layer with a thickness of 3-30 nm and a boron content of 20-50% by mass. The second oxide layer is a PSG oxide layer with a thickness of 1-10 nm and a phosphorus content of 10%-50% by mass. When the first amorphous silicon layer is a phosphorus-doped amorphous silicon layer, its thickness is 200-400 nm, and the phosphorus doping concentration is 5E18-1E20. The first oxide layer is a phosphorus-doped oxide layer with a thickness of 3-30 nm and a phosphorus content of 20-50% by mass. The second oxide layer is a BSG oxide layer with a thickness of 1-10 nm and a boron content of 10%-50% by mass.

[0028] Step 3: A first laser scan is performed on the back side of the pretreated silicon wafer after the first oxide layer is deposited to remove part of the first oxide layer and form a patterned first electrode region. The frequency of the first laser scan is 200-500 kHz, the power is 30-100 W, the spot size is 100-200 μm × 100-200 μm, and the linewidth of the patterned area is 200-400 μm. The laser-scanned area is then removed by chemical etching until the N-type substrate silicon wafer is exposed. The chemical etching is performed using an alkaline solution, which can be one or more of KOH, NaOH, and LiOH, with a mass concentration of 20%-40% and a temperature of 60-80℃.

[0029] Step 4: Sequentially deposit a second tunneling oxide layer, a second amorphous silicon layer, and a second oxide layer in the chemically etched area of ​​the pretreated silicon wafer. Control the deposition temperature of the second tunneling oxide layer to be 580-630℃, the deposition time to be 1800s-3600s, and the deposition thickness to be 1-3nm; control the deposition temperature of the second amorphous silicon layer to be 580-630℃, the deposition time to be 900s-3600s, and the deposition thickness to be 70-150nm; control the deposition temperature of the second oxide layer to be 800-900℃, and the surface concentration of doping to the second amorphous silicon layer to be 1E17-5E18.

[0030] Step 5: Perform a second laser scan on the back side of the pretreated silicon wafer after depositing the second oxide layer. The frequency of the second laser scan is 200-500kHz, the power is 30-100w, and the spot size is 100-200μm×100-200μm. This forms doped and undoped regions. The undoped region forms a patterned second electrode region, and the doped region forms doped polysilicon with a preset doping concentration. Low-doped N-poly or P-poly is used as the GAP layer.

[0031] Step 6: Remove the mask, the first oxide layer, and the second oxide layer with HF solution, wherein the mass concentration of HF solution is 3-20% and the temperature is 20-40℃.

[0032] Step 7: After the second laser scan, a passivation layer and an anti-reflection film are sequentially formed on the front and back sides of the pre-treated silicon wafer. The front passivation layer is aluminum oxide with a thickness of 3-10 nm; the front anti-reflection film is SiN. X or SiON X The thickness is 60-100nm; the back passivation layer is aluminum oxide with a thickness of 3-10nm; the back antireflection film is SiN. X or SiON X The thickness is 80-120 nm. Metallization is performed in the first and second electrode regions to obtain a back-contact crystalline silicon solar cell.

[0033] This application also discloses a back-contact crystalline silicon solar cell prepared by the above method, such as... Figure 2 As shown, the GAP region of the back-contact crystalline silicon cell is doped polycrystalline silicon with a preset doping concentration.

[0034] To better illustrate this solution, the following embodiments and comparative examples are provided.

[0035] Example 1 S1: Texturing the front and back sides of the N-type substrate silicon wafer to create a textured surface with a pyramidal structure and a reflectivity of 9%-13%. Specifically, this includes pre-cleaning, water washing, texturing, water washing, post-cleaning, water washing, acid washing, slow lifting, and drying.

[0036] Pre-cleaning: A mixture of hydrogen peroxide and alkaline solution is used to bubble and stir the N-type substrate silicon wafer to remove metal and oil contaminants from its surface. The process temperature is 75℃, and the process time is 240 seconds. Water washing: The overflow mode washes away the mixture from the previous step. The process temperature is 25℃ and the process time is 120s. Texturing: The surface of the silicon wafer is treated with an aqueous solution of potassium hydroxide to obtain the desired tower base size. Process temperature: 81℃; Process time: 480s. Post-cleaning: The silicon wafer is bubbled and stirred using a mixture of hydrogen peroxide and alkaline solution to remove residual sodium silicate and other substances. Process temperature: 70℃; Process time: 200s. Mixed acid washing: Using a mixture of HF and HCl, metal ions are removed from the surface of the silicon wafer, making the surface of the silicon wafer hydrophobic and easy to dry.

[0037] S2: A mask is prepared on the front side of an N-type substrate silicon wafer by PECVD. The mask is one or more of silicon nitride, silicon oxynitride, and silicon oxide. The mask thickness is 30-80 nm, the deposition temperature is 500 °C, and the deposition time is 400 s.

[0038] S3: Polish the back side of the N-type substrate silicon wafer after S2 treatment, controlling the side length of the remaining pyramid structure base to 5-25 micrometers, preferably 15 micrometers. The back side of the polished N-type substrate silicon wafer is as follows: Figure 3 As shown, the base of the pyramid structure is uniform and dense. The polishing steps specifically include pre-cleaning, water washing, alkaline washing, water washing, post-cleaning, water washing, acid washing, slow lifting, and drying.

[0039] Pre-cleaning: The silicon wafer is bubbled and stirred using a mixture of hydrogen peroxide and alkaline solution to remove metal and oil stains from the surface of the silicon wafer. The process temperature is 75℃ and the process time is 240s. Water washing: The overflow mode washes away the alkali solution from the previous step. The process temperature is 25℃ and the process time is 120s. Alkali: An aqueous solution of potassium hydroxide is used to treat the surface of the silicon wafer to achieve the desired tower base size. The process temperature is 76℃, and the process time is 80s. Post-cleaning: The silicon wafer is bubbled and stirred using a mixture of hydrogen peroxide and alkaline solution to remove residual sodium silicate and other substances. The process temperature is 70℃ and the process time is 200s. Mixed acid washing: Using a mixed solution of HF and HCl, metal ions are removed from the surface of the silicon wafer, making the surface of the silicon wafer hydrophobic and easy to dry.

[0040] S4: A first tunneling oxide layer, a boron-doped amorphous silicon layer, and a boron-doped oxide layer are sequentially deposited on the back side of the N-type substrate silicon wafer after S3 processing using a PECVD equipment. The first tunneling oxide layer has a thickness of 1.5 nm and exhibits tunneling properties. In the boron-doped amorphous silicon layer, the amorphous silicon thickness is 300 nm, the boron doping surface concentration is 1E19, and the junction depth into the silicon substrate is 1-3 micrometers, preferably 2 micrometers. The boron-doped oxide layer has a thickness of 7 nm, and the boron content is 30%.

[0041] S5: A patterned P-region (poly) is formed on the back side of the N-type substrate silicon wafer after S4 treatment using a laser device. The laser-etched areas are then removed using a wet process until the N-type substrate silicon wafer is exposed. The N-type substrate silicon wafer is then cleaned. The laser device has a frequency of 200 kHz, a power of 50 W, a spot size of 100-200 μm × 100-200 μm, and a patterned linewidth of 200 μm. The etched areas are removed by alkaline etching. The alkaline can be one or more of KOH, NaOH, and LiOH, the alkaline solution temperature is 70℃, and the mass fraction of the alkaline solution is 25%.

[0042] S6: In the region of the N-type substrate silicon wafer after alkaline etching, a second tunneling oxide layer and a second amorphous silicon layer are sequentially deposited using an LPCVD device. The deposition temperature of the second tunneling oxide layer is 600℃, the deposition time is 1800s, and the thickness of the second tunneling oxide layer is 1.5nm; the deposition temperature of the second amorphous silicon layer is 600℃, the deposition time is 1200s, and the thickness is 70nm.

[0043] S7: A PSG oxide layer is deposited on the surface of the second amorphous silicon layer using a diffusion device. The PSG contains 15% phosphorus by mass, the deposition temperature is 850℃, the doping concentration on the amorphous silicon surface is 1E17, and the PSG thickness is 10nm.

[0044] S8: A second laser scan is performed on the back side of the pre-treated silicon wafer after the PSG oxide layer is deposited, forming doped and undoped regions. The undoped region forms a patterned second electrode region, and the doped region forms doped polysilicon with a preset doping concentration, using low-doped N-poly or P-poly as the GAP layer. The laser parameters are: frequency 200kHz, power 60W, spot size 100-200 μm × 100-200 μm, with a phosphorus concentration of 5E20 on the surface of the doped region and 1E17 on the surface of the undoped region.

[0045] S9: The mask, first oxide layer, and second oxide layer are removed using an HF solution with a mass concentration of 15% at a temperature of 30°C. Then, a passivation layer and an anti-reflection film are sequentially formed on the front and back sides of the pre-treated silicon wafer after the second laser scan. Metallization is then performed in the N-region and P-region to obtain a back-contact crystalline silicon solar cell. The front passivation layer is aluminum oxide with a thickness of 5 nm; the front anti-reflection film is SiN. X or SiON X The thickness is 70nm; the back passivation layer is aluminum oxide with a thickness of 7nm; the back antireflection coating is SiN. X or SiON X The thickness is 120nm.

[0046] Comparative Example S1: Double-sided polishing of N-type substrate silicon wafers, including: Pre-cleaning - water washing - polishing - water washing - post-cleaning - water washing - ozone washing - water washing - acid washing - water washing - slow lifting - drying.

[0047] Pre-cleaning: The silicon wafer is bubbled and stirred with a mixture of hydrogen peroxide and alkaline solution to remove metal and oil stains from the surface of the silicon wafer. The process temperature is 75℃ and the process time is 240s. Water washing: The overflow mode washes away the mixture from the previous step. The process temperature is 25℃ and the process time is 120s. Polishing: The silicon wafer surface is treated with an aqueous solution of potassium hydroxide to obtain the desired tower base size. The process temperature is 77℃ and the process time is 240s. Post-cleaning: The silicon wafer is bubbled and stirred with a mixture of hydrogen peroxide and alkaline solution to remove residual sodium silicate and other substances from the silicon wafer. The process temperature is 70℃ and the process time is 200s. Ozone cleaning: Ozone is used to remove metal ions and their compounds from the surface of silicon wafers, with an ozone concentration of 100 ppm and a temperature of 25°C. Mixed acid washing: Using a mixed solution of HF and HCl, metal ions are removed from the surface of the silicon wafer, making the surface of the silicon wafer hydrophobic and easy to dry.

[0048] The surface of the polished N-type substrate silicon wafer is as follows: Figure 4 As shown, there are heavy line marks in the silicon wafer, and the base of the pyramid structure is scattered and uneven.

[0049] S2: A first tunneling oxide layer and a first amorphous silicon layer are deposited on the back side of the silicon wafer using an LPCVD device. The thickness of the tunneling oxide layer is 1.5 nm, the deposition temperature is 600 °C, and the oxidation time is 2400 s. The thickness of the amorphous silicon layer is 300 nm.

[0050] S3: Boron diffusion is performed on the above silicon wafer using a tubular diffusion device to obtain a BSG layer with a boron doping concentration of 1E19 and a junction depth of 2 micrometers.

[0051] S4: Clean the surface BSG layer to 5-30nm using HF.

[0052] S5: SiN deposition on the back side of the silicon wafer via PECVD X Or SiON X The mask has a thickness of 140nm.

[0053] S6: Laser grooving is performed using laser equipment, with a line width of 220 micrometers.

[0054] S7: Remove laser damage in the grouted area using wet cleaning equipment, specifically including pre-cleaning, water washing, alkaline washing, water washing, post-cleaning, water washing, acid washing, slow lifting, and drying.

[0055] S8: A second tunneling oxide layer and a second amorphous silicon layer are deposited in the trench area using an LPCVD device. The thickness of the second tunneling oxide layer is 1.5 nm, the deposition temperature is 600 °C, and the oxidation time is 1400 s. The thickness of the second amorphous silicon layer is 70 nm.

[0056] S9: The second amorphous silicon layer is phosphorus diffused to form a PSG layer using a tubular diffusion device. The phosphorus doping concentration is 5E20, the junction depth is 2 micrometers, and the PSG layer thickness is 20-30nm.

[0057] S10: Using laser equipment, a layered N-area is formed, and a GAP area is further formed.

[0058] S11: Remove the BSG layer, PSG layer and mask using a mixture of HNO3 and HF.

[0059] S12: The front and GAP areas are lined using wet equipment, specifically including pre-cleaning, washing, lined, washing, post-cleaning, washing, pickling, slow lifting, and drying.

[0060] Pre-cleaning: The silicon wafer is bubbled and stirred with a mixture of hydrogen peroxide and alkaline solution to remove metal and oil stains from the surface of the silicon wafer. The process temperature is 75℃ and the process time is 240s. Water washing: The overflow mode washes away the alkali solution from the previous step. The process temperature is 25℃ and the process time is 120s. Texturing: The surface of the silicon wafer is treated with an aqueous solution of potassium hydroxide to obtain the desired tower base size. The process temperature is 81℃ and the process time is 480s. Post-cleaning: The silicon wafer is bubbled and stirred with a mixture of hydrogen peroxide and alkaline solution to remove residual sodium silicate and other substances from the silicon wafer. The process temperature is 70℃ and the process time is 200s. Mixed acid washing: Using a mixed solution of HF and HCl to remove metal ions from the surface of silicon wafers, making the silicon wafer surface hydrophobic and easier to dry.

[0061] S13: A passivation layer and an anti-reflection film are sequentially formed on the front and back sides of the texturized silicon wafer. Metallization is then performed in the N-region and P-region to obtain a back-contact crystalline silicon solar cell. The front passivation layer is aluminum oxide with a thickness of 5 nm; the front anti-reflection film is SiN. X or SiON X The thickness is 70nm; the back passivation layer is aluminum oxide with a thickness of 7nm; the back antireflection coating is SiN. X or SiON X The thickness is 120nm.

[0062] The back-contact crystalline silicon solar cells prepared in Example 1 and the comparative example were subjected to performance testing and evaluation. The results are shown in Table 1. The back-contact crystalline silicon solar cell of Example 1 showed a photoelectric conversion efficiency improvement of 0.12 compared with the back-contact crystalline silicon solar cell of the comparative example. This indicates that the preparation method of this application has achieved optimization of the cell structure without reducing the photoelectric conversion efficiency of the back-contact crystalline silicon solar cell. By eliminating the traditional GAP layer, the damage of laser to silicon wafers can be effectively reduced, the alkaline etching time and process flow can be reduced, thereby increasing the silicon wafer thickness and increasing the product qualification rate from silicon wafer to solar cell.

[0063] Table 1. Performance test results of the solar cells prepared in Example 1 and the comparative example.

[0064] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a tunneling passivated back-contact crystalline silicon solar cell, characterized in that, include: The N-type substrate silicon wafer is texturized and polished to obtain a pretreated silicon wafer; A first tunneling oxide layer, a first amorphous silicon layer, and a first oxide layer are sequentially deposited on the back side of the pretreated silicon wafer; A first laser scan is performed on the back side of the pretreated silicon wafer after the first oxide layer is deposited to remove part of the first oxide layer and form a patterned first electrode area. The laser-scanned area is then removed by chemical etching until the N-type substrate silicon wafer is exposed. A second tunneling oxide layer, a second amorphous silicon layer, and a second oxide layer are sequentially deposited in the chemically etched region of the pretreated silicon wafer. A second laser scan is performed on the back side of the pretreated silicon wafer after the second oxide layer is deposited to form doped and undoped regions. The undoped regions form patterned second electrode regions, and the doped regions form doped polysilicon with a preset doping concentration. After the second laser scan, a passivation layer and an anti-reflection film are formed sequentially on the front and back sides of the pretreated silicon wafer, and metallization is performed in the first electrode region and the second electrode region to obtain a back-contact crystalline silicon solar cell.

2. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, The texturing and polishing of the N-type substrate silicon wafer includes: The front and back sides of the N-type substrate silicon wafer are texturized to obtain a pyramid-shaped textured surface, with a reflectivity of 9%-13% on the front side; A mask is formed on the front side of the N-type substrate silicon wafer after texturing; The back side of the N-type substrate silicon wafer with a mask is polished to form a polished substrate. The base of the remaining pyramid structure on the back side has a side length of 7-30 micrometers and a reflectivity of 35-45%.

3. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, The thickness of the first tunneling oxide layer is 0.5nm-5nm.

4. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, When the first amorphous silicon layer is a boron-doped amorphous silicon layer, its thickness is 200-400 nm and the boron doping surface concentration is 5E18-1E20; when the first oxide layer is a boron-doped oxide layer, its thickness is 3-30 nm and the boron content is 20-50% by mass; when the second oxide layer is a PSG oxide layer, its thickness is 1-10 nm and the phosphorus content is 10%-50% by mass. When the first amorphous silicon layer is a phosphorus-doped amorphous silicon layer, its thickness is 200-400 nm and the phosphorus doping surface concentration is 5E18-1E20. When the first oxide layer is a phosphorus-doped oxide layer, its thickness is 3-30 nm and the phosphorus content is 20-50% by mass. When the second oxide layer is a BSG oxide layer, its thickness is 1-10 nm and the boron content is 10%-50% by mass.

5. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, The first laser scan has a frequency of 200-500kHz, a power of 30-100w, a spot size of 100-200μm × 100-200μm, and a patterned line width of 200-400μm.

6. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, The chemical corrosion is carried out using an alkaline solution, which is one or more of KOH, NaOH, and LiOH, with a mass concentration of 20%-40% and a temperature of 60-80℃.

7. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, A second tunneling oxide layer, a second amorphous silicon layer, and a second oxide layer are sequentially deposited in the chemically etched region of the pretreated silicon wafer, including: The deposition temperature of the second tunneling oxide layer is controlled to be 580-630℃, the deposition time to be 1800s-3600s, and the deposition thickness to be 1-3nm; The deposition temperature of the second amorphous silicon layer is controlled at 580-630℃, the deposition time at 900s-3600s, and the deposition thickness at 70-150nm. The deposition temperature of the second oxide layer is controlled at 800-900℃, and the surface concentration of doped into the second amorphous silicon layer is 1E17-5E18.

8. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, The second laser scan has a frequency of 200-500kHz, a power of 30-100w, and a spot size of 100-200 micrometers × 100-200 micrometers.

9. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 2, characterized in that, Before the passivation layer and antireflection film are sequentially formed on the front and back sides of the pretreated silicon wafer after deposition, the process includes: The mask, the first oxide layer, and the second oxide layer are removed using an HF solution, wherein the HF solution has a mass concentration of 3-20% and the temperature is 20-40°C.

10. The method for fabricating a tunneling passivated back-contact crystalline silicon solar cell according to claim 1, characterized in that, The passivation layer on the front side is aluminum oxide, with a thickness of 3-10nm; The front antireflective coating is SiN X or SiON X The thickness is 60-100nm; The back passivation layer is aluminum oxide with a thickness of 3-10 nm; The anti-reflective coating on the back is SiN X or SiON X The thickness is 80-120nm.

11. A back-contact crystalline silicon solar cell prepared by the method according to any one of claims 1-10, characterized in that, The GAP region of the back-contact crystalline silicon cell is doped polycrystalline silicon with a preset doping concentration.

Images