Back contact battery and preparation method thereof

Abstract

The invention provides a back contact cell and a preparation method thereof, a dielectric layer is arranged between two doped layers of different conductive types of the back contact cell, and in the process of preparing the doped layers, a dopant diffuses to form the doped layer and penetrates through the dielectric layer to form nano-sized and uniformly distributed holes in the dielectric layer, so that the back contact cell is prepared. The doped layer is used for carrier transmission and serves as an electric leakage channel between the two doped layers, the hot spot risk is reduced, the preparation process is simple, and no extra process step needs to be added.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more specifically, to a back contact cell and its preparation method. Background Technology

[0002] Back-contact solar cells are solar cells where the light-facing side of the cell has no electrodes, and both the positive and negative electrodes are located on the back side of the cell. This reduces electrode shading of the cell, increases the short-circuit current, and improves the cell's energy conversion efficiency. In this type of back-contact cell, to improve efficiency, the doped layer and dielectric layer on the back side consist of a contact passivation structure. This passivation structure often consists of a passivation dielectric layer and doped polycrystalline silicon / doped amorphous silicon / microcrystalline silicon. Existing back-contact cells are shown in the attached manual. Figure 1 As shown, a first dielectric layer 202 and a second dielectric layer 203 are respectively disposed on the substrate 201. A first conductivity type doped layer 204 and a second conductivity type doped layer 205 are respectively disposed on the first dielectric layer 202 and the second dielectric layer 203. The two doped layers 204 and 205 are insulated from each other by an isolation region 212 to reduce the reverse leakage current of the back contact cell, thereby reducing the risk of hot spots at the module end. During manufacturing, it is necessary to control the reverse leakage current of the cell to a low value. During the fabrication process, various defects exist, leading to the generation of local leakage points, including local contact between the two doped layers 204 and 205 with opposite conductivity types. This makes the back contact cell very prone to exceeding the control value of the reverse leakage current, resulting in low cell manufacturing efficiency. Therefore, how to improve the structure and manufacturing process of the back contact cell to reduce the risk of hot spots at the module end has become an important aspect affecting its reliability. Summary of the Invention

[0003] This invention provides a back-contact solar cell. By forming nanoscale, uniformly distributed leakage channels in a dielectric layer between two doped layers with opposite conductivity types, the two doped layers achieve localized and uniform contact. This uniform contact improves the cell's leakage capability, reduces the voltage across the cell when shaded, and thus lowers the heat generation power at the leakage point, reducing the risk of hot spots. Furthermore, by introducing leakage channels at predetermined locations, this invention protects against hot spots caused by defects, reducing the requirements for defect control and improving the manufacturing capability of solar cells while mitigating the risk of hot spots. Moreover, this invention can form uniformly distributed pores as leakage channels in the dielectric layer through the diffusion formation step of the doped layers, based on existing back-contact solar cell fabrication processes. The process is simple and does not require additional processes to form the leakage channels.

[0004] The specific scheme of the back contact battery structure and manufacturing process of the present invention is as follows.

[0005] A back contact cell, comprising a plurality of back contact cell units, each back contact cell unit comprising: a semiconductor substrate, a first conductive type structure, a second conductive type structure and at least one leakage region,

[0006] The first conductive type structure comprises a first dielectric layer and a first doped layer, and the second conductive type structure comprises a second dielectric layer and a second doped layer;

[0007] The first conductive type structure and the second conductive type structure comprise at least one leakage region therebetween;

[0008] The first conductive type structure and the second conductive type structure are arranged in a first direction on a back side of the semiconductor substrate in a plane parallel to the semiconductor substrate, and the first conductive type structure and the second conductive type structure extend in a second direction, the first direction being perpendicular to the second direction;

[0009] The first dielectric layer and the second dielectric layer are formed on a back side of the semiconductor substrate, the first doped layer is located on the first dielectric layer, and the second doped layer is located on the second dielectric layer, the conductive type of the first doped layer being opposite to that of the second doped layer;

[0010] The leakage region comprises a third dielectric layer and a third doped layer formed in a thickness direction of the semiconductor substrate, the third doped layer having the same conductive type as the second doped layer, the third doped layer being adjacent to a side surface of the first doped layer through the third dielectric layer in the thickness direction of the semiconductor substrate, the first dopant of the first doped layer or the second dopant of the second doped layer diffusing through the third dielectric layer to form a hole for carrier transmission in a local part of the third dielectric layer, and the second doped layer being locally conductive to the first doped layer.

[0011] Further, the hole is of nanometer size.

[0012] Further, the holes are uniformly distributed.

[0013] Further, the first dielectric layer and the second dielectric layer are flush or have a height difference in the thickness direction of the semiconductor substrate, the height difference being less than or equal to 4 μm.

[0014] Further, the first dielectric layer and the second dielectric layer are flush in the thickness direction of the semiconductor substrate.

[0015] The first conductive type structure further comprises a first doped region, and the first dopant of the first doped layer forms the first doped region inside the semiconductor substrate through the first dielectric layer.

[0016] The second conductive type structure further comprises a second doped region, the second dopant of the second doped layer penetrating the second dielectric layer to form a second doped region inside the semiconductor substrate;

[0017] The leakage region further comprises a third doped region, the third doped region being formed by the first dopant diffusing through the third dielectric layer inside the third doped layer, or being formed by the second dopant diffusing through the third dielectric layer inside the first doped layer.

[0018] Further, the first dielectric layer and the second dielectric layer have a height difference along the thickness direction of the semiconductor substrate,

[0019] The first conductive type structure further comprises a first doped region, the first dopant of the first doped layer penetrating the first dielectric layer to form a first doped region inside the semiconductor substrate;

[0020] The second conductive type structure further comprises a second doped region, the second dopant of the second doped layer penetrating the second dielectric layer to form a second doped region inside the semiconductor substrate;

[0021] The leakage region further comprises a third doped region and a fourth doped region, the third doped region and the fourth doped region being formed by the first dopant diffusing through the third dielectric layer inside the third doped layer, or the third doped region and the fourth doped region being formed by the second dopant diffusing through the third dielectric layer inside the first doped layer and the first doped region respectively.

[0022] Further, in the leakage region, the first dopant diffuses through the third dielectric layer, the contact resistance between the third doped region and the first doped layer being 0.01-100 mohmcm 2 , and the contact resistance between the fourth doped region and the first doped layer being 0.01-100 mohmcm 2 ;

[0023] Or the second dopant diffuses through the third dielectric layer, the contact resistance between the third doped region and the third doped layer being 0.01-100 mohmcm 2 , and the contact resistance between the fourth doped region and the third doped layer being 0.01-100 mohmcm 2 .

[0024] Further, the third doped region is formed by the first dopant diffusing through the third dielectric layer inside the third doped layer, the highest doping concentration of the third doped region being less than the doping concentration of the first doped layer, and the lowest doping concentration being equal to the concentration of the third doped layer;

[0025] or the third doped region is formed by the second dopant diffusing through the third medium layer into the first doped layer, the highest doping concentration of the third doped region is less than the doping concentration of the third doped layer, and the lowest doping concentration of the third doped region is equal to the doping concentration of the first doped layer.

[0026] Further, the third doped region and the fourth doped region are formed by the first dopant diffusing through the third medium layer into the third doped layer, the highest doping concentration of the third doped region and the fourth doped region is less than the doping concentration of the first doped layer, and the lowest doping concentration of the third doped region and the fourth doped region is equal to the doping concentration of the third doped layer.

[0027] or the third doped region and the fourth doped region are formed by the second dopant diffusing through the third medium layer into the first doped layer and the first doped region respectively, the highest doping concentration of the third doped region and the fourth doped region is less than the doping concentration of the third doped layer, the lowest doping concentration of the third doped region is equal to the doping concentration of the first doped layer, and the lowest doping concentration of the fourth doped region is equal to the doping concentration of the first doped region at the same depth.

[0028] Further, the third doped layer is the same as the second doped layer and is integrally formed in the same process, and the doping concentration of the third doped layer is equal to the doping concentration of the second doped layer.

[0029] Further, the doping concentration of the first doped region, the second doped region, the third doped region and the fourth doped region gradually decreases in the semiconductor substrate away from the back surface of the substrate.

[0030] Further, the highest doping concentration of the one of the first doped region and the second doped region with higher concentration is 1E20-1E21atm / cm 3 , and the highest doping concentration of the one of the first doped region and the second doped region with lower concentration is 1E19-1E20atm / cm 3 .

[0031] Further, along the thickness direction of the semiconductor substrate, the depth of the first doped region is 0.01μm-0.6μm, and the depth of the second doped region is 0.01μm-0.6μm.

[0032] Further, along the first direction, the depth of the third doped region and the fourth doped region is 0.001μm-0.3μm.

[0033] Further, the thickness of the first medium layer is 1.0nm-2.5nm, and the thickness of the second medium layer is 1.0nm-2.5nm.

[0034] Further, the leakage region further comprises: a first sub-doped layer, a first sub-medium layer,

[0035] The first sub-dielectric layer is located on the semiconductor substrate, and one side of the first sub-dielectric layer is connected with the third dielectric layer and the other side is connected with the second dielectric layer along the first direction,

[0036] The first sub-doped layer is located on the first sub-dielectric layer, and one side of the first sub-doped layer is connected with the third doped layer and the other side is connected with the second doped layer along the first direction, and the first sub-doped layer has the same conductivity type as the third doped layer and the second doped layer.

[0037] Further, the first sub-doped layer is integrally formed with the third doped layer and the second doped layer in the same process, and the first sub-dielectric layer is integrally formed with the second dielectric layer and the third dielectric layer in the same process.

[0038] Further, the leakage region includes: a second sub-doped layer, a second sub-dielectric layer,

[0039] The second sub-dielectric layer is located on the first doped layer, and one side of the second sub-dielectric layer is connected with the third dielectric layer along the first direction,

[0040] The second sub-doped layer is located on the second sub-dielectric layer, and one side of the second sub-doped layer is connected with the third doped layer along the first direction, and the second sub-doped layer has the same conductivity type as the third doped layer.

[0041] Further, the second sub-doped layer is integrally formed with the third doped layer and the second doped layer in the same process.

[0042] Further, the thickness of the second sub-dielectric layer is 5nm-100nm.

[0043] Further, in each of the back contact cell, the first conductive type structure and the second conductive type structure are respectively strip-shaped regions extending along the second direction, and the first conductive type structure and the conductive type structure are parallel and spaced apart.

[0044] Further, in each of the back contact cell, the first conductive type structure and the second conductive type structure include at least one insulating region therebetween.

[0045] Further, in each of the back contact cell, along the first direction, the width of the insulating region is D1, the width of the first doped layer is D2, and the width of the second doped layer is D3, 20μm≤D1≤500μm, 100μm≤D2≤800μm, and 100μm≤D3≤800μm.

[0046] Further, along the first direction, the second sub-doped layer is located on the first doped layer with a width of X1, X1 < (1 / 2)D2, and along the second direction, the second sub-doped layer is located on the first doped layer with a length of W, 5μm≤W≤600μm.

[0047] Further, in the case that the back contact cell is a whole back contact cell, the number of the third doped regions and the fourth doped regions of the back contact cell is N1, 20≤N1≤8000; in the case that the back contact cell is an N-th fraction back contact cell, the number of the third doped regions and the fourth doped regions of the back contact cell is N2, 30 / N≤N2≤8000 / N, wherein N is a positive integer greater than or equal to 2.

[0048] A preparation method of a back contact cell unit, comprising the following steps:

[0049] Step (1), forming a first dielectric layer on the back light side of a semiconductor substrate;

[0050] Step (2), growing a first intrinsic polysilicon layer on the first dielectric layer, diffusing a first dopant into the first intrinsic polysilicon layer to form a first doped layer, and the first dopant locally penetrates the first dielectric layer along the thickness direction of the semiconductor substrate and diffuses into the semiconductor substrate to form a first doped region;

[0051] Step (3), forming a second sub-dielectric layer on the first doped layer;

[0052] Step (4), removing a part of the second sub-dielectric layer, the first doped layer and the first dielectric layer formed on the back light side of the semiconductor substrate;

[0053] Step (5), growing a first sub-dielectric layer and a second dielectric layer on the surface of the semiconductor substrate, and growing a third dielectric layer on the side of the remaining first dielectric layer, first doped layer and second sub-dielectric layer along the thickness direction of the semiconductor substrate, the first sub-dielectric layer, second dielectric layer and third dielectric layer are integrally formed in this step;

[0054] Step (6), growing a second intrinsic polysilicon on the upper surface of the first sub-dielectric layer and the second dielectric layer and the side of the third dielectric layer, and on the upper surface of the second sub-dielectric layer, a part of the second intrinsic polysilicon layer is adjacent to the surface of the semiconductor substrate through the first sub-dielectric layer and the second dielectric layer, a part of the second intrinsic polysilicon layer is adjacent to the side of the remaining first dielectric layer, first doped layer and second sub-dielectric layer through the third dielectric layer, and a part of the second intrinsic polysilicon layer is adjacent to the first doped layer through the second sub-dielectric layer;

[0055] Step (7), diffusing the second dopant into the second intrinsic polysilicon layer, comprising: doping the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the first sub dielectric layer to form a first sub-doped layer, doping the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the second dielectric layer to form a second doped layer, doping the second intrinsic polysilicon layer adjacent to the side surface of the remaining first dielectric layer, first doped layer, second sub-dielectric layer through the third dielectric layer to form a third doped layer, and doping the second intrinsic polysilicon layer adjacent to the first doped layer through the second sub-dielectric layer to form a second sub-doped layer;

[0056] The second dopant also partially penetrates the first sub-dielectric layer and the second dielectric layer in the thickness direction of the substrate and diffuses into the substrate to form a second doped region;

[0057] Meanwhile, the second dopant partially penetrates the third dielectric layer, or the first dopant partially penetrates the third dielectric layer, to form a hole for carrier passing in the third dielectric layer.

[0058] A method for manufacturing a back contact cell, comprising the following steps:

[0059] Step (1), forming a first dielectric layer on the back side of a semiconductor substrate;

[0060] Step (2), growing a first intrinsic polysilicon layer on the first dielectric layer, diffusing a first dopant into the first intrinsic polysilicon layer to form a first doped layer, and the first dopant partially penetrates the first dielectric layer in the thickness direction of the semiconductor substrate and diffuses into the semiconductor substrate to form a first doped region;

[0061] Step (3), forming a second sub-dielectric layer on the first doped layer;

[0062] Step (4), removing a part of the second sub-dielectric layer, first doped layer, first dielectric layer and first doped region formed on the back side of the semiconductor substrate to expose the surface of the semiconductor substrate;

[0063] Step (5), growing a first sub-dielectric layer, a second dielectric layer on the surface of the semiconductor substrate, and a third dielectric layer on the side surface of the remaining first doped region, first dielectric layer, first doped layer and second sub-dielectric layer in the thickness direction of the semiconductor substrate, wherein the first sub-dielectric layer, second dielectric layer and third dielectric layer are formed integrally in this step;

[0064] Step (6), growing a second intrinsic polysilicon layer on the upper surface of the first and second dielectric layers and the side surface of the third dielectric layer, and the upper surface of the second sub-dielectric layer, a part of the second intrinsic polysilicon layer being adjacent to the surface of the semiconductor substrate through the first and second dielectric layers, a part of the second intrinsic polysilicon layer being adjacent to the side surface of the remaining first doped region, the first dielectric layer, the first doped layer and the second sub-dielectric layer through the third dielectric layer, and a part of the second intrinsic polysilicon layer being adjacent to the first doped layer through the second sub-dielectric layer;

[0065] Step (7), diffusing a second dopant into the second intrinsic polysilicon layer, including: doping the part of the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the first dielectric layer to form a first sub-doped layer, doping the part of the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the second dielectric layer to form a second doped layer, doping the part of the second intrinsic polysilicon layer adjacent to the side surface of the remaining first doped region, the first dielectric layer, the first doped layer and the second sub-dielectric layer through the third dielectric layer to form a third doped layer, and doping the part of the second intrinsic polysilicon layer adjacent to the first doped layer through the second sub-dielectric layer to form a second sub-doped layer;

[0066] The second dopant also partially penetrates the first and second dielectric layers in the thickness direction of the substrate and diffuses into the substrate to form a second doped region.

[0067] Meanwhile, the second dopant partially penetrates the third dielectric layer, or the first dopant partially penetrates the third dielectric layer, to form a hole for carrier transmission in the third dielectric layer.

[0068] Further, in step (2), the first dopant is BCl3 or BBr3, and the diffusion of BCl3 or BBr3 is performed at a temperature of 850-1000°C. During the diffusion process, BCl3 or BBr3 decomposes, B elements diffuse into the first intrinsic polysilicon layer to form the first doped layer, and partially penetrate the first dielectric layer to form the first doped region.

[0069] In step (7), the second dopant is POCl3, and the diffusion of POCl3 is performed at a temperature of 800-1000°C. During the diffusion process, POCl3 decomposes, P elements diffuse into the second intrinsic polysilicon layer to form the second doped layer, and partially penetrate the first and second dielectric layers to form the second doped region.

[0070] And P elements partially penetrate the third dielectric layer to form a hole for carrier transmission in the third dielectric layer.

[0071] Further, in step (2), the first dopant is POCl3, POCl3 diffusion is performed at a temperature of 800-1000℃, in the diffusion process, POCl3 decomposes, P element diffuses into the first intrinsic polysilicon layer to form the first doped layer, and partially penetrates the first dielectric layer to form the first doped region;

[0072] In step (7), the second dopant is BCl3 or BBr3, BCl3 or BBr3 diffusion is performed at a temperature of 850-1000℃, in the diffusion process, BCl3 or BBr3 decomposes, B element diffuses into the second intrinsic polysilicon layer to form the second doped layer, and partially penetrates the first sub-dielectric layer and the second dielectric layer to form the second doped region;

[0073] At the same time, P element partially penetrates the third dielectric layer to form a hole for carrier transport in the third dielectric layer.

[0074] Further, in step (7), the second dopant partially penetrates the third dielectric layer to form a third doped region in the first doped layer, or the first dopant partially penetrates the third dielectric layer to form a third doped region in the first doped layer.

[0075] Further, in step (7), the second dopant partially penetrates the third dielectric layer to form a third doped region in the first doped layer and a fourth doped region in the first doped region, or the first dopant partially penetrates the third dielectric layer to form a third doped region in the first doped layer and a fourth doped region in the first doped region.

[0076] Further, the preparation method further comprises step (8), removing a part of the second sub-dielectric layer located on the first doped layer and a part of the second sub-doped layer located on the second sub-dielectric layer.

[0077] Further, the preparation method further comprises step (8), removing a part of the second sub-dielectric layer located on the first doped layer and a part of the second sub-doped layer located on the second sub-dielectric layer.

[0078] Further, the preparation method further comprises step (9), in the plane parallel to the semiconductor substrate, the first doped layer and the second doped layer extend in a second direction perpendicular to the first direction, and along the second direction, the following first structure, second structure and third structure are removed at intervals:

[0079] (a) Intervals of the first structure: intervals of the second sub-doped layer and the second sub-dielectric layer located above the first doped layer are removed;

[0080] (b) interval removal of the second structure: interval removal of part of the third doped region, part of the third dielectric layer, part of the third doped layer, part of the first sub-doped layer, and part of the first sub-dielectric layer;

[0081] (c) interval removal of the third structure: interval removal of part of the third structure under the second structure until the surface of the semiconductor substrate is exposed;

[0082] After interval removal of the first structure, the second structure, and the third structure, at least one or more interval-distributed exposed semiconductor substrate surface regions are formed, which constitute insulation regions, and a leakage region is formed between two adjacent insulation regions.

[0083] Further, the preparation method further comprises step (9), in the plane parallel to the semiconductor substrate, the first doped layer and the second doped layer extend along a second direction perpendicular to the first direction, and along the second direction, the following first structure, second structure, and third structure are interval removed:

[0084] (a) interval removal of the first structure: interval removal of part of the second sub-doped layer and part of the second sub-dielectric layer above the first doped layer;

[0085] (b) interval removal of the second structure: interval removal of part of the third doped region, part of the fourth doped region, part of the third dielectric layer, part of the third doped layer, part of the first sub-doped layer, and part of the first sub-dielectric layer;

[0086] (c) interval removal of the third structure: interval removal of part of the third structure under the second structure until the surface of the semiconductor substrate is exposed;

[0087] After interval removal of the first structure, the second structure, and the third structure, at least one or more interval-distributed exposed semiconductor substrate surface regions are formed, which constitute insulation regions, and a leakage region is formed between two adjacent insulation regions.

[0088] Further, in steps (1) and (5), the first dielectric layer, the first sub-dielectric layer, the second dielectric layer, and the third dielectric layer are formed by thermal growth, and the growth temperature is 550-650°C, and the thickness is 1.0-2.5 nm.

[0089] Further, in steps (2) and (6), the first intrinsic polysilicon layer and the second intrinsic polysilicon layer are prepared by an LPCVD process at a temperature of 550-650°C, the thickness of the first intrinsic polysilicon layer is 20-400 nm, and the thickness of the second intrinsic polysilicon layer is 20-400 nm. BRIEF DESCRIPTION OF DRAWINGS

[0090] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0091] Figure 1 A three-dimensional structure diagram of the back contact battery in the prior art;

[0092] Figures 2(a) to 2(i) A structure diagram of each step in the preparation process of the back contact battery of the present application;

[0093] Figure 3 A three-dimensional diagram of the back contact battery cell of the present application;

[0094] Figure 4 A top view of the back contact battery of the present application;

[0095] Figure 5 A cross-sectional view of the back contact battery cell of the present application including a leakage area;

[0096] Figure 6 A cross-sectional view of the back contact battery cell of the present application including a leakage area;

[0097] Figure 7 A cross-sectional view of the back contact battery cell of the present application including a leakage area;

[0098] Figure 8 A cross-sectional view of the back contact battery cell of the present application including a leakage area;

[0099] Figure 9 A cross-sectional view of the back contact battery cell of the present application including a leakage area;

[0100] In the drawings, 101. semiconductor substrate, 102. first dielectric layer, 103. second dielectric layer, 1031. first sub-dielectric layer, 1032. second sub-dielectric layer, 1033. third dielectric layer, 104. first doped layer, 105. second doped layer, 1051. first sub-doped layer, 1052. second sub-doped layer, 1053. third doped layer, 106. first doped region, 107. second doped region, 109. third doped region, 110. hole, 111. fourth doped region, 112. insulating region, 113. leakage region, 114. removal region, 201. semiconductor substrate, 202. first dielectric layer, 203. second dielectric layer, 204. first doped layer, 205. second doped layer, 212. isolation region. DETAILED DESCRIPTION

[0101] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0102] The present application provides a preparation process of a back contact cell, specifically comprising:

[0103] Step (1), forming a first dielectric layer 102 on the back side of the semiconductor substrate 101;

[0104] Step (2), as shown in FIG. 2(a), growing a first intrinsic polysilicon layer on the first dielectric layer 102, diffusing a first dopant into the first intrinsic polysilicon layer to form a first doped layer 104, the dopant locally penetrates the first dielectric layer 102 along the thickness direction of the semiconductor substrate 101, forming a hole 110 in the first dielectric layer 102 for carrier transmission, and the dopant diffuses into the substrate 101 to form a first doped region 106;

[0105] Step (3), as shown in FIG. 2(b), forming a second sub-dielectric layer 1032 on the first doped layer 104;

[0106] Step (4), as shown in FIG. 2(c), removing a part of the formed second sub-dielectric layer 1032, first doped layer 104, first dielectric layer 102 and first doped region 106 on the back side of the semiconductor substrate 101, exposing the surface of the silicon substrate 101 after removing the first doped region 106;

[0107] Step (5), as shown in FIG. 2(d), growing a first sub-dielectric layer 1031 and a second dielectric layer 103 on the exposed surface of the silicon substrate 101, and growing a third dielectric layer 1033 along the thickness direction of the semiconductor substrate 101 on the side surface of the remaining first doped region 106, first dielectric layer 102, first doped layer 104 and second sub-dielectric layer 1032, the first sub-dielectric layer 1031, second dielectric layer 103 and third dielectric layer 1033 are formed integrally in this step; and there is a height difference between the first sub-dielectric layer 1031, second dielectric layer 103 and first dielectric layer 102;

[0108] Step (6), as shown in Fig. 2 (e), growing a second intrinsic polysilicon layer on the upper surface of the first sub dielectric layer 1031, the second dielectric layer 103 and the side surface of the third dielectric layer 1033, and the upper surface of the second sub dielectric layer 1032, a part of the second intrinsic polysilicon layer is adjacent to the surface of the semiconductor substrate 101 through the first sub dielectric layer 1031 and the second dielectric layer 103, a part of the second intrinsic polysilicon layer is adjacent to the side surface of the remaining first doped region 106, the first dielectric layer 102, the first doped layer 104 and the second sub dielectric layer 1032 through the third dielectric layer 1033, and a part of the second intrinsic polysilicon layer is adjacent to the first doped layer 104 through the second sub dielectric layer 1032;

[0109] Step (7), diffusing the second dopant into the second intrinsic polysilicon layer, including: doping the part of the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the first sub dielectric layer 1031 to form the first sub doped layer 1051, doping the part of the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the second dielectric layer 103 to form the second doped layer 105, doping the part of the second intrinsic polysilicon layer adjacent to the side surface of the remaining first doped region 106, the first dielectric layer 102, the first doped layer 104 and the second sub dielectric layer 1032 through the third dielectric layer 1033 to form the third doped layer 1053, and doping the part of the second intrinsic polysilicon layer adjacent to the first doped layer 104 through the second sub dielectric layer 1032 to form the second sub doped layer 1052.

[0110] The second dopant also partially penetrates the first sub dielectric layer 1031 and the second dielectric layer 103 in the thickness direction of the substrate 101, forming a hole 110 for carrier transmission in the first sub dielectric layer 1031 and the second dielectric layer 103, and the second dopant diffuses into the substrate 101 to form the second doped region 107.

[0111] If the first dopant is a P-type dopant and the second dopant is an N-type dopant, in step (7), while the second dopant diffuses to form the second doped layer 105 and the second doped region 107, the second dopant also partially penetrates the third dielectric layer 1033 to diffuse into the first doped layer 104 and the first doped region 106, forming a hole 110 for carrier transmission in the third dielectric layer 1033, a third doped region 109 in the first doped layer 104 and a fourth doped region 111 in the first doped region 106, as shown in Fig. 2 (f).

[0112] If the first dopant is an N-type dopant and the second dopant is a P-type dopant, in step (7), the first dopant diffuses into the third doped layer 1053 through the third medium layer 1033, forming a hole 110 for carrier transmission in the third medium layer 1033, and forming the third doped region 109 and the fourth doped region 111 in the third doped layer 1053, as shown in Fig. 2(g).

[0113] In step (8), as an example, the second sub-medium layer 1032 above the first doped layer 104 and the second sub-doped layer 1052 above the second sub-medium layer 1032 are removed in the plane parallel to the semiconductor substrate 101, as shown in Fig. 2(h).

[0114] In step (9), as an example, the first doped layer 104 and the second doped layer 105 are arranged in the first direction and extend in the second direction perpendicular to the first direction, as shown in Fig. 2(i). Figure 3

[0115] (a) The first structure is removed in intervals: the second sub-medium layer 1032 above the first doped layer 104 and the second sub-doped layer 1052 are removed in intervals.

[0116] (b) The second structure is removed in intervals: the third doped region 109, the fourth doped region 111, the third medium layer 1033, the third doped layer 1053, the first sub-doped layer 1051, and the first sub-medium layer 1031 are removed in intervals.

[0117] (c) The third structure is removed in intervals: the third structure below the second structure is removed in intervals until the surface of the semiconductor substrate is exposed.

[0118] After the interval removal of the region 114, at least one or more exposed semiconductor substrate surface regions are formed in intervals, which are the insulating regions 112, and the leakage regions 113 are formed between two adjacent insulating regions.

[0119] ​Since the third doped region 109 and the fourth doped region 111 formed in step (7) can make the carriers generated in the operation of the cell recombine, reducing the operation efficiency of the cell, in step (9), by reserving a small amount of leakage region 113 along the second direction at intervals, removing the region 114 in sections, and forming the insulating region 112 at intervals, the efficiency loss caused by recombination can be reduced, and enough leakage region 113 is reserved to reduce the risk of hot spots.

[0120] Preferably, in steps (1) and (5), the first dielectric layer 102 and the second dielectric layer 103 are formed by thermal growth, the growth temperature is 550-650°C, and the thickness is 1.0-2.5 nm.

[0121] Preferably, in steps (2) and (6), the first intrinsic polysilicon layer and the second intrinsic polysilicon layer are prepared by LPCVD process at a temperature of 550-650°C, the thickness of the first intrinsic polysilicon layer is 20-400 nm, and the thickness of the second intrinsic polysilicon layer is 20-400 nm.

[0122] Preferably, in steps (2) and (7), the P-type dopant is BCl3 or BBr3, BCl3 or BBr3 diffusion is carried out at a temperature of 850-1000°C, in the diffusion process, BCl3 or BBr3 decomposes, B element diffuses into the intrinsic polysilicon layer to form a doped layer, and locally penetrates the dielectric layer below it to form a hole 110 in the dielectric layer and a doped region in the substrate 101 below the dielectric layer; the N-type dopant is POCl3, POCl3 diffusion is carried out at a temperature of 800-1000°C, in the diffusion process, POCl3 decomposes, P element diffuses into the intrinsic polysilicon layer to form a doped layer, and locally penetrates the dielectric layer below it to form a hole 110 in the dielectric layer and a doped region in the substrate 101 below the dielectric layer, and the P element can penetrate the third dielectric layer 1033 and form a hole 110 therein, while the P element diffuses to form the third doped region 109 and the fourth doped region 111.

[0123] In addition, in the present solution, in step (4), a part of the formed second sub dielectric layer 1032, the first doped layer 104 and the first dielectric layer 102 can be removed from the back side of the semiconductor substrate 101, in step (5), the first sub dielectric layer 1031 and the second dielectric layer 103 can be grown at the position flush with the first dielectric layer 102, and the third dielectric layer 1033 can be grown along the thickness direction of the substrate 101 at the side of the first dielectric layer 102, the first doped layer 104 and the second sub dielectric layer 1032, and the subsequent steps (5)-(9) can be continued. Since the first dielectric layer 102 is flush with the first sub dielectric layer 1031 and the second dielectric layer 103 in step (4), only the third doped region 109 can be formed in the first or third doped layer in step (7).

[0124] The preparation process of the back contact cell provided by the present solution has the following advantages:

[0125] (1) The present solution forms the leakage region with interval distribution between the first doped layer 104 and the second doped layer 105, the leakage region is formed by forming the dielectric layer 1033 between two adjacent first doped layers 104 and second doped layers 105 with different conductive types, and the nanoscale and uniformly distributed holes 110, i.e., the leakage channels, are formed in the dielectric layer 1033 for the carriers to pass through. Compared with the random distribution of the leakage region formed by the two doped layers in the prior art, the leakage region is less and not uniformly distributed. The leakage region with interval distribution formed by the present solution can improve the leakage capacity of the cell, reduce the reverse bias voltage between the two ends of the cell when it is shielded, thereby reducing the heating power when it is shielded, and thus reducing the risk of hot spot of the cell. At the same time, the control requirement for low leakage current in the prior art is cancelled, and the productivity of the cell is improved.

[0126] (2) The holes 110 formed in the third dielectric layer 1033 between the two doped layers can make the carriers directly pass through, which greatly reduces the transmission resistance of the carriers passing through the third dielectric layer 1033 compared with the direct tunneling to realize the leakage channel, and thus the conduction effect of the leakage channel formed by the holes 110 is remarkable.

[0127] (3) The present solution can realize the accurate control of the size of the holes 110, such as Figure 9The third dielectric layer 1033 has two locations of texture discontinuity, i.e. the nano-sized holes 110. The holes 110 formed by the present application are in the nano scale, thus reducing the damage to the third dielectric layer 1033. The third dielectric layer 1033 still has good passivation effect after the holes 110 are formed, thus avoiding the reduction of the efficiency of the back contact cell. If the third dielectric layer 1033 is etched by a chemical method to form holes in the micron scale or larger, on one hand, it is unable to form uniformly distributed leakage channels, and the hot spot reduction effect is not obvious. On the other hand, it seriously damages the dielectric layer and causes the passivation effect of the dielectric layer to decrease significantly, thus reducing the efficiency of the cell.

[0128] (4) The present application can be based on the existing back contact cell preparation process. First, a dielectric layer 1033 is formed on the side of a doped layer. Then, in the process of forming another doped layer, the dopant is diffused through the dielectric layer 1033 between the two doped layers to form uniformly distributed holes 110 as leakage channels. The process is simple and does not require additional processes to form leakage channels.

[0129] The back contact cells in Embodiment 1-Embodiment 4 are prepared by using the back contact cell preparation process provided by the present application.

[0130] Embodiment 1

[0131] Embodiment 1 provides a back contact cell, which includes a plurality of back contact cell units arranged along a first direction, as shown in Figure 4 .

[0132] Each back contact cell unit includes a semiconductor substrate 101, a first conductive type structure, a second conductive type structure, and at least one leakage region 113, as shown in Figure 3 . Figure 4 The first conductive type structure and the second conductive type structure are arranged on the back side of the semiconductor substrate 101 along the first direction in parallel to the plane of the semiconductor substrate 101, and extend along a second direction perpendicular to the first direction.

[0133] Figure 5 The cross-sectional view of each back contact cell unit including the leakage region 113 in the present embodiment is shown in

[0134] The first doped layer 104 and the second doped layer 105 are arranged on the backside of the semiconductor substrate with a spacing, and the first doped layer 104 and the second doped layer 105 are opposite in conductive type. The first doped layer 104 is located on the first dielectric layer 102, and the second doped layer 105 is located on the second dielectric layer 103, as shown in Figure 5 The surface of the two dielectric layers 102 and 103 has a height difference h, 0 < h ≤ 4 μm.

[0135] The leakage region 113 includes a third dielectric layer 1033 and a third doped layer 1053 formed along the thickness direction of the semiconductor substrate. The third doped layer 1053 has the same conductive type as the second doped layer 105, and along the thickness direction of the semiconductor substrate 101, the third doped layer 1053 is adjacent to the side surface of the first doped layer 104 through the third dielectric layer 1033. In addition, the leakage region 113 can also include a first sub-dielectric layer 1031 and a first sub-doped layer 1051, and a second sub-dielectric layer 1032 and a second sub-doped layer 1052. The first sub-dielectric layer 1031, the third dielectric layer 1033 and the second dielectric layer 103 are formed integrally in the same step, and the first sub-doped layer 1051, the second sub-doped layer 1052 and the third doped layer 1053 are formed integrally in the same step.

[0136] In the embodiment, the second doped layer 105 is an N-type doped layer, and the first doped layer 104 is a P-type doped layer. In the step of forming the second doped layer 105, the first sub-doped layer 1051, the second sub-doped layer 1052 and the third doped layer 1053, there are also: (1) N-type dopants diffuse through the third dielectric layer 1033 to form nanoscale and uniformly distributed carrier transport holes 110 in the third dielectric layer 1033, to locally conduct the second doped layer 105 and the first doped layer 104; and the N-type dopants penetrate the third dielectric layer 1033 to form a third doped region 109 in the first doped layer 104, and a fourth doped region 111 in the first doped region 106; (2) N-type dopants diffuse through the second dielectric layer 103 to form holes 110 therein, and form a second doped region 107 below the second dielectric layer 103 in the substrate.

[0137] The first doped region 106 and the second doped region 107 are formed by penetrating the first dielectric layer 102 and the second dielectric layer 103 respectively by P-type dopants and N-type dopants, so that the doping concentration of the first doped region 106 and the second doped region 107 gradually decreases in the semiconductor substrate 101 along the direction away from the back surface of the substrate. The third doped region 109 and the fourth doped region 111 are formed in the first doped layer 104 and the first doped region 106 respectively by penetrating the third dielectric layer 1033 by N-type dopants, so that the highest doping concentration of the third doped region 109 is less than the doping concentration of the second doped layer 105, and the lowest doping concentration is equal to the doping concentration of the first doped layer 104, and the highest doping concentration of the fourth doped region 111 is less than the doping concentration of the second doped layer 105, and the lowest doping concentration is equal to the doping concentration of the first doped region 106 at the same depth position as the fourth doped region 111.

[0138] Specifically, the first doped layer 104 is a boron-doped polysilicon layer with a thickness of 300 nm and a doping concentration of 6.5E19atm / cm 3 .

[0139] The second doped layer 105 is a phosphorus-doped polysilicon layer with a thickness of 200 nm and a doping concentration of 7E20atm / cm 3 .

[0140] The first doped region 106 has a depth of 0.4 μm and a highest doping concentration of 6.5E19atm / cm 3 .

[0141] The second doped region 107 has a depth of 0.35 μm and a highest doping concentration of 7E20atm / cm 3 .

[0142] The third doped region 109 and the fourth doped region 111 are phosphorus-doped polysilicon layers, and the higher the doping concentration and the deeper the doping depth, the better the leakage effect between the first and second doped layers 104 and 105. Therefore, in the present embodiment, the depth of the third doped region 109 and the fourth doped region 111 along the first direction is 0.06 μm, and the highest doping concentration is 6.35E20atm / cm 3 .

[0143] In the present example, the contact resistance between the third doped region 109, the fourth doped region 111 and the third doped layer 1053 is 1.7 mohmcm 2The lower the contact resistance, the stronger the conduction of charge carriers between the first doped layer 104 and the second doped layer 105, and the higher the leakage current capability. Therefore, in addition to controlling the concentration of the dopant and the diffusion temperature, the thickness of the third dielectric layer 1033 between the first doped layer 104 and the second doped layer 105 is controlled. This reduces the contact resistance by decreasing the thickness of the dielectric layer and increasing the density of the pores 110 therein.

[0144] Specifically, the thickness of the second dielectric layer 103, the first sub-dielectric layer 1031, and the third dielectric layer 1033 is 1.6 nm. Additionally, the thickness of the first dielectric layer 102 is 1.9 nm. In the fabrication process, to protect the underlying first doped layer 104, the thickness of the second sub-dielectric layer 1032 is relatively large, often set to the tens to hundreds of nanometers, much greater than the thickness of the first dielectric layer 102 and the second dielectric layer 103. In this embodiment, the thickness of the second sub-dielectric layer 1032 is 28 nm.

[0145] like Figure 4 As shown, the back contact battery of this embodiment includes multiple back contact battery cells arranged along a first direction. In each back contact battery cell, one or more spaced insulating regions 112 are included between the first conductivity type structure and the second conductivity type structure. In the first direction, the width D2 of the first doped layer 104 is 400 μm, the width D3 of the second doped layer 105 is 400 μm, and the width X1 of the second sub-doped layer 1052 in the leakage region 113 on the first doped layer 104 is 150 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 500 μm.

[0146] In this embodiment, the number of the third doped region 109 and the fourth doped region 111 are 300 each.

[0147] Example 2

[0148] Example 2 provides a back contact battery, such as Figure 6 The diagram shows a cross-sectional view of the back contact battery cell in Embodiment 2, including the leakage region 113. Unlike Embodiment 1, the back contact battery cell in Embodiment 2 first grows an N-type doped layer as the first doped layer 104 and then grows a P-type doped layer as the second doped layer 105. Therefore, the N-type dopant penetrates the third dielectric layer 1033 and forms the third doped region 109 and the fourth doped region 111 in the third doped layer 1053.

[0149] The thickness of the first dielectric layer 102 is 1.8 nm, and the thickness of the second dielectric layer 103 is 1.4 nm.

[0150] The first doped layer 104 is a phosphorus-doped polycrystalline silicon layer with a thickness of 220 nm and a doping concentration of 6E20 atm / cm². 3 .

[0151] The first doped region, 106, has a depth of 0.4 μm and a maximum doping concentration of 6E20 atm / cm². 3 .

[0152] The second doped layer 105 is a boron-doped polycrystalline silicon layer with a thickness of 250 nm and a doping concentration of 7E19 atm / cm². 3 .

[0153] The second doped region, 107, has a depth of 0.35 μm and a maximum doping concentration of 7E19 atm / cm². 3 .

[0154] The third doped region 109 and the fourth doped region 111 are phosphorus-doped polycrystalline silicon layers with a depth of 0.08 μm and a maximum doping concentration of 5.3E20 atm / cm². 3 It is located within the third doped layer 1053.

[0155] The thickness of the second sub-dielectric layer 1032 is 30 nm.

[0156] The contact resistance between the third doped region 109 and the first doped layer 104 is 1.5 mol / cm². 2 .

[0157] The contact resistance between the fourth doped region 111 and the first doped region 106 is 1.5 mol / cm². 2 .

[0158] like Figure 4 As shown, along the first direction, the width D2 of the first doped layer is 450 μm, the width D3 of the second doped layer is 400 μm, and the width X1 of the second sub-doped layer 1052 on the first doped layer 104 is 160 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 450 μm.

[0159] The number of third doped regions 109 is 200, and the number of fourth doped regions 111 is 200.

[0160] Example 3

[0161] Example 3 provides a back contact battery, such as Figure 7The diagram shows a cross-sectional view of the back contact battery cell in Embodiment 3, including the leakage region 113. Unlike Embodiments 1 and 2, in step (4), a portion of the already formed second sub-dielectric layer 1032, first doped layer 104, and first dielectric layer 102 are removed on the back surface side of the semiconductor substrate 101. In step (5), a second dielectric layer 103 and a first sub-dielectric layer 1031 are grown at a position flush with the first dielectric layer 102. The first doped layer 104 is a P-type doped layer, and the second doped layer 105 is an N-type doped layer. Therefore, in step (7), a third doped region 109 is formed only in the first doped layer 105.

[0162] The thickness of the first dielectric layer 102 is 1.7 nm, and the thickness of the second dielectric layer 103 is 1.5 nm.

[0163] The first doped layer 104 is a boron-doped polycrystalline silicon layer with a thickness of 250 nm and a doping concentration of 6E19 atm / cm². 3 .

[0164] The first doped region, 106, has a depth of 0.4 μm and a maximum doping concentration of 6E19 atm / cm². 3 .

[0165] The second doped layer 105 is a phosphorus-doped polycrystalline silicon layer with a thickness of 200 nm and a doping concentration of 5E20 atm / cm². 3 .

[0166] The second doped region, 107, has a depth of 0.35 μm and a maximum doping concentration of 5E20 atm / cm. 3 .

[0167] The third doped region 109 is a phosphorus-doped polycrystalline silicon layer with a depth of 0.1 μm and a maximum doping concentration of 4.4E20 atm / cm². 3 It is located within the first doped layer 104.

[0168] The contact resistance between the third doped region 109 and the third doped layer 1053 is 1 mol / cm². 2 .

[0169] like Figure 4 As shown, along the first direction, the width D2 of the first doped layer is 400 μm, the width D3 of the second doped layer is 350 μm, and the width X1 of the second sub-doped layer 1052 on the first doped layer 104 is 150 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 400 μm.

[0170] The number of third doped regions 109 is 100.

[0171] Example 4

[0172] Embodiment 4 provides a back contact cell, as Figure 8 The cross-sectional view of the back contact cell unit in Embodiment 4 including the leakage region 113 is shown, which is different from Embodiments 1 and 2 in that, in step (4), a part of the second sub dielectric layer 1032, the first doped layer 104, and the first dielectric layer 102 formed on the back side of the semiconductor substrate 101 are removed, in step (5), the second dielectric layer 103 and the first sub dielectric layer 1031 are grown at the level of the first dielectric layer 102, and the first doped layer 104 is an N-type doped layer and the second doped layer 105 is a P-type doped layer, so that in step (7), only the third doped region 109 is formed in the third doped layer 1053.

[0173] The thickness of the first dielectric layer 102 is 1.8 nm and the thickness of the second dielectric layer 103 is 1.4 nm.

[0174] The first doped layer 104 is a phosphorus-doped polysilicon layer with a thickness of 220 nm and a doping concentration of 6E20atm / cm 3 .

[0175] The first doped region 106 has a depth of 0.4 μm and a maximum doping concentration of 6E20atm / cm 3 .

[0176] The second doped layer 105 is a boron-doped polysilicon layer with a thickness of 250 nm and a doping concentration of 7E19atm / cm 3 .

[0177] The second doped region 107 has a depth of 0.35 μm and a maximum doping concentration of 7E19atm / cm 3 .

[0178] The third doped region 109 is a phosphorus-doped polysilicon layer with a depth of 0.08 μm and a maximum doping concentration of 5.3E20atm / cm 3 , located in the third doped layer 1053.

[0179] The thickness of the second sub dielectric layer 1032 is 30 nm.

[0180] The contact resistance between the third doped region 109 and the first doped layer 104 is 1.5 mohmcm 2 .

[0181] As Figure 4As shown, along the first direction, the width D2 of the first doped layer 104 is 450 μm, the width D3 of the second doped layer 105 is 400 μm, and the width X1 of the second sub-doped layer 1052 on the first doped layer 104 is 160 μm. Along the second direction, the length W of the second sub-doped layer 1052 on the first doped layer 104 is 350 μm.

[0182] The number of the third doped regions 109 is 200.

[0183] The back contact cell structure provided in Embodiment 1 of the present application is tested according to the following test method. Figure 3 As the number of the leakage areas 113 retained between the first conductive type structure and the second conductive type structure is different, as Test Examples 1-4, the number of the leakage areas 113 gradually increases from Test Example 1 to Test Example 4, and the test results are compared with those of Comparative Example 1. Figure 1 The back contact cell of the prior art is tested as Comparative Example 1, and the test result data are shown in Table 1. As shown in Table 1, in the comparative example, the reverse saturation current is small, the maximum reverse voltage is too large, and the maximum hot spot temperature is as high as 160℃, which is easy to burn the back plate of the cell, because the number of the leakage conduction structures randomly existing between the two doped layers is small and the distribution is uneven. In Test Examples 1-4, as the nano-sized, uniformly distributed multiple leakage conduction structures are arranged between the first doped layer and the second doped layer, and as the number of the leakage areas 113 increases, the reverse protection current increases, the maximum reverse voltage decreases, and the maximum hot spot temperature can be reduced to 140℃ or even 100℃, which greatly reduces the risk of hot spots.

[0184] Table 1 Test results of Test Examples 1-4 and Comparative Example 1

[0185] Comparative Example Reverse Saturation Current Maximum Reverse Voltage Maximum Hot Spot Temperature Efficiency Gain Comparative Example 1 0.2A 17V 160℃ / Test Example 1 5A 15V 140℃ -0.05％ Test Example 2 10A 12V 130℃ -0.08％ Test Example 3 20A 7V 120℃ -0.1％ Test Example 4 20A 4V 100℃ -0.12％

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A back-contact battery, comprising a plurality of back-contact battery cells, each back-contact battery cell comprising: A semiconductor substrate, a first conductivity type structure, a second conductivity type structure, and at least one leakage region. The first conductivity type structure includes a first dielectric layer and a first doped layer, and the second conductivity type structure includes a second dielectric layer and a second doped layer; There is at least one leakage region between the first conductivity type structure and the second conductivity type structure. On a plane parallel to the semiconductor substrate, the first conductivity type structure and the second conductivity type structure are arranged at intervals along a first direction on one side of the backlight surface of the semiconductor substrate, and the first conductivity type structure and the second conductivity type structure extend along a second direction, with the first direction being perpendicular to the second direction. The first dielectric layer and the second dielectric layer are formed on the back side of the semiconductor substrate. The first doped layer is located on the first dielectric layer, and the second doped layer is located on the second dielectric layer. The first doped layer and the second doped layer have opposite conductivity types. The feature is that the leakage region includes: a third dielectric layer and a third doped layer formed along the thickness direction of the semiconductor substrate, wherein the third doped layer has the same conductivity type as the second doped layer, and along the thickness direction of the semiconductor substrate, the third doped layer is adjacent to the side of the first doped layer through the third dielectric layer, wherein the first dopant of the first doped layer or the second dopant of the second doped layer diffuses through the third dielectric layer, forming a hole for carrier transport in a local area of ​​the third dielectric layer, thereby locally connecting the second doped layer and the first doped layer.

2. A back contact battery according to claim 1, characterized in that, In the third dielectric layer, the pores are nanoscale.

3. A back contact battery according to claim 1, characterized in that, In the third dielectric layer, the pores are evenly distributed.

4. A back contact battery according to any one of claims 1-3, characterized in that, The first dielectric layer and the second dielectric layer are flush with each other or have a height difference along the thickness direction of the semiconductor substrate, and the height difference is less than or equal to 4 μm.

5. A back contact battery according to claim 4, characterized in that, The first dielectric layer and the second dielectric layer are flush along the thickness direction of the semiconductor substrate; The first conductivity type structure further includes a first doped region, wherein the first dopant of the first doped layer penetrates the first dielectric layer to form a first doped region inside the semiconductor substrate; The second conductivity type structure further includes a second doped region, wherein the second dopant of the second doped layer penetrates the second dielectric layer to form a second doped region inside the semiconductor substrate; The leakage region also includes a third doped region, which is formed by the diffusion of a first dopant through the third dielectric layer within the third doped layer, or by the diffusion of a second dopant through the third dielectric layer within the first doped layer.

6. A back contact battery according to claim 4, characterized in that, The first dielectric layer and the second dielectric layer have a height difference along the thickness direction of the semiconductor substrate. The first conductivity type structure further includes a first doped region, wherein the first dopant of the first doped layer penetrates the first dielectric layer to form a first doped region inside the semiconductor substrate; The second conductivity type structure further includes a second doped region, wherein the second dopant of the second doped layer penetrates the second dielectric layer to form a second doped region inside the semiconductor substrate; The leakage region further includes a third doped region and a fourth doped region. The third doped region and the fourth doped region are formed in the third doped layer by the diffusion of the first dopant through the third dielectric layer, or the third doped region and the fourth doped region are formed in the first doped layer and the first doped region by the diffusion of the second dopant through the third dielectric layer.

7. A back contact battery according to claim 5, characterized in that, In the leakage region, the first dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the first doped layer is 0.01-100 mol / cm². 2 ; Alternatively, the second dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the third doped layer is 0.01-100 mol / cm². 2 .

8. A back contact battery according to claim 6, characterized in that, In the leakage region, the first dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the first doped layer is 0.01-100 mol / cm². 2 The contact resistance between the fourth doped region and the first doped layer is 0.01-100 mol / cm². 2 ; Alternatively, the second dopant diffuses through the third dielectric layer, and the contact resistance between the third doped region and the third doped layer is 0.01-100 mol / cm². 2 The contact resistance between the fourth doped region and the third doped layer is 0.01-100 mol / cm². 2 .

9. A back contact battery according to claim 5, characterized in that, The third doped region is formed within the third doped layer by the diffusion of the first dopant through the third dielectric layer. The highest doping concentration of the third doped region is less than the doping concentration of the first doped layer, and the lowest doping concentration is equal to the concentration of the third doped layer. Alternatively, the third doped region may be formed within the first doped layer by the diffusion of the second dopant through the third dielectric layer, wherein the highest doping concentration of the third doped region is less than the doping concentration of the third doped layer, and the lowest doping concentration is equal to the doping concentration of the first doped layer.

10. A back contact battery according to claim 6, characterized in that, The third and fourth doped regions are formed within the third doped layer by the diffusion of the first dopant through the third dielectric layer. The highest doping concentration of the third and fourth doped regions is less than the doping concentration of the first doped layer, and the lowest doping concentration of the third and fourth doped regions is equal to the concentration of the third doped layer. Alternatively, the third and fourth doped regions may be formed by the diffusion of the second dopant through the third dielectric layer within the first doped layer and the first doped region, respectively. The highest doping concentration of the third and fourth doped regions is less than the doping concentration of the third doped layer, the lowest doping concentration of the third doped region is equal to the concentration of the first doped layer, and the lowest doping concentration of the fourth doped region is equal to the doping concentration at the same depth within the first doped region.

11. A back contact battery according to claim 9 or 10, characterized in that, The third doped layer is the same as the second doped layer and is integrally formed in the same process. The doping concentration of the third doped layer is equal to the doping concentration of the second doped layer.

12. A back contact battery according to claim 5, characterized in that, The doping concentration of the first doped region, the second doped region, and the third doped region gradually decreases in the semiconductor substrate along the direction away from the back surface of the substrate.

13. A back contact battery according to claim 6, characterized in that, The doping concentration of the first doped region, the second doped region, the third doped region, and the fourth doped region gradually decreases in the semiconductor substrate along the direction away from the back surface of the substrate.

14. A back-contact battery according to claim 5 or 6, characterized in that, The highest doping concentration of the higher doping region among the first and second doping regions is 1E20-1E21 atm / cm³. 3 The highest doping concentration of the one with the lower concentration is 1E19-1E20 atm / cm³. 3 .

15. A back contact battery according to claim 5 or 6, characterized in that, Along the thickness direction of the semiconductor substrate, the depth of the first doped region is 0.01μm-0.6μm, and the depth of the second doped region is 0.01μm-0.6μm.

16. A back contact battery according to claim 5, characterized in that, Along the first direction, the depth of the third doped region is 0.001 μm-0.3 μm.

17. A back contact battery according to claim 6, characterized in that, Along the first direction, the depths of the third doped region and the fourth doped region are both 0.001 μm to 0.3 μm.

18. A back contact battery according to any one of claims 1-3, characterized in that, The thickness of the first dielectric layer is 1.0 nm-2.5 nm, and the thickness of the second dielectric layer is 1.0 nm-2.5 nm.

19. A back contact battery according to any one of claims 1-3, characterized in that, The leakage region further includes: a first sub-doped layer and a first sub-dielectric layer. The first sub-dielectric layer is located on the semiconductor substrate. Along the first direction, one side of the first sub-dielectric layer is connected to the third dielectric layer, and the other side is connected to the second dielectric layer. The first sub-doped layer is located on the first sub-dielectric layer. Along the first direction, one side is connected to the third doped layer and the other side is connected to the second doped layer. The first sub-doped layer has the same conductivity type as the third doped layer and the second doped layer.

20. A back contact battery according to claim 19, characterized in that, The first sub-doped layer, the third doped layer, and the second doped layer are integrally formed in the same process, and the first sub-dielectric layer, the second dielectric layer, and the third dielectric layer are integrally formed in the same process.

21. A back contact battery according to any one of claims 1-3, characterized in that, The leakage region includes: a second sub-doped layer and a second sub-dielectric layer. The second sub-dielectric layer is located on the first doped layer, and in the first direction, one side of the second sub-dielectric layer is connected to the third dielectric layer. The second sub-doped layer is located on the second sub-dielectric layer. In the first direction, one side of the second sub-doped layer is connected to the third doped layer. The second sub-doped layer and the third doped layer have the same conductivity type.

22. A back contact battery according to claim 21, characterized in that, The second sub-doped layer, the third doped layer, and the second doped layer are integrally formed in the same process.

23. A back contact battery according to claim 21, characterized in that, The thickness of the second sub-dielectric layer is 5nm-100nm.

24. A back contact battery according to claim 21, characterized in that, In each of the back contact battery cells, the first conductive type structure and the second conductive type structure are strip-shaped regions extending along the second direction, and the first conductive type structure and the conductive type structure are parallel and spaced apart.

25. A back contact battery according to claim 24, characterized in that, In each of the back contact battery cells, at least one insulating region is included between the first conductive type structure and the second conductive type structure.

26. A back contact battery according to claim 25, characterized in that, In each back-contact battery cell, along the first direction, the width of the insulating region is D1, the width of the first doped layer is D2, and the width of the second doped layer is D3, where 20μm≤D1≤500μm, 100μm≤D2≤800μm, and 100μm≤D3≤800μm.

27. A back contact battery according to claim 26, characterized in that, Along the first direction, the width of the second sub-doped layer on the first doped layer is X1, X1 < (1 / 2)D2, and along the second direction, the length of the second sub-doped layer on the first doped layer is W, 5μm ≤ W ≤ 600μm.

28. A back contact battery according to claim 5, characterized in that, When the back contact battery is a whole back contact battery, the number of third doped regions in the back contact battery is N1, 20≤N1≤8000; when the back contact battery is a 1 / N segment back contact battery, the number of third doped regions in the back contact battery is N2, 30 / N≤N2≤8000 / N, where N is a positive integer greater than or equal to 2.

29. A back contact battery according to claim 6, characterized in that, When the back contact battery is a whole back contact battery, the number of the third doped region and the fourth doped region of the back contact battery is N1, and 20≤N1≤8000; when the back contact battery is a 1 / N segment back contact battery, the number of the third doped region and the fourth doped region of the back contact battery is N2, and 30 / N≤N2≤8000 / N, where N is a positive integer greater than or equal to 2.

30. A method for preparing a back-contact battery cell, characterized in that, Includes the following steps: Step (1): A first dielectric layer is formed on the backlight side of the semiconductor substrate; Step (2): A first intrinsic polysilicon layer is grown on the first dielectric layer, and a first dopant is diffused into the first intrinsic polysilicon layer to form a first doped layer. The first dopant partially penetrates the first dielectric layer along the thickness direction of the semiconductor substrate and diffuses into the semiconductor substrate to form a first doped region. Step (3): A second sub-dielectric layer is formed on the first doped layer; Step (4): Remove a portion of the already formed second sub-dielectric layer, first doped layer, and first dielectric layer on the back side of the semiconductor substrate; Step (5): A first sub-dielectric layer and a second dielectric layer are grown on the surface of the semiconductor substrate, and a third dielectric layer is grown along the thickness direction of the semiconductor substrate on the side of the remaining first dielectric layer, first doped layer and second sub-dielectric layer. The first sub-dielectric layer, the second dielectric layer and the third dielectric layer are integrally formed in this step. Step (6): A second intrinsic polysilicon layer is grown on the upper surface of the first sub-dielectric layer and the second dielectric layer, the side surface of the third dielectric layer, and the upper surface of the second sub-dielectric layer. A portion of the second intrinsic polysilicon layer is adjacent to the surface of the semiconductor substrate through the first sub-dielectric layer and the second dielectric layer. A portion of the second intrinsic polysilicon layer is adjacent to the side surface of the remaining first dielectric layer, the first doped layer, and the second sub-dielectric layer through the third dielectric layer. A portion of the second intrinsic polysilicon layer is adjacent to the first doped layer through the second sub-dielectric layer. Step (7) involves diffusing the second dopant into the second intrinsic polysilicon layer, including: forming a first sub-doped layer by partially doping the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the first sub-dielectric layer; forming a second doped layer by partially doping the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the second dielectric layer; forming a third doped layer by partially doping the second intrinsic polysilicon layer adjacent to the side of the remaining first dielectric layer, first doped layer, and second sub-dielectric layer through the third dielectric layer; and forming a second sub-doped layer by partially doping the second intrinsic polysilicon layer adjacent to the first doped layer through the second sub-dielectric layer. The second dopant also partially penetrates the first sub-dielectric layer and the second dielectric layer along the thickness direction of the substrate, and diffuses into the substrate to form a second doped region; Simultaneously, the second dopant partially penetrates the third dielectric layer, or the first dopant partially penetrates the third dielectric layer, forming a hole in the third dielectric layer through which charge carriers pass.

31. The method for preparing a back contact battery cell according to claim 30, characterized in that, In step (7), the second dopant partially penetrates the third dielectric layer and forms a third doped region in the first doped layer, or the first dopant partially penetrates the third dielectric layer and forms a third doped region in the third doped layer.

32. The method for preparing a back contact battery cell according to claim 31, characterized in that, It also includes step (8), removing a portion of the second sub-dielectric layer located on the first doped layer and the second sub-doped layer located on the second sub-dielectric layer.

33. The method for preparing a back contact battery cell according to claim 32, characterized in that, The process also includes step (9), in which the first doped layer and the second doped layer are arranged at intervals along a first direction on a plane parallel to the semiconductor substrate, and the first doped layer and the second doped layer extend along a second direction, which is perpendicular to the first direction. Along the second direction, the following first structure, second structure, and third structure are removed at intervals: (a) Interval removal of the first structure: Interval removal of a portion of the second sub-doped layer and a portion of the second sub-dielectric layer located above the first doped layer; (b) Interval removal of the second structure: Interval removal of a portion of the third doped region, a portion of the third dielectric layer, a portion of the third doped layer, a portion of the first sub-doped layer, and a portion of the first sub-dielectric layer; (c) Interval removal of the third structure: Interval removal of the third structure located below the second structure until the surface of the semiconductor substrate is exposed; After the first structure, the second structure, and the third structure are removed at intervals, at least one or more spaced-distributed exposed semiconductor substrate surface regions are formed, the exposed semiconductor substrate surface regions constituting insulating regions, and leakage regions are formed between two adjacent insulating regions.

34. A method for preparing a back-contact battery cell, characterized in that, Includes the following steps: Step (1): A first dielectric layer is formed on the backlight side of the semiconductor substrate; Step (2): A first intrinsic polysilicon layer is grown on the first dielectric layer, and a first dopant is diffused into the first intrinsic polysilicon layer to form a first doped layer. The first dopant partially penetrates the first dielectric layer along the thickness direction of the semiconductor substrate and diffuses into the semiconductor substrate to form a first doped region. Step (3): A second sub-dielectric layer is formed on the first doped layer; Step (4): Remove a portion of the formed second sub-dielectric layer, first doped layer, first dielectric layer and first doped region on the back side of the semiconductor substrate to expose the surface of the semiconductor substrate; Step (5): A first sub-dielectric layer and a second dielectric layer are grown on the surface of the semiconductor substrate, and a third dielectric layer is grown along the thickness direction of the semiconductor substrate on the side of the remaining first doped region, the first dielectric layer, the first doped layer, and the second sub-dielectric layer. The first sub-dielectric layer, the second dielectric layer, and the third dielectric layer are integrally formed in this step. Step (6): A second intrinsic polysilicon layer is grown on the upper surface of the first sub-dielectric layer and the second dielectric layer, the side surface of the third dielectric layer, and the upper surface of the second sub-dielectric layer. A portion of the second intrinsic polysilicon layer is adjacent to the surface of the semiconductor substrate through the first sub-dielectric layer and the second dielectric layer. A portion of the second intrinsic polysilicon layer is adjacent to the side surface of the remaining first doped region, the first dielectric layer, the first doped layer, and the second sub-dielectric layer through the third dielectric layer. A portion of the second intrinsic polysilicon layer is adjacent to the first doped layer through the second sub-dielectric layer. Step (7) involves diffusing the second dopant into the second intrinsic polysilicon layer, including: forming a first sub-doped layer by partially doping the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the first sub-dielectric layer; forming a second doped layer by partially doping the second intrinsic polysilicon layer adjacent to the surface of the semiconductor substrate through the second dielectric layer; forming a third doped layer by partially doping the second intrinsic polysilicon layer adjacent to the remaining first doped region, the first dielectric layer, the first doped layer, and the side of the second sub-dielectric layer through the third dielectric layer; and forming a second sub-doped layer by partially doping the second intrinsic polysilicon layer adjacent to the first doped layer through the second sub-dielectric layer. The second dopant also partially penetrates the first sub-dielectric layer and the second dielectric layer along the thickness direction of the substrate, and diffuses into the substrate to form a second doped region; Simultaneously, the second dopant partially penetrates the third dielectric layer, or the first dopant partially penetrates the third dielectric layer, forming a hole in the third dielectric layer through which charge carriers pass.

35. A method for preparing a back-contact battery cell according to claim 34, characterized in that, In step (7), the second dopant partially penetrates the third dielectric layer and forms a third doped region and a fourth doped region in the first doped layer, or the first dopant partially penetrates the third dielectric layer and forms a third doped region and a fourth doped region in the third doped layer.

36. The method for preparing a back-contact battery cell according to claim 35, characterized in that, It also includes step (8), removing a portion of the second sub-dielectric layer located on the first doped layer and the second sub-doped layer located on the second sub-dielectric layer.

37. The method for preparing a back-contact battery cell according to claim 36, characterized in that, The process also includes step (9), in which the first doped layer and the second doped layer are arranged at intervals along a first direction on a plane parallel to the semiconductor substrate, and the first doped layer and the second doped layer extend along a second direction, which is perpendicular to the first direction. Along the second direction, the following first structure, second structure, and third structure are removed at intervals: (a) Interval removal of the first structure: Interval removal of a portion of the second sub-doped layer and a portion of the second sub-dielectric layer located above the first doped layer; (b) Interval removal of the second structure: Interval removal of a portion of the third doped region, a portion of the fourth doped region, a portion of the third dielectric layer, a portion of the third doped layer, a portion of the first sub-doped layer, and a portion of the first sub-dielectric layer; (c) Interval removal of the third structure: Interval removal of the third structure located below the second structure until the surface of the semiconductor substrate is exposed; After the first structure, the second structure, and the third structure are removed at intervals, at least one or more spaced-distributed exposed semiconductor substrate surface regions are formed, the exposed semiconductor substrate surface regions constituting insulating regions, and leakage regions are formed between two adjacent insulating regions.

38. A method for preparing a back-contact battery cell according to claim 30 or 34, characterized in that, In step (2), the first dopant is BCl3 or BBr3. BCl3 or BBr3 is diffused at a temperature of 850℃-1000℃. During the diffusion process, BCl3 or BBr3 decomposes and B element diffuses into the first intrinsic polysilicon layer to form the first doped layer and partially penetrates the first dielectric layer to form the first doped region. In step (7), the second dopant is POCl3. POCl3 is diffused at a temperature of 800℃-1000℃. During the diffusion process, POCl3 decomposes and P element diffuses into the second intrinsic polysilicon layer to form the second doped layer. It also partially penetrates the first sub-dielectric layer and the second dielectric layer to form the second doped region. Furthermore, the P element partially penetrates the third dielectric layer, forming a hole for carrier transport within the third dielectric layer.

39. A method for preparing a back-contact battery cell according to claim 30 or 34, characterized in that, In step (2), the first dopant is POCl3. POCl3 is diffused at a temperature of 800℃-1000℃. During the diffusion process, POCl3 decomposes and P element diffuses into the first intrinsic polysilicon to form the first doped layer and partially penetrates the first dielectric layer to form the first doped region. In step (7), the second dopant is BCl3 or BBr3. BCl3 or BBr3 is diffused at a temperature of 850℃-1000℃. During the diffusion process, BCl3 or BBr3 decomposes and B element diffuses into the second intrinsic polysilicon layer to form the second doped layer and partially penetrates the first sub-dielectric layer and the second dielectric layer to form the second doped region. Simultaneously, the P element partially penetrates the third dielectric layer, forming a hole for carrier transport within the third dielectric layer.

40. A method for preparing a back-contact battery cell according to claim 30 or 34, characterized in that, In steps (1) and (5), the first dielectric layer, the first sub-dielectric layer, the second dielectric layer, and the third dielectric layer are formed by thermal growth. The growth temperature is 550℃-650℃ and the thickness is 1.0nm-2.5nm.

41. A method for preparing a back-contact battery cell according to claim 30 or 34, characterized in that, In steps (2) and (6), a first intrinsic polysilicon layer and a second intrinsic polysilicon layer are prepared using LPCVD process at a temperature of 550℃-650℃. The thickness of the first intrinsic polysilicon layer is 20nm-400nm, and the thickness of the second intrinsic polysilicon layer is 20nm-400nm.

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