Test machine detection system and detection method, medium and computer equipment

Abstract

The invention discloses a test machine detection system and method, a medium and computer equipment, and belongs to the field of semiconductor tests.The method comprises the steps that a program detection code is run through a test machine; sending an instruction code to the detection board by using the test mother board; executing the instruction code by using the detection board; the detection result of the instruction code executed by the detection board is displayed by using the on-off of the light-emitting diode; a detection result is fed back to the test machine through the detection plate; performing data comparison on the detection result by utilizing the test machine, and if the detection result is abnormal, displaying fail output by utilizing a test interface; and if the detection result is normal, displaying pass output by using a test interface. According to the application of the invention, each module in the system can be detected, the detection result can be synchronously displayed on the test machine and the detection board, the abnormal position and the abnormal type of the abnormal module can be rapidly locked, and the formation of a rapid abnormal processing scheme is facilitated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor tester detection, in particular to a tester detection system, a detection method, a medium and a computer device. BACKGROUND

[0002] The tester is one of the core devices in the field of semiconductor testing, and is an automatic system mainly used for verifying the function, performance and reliability of chips. A tester that is in normal operation and has perfect functions is a powerful defense line for verifying the reliability of chips, and can intercept defective chips through parameter testing and optical detection, accurately measure various key performance indicators of the chips, and further perform performance grading on the chips according to the results to maximize product value.

[0003] System resource detection of the tester is a prerequisite for handling system exceptions of the tester, and can greatly affect the efficiency of production line production and the timeliness of handling exceptions. At present, there are only two ways for system detection of the tester: power-on self-test, which obtains a detection result of a single resource board card, and further analysis and verification of the specific abnormal channel of the abnormal resource board card are required; and calibration, which comprehensively detects multiple parameters of the hardware of the tester to find the running status of the specific board card and further locks and solves the specific abnormal channel of the abnormal resource board card, but it takes 7-8 hours to calibrate each time, which cannot be used for rapid locking and solving of the root cause of abnormal problems in daily production line production, and calibration requires time to match calibration instruments. The method of theoretically detecting the appearance of each resource board card by the naked eye and determining the abnormality of each resource board card by program debugging is not very feasible in actual pre-production, and cannot form an intuitive and rapid processing scheme.

[0004] Therefore, there is currently no direct application scheme for intuitive system resource detection and display of the tester. SUMMARY

[0005] In view of the above technical problems in the prior art, the present application provides a tester detection system, a detection method, a medium and a computer device.

[0006] In one technical solution of the present application, a tester detection system is provided, which comprises: a tester, which generates system detection instruction code according to received predetermined system detection program code; a test motherboard; a detection board, which detects the tester and the test motherboard according to the system detection instruction code transmitted through the test motherboard, and feeds back the detection result to the tester, wherein the tester judges whether at least one of the tester and the test motherboard is abnormal according to the detection result, and displays the judgment result on the test interface of the tester.

[0007] In another technical solution of the present application, a tester detection method is provided, which can be detected by using the tester system in solution one.

[0008] In another technical solution of the present application, a computer readable storage medium is provided, which stores computer instructions, wherein the computer instructions are operated to execute the test machine detection method in solution two.

[0009] In another technical solution of the present application, a computer device is provided, which comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to execute the test machine detection method in solution two.

[0010] The beneficial effects achieved by the technical solutions of the present application are that the system can detect the test machine and the test motherboard abnormally and visualize the detection results, which helps the technical personnel to quickly lock the abnormal position. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a schematic diagram of one specific embodiment of the test machine detection system method of the present application;

[0012] Figure 2 is a flowchart of one specific embodiment of the program detection code;

[0013] Figure 3 is a flowchart of one specific embodiment of the test board of the present application;

[0014] Figure 4 is a schematic diagram of one specific embodiment of the test machine detection system of the present application;

[0015] Reference signs: 1, test machine, 2, test motherboard, 3, detection board, 4, 64-pin flat cable. DETAILED DESCRIPTION

[0016] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the protection scope of the present application can be more clearly and definitely defined.

[0017] It should be noted that "first", "second", "third" and the like in the claims and the specification of the present application are only used to distinguish similar objects, and do not necessarily mean a specific order or sequence.

[0018] Figure 1 is a schematic diagram of one specific embodiment of the test machine detection system of the present application.

[0019] In Figure 1 the specific embodiment shown, it comprises a test machine, a test motherboard and a detection board. The test machine and the detection board are electrically connected through the test motherboard.

[0020] The tester is one of the core devices of semiconductor testing, which can test the electrical characteristics and function verification of the chip; the tester usually automatically executes the test program according to the various program codes input to the tester to meet the different test requirements of the chip, such as voltage, current, power, frequency, timing, etc. Test, while generating test report and data analysis results. The test motherboard is one of the key components of the tester to connect the tested chip in the prior art, by designing the motherboard and the daughterboard to realize the standardization of the motherboard and the modularization of the daughterboard, only the differentiated part is realized by the daughterboard, realizing the flexible test system, meeting the actual test requirements. The detection board is a component for abnormality checking of the tester and the test motherboard.

[0021] For the detection of the tester and the test motherboard, the system inputs the predetermined system detection program code based on the tester detection to the tester, generates the system detection instruction code by the tester, and transmits the system detection instruction code generated by the tester to the detection board to detect the tester and the test motherboard, and feeds back the detection result to the tester. For the detection result, the tester can judge whether the tester and the test motherboard are running normally when running the part of the system detection code, and display the result on the test interface of the tester. The intuitive performance of the detection result is realized in the scheme, which is beneficial for the technician to observe; according to the running code, the more specific abnormal position of the tester and the test motherboard can be locked, which is helpful for the technician to make a quick judgment.

[0022] In one specific embodiment of the present application, the predetermined system detection program code can include at least one of the CBIT control bit module code, the FPVI detection module code, the FOVI detection module code, the DIO pattern output module code, and the TMU time measurement module code.

[0023] Figure 3 In one specific embodiment of the detection board, the detection board includes three resource detection modules: a first detection module, a second detection module, and a third detection module; wherein the first detection module can detect the tester and the test motherboard according to the system detection instruction code corresponding to the CBIT control bit module code, the FPVI detection module code, and / or the FOVI detection module code; the second detection module can detect the tester and the test motherboard according to the system detection instruction code corresponding to the DIO pattern output module code; and the third detection module can detect the tester and the test motherboard according to the system detection instruction code corresponding to the TMU time measurement module code.

[0024] The CBIT control bit module code is used to generate corresponding system detection instruction code and send to the detection board. The first detection module in the detection board detects whether the CBIT control bit module controlled by the test machine and the test motherboard operates normally. The FPVI detection module code is used to generate corresponding system detection instruction code and send to the detection board. The first detection module in the detection board detects whether the FPVI detection module controlled by the test machine and the test motherboard operates normally. The FOVI detection module code is used to generate corresponding system detection instruction code and send to the detection board. The first detection module in the detection board detects whether the FOVI detection module controlled by the test machine and the test motherboard operates normally. The DIO pattern output module code is used to generate corresponding system detection instruction code and send to the detection board. The second detection module in the detection board detects whether the DIO detection module controlled by the test machine and the test motherboard operates normally. The TMU time measurement module code is used to generate corresponding system detection instruction code and send to the detection board. The third detection module in the detection board detects whether the TMU time measurement module controlled by the test machine and the test motherboard operates normally. The detection board feeds back the detection results of each module control code in the test machine and test motherboard to the test interface, which realizes the rapid positioning of the module control problem by the technician and is beneficial to the rapid judgment of the technician.

[0025] In an embodiment of the present application, the CBIT control bit module code has a plurality of CBIT control bits, each of which is provided with corresponding system detection instruction code. The first detection module is provided with a CBIT control bit channel corresponding to each CBIT control bit, and a relay controlled by the CBIT control bit channel, and the relay is electrically connected with a corresponding light emitting diode. When the first detection module receives the system detection instruction code sent by a certain CBIT control bit, the CBIT control bit channel corresponding to the CBIT control bit is closed, and the relay controlled by the CBIT control bit channel is closed, so that the light emitting diode electrically connected with the relay is lit, and the detection result is fed back to the test interface of the test machine and displayed as pass. If a certain CBIT control bit cannot normally send corresponding system detection instruction code, the corresponding light emitting diode will not light up, and the detection result will be fed back to the test interface of the test machine and displayed as fail. Through this scheme, the detection results of specific CBIT control bits in the CBIT control bit module code can be displayed, and the abnormally operating CBIT control bits can be intuitively displayed on the test interface, further facilitating the locking and processing of the abnormal position by the technician.

[0026] In one preferred embodiment of the present application, a CBIT control bit is repeatedly run by the test machine to continuously generate system detection instruction code corresponding to the CBIT control bit, and the detection board receives the system detection instruction code corresponding to the CBIT control bit to light the corresponding light-emitting diode. The stability of the CBIT control bit in operation is determined by whether the light-emitting diode is lit or not lit during the cycle of the CBIT control bit.

[0027] In one preferred embodiment of the present application, the FPVI detection module code and / or the FOVI detection module code is provided with corresponding system detection instruction code. During detection, the FPVI detection module code and / or the FOVI detection module code is run by the first detection module in the test machine to generate corresponding system detection instruction code, which is transmitted to the detection board by the test motherboard; at the same time, the test machine inputs a given voltage to the detection board, and a current is generated due to the specific resistance in the detection board. According to I=V / R, the target current value is obtained, which is stored in the test machine. The actual current value generated by the detection board is measured and fed back to the test machine for comparison with the target current value. If they are the same, the detection result is fed back to the test machine test interface to display pass, and if they are different, the detection result is fed back to the test machine test interface to display fail; that is, whether the FPVI detection module code and / or the FOVI detection module code is running normally can be displayed, and whether the actual current value fed back to the test machine is similar to the target current value can also be determined, and the current error generated by the FPVI detection module code and / or the FOVI detection module code can also be determined.

[0028] In one preferred embodiment of the present application, the DIO pattern output module code has multiple channels, and each channel is provided with corresponding system detection instruction code. During detection, each channel of the DIO pattern output module code is run by the test machine to generate system detection instruction code corresponding to each channel, which is transmitted to the detection board by the test motherboard; the second detection module in the detection board receives the corresponding system detection instruction code and controls the corresponding light-emitting diode to be lit and to flash at a set frequency, and the second detection module feeds back information about whether the light-emitting diode is lit and the actual flashing frequency to the test machine. The test machine stores information about the set lighting and fixed flashing frequency of the light-emitting diode when the DIO pattern output module code is run, and the abnormal channel position can be directly locked by comparing the two.

[0029] In a preferred embodiment of the present application, the TMU time measurement module code has corresponding system detection instruction code, the tester runs the TMU time measurement module code, and the second detection module in the detection board provides a fixed frequency square wave, and the third detection module receives the system detection instruction code corresponding to the TMU time measurement module code and performs frequency detection on the fixed frequency square wave provided by the second detection module. Since the duty cycle of the fixed frequency square wave is fixed, the target frequency value is generated by the TMU time measurement module code, and the frequency detection by the system detection instruction code is the actual measurement value. The detection board feeds back the measurement result to the tester, and the comparison of the two values can determine whether there is an error in the TMU time measurement module code.

[0030] In a preferred embodiment of the present application, the tester detection system includes: a relay matrix module integrating relays with different functions; a corresponding light-emitting diode display matrix module electrically connected to each relay; and a simplified installation process, reduced installation space for each relay and light-emitting diode, and further reduced volume of the detection board.

[0031] As shown in Figure 4 In a preferred embodiment of the present application: a tester detection system includes a tester 1, a test motherboard 2, and a detection board 3 connected by a 64PIN flat cable 4. The detection board includes a first detection module, a second detection module, and a third detection module. The first detection module can receive system detection instruction code generated by running CBIT control bit module code, FPVI detection module code, and / or FOVI detection module code. The second detection module can receive system detection instruction code generated by running DIO pattern output module code. The third detection module can receive system detection instruction code generated by running TMU time measurement module code. The first detection module is set as four independent and parallel test units, each test unit having 30 CBIT bits corresponding to 30 CBIT control bits, FPVI bits and FOVI bits corresponding to 2 FPVI sources and 10 FOVI sources. The detection board is provided with an area below the four independent test units to receive system detection instruction code generated by the DIO pattern output module code and the TMU time measurement module code.

[0032] The specific detection method of the tester and the test motherboard in this example is as follows: for the system detection instruction code generated by the CBIT control bit module code, the first detection module receives the system detection instruction code sent by each CBIT control bit, the CBIT control bit channel corresponding to the CBIT control bit is closed, and then the relay controlled by the CBIT control bit channel is closed, so that the light-emitting diode electrically connected to the relay is lit, and the detection result is fed back to the tester test interface to display pass; if a certain CBIT control bit cannot normally send the corresponding system detection instruction code, resulting in that the corresponding light-emitting diode does not light up, then the detection result is fed back to the tester test interface to display fail; for the CBIT control bit whose detection result is fed back to the tester test interface to display pass, the tester can be run multiple times to continuously generate the system detection instruction code corresponding to the CBIT control bit, and the detection board receives the system detection instruction code corresponding to the control bit to light up the corresponding light-emitting diode. Through this process, whether the light-emitting diode lights up during the cycle of the CBIT control bit and the number of times that the light-emitting diode does not light up are used to judge the stability of the CBIT control bit in operation.

[0033] The FPVI detection module code and / or the FOVI detection module code is provided with corresponding system detection instruction code, the first detection module in the tester runs the FPVI detection module code and / or the FOVI detection module code to generate corresponding system detection instruction code, which is transmitted to the detection board by the test motherboard; at the same time, the tester inputs a given voltage to the detection board, and since the detection board has a specific resistance, an electric current is generated. According to I=V / R, the target current value can be obtained, which is stored in the tester. The actual current value generated by the detection board is measured, and the actual current value is fed back to the tester to compare whether it is the same as the target current value. If they are the same, the detection result is fed back to the tester test interface to display pass; if they are different, the detection result is fed back to the tester test interface to display fail; that is, whether the FPVI detection module code and / or the FOVI detection module code is running normally can be displayed, and according to whether the actual current value fed back to the tester is the same as the target current value, it can also be judged whether the current error generated by the FPVI detection module code and / or the FOVI detection module code is running normally.

[0034] The test machine runs the DIO pattern output module code of each channel and generates system detection instruction code corresponding to the channel, which is transmitted to the detection board by the test motherboard. The second detection module in the detection board receives the corresponding system detection instruction code and controls the corresponding light-emitting diode to light up and flicker at a set frequency. The second detection module feeds back the information of whether the light-emitting diode lights up and the actual flicker frequency to the test machine. The test machine stores the set light-emitting diode lighting and fixed flicker frequency information when running the DIO pattern output module code. By comparing the two, if they are the same, the detection result is fed back to the test machine test interface to display pass; if they are different, the detection result is fed back to the test machine test interface to display fail; that is, the abnormal channel position can be directly locked.

[0035] The TMU time measurement module code has corresponding system detection instruction code. The test machine runs the TMU time measurement module code, and the second detection module in the detection board provides a fixed frequency square wave. The third detection module receives the system detection instruction code corresponding to the TMU time measurement module code and performs frequency detection on the fixed frequency square wave provided by the second detection module. Since the duty cycle of the fixed frequency square wave is fixed, it is the target frequency value. The system detection instruction code generated by the TMU time measurement module code performs frequency detection as the actual measurement value. The detection board feeds back the measurement result to the test machine. By comparing the two values: if they are the same, the detection result is fed back to the test machine test interface to display pass; if they are different, the detection result is fed back to the test machine test interface to display fail; that is, it can be judged that there is an error in the TMU time measurement module code.

[0036] In one specific embodiment of the present application, a test machine detection method can be used to perform the test machine detection described in any of the above embodiments.

[0037] In one specific embodiment of the present application, a computer readable storage medium stores computer instructions, which are operated to perform the test machine detection method described in any of the embodiments.

[0038] In one specific embodiment of the present application, a computer device includes a processor and a memory, and the memory stores computer instructions, wherein: the processor operates the computer instructions to perform the test machine detection method described in any of the embodiments.

[0039] In the embodiments of the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the described apparatus embodiment is merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0040] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0041] The above description is merely an embodiment of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure transformation made by using the content of the present application specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A test machine detection system, characterized by, The test machine generates system detection instruction code according to the received predetermined system detection program code; The test motherboard; The detection board detects the test machine and test motherboard according to the system detection instruction code transmitted by the test motherboard, and feeds back the detection result to the test machine, wherein The test machine judges whether at least one of the test machine and test motherboard is abnormal according to the detection result, and displays the judgment result on the test interface of the test machine.

2. The test machine detection system according to claim 1, wherein The predetermined system detection program code includes at least one of CBIT control bit module code, FPVI detection module code, FOVI detection module code, DIO pattern output module code, and TMU time measurement module code. The detection board includes:

3. The tester detection system of claim 2, wherein, A first detection module detects the test machine and test motherboard according to the system detection instruction code corresponding to the CBIT control bit module code, FPVI detection module code, and / or FOVI detection module code; A second detection module detects the test machine and test motherboard according to the system detection instruction code corresponding to the DIO pattern output module code; A third detection module detects the test machine and test motherboard according to the system detection instruction code corresponding to the TMU time measurement module code.

4. The test machine detection system according to claim 3, wherein The first detection module detects the test machine and test motherboard according to the system detection instruction code corresponding to each control bit of the CBIT control bit module code; The first detection module detects the test machine and test motherboard according to the system detection instruction code corresponding to the FPVI detection module code and / or FOVI detection module code, and the given voltage and the corresponding measured current.

5. The test machine detection system according to claim 3, wherein The third detection module detects the test machine and test motherboard according to the system detection instruction code corresponding to the TMU time measurement module code, and the square wave of the predetermined frequency provided by the second detection module.

6. The test machine detection system according to claim 2, wherein The detection board includes a plurality of light-emitting diodes, and The detection board controls the light-emitting state of the corresponding light-emitting diode in the plurality of light-emitting diodes according to the detection result.

7. The test machine detection system according to claim 6, wherein The light-emitting state of the corresponding light-emitting diode in the plurality of light-emitting diodes corresponds to at least one of the CBIT control bit module code, FPVI detection module code, FOVI detection module code, DIO pattern output module code, and TMU time measurement module code.

8. A test machine detection method using the test machine detection system according to any one of claims 1-7. ​ 9. A computer-readable storage medium storing computer instructions, wherein, The computer instructions are operative to perform the test handler detection method recited in claim 8.

10. A computer device comprising a memory, a processor, and a computer program stored on the memory, wherein, The processor executes the computer program to implement the test handler detection method recited in claim 8.

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