Configurable high-precision time-to-digital converter applied to large-area-array image sensor system

Abstract

The invention relates to a configurable high-precision time-to-digital converter applied to a large-area-array image sensor system, belongs to the technical field of time-to-digital converters, and aims to solve the problems that the resolution of a traditional TDC is limited by process delay, the dead time is too long, and the resource efficiency and the measurement performance are difficult to balance. According to the technical scheme, the method comprises the steps that a non-uniform delay chain is constructed through a multi-period multi-coupling method to improve the resolution; the priority arbiter and the parallel decoding module cooperatively shorten the dead time; approximate dichotomy decoding can be configured to dynamically adjust the iteration depth. The method has the technical effects that high-precision time measurement, low-dead-zone continuous operation and flexible adaptation to multi-scene resource optimization are realized.

Description

Technical Field

[0001] This invention belongs to the field of time-to-digital converter technology, and relates to a configurable high-precision time-to-digital converter for use in large-area image sensor systems. Background Technology

[0002] The time-to-digital converter (TDC) is a key module in the high-speed circuitry of large-area image sensor systems. Current mainstream digital TDC implementations include five architectures: counting, delay chain, multiphase clock, vernier delay chain, and ring oscillator. Counting and multiphase clock TDCs are simple in structure and consume few resources, but their resolution is limited by the system clock frequency and the number of fixed phase differences. Vernier delay chain TDCs can achieve high resolution, but require a large number of delay units, leading to a significant increase in hardware resource consumption, longer dead time, and limited dynamic range. Ring oscillator and delay chain TDCs offer a trade-off between performance and resource consumption, but their resolution is still limited by the basic gate delay time of the manufacturing process.

[0003] Counting-type TDCs count the number of clock pulses (rising or falling edges) between the start signal (START) and the stop signal (STOP) using a set of triggers; their resolution is directly limited by the upper limit of the system clock frequency. Delay-chain TDCs use sub-clock cycle delay units for time interpolation, but the minimum delay time is limited by process physical constraints. Multiphase clock TDCs use phase-locked loops to generate multi-phase clock sampling signal transition points; while simplifying the architecture, the limited number of phases results in insufficient resolution. Vernier delay-chain TDCs (VDL-TDCs) overcome the limitations of single delay units through heterogeneous delay-chain structures, but require a significantly increased delay-chain length, leading to increased area and power consumption. Ring oscillator-type TDCs (RO-TDCs), while possessing a wide dynamic range, have resolution equivalent to the gate delay of a basic delay unit, and the continuous oscillation mechanism introduces higher power consumption; they are also susceptible to fluctuations in process voltage and temperature.

[0004] Traditional high-resolution solutions rely on application-specific integrated circuits (ASICs) to achieve uniform delay chains, but these solutions suffer from bottlenecks such as long development cycles, high design costs, and poor flexibility. In FPGA platforms, the carry chain delay time cannot be further reduced, necessitating a breakthrough architecture to address resolution limitations. Furthermore, existing time-to-digital converters (TDCs) generally suffer from excessively long decoding dead times, difficulty in balancing resource efficiency and measurement accuracy, and limited application scenarios. Therefore, a high-precision time-to-digital converter that can dynamically configure resolution, compress dead times, and adapt to multiple scenarios is urgently needed. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a configurable high-precision time-to-digital converter (TDC) for use in large-area image sensor systems. The core performance indicator of a TDC is resolution, which directly determines the accuracy of time measurement. In addition, parameters such as linearity, dead time, and conversion time are also key factors in evaluating TDC performance. Currently, foreign research often uses application-specific integrated circuits (ASICs) to construct high-resolution TDC delay chains. While this approach provides high resolution and good stability, it also faces problems such as long development cycles, high R&D costs, customized design, and poor flexibility. To develop and verify TDCs in a shorter period and at a lower cost, this invention designs and implements a high-precision and configurable TDC based on FPGA. The main problems solved by this invention are as follows:

[0006] (1) To address the limitations of resolution in traditional time-delay converters (TDCs) due to the minimum delay of delay units and high decoding complexity, this invention proposes a non-uniform delay chain construction method based on multi-phase clock multi-cycle coupling (MCMC). This scheme overcomes the resolution limitation imposed by the delay time of delay units through a multi-cycle phase coupling mechanism and utilizes the periodic clock characteristics to achieve simplified decoding logic. Experimental results show that the average resolution of the constructed delay chain reaches 1.67 ps. Furthermore, this invention employs a structure combining coarse and fine timestamps based on the periodic characteristics of the delay chain information.

[0007] (2) To address the problem of excessively long dead time and limited efficiency caused by multi-cycle decoding in TDC, this invention proposes a collaborative architecture based on a priority arbitrator and a parallel decoding module. This design significantly shortens the dead time through dynamic arbitration and parallel processing mechanisms, ultimately achieving a TDC dead time of only 20ns.

[0008] (3) To address the trade-off between resource efficiency and measurement performance in TDC, and the needs of diverse application scenarios, this invention proposes a delay chain decoding scheme based on a configurable approximate binary search method. This scheme reduces the combinational logic between flip-flops and increases the clock frequency by decoding step by step, and supports dynamic adjustment of the number of binary search steps (6–10 levels), thereby achieving flexible optimization between resolution (1.67ps–15.68ps) and resource overhead (732–7174 LUTs, 1482–11423 FFs), adapting to the needs of different time measurement scenarios.

[0009] This invention designs and implements a high-precision and configurable Time Control Module (TDC) based on the Xilinx FPGA platform, and its performance is systematically tested through code density and single-precision tests. Static test results show that the resolution of this TDC can be adjusted within the range of 1.67–15.68 ps while maintaining excellent linearity (DNLpk-pk: 0.384–1.61 LSB, INLpk-pk: 0.456–5.23 LSB). Dynamic tests further confirm its high-precision characteristics.

[0010] To achieve the above objectives, the present invention provides the following technical solution:

[0011] A configurable high-precision time-to-digital converter (TDC) for use in large-area image sensor systems includes the following interconnected modules:

[0012] The delay chain module receives START and STOP signals at its input and constructs a non-uniform delay chain based on the multi-period multi-coupling MCMC method for time interpolation of the input signals.

[0013] The synchronizer module, whose input is connected to the output of the delay chain module, is used to synchronize the data output by the delay chain in the clock domain.

[0014] The priority arbitrator module includes a first priority arbitrator and a second priority arbitrator. The input of the first priority arbitrator is connected to the START signal data output of the synchronizer module, and the input of the second priority arbitrator is connected to the STOP signal data output of the synchronizer module, which is used to dynamically allocate decoding tasks.

[0015] The parallel decoding module contains multiple independent decoding blocks. The input of each decoding block is connected to the task allocation output of the priority arbitrator module, and the delayed chain data is decoded using an approximate binary search method.

[0016] The decoding time selector module includes a first selector and a second selector. The input of the first selector is connected to the decoding result output of the START signal of the parallel decoding module, and the input of the second selector is connected to the decoding result output of the STOP signal of the parallel decoding module. This module is used to extract fine timestamps.

[0017] The coarse time counter module has START and STOP signals connected to its input terminals to count the number of clock cycles between the two signals.

[0018] The time length calculator module has its input terminals connected to the output terminals of the decoding time selector module and the coarse time counter module, respectively, and is used to merge the coarse timestamp and the fine timestamp and output the final time interval.

[0019] The delay chain module is implemented through a multi-cycle phase coupling mechanism, and the resolution of its equivalent delay unit satisfies the formula:

[0020]

[0021] Where R is the resolution, T clk Where N is the system clock cycle, N is the delay chain stage, and M is the phase coupling factor.

[0022] The approximate binary decoding process of the parallel decoding module includes:

[0023] Perform K-level binary search iterations on the delay chain data with a bit width of W, where W = 320 and K ∈ [6, 10].

[0024] Each iteration determines the interval where the signal transition point is located using a set of comparators;

[0025] The final output is log2 W-bit fine-grained time encoding.

[0026] The number of binary search iterations K can be dynamically configured, allowing the resolution to be adjusted within the range of 1.67ps to 15.68ps, while satisfying the following resource consumption requirements:

[0027] The number of lookup table LUTs is 732 when K is 6 and 7174 when K is 10;

[0028] The number of triggers (FFs) is 1483 when K is 6 and 11423 when K is 10.

[0029] The priority arbitrator module adopts the idle priority scheduling algorithm, which compresses the dead time to less than 20ns.

[0030] A time measurement method based on the TDC includes the following steps:

[0031] S1: The START signal triggers delay chain sampling, and the synchronizer captures the delay chain state;

[0032] S2: The first priority arbiter allocates the START-related delay chain data to the idle decoding block, and outputs the START fine timestamp after approximately binary decoding.

[0033] S3: The second priority arbitrator allocates the STOP-related delay chain data to the idle decoding block, and outputs the STOP fine timestamp through approximate binary decoding. S3 and S2 are executed in parallel.

[0034] S4: The coarse time counter counts the number of clock cycles from START to STOP. This step is executed synchronously with S1 to S3.

[0035] S5: The time length calculator combines the START fine timestamp output by S2, the STOP fine timestamp output by S3, and the coarse timestamp output by S4 to calculate the final time interval.

[0036] Furthermore, in S2 and S3, the approximate binary code decoding includes:

[0037] S21: Initialize the iteration count K and the interval boundary; K∈[6,10];

[0038] S22: Gradually reduce the jump point interval over K clock cycles;

[0039] S23: The final stage outputs the fine-grained time value of the binary code.

[0040] Furthermore, in S22, the interval reduction operation of each iteration is implemented by a parallel comparator group, and the number of comparators satisfies:

[0041] C k =2 (K-k) k = 1, 2, ..., K

[0042] Where C k The number of comparators required for the k-th iteration.

[0043] Furthermore, in S5, the time fusion calculation satisfies the formula:

[0044] T means =N·T clk +(T stop -T start )

[0045] Where T means For measurement time, N is the coarse count value, and T is the measurement time. clk T is the clock period. start and T stop For fine-grained timestamps.

[0046] The beneficial effects of this invention are as follows:

[0047] (1) Traditional time-delay units (TDCs) are limited by the minimum delay time of the basic delay unit and the decoding complexity of the process technology, resulting in a physical bottleneck in resolution. The multi-period multi-coupling method proposed in this invention effectively breaks through the time resolution limit of a single delay unit by constructing a delay chain through periodic phase superposition and non-uniformity. This mechanism enables a leapfrog improvement in the quantization capability of fine timestamps, achieving sub-picosecond high-precision measurement and completely solving the problem of insufficient resolution caused by clock frequency, number of phases, or process limitations in traditional solutions.

[0048] (2) To address the task blocking problem caused by multi-cycle decoding, this invention pioneers a dynamic collaborative architecture between a priority arbiter and a parallel decoding module. By scheduling idle decoding resources in real time and performing parallel processing, the waiting delay of traditional serial decoding is eliminated. This design enables the system to respond to new signals immediately after completing the current measurement, significantly compressing the signal interval processing time, achieving high-speed continuous measurement, and overcoming the inefficiency caused by the long dead time of traditional TDC.

[0049] (3) The configurable approximate binary decoding mechanism proposed in this invention establishes an adjustable balance between hardware resources and measurement accuracy by dynamically adjusting the iteration depth. Users can dynamically select different levels of binary decoding strategies according to actual scenario requirements: reducing the number of iterations to save hardware overhead in resource-constrained scenarios, and increasing the iteration depth to obtain ultimate resolution in high-precision scenarios. This flexible configuration capability enables a single volume to simultaneously meet the measurement needs of differentiated scenarios such as lidar, high-energy physics experiments, and biomedical imaging.

[0050] (4) The above three innovations create synergistic benefits:

[0051] The high-resolution architecture avoids performance loss through a parallel arbitration mechanism, achieving "high precision + low latency" synchronization.

[0052] Configurable decoding breaks the strong coupling between resource consumption and resolution, enabling the system to maximize measurement capabilities within the resource efficiency boundary;

[0053] FPGA-based implementations combine ASIC-level performance with hardware reconfigurability, providing a universal solution for scientific research and industrial applications.

[0054] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0055] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0056] Figure 1 TDC architecture diagram;

[0057] Figure 2 For constructing high-resolution MCMC methods;

[0058] Figure 3 This is a schematic diagram of approximate binary code decoding;

[0059] Figure 4 A circuit implementation for an approximate bisection method;

[0060] Figure 5 These are the static performance parameters configured for 10 binary search iterations.

[0061] Figure 6 Code width distribution of equivalent delay units under different configurations

[0062] Figure 7 DNL distribution of equivalent delay units under different configurations

[0063] Figure 8 The DNL distribution of equivalent delay units under different configurations. Detailed Implementation

[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0065] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0066] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0067] The overall architecture of this invention is as follows Figure 1As shown. The main modules included in this architecture are: a delay chain, a synchronizer, a priority arbiter for selecting decoding blocks for the delay chain information of the start signal, a priority arbiter for selecting decoding blocks for the delay chain information of the stop signal, multiple parallel decoding blocks for decoding the delay chain information of the start signal, multiple parallel decoding blocks for decoding the delay chain information of the stop signal, a decoding time selector for selecting the fine timestamp of the start signal, a decoding time selector for selecting the fine timestamp of the stop signal, a coarse time counter, and a time length calculator that combines the coarse and fine timestamps for final calculation.

[0068] Coarse timestamps are fundamental for large-scale measurements. Implemented using a counter, they count the number of clock cycles between the start and stop signals. Multiplying the counter value by the clock cycle yields a rough estimate of the measurement time (coarse timestamp). Fine timestamps are crucial for achieving high resolution, and their core is the delay chain. When the rising edge of the start or stop pulse signal arrives, the Time Control Controller (TDC) samples the delay chain data and transmits it to the priority arbitrator via a synchronizer. This paper designs an architecture integrating a priority arbitrator and multiple parallel decoding blocks to improve the efficiency of the TDC and avoid blocking the decoding of new time measurement data due to incomplete decoding of previous time measurement data. The decoding process for the fine timestamps of the start and stop signals is the same. The priority arbitrator sends the data from the delay chain to the idle and highest-priority decoding block for decoding. The decoding block decodes the received delay chain information and obtains the corresponding time value. The decoding time selector retrieves the corresponding time information from the decoding block based on the indication signal and transmits it to the time length calculator. The time length calculator combines the coarse timestamp with the fine timestamps from the start and stop signals to calculate the final measurement time.

[0069] Figure 2 This is a schematic diagram of the multi-cycle multi-coupling (MCMC) method used to construct the delay chain of this invention, which is the basis for achieving the high precision of this invention.

[0070] Figure 3 This is a schematic diagram of the binary search method used in this invention to perform binary search iterative decoding on the delay chain. This is the basis for the configurability of this invention.

[0071] Figure 4 This is a schematic diagram of the circuit implementation of the approximate binary search method. In order to reduce the combinational logic between flip-flops, the binary search iteration of this invention is implemented in multiple clock cycles.

[0072] Figure 5These are the static performance parameters of this invention when configured for 10 binary iterations. At this time, the average resolution is 1.67 ps, the DNL range is [-0.52 LSB, 1.09 LSB], and the INL range is [2.13 LSB, 3.1 LSB].

[0073] Figure 6 This illustrates the code width distribution of the equivalent delay unit when configured with different binary search iteration numbers according to the present invention.

[0074] Figure 7 This diagram illustrates the distribution of the differential nonlinearity (DNL) of the equivalent delay unit when configured with different binary iteration numbers according to the present invention.

[0075] Figure 8 This diagram illustrates the distribution of the integral nonlinearity (INL) of the equivalent delay unit when configured with different numbers of bisection iterations according to the present invention.

[0076] Table 1 shows the amount of FPGA resources consumed by the present invention when configured with different numbers of binary search iterations.

[0077] Table 1

[0078] Binary decoding count LUT FF 10 7174 111423 9 4585 10603 8 2441 6257 7 1477 3344 6 732 1483

[0079] Example 1: High-resolution time measurement mode (K = 10 iterations)

[0080] 1.1 Signal Trigger

[0081] The rising edge of the START signal triggers delay chain sampling, and the 320-bit delay chain state is captured by the synchronizer.

[0082] At the same time, the coarse time counter begins to count the clock cycle.

[0083] 1.2 Parallel Decoding Processing

[0084] The first-priority arbiter detects idle decoding blocks and allocates START data to decoding block A.

[0085] Decoding block A performs 10 levels of binary search iteration:

[0086] Level 1: 512 comparators divide the 320-bit data into two 160-bit ranges.

[0087] Level 2: 256 comparators narrow the range to 80 bits. ...

[0089] Level 10: One comparator pinpoints the precise jump point.

[0090] After 10 clock cycles, a 19-bit fine timestamp is output (log2320≈8.3, rounded to 19 bits).

[0091] 1.3 Dual-signal coordination

[0092] When the STOP signal is triggered, the second arbitrator assigns the task to decoding block B.

[0093] Decoding block B executes the same process independently, running in parallel with START decoding.

[0094] 1.4 Time Fusion Computation

[0095] The number of output cycles for the coarse counter is N = 150 (assuming).

[0096] Time calculator execution:

[0097] T_meas=150×5ns+(T_stop-T_start)=750ns+(32.5ps-15.2ps)=750.0173ns.

[0098] Example 2: Resource Optimization Mode (K = 6 iterations)

[0099] 2.1 Dynamic Reconfiguration

[0100] The system receives the configuration command and sets the number of binary search iterations to K=6.

[0101] The decoding module automatically adjusts the comparator quantity cascade method.

[0102] 2.2 Fast Decoding Process: After the START signal is triggered, decoding block C executes:

[0103] Level 1: 32 comparators (C1 = 2) (6-1) =32)

[0104] Level 6: 1 comparator

[0105] Output timestamp in just 6 clock cycles

[0106] 2.3 Dead Time Compression

[0107] The priority arbiter completes new task assignment within 15ns. When the STOP signal interval is >20ns, it can continuously process 100+ events / μs. 2.4 Precision balance calculation

[0108] The resolution is reduced to 15.68ps (Formula R = T_clk / (N × M)).

[0109] The measured DNL < 0.52 LSB meets the requirements of lidar.

[0110] Example 3: High-speed continuous measurement mode

[0111] 3.1 Event Outbreak Handling t=0ns: START1 arrives, the arbitrator allocates to decoder block A

[0112] t = 5ns: START2 arrives, arbiter assigns to decoder block B. t = 10ns: STOP1 arrives, assigns to decoder block C.

[0113] 3.2 Pipeline Architecture Timeline

[0114] title 20ns event processing flow section Decoding block A

[0115] START1 decoding: 0-10ns

[0116] Section Decoding Block B

[0117] START2 decoding: 5-15ns

[0118] section decoding block C

[0119] STOP1 decoding: 10-20ns

[0120] 3.3 Zero-blocking output

[0121] The time selector extracts the START1 result at t = 10 ns.

[0122] Extracting START2 results at t=15ns

[0123] Extract STOP1 results at t=20ns

[0124] 3.4 Dead Time Verification

[0125] The measured event interval of 18ns can still be accurately captured.

[0126] Example 4: Adaptive Linearity Optimization Mode

[0127] 4.1 Linearity Monitoring

[0128] The system runs code density tests periodically.

[0129] Generate DNL / INL distribution map

[0130] 4.2 Dynamic parameter tuning

[0131] When INL > 4 LSB is detected (K = 7)

[0132] Automatically switch to K=9 mode (INL<2.1LSB)

[0133] 4.3 Thermogravimetric Configuration Process

[0134] The clock pauses for 1 cycle to load new parameters.

[0135] Comparator group by C k =2(9-k) Reorganization

[0136] 4.4 Accuracy Recovery Verification

[0137] After reconfiguration, INL decreased from 5.23 LSB to 1.89 LSB;

[0138] The resolution remains unchanged at 8.34ps.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A configurable high-precision time-to-digital converter (TDC) for use in large-area image sensor systems, characterized in that: Includes modules with interconnected signals: The delay chain module receives START and STOP signals at its input and constructs a non-uniform delay chain based on the multi-period multi-coupling MCMC method for time interpolation of the input signals. The synchronizer module, whose input is connected to the output of the delay chain module, is used to synchronize the data output by the delay chain in the clock domain. The priority arbitrator module includes a first priority arbitrator and a second priority arbitrator. The input of the first priority arbitrator is connected to the START signal data output of the synchronizer module, and the input of the second priority arbitrator is connected to the STOP signal data output of the synchronizer module, which is used to dynamically allocate decoding tasks. The parallel decoding module contains multiple independent decoding blocks. The input of each decoding block is connected to the task allocation output of the priority arbitrator module, and the delayed chain data is decoded using an approximate binary search method. The decoding time selector module includes a first selector and a second selector. The input of the first selector is connected to the decoding result output of the START signal of the parallel decoding module, and the input of the second selector is connected to the decoding result output of the STOP signal of the parallel decoding module. This module is used to extract fine timestamps. The coarse time counter module has START and STOP signals connected to its input terminals to count the number of clock cycles between the two signals. The time length calculator module has its input terminals connected to the output terminals of the decoding time selector module and the coarse time counter module, respectively, and is used to merge the coarse timestamp and the fine timestamp and output the final time interval.

2. The configurable high-precision time-to-digital converter for a large-area image sensor system according to claim 1, characterized in that: The delay chain module is implemented through a multi-cycle phase coupling mechanism, and the resolution of its equivalent delay unit satisfies the formula: Where R is the resolution, T clk Where N is the system clock cycle, N is the delay chain stage, and M is the phase coupling factor.

3. The configurable high-precision time-to-digital converter for a large-area image sensor system according to claim 1, characterized in that: The approximate binary decoding process of the parallel decoding module includes: Perform K-level binary search iterations on the delay chain data with a bit width of W, where W = 320 and K ∈ [6, 10]. Each iteration determines the interval where the signal transition point is located using a set of comparators; The final output is log2 W-bit fine-grained time encoding.

4. The configurable high-precision time-to-digital converter for a large-area image sensor system according to claim 3, characterized in that: The number of binary search iterations K can be dynamically configured, allowing the resolution to be adjusted within the range of 1.67ps to 15.68ps, while satisfying the following resource consumption requirements: The number of lookup table LUTs is 732 when K is 6 and 7174 when K is 10; The number of triggers (FFs) is 1483 when K is 6 and 11423 when K is 10.

5. The configurable high-precision time-to-digital converter for a large-area image sensor system according to claim 1, characterized in that: The priority arbitrator module adopts the idle priority scheduling algorithm, which compresses the dead time to less than 20ns.

6. A time measurement method based on the TDC according to any one of claims 1 to 5, characterized in that: Includes the following steps: S1: The START signal triggers delay chain sampling, and the synchronizer captures the delay chain state; S2: The first priority arbiter allocates the START-related delay chain data to the idle decoding block, and outputs the START fine timestamp after approximately binary decoding. S3: The second priority arbitrator allocates the STOP-related delay chain data to the idle decoding block, and outputs the STOP fine timestamp through approximate binary decoding. S3 and S2 are executed in parallel. S4: A coarse time counter counts the number of clock cycles from START to STOP, and executes synchronously with S1 to S3; S5: The time length calculator combines the START fine timestamp output by S2, the STOP fine timestamp output by S3, and the coarse timestamp output by S4 to calculate the final time interval.

7. The time measurement method according to claim 6, characterized in that: In S2 and S3, the approximate binary code decoding includes: S21: Initialize the iteration count K and the interval boundary; K∈[6,10]; S22: Gradually reduce the transition point interval over K clock cycles; S23: The final stage outputs the fine-grained time value of the binary code.

8. The time measurement method according to claim 7, characterized in that: In step S22, the interval reduction operation of each iteration is implemented by a parallel comparator group, and the number of comparators satisfies: C k =2 (K-k) ,k=1,2,...,K Where C k The number of comparators required for the k-th iteration.

9. The time measurement method according to claim 6, characterized in that: In S5, the time fusion calculation satisfies the formula: T means =N·T clk +(T stop -T start ) Where T means For measurement time, N is the coarse count value, and T is the measurement time. clk T is the clock period. start and T stop For fine-grained timestamps.

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