High-gain high-bandwidth voltage adaptive BUFFER circuit

Abstract

The invention discloses a high-gain high-bandwidth voltage adaptation BUFFER circuit, the circuit comprises a voltage adaptation stage, a fixed gain stage and a BUFFER main circuit, the voltage adaptation stage is composed of an NM1 tube, an NM2 tube, a resistor R1, a resistor R2, a pull-down current source I1 and a pull-up current source I2, the fixed gain stage is composed of an NM3 tube, an NM4 tube, an NM5 tube and a pull-down current source I3, and the BUFFER main circuit is composed of a BUFFER main circuit. The BUFFER main circuit is composed of an NM7 tube, an NM8 tube, a PM1 tube, a PM2 tube, a PM3 tube, a PM4 tube, an NPN1 tube, an NPN2 tube, an NPN3 tube, an NPN4 tube, a pull-down current source I4, a pull-down current source I5 and a pull-down current source I6. According to the circuit, the voltage adaptation stage and the fixed gain stage are added, and a low VDS current mirror structure is adopted, so that the whole feedback system can be kept stable, and relatively high precision of an error amplifier can be kept.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a high-gain, high-bandwidth voltage adapter buffer circuit. Background Technology

[0002] LDO, or Low Dropout Regulator, is a type of low-dropout linear regulator primarily used to regulate a higher input voltage to a lower output voltage with a very small voltage drop during this process. LDOs offer advantages such as high efficiency, low output noise, low temperature coefficient, simple structure, easy integration, small size, and low cost. These characteristics make them widely used in precision equipment and low-power systems, such as mobile phones, IoT devices, and medical devices. The core circuit module of an LDO chip is the error amplifier EA. The main parameters of an LDO, such as load modulation, linear modulation, dynamic response, and power supply rejection, are primarily determined by the performance of the error amplifier EA.

[0003] Currently, commonly used error amplifier structures are as follows: Figure 1 As shown, a feedback loop is formed by the first stage of EA, the buffer, and the output stage. The first stage of EA amplifies the error, the buffer provides the driving capability for the output stage, and the output stage provides the load capacity. The specific working process is as follows: The positive input of the first stage of EA is connected to V... REF The reference voltage is connected to the negative terminal via the output voltage V. OUT V is generated through resistive voltage division FB Feedback voltage; for example, when the output voltage V OUT When V decreases, FB The voltage also dropped, V FB Then less than V REF If the voltage is increased, the first-stage output voltage of EA will rise, and the output voltage of BUFFER GDRV will also rise to increase the output stage capability, thus increasing V. OUT As a feedback loop, its stability is particularly important. Here, the first-stage output of EA, the output of the BUFFER, and the output stage all have poles. A common compensation method is to compensate the first-stage output of EA with capacitor Cg as the primary pole, and to use a suitable output capacitor as the secondary pole in the output stage. At an appropriate position, a zero is added through Cg and Rg to perform frequency compensation so that the feedback system reaches a stable state. The performance of the BUFFER has a significant impact on the entire feedback system in terms of both static characteristics and stability.

[0004] However, under certain extreme conditions, the input and output voltages of a traditional buffer circuit are the same. Under high load current, the GDRV voltage is high, causing the load transistor at the first stage output of EA to enter the linear region, reducing the gain and thus the accuracy of the error amplifier. Furthermore, the output poles of a traditional buffer circuit are low, which can lead to instability in the feedback system, thereby affecting the dynamic response performance of the error amplifier. The Bode plot of the feedback system of a traditional buffer circuit is shown below. Figure 2 As shown. Summary of the Invention

[0005] To address the aforementioned problems, the purpose of this invention is to propose a high-gain, high-bandwidth voltage-adaptive buffer circuit. This is achieved by increasing the gain of the buffer circuit through the addition of a voltage adaptation stage and a fixed-gain stage. Furthermore, the load in the main buffer circuit uses a low-V... DS With the current mirror structure, the output pole of the BUFFER circuit is pushed to a high frequency, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier.

[0006] This was achieved through the following technical solutions: A high-gain, high-bandwidth voltage adapter buffer circuit, comprising transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, PM1, PM2, PM3, PM4, NPN1, NPN2, NPN3, NPN4, resistors R1 and R2, pull-down current source I1, pull-up current source I2, pull-down current source I3, and a pull-down current source. The circuit consists of current source I4, pull-down current source I5, and pull-down current source I6. The first stage output of EA is connected to the gate of NM1 transistor. The drain of NM1 transistor is connected to the power supply via resistor R1. The sources of NM1 and NM2 transistors are connected to the pull-down current source I1. The drain of NM2 transistor is connected to the pull-up current source I2 via resistor R2. The gate of NM2 transistor is connected to the pull-up current source I2 and the gate of NM3 transistor. The drain of NM3 transistor is connected to the source of NM5 transistor and the base of NPN1 transistor. The current sources of NM3 and NM4 transistors are connected to the power supply via resistor R1. The source of NM4 is connected to a common pull-down current source I3; the gate of NM4 is connected to the GDRV signal, the drain of NM4 is connected to the source of NM6 and the base of NPN2, and the gates and drains of NM5 and NM6 are connected to a common power supply; the emitters of NPN1 and NPN2 are connected to a common pull-down current source I4, the collector of NPN1 is connected to the drain of PM2 and the base of NPN4, and the collector of NPN2 is connected to the drain of PM3 and the base of NPN3; the emitters of NPN3 and NPN4 are connected to a common pull-down current source I4. The collectors of transistors are connected to a common power supply. The emitter of NPN3 is connected to a pull-down current source I6, and the emitter of NPN4 is connected to a pull-down current source I5. The sources of transistors PM1, PM2, PM3, and PM4 are connected to a common power supply. The drain of PM1 is connected to the drain and gate of NM7 and the gate of NM8, and the gate of PM1 is connected to the gate of PM2. The gate of PM3 is connected to the gate of PM4, and the drain of PM4 is connected to the drain of NM8. The sources of NM7 and NM8 are grounded. This invention's circuit improves upon this by adding a voltage adaptation stage and a fixed gain stage, and by using a low-V... DS The current mirror structure can keep the entire feedback system stable and maintain the high accuracy of the error amplifier.

[0007] Preferably, the BUFFER circuit includes a voltage adaptation stage, a fixed gain stage, and a BUFFER main circuit. The BUFFER circuit increases the gain, ensuring the dynamic response performance of the error amplifier.

[0008] Preferably, the voltage adapter stage consists of transistors NM1 and NM2, resistors R1 and R2, a pull-down current source I1, and a pull-up current source I2. By adding a voltage adapter stage to the buffer circuit, a high gain can be maintained, thus preserving the high accuracy of the error amplifier.

[0009] Preferably, the fixed gain stage consists of transistors NM3, NM4, NM5, and NM6, and a pull-down current source I3. By adding a fixed gain stage to the buffer circuit, the gain of the buffer circuit can be increased.

[0010] Preferably, the main BUFFER circuit consists of transistors NM7, NM8, PM1, PM2, PM3, PM4, NPN1, NPN2, NPN3, NPN4, pull-down current source I4, pull-down current source I5, and pull-down current source I6. By using a low-V load in the main BUFFER circuit... DS With the current mirror structure, the output pole of the BUFFER circuit is pushed to a high frequency, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier.

[0011] Preferably, the voltage adapter stage employs a current imbalance design between transistors NM1 and NM2. When the current of transistor NM1 is less than that of transistor NM2, the gate voltage of transistor NM1 is lower than that of transistor NM2, resulting in a lower output voltage of the first stage EA compared to the GDRV signal voltage. This current imbalance design between transistors NM1 and NM2 allows the BUFFER circuit to maintain high gain and the error amplifier to maintain high accuracy.

[0012] Preferably, when the output voltage of the first stage of EA is lower than the GDRV signal voltage, the load transistor at the output terminal of the first stage of EA will operate in the saturation region. By making the load transistor operate in the saturation region, a high gain for the first stage of EA can be guaranteed.

[0013] Preferably, the fixed-gain stage provides a fixed voltage gain between the voltage adapter stage and the main buffer circuit. By providing a fixed voltage gain between the voltage adapter stage and the main buffer circuit, the entire feedback system can remain stable.

[0014] Preferably, the BUFFER main circuit load uses a low V DS Current mirror structure, low V DS The current mirror structure increases bandwidth by reducing the output resistance of the buffer main circuit. This is achieved by using a low V load in the buffer main circuit. DS The current mirror structure can effectively reduce the output impedance of the BUFFER circuit and increase the bandwidth, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier.

[0015] The beneficial effects of this invention compared to the prior art are: The technical solution of this invention, by adding a voltage adaptation stage to the BUFFER circuit, enables the output voltage of the first stage EA to be slightly lower than the GDRV signal voltage. This ensures that the static operating point of the load transistor output by the first stage EA can be guaranteed under certain extreme conditions, thereby maintaining a high circuit gain and high accuracy of the error amplifier. Simultaneously, by adding a fixed gain stage to the BUFFER circuit, the gain of the BUFFER circuit is increased, and a low-V load is used in the BUFFER main circuit load. DS With the current mirror structure, the output pole of the BUFFER circuit is pushed to a high frequency, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier. Attached Figure Description

[0016] Figure 1 The EA circuit diagram for a general-purpose buffer circuit; Figure 2 Bode plot of the feedback system for a general-purpose buffer circuit; Figure 3 The EA circuit diagram is for a high-gain, high-bandwidth voltage adapter buffer circuit. Figure 4 Bode plot of a feedback system for a high-gain, high-bandwidth voltage-adaptive buffer circuit. Detailed Implementation

[0017] The attached image Figure 1-2 This is existing technology, and the following will be combined with the appendix in the embodiments of the present invention. Figure 3-4 The technical solutions in the embodiments of the present invention will be described in detail below.

[0018] like Figure 3 The diagram shown is an EA circuit diagram of a high-gain, high-bandwidth voltage-adaptive buffer circuit. The diagram includes: the first stage of EA, the buffer circuit, and the output stage. The buffer circuit comprises a voltage adaptation stage, a fixed-gain stage, and a main buffer circuit. The voltage adaptation stage consists of transistors NM1 and NM2, resistors R1 and R2, a pull-down current source I1, and a pull-up current source I2. The fixed-gain stage consists of transistors NM3, NM4, and NM5, and a pull-down current source I3. The main buffer circuit consists of transistors NM7, NM8, PM1, PM2, PM3, and PM4, NPN1, NPN2, NPN3, and NPN4, pull-down current sources I4, I5, and I6, as well as I in the diagram. L This indicates a pull-down current source; thus, the circuit of this invention achieves this by adding a voltage adaptation stage and a fixed gain stage, and by using a low V... DS The current mirror structure can keep the entire feedback system stable and maintain the high accuracy of the error amplifier.

[0019] Among them, EA stands for Error Amplifier, which means error amplifier. The first stage of EA represents the input stage circuit of the error amplifier, which is used to detect the error between the input signal and the reference signal and perform preliminary amplification. NM1, NM2, NM3, NM4, NM5, NM6, NM7 and NM8 are all NMOS transistors, PM1, PM2, PM3 and PM4 are all PMOS transistors, and NPN1, NPN2, NPN3 and NPN4 are all NPN bipolar junction transistors.

[0020] The buffer circuit specifically includes the following components: The BUFFER circuit consists of transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, PM1, PM2, PM3, PM4, NPN1, NPN2, NPN3, NPN4, resistors R1 and R2, pull-down current source I1, pull-up current source I2, pull-down current source I3, pull-down current source I4, pull-down current source I5, and pull-down current source I6.

[0021] In this circuit, the first stage output of EA is connected to the gate of NM1 transistor, the drain of NM1 transistor is connected to the power supply via resistor R1, and the sources of NM1 and NM2 transistors are connected to the pull-down current source I1. The drain of NM2 transistor is connected to the pull-up current source I2 via resistor R2, and the gate of NM2 transistor is connected to the pull-up current source I2 and the gate of NM3 transistor.

[0022] The drain of NM3 is connected to the source of NM5 and the base of NPN1. The sources of NM3 and NM4 are connected to the pull-down current source I3. The gate of NM4 is connected to the GDRV signal. The drain of NM4 is connected to the source of NM6 and the base of NPN2. The gates and drains of NM5 and NM6 are connected to the power supply.

[0023] The emitters of NPN1 and NPN2 are connected to a common pull-down current source I4. The collector of NPN1 is connected to the drain of PM2 and the base of NPN4. The collector of NPN2 is connected to the drain of PM3 and the base of NPN3. The collectors of NPN3 and NPN4 are connected to a common power source. The emitter of NPN3 is connected to a pull-down current source I6, and the emitter of NPN4 is connected to a pull-down current source I5. The sources of PM1, PM2, PM3, and PM4 are connected to a common power source. The drain of PM1 is connected to the drain and gate of NM7 and the gate of NM8. The gate of PM1 is connected to the gate of PM2. The gate of PM3 is connected to the gate of PM4. The drain of PM4 is connected to the drain of NM8, and the drain of PM4 is connected to the drain of NM8 as the output terminal of the BUFFER circuit. The sources of NM7 and NM8 are grounded.

[0024] In this embodiment, the BUFFER circuit includes a voltage adaptation stage, a fixed gain stage, and a BUFFER main circuit.

[0025] Specifically, the voltage adapter stage consists of transistors NM1 and NM2, resistors R1 and R2, pull-down current source I1, and pull-up current source I2; the fixed gain stage consists of transistors NM3, NM4, NM5, and NM6, and pull-down current source I3; the BUFFER main circuit consists of transistors NM7, NM8, PM1, PM2, PM3, and PM4, NPN1, NPN2, NPN3, and NPN4, and pull-down current sources I4, I5, and I6.

[0026] This invention relates to a buffer circuit that, under high load current conditions and with a high GDRV signal voltage, maintains high circuit gain and high error amplifier accuracy by adding a voltage adaptation stage. Furthermore, by adding a fixed gain stage to the buffer circuit, the gain of the buffer circuit can be increased, and a low voltage load is used in the main buffer circuit. DS The current mirror structure can effectively reduce the output impedance of the BUFFER circuit and increase the bandwidth. The output pole of the BUFFER circuit is pushed to a high frequency, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier.

[0027] In this embodiment, the voltage adapter stage uses a current imbalance design between transistors NM1 and NM2. When the current of transistor NM1 is less than that of transistor NM2, the gate voltage of transistor NM1 is lower than that of transistor NM2, and the output voltage of the first stage EA is lower than the GDRV signal voltage. The circuit of this invention, through the current imbalance design between transistors NM1 and NM2, can maintain a high gain of the BUFFER circuit and a high accuracy of the error amplifier.

[0028] Specifically, when the output voltage of the first stage of EA is lower than the signal voltage of GDRV, the load transistor at the output terminal of the first stage of EA will operate in the saturation region, thereby ensuring that the first stage of EA has a high gain.

[0029] In this embodiment, the fixed gain stage is used to provide a fixed voltage gain between the voltage adapter stage and the main BUFFER circuit, which can increase the gain of the BUFFER circuit and keep the entire feedback system stable.

[0030] In this embodiment, the BUFFER main circuit load uses a low V DS Current mirror structure, low V DSThe current mirror structure increases bandwidth by reducing the output resistance of the BUFFER main circuit, which can effectively reduce the output impedance of the BUFFER circuit and increase the bandwidth, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier.

[0031] like Figure 4 The figure shows a Bode plot of a feedback system with a high-gain, high-bandwidth voltage-adaptive buffer circuit. This Bode plot primarily represents the stability of the feedback system. Specifically, the horizontal axis represents frequency, and the vertical axis represents gain. The data on the horizontal axis, from low frequency to high frequency, are: dominant pole frequency, dominant pole frequency, and dominant pole frequency. Zero-point compensation frequency First-level EA bandwidth And the frequency of the BUFFER output poles, and the frequency of the BUFFER output poles is very high; data on the y-axis. Indicates circuit gain; The output is the secondary pole frequency, meaning the secondary pole frequency shifts with load changes; where C g C represents the transistor capacitance. L Indicates the output capacitor; R g R represents the resistance; r0 represents the transistor output resistance; g mi Indicates the transconductance of the input stage transistor; g mo This represents the transconductance of the power transistor. -20dB / and -40dB / both represent the gain increase / decrease rate. Generally, in a feedback system's Bode plot, the system is more stable when the gain crosses the horizontal axis at a rate of approximately -20dB / . The two solid black lines in the figure represent the low and high output poles, respectively, both crossing the horizontal axis at a rate of -20dB / . One pole causes the gain to decrease at a rate of -20dB / , and the other zero causes the gain to increase at a rate of 20dB / , so the system is stable here. The attached... Figure 3 The red line in the diagram represents a pole that causes the gain to drop at a rate of -60 dB / s, indicating that the system is unstable.

[0032] In summary, this invention, by adding a voltage adaptation stage to the BUFFER circuit, enables the output voltage of the first stage EA to be slightly lower than the GDRV signal voltage. This ensures that the static operating point of the load transistor output by the first stage EA can be guaranteed under certain extreme conditions, thereby maintaining a high circuit gain and high accuracy of the error amplifier. Simultaneously, by adding a fixed gain stage to the BUFFER circuit, the gain of the BUFFER circuit is increased, and a low-V load is used in the BUFFER main circuit load. DS The current mirror structure pushes the output pole of the BUFFER circuit to a high frequency, thereby keeping the entire feedback system stable and ensuring the dynamic response performance of the error amplifier, which is a significant improvement.

[0033] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A high-gain, high-bandwidth voltage adapter buffer circuit, characterized in that, The BUFFER circuit consists of transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, PM1, PM2, PM3, PM4, NPN1, NPN2, NPN3, NPN4, resistors R1 and R2, pull-down current source I1, pull-up current source I2, pull-down current source I3, pull-down current source I4, pull-down current source I5, and pull-down current source I6. In this circuit, the first stage output of EA is connected to the gate of NM1 transistor, the drain of NM1 transistor is connected to the power supply via resistor R1, and the sources of NM1 and NM2 transistors are connected to the pull-down current source I1. The drain of NM2 transistor is connected to the pull-up current source I2 via resistor R2, and the gate of NM2 transistor is connected to the pull-up current source I2 and the gate of NM3 transistor. The drain of NM3 is connected to the source of NM5 and the base of NPN1. The sources of NM3 and NM4 are connected to the pull-down current source I3. The gate of NM4 is connected to the GDRV signal. The drain of NM4 is connected to the source of NM6 and the base of NPN2. The gates and drains of NM5 and NM6 are connected to the power supply. The emitters of NPN1 and NPN2 are connected to a common pull-down current source I4. The collector of NPN1 is connected to the drain of PM2 and the base of NPN4. The collector of NPN2 is connected to the drain of PM3 and the base of NPN3. The collectors of NPN3 and NPN4 are connected to a common power source. The emitter of NPN3 is connected to a pull-down current source I6, and the emitter of NPN4 is connected to a pull-down current source I5. The sources of PM1, PM2, PM3, and PM4 are connected to a common power source. The drain of PM1 is connected to the drain and gate of NM7 and the gate of NM8. The gate of PM1 is connected to the gate of PM2. The gate of PM3 is connected to the gate of PM4. The drain of PM4 is connected to the drain of NM8. The sources of NM7 and NM8 are grounded.

2. The high-gain, high-bandwidth voltage adapter buffer circuit according to claim 1, characterized in that, The BUFFER circuit includes a voltage adaptation stage, a fixed gain stage, and the BUFFER main circuit.

3. The high-gain, high-bandwidth voltage adapter buffer circuit according to claim 2, characterized in that, The voltage adapter stage consists of transistors NM1 and NM2, resistors R1 and R2, pull-down current source I1, and pull-up current source I2.

4. The high-gain, high-bandwidth voltage adapter buffer circuit according to claim 2, characterized in that, The fixed gain stage consists of transistors NM3, NM4, NM5, and NM6, and a pull-down current source I3.

5. A high-gain, high-bandwidth voltage adapter buffer circuit according to claim 2, characterized in that, The main circuit of the BUFFER consists of NM7, NM8, PM1, PM2, PM3, PM4, NPN1, NPN2, NPN3, NPN4, pull-down current source I4, pull-down current source I5, and pull-down current source I6.

6. A high-gain, high-bandwidth voltage adapter buffer circuit according to claim 2, characterized in that, The voltage adapter stage uses the current imbalance design between transistors NM1 and NM2. When the current of transistor NM1 is less than that of transistor NM2, the gate voltage of transistor NM1 is lower than that of transistor NM2. Therefore, the output voltage of the first stage of EA is lower than the GDRV signal voltage.

7. A high-gain, high-bandwidth voltage adapter buffer circuit according to claim 6, characterized in that, When the output voltage of the first stage of EA is lower than the signal voltage of GDRV, the load transistor at the output terminal of the first stage of EA will operate in the saturation region.

8. A high-gain, high-bandwidth voltage adapter buffer circuit according to claim 2, characterized in that, The fixed gain stage is used to provide a fixed voltage gain between the voltage adapter stage and the BUFFER main circuit.

9. A high-gain, high-bandwidth voltage adapter buffer circuit according to claim 2, characterized in that, The main circuit load of the buffer uses a low voltage. DS Current mirror structure, low V DS The current mirror structure increases bandwidth by reducing the output resistance of the BUFFER main circuit.

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