Internal error correction sequence for memory devices

Abstract

The invention relates to an internal error correction sequence for a memory device. In some embodiments, a memory device may determine that the memory device has encountered an internal error that requires an internal reset of at least one component of the memory device. The memory device may transmit a first stage notification to a host device indicating that the memory device has encountered the internal error. The memory device may store diagnostic data associated with the internal error to a non-volatile storage component of the memory device. The memory device may perform a first stage reset of a first set of internal memory device subsystems based on storing the diagnostic data to the non-volatile storage component. The memory device may transmit a second stage notification to the host device after the first stage notification and based on performing the first stage reset indicating that the host device is to perform a memory device reset procedure.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 650,176, filed May 21, 2024, entitled “INTERNAL ERROR CORRECTION SEQUENCES FOR A MEMORY DEVICE,” and assigned to the present assignee. The disclosure of the prior application is considered part of this patent application and is hereby incorporated by reference into this patent application. TECHNICAL FIELD

[0003] The present disclosure generally relates to memory devices, memory device operations, and, for example, to internal error correction sequences for a memory device. BACKGROUND

[0004] Memory devices are widely used in electronic devices to store information. A memory device includes memory cells. A memory cell is an electronic circuit that can be programmed to a data state of two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value, typically represented by a binary “1” or a binary “0.” As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, etc.). To store information, an electronic device can write or program a set of memory cells. To access stored information, an electronic device can read or sense the stored state from a set of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND and NOR flash memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for a long period of time even in the absence of an external power source. Volatile memory (e.g., DRAM) can lose stored data over time unless refreshed by a power source. In some examples, a memory device can be associated with compute express link (CXL). For example, a memory device can be a CXL compatible memory device and / or can include a CXL interface. SUMMARY

[0006] Aspects of the present disclosure relate to a memory device comprising one or more components configured to: determine that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; transmit, to a host device, a first stage notification indicating that the memory device has encountered the internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the memory device; perform a first stage reset of a first set of internal memory device subsystems; and transmit, to the host device and based on performing the first stage reset, a second stage notification indicating that the host device is to perform a memory device reset procedure after the first stage notification.

[0007] Another aspect of the present disclosure relates to a method comprising: determining, by a memory device, that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; transmitting, by the memory device, to a host device, a first stage notification indicating that the memory device has encountered the internal error; saving, by the memory device, diagnostic data associated with the internal error to a byte-addressable non-volatile storage component of the memory device; performing a first stage reset of a first set of internal memory device subsystems; and transmitting, by the memory device, to the host device and based on performing the first stage reset, a second stage notification indicating that the host device is to perform a memory device reset procedure after the first stage notification.

[0008] Yet another aspect of the present disclosure relates to a compute express link (CXL) memory module comprising one or more components configured to: determine that the CXL memory module has encountered an internal error requiring an internal reset of at least one component of the CXL memory module; transmit, to a host system, a first stage notification indicating that the CXL memory module has encountered the internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the CXL memory module; determine a type of the internal reset to be performed; select, based on determining the type of the internal reset to be performed, one or more reset levels of a plurality of potential reset levels to be used for the internal reset; and perform a first stage reset of a first set of internal memory device subsystems based on the one or more reset levels. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a diagram illustrating an example system capable of implementing an internal error correction sequence for a memory device.

[0010] Figure 2 is a diagram illustrating another example system capable of implementing an internal error correction sequence for a memory device.

[0011] Figures 3A to 3Cis a diagram of an example associated with an internal error correction sequence for a memory device.

[0012] Figure 4 is a flow diagram of an example method associated with an internal error correction sequence for a memory device.

[0013] Figure 5 is a flow diagram of another example method associated with an internal error correction sequence for a memory device.

[0014] Figure 6 is a flow diagram of another example method associated with an internal error correction sequence for a memory device. DETAILED DESCRIPTION

[0015] In some examples, a memory device can be configured to detect and / or handle internal errors, such as by initiating a firmware emergency sequence. A "firmware emergency sequence" can refer to a series of actions and / or events triggered by the firmware of a device when the device encounters a critical error or failure that cannot be corrected by the normal progression of the firmware. In some examples, a memory device can detect an internal error (e.g., a critical error), such as an error due to a hardware failure, corrupted data, and / or other issues that compromise the integrity and / or functionality of the memory device. Accordingly, the memory device (e.g., the firmware of the memory device) can initiate an emergency sequence, which can be a sequence designed to prevent further damage and / or data loss and / or to notify a user of the critical error. In some cases, the firmware can interrupt ongoing operations and / or processes that can lead to further errors, such as by stopping data transfer, disabling write operations, placing the memory device in a safe state, and / or the like. Further, the firmware can record information about the error, such as by saving details (e.g., in a non-volatile storage device), such as an error code, a timestamp, and / or other diagnostic information that can later be used to help identify the root cause of the problem. In some examples, the firmware can notify a user of the error, such as by providing a visual indication (e.g., via a light associated with the memory device) and / or by transmitting certain indications via a system log, among other examples. Further, the firmware can attempt to recover from the error condition, such as by resetting the memory device, performing internal diagnostics and / or self-tests, attempting to restore the memory device to a known good state, and / or performing similar operations.

[0016] In some instances, despite the above procedures and / or similar emergency sequence operations, the memory device emergency sequence can result in silent data corruption, cascading errors, and / or similar errors at the memory device and / or connected host device. For example, any data sent from the memory device to the host device after an internal error has been detected and before an appropriate error recovery sequence occurs can be invalid due to the error condition that caused the device firmware emergency sequence to be initiated. However, the host device can not know that the data is corrupted until after certain error handling operations are completed, resulting in silent data corruption at the host device. On the other hand, in cases where the memory device immediately stops transmission of data to the host device in response to detecting an internal error, the stopped transmission can result in a repeated host command timeout at the host device, resulting in an error cascade and thus more difficult fault analysis and / or error recovery procedures.

[0017] Further, due to the nature of the internal error, recording error information, such as by saving diagnostic data in non-volatile storage, can be time consuming, resource intensive, and / or unavailable. For example, recording diagnostic data, sometimes referred to herein as performing an emergency dump, can be implemented using page-addressable non-volatile memory that requires durability management. In such instances, durability management can be provided by a flash translation layer (FTL), and thus in order to store an emergency dump into the page-addressable non-volatile memory, recovery of the FTL firmware can be required. Recovery of the FTL firmware can be performed by rebooting one or more memory device central processing units (CPUs), which can be a time-intensive and / or resource-intensive process. Further, rebooting one or more CPUs can require execution of firmware in hardware that causes the firmware emergency sequence to be initiated, which can thus fail when the memory device attempts to initialize the hardware that is in a fault state. In such cases, the emergency dump can not be saved, resulting in the inability to diagnose the internal error and / or resulting in the memory device experiencing a similar internal error in the future.

[0018] Additionally or alternatively, in some examples, a memory device (e.g., a compute express link (CXL) compatible memory device) can be a coherent device with a processor (e.g., a host device), and thus can be considered another processor package, among other examples. In such examples, the memory device can be associated with a fabric manager, and / or can need to provide notification to the fabric manager prior to a managed hot removal and / or sudden removal of the memory device to avoid a host device panic and / or crash. In some other examples, the memory device can be a single logical device (SLD) or a dual ported device that is not associated with a fabric manager, and thus can need to avoid sudden removal conditions entirely to avoid a host device panic and / or crash. However, certain processes of a firmware panic sequence can result in a sudden removal condition without notification to the fabric manager. For example, a memory device firmware can initiate a panic sequence in response to detecting an issue in a host interface management component (sometimes referred to herein as a host interface module). In such examples, resetting the host interface management component in an attempt to recover from an internal error can result in a sudden removal condition, which can result in a host device panic and / or crash.

[0019] Some implementations described herein implement improved memory device internal error handling sequences (e.g., improved firmware panic sequences), for example by implementing internal error handling sequences that result in reduced silent data corruption, reduced cascading errors, improved panic dump sparing operations resulting in more reliable diagnostic information and / or reduced time and / or resource consumption associated with diagnostic procedures, and / or reduced sudden removal conditions resulting in reduced occurrences of host device panics and / or crashes. In some implementations, a memory device can be configured to utilize a two-stage notification procedure, for example by transmitting a first stage notification indicating that the memory device has encountered an internal error to a host device in response to determining that the memory device has encountered an internal error, and then transmitting a second stage notification after performing certain internal error handling steps. In this way, the memory device can continue to transmit data (e.g., flits) to the host device during the internal handling procedure to avoid host command timeouts and / or similar cascading errors, while notifying the host device that an error has occurred early in the internal error handling sequence to avoid silent data corruption.

[0020] Additionally or alternatively, the two-stage notification procedure can enable the memory device to complete certain time-consuming steps (e.g., steps associated with saving diagnostic data to non-volatile byte-addressable memory and / or steps associated with performing a first-stage internal reset, among other time-consuming steps) prior to any notification stage associated with certain time limits. For example, a peripheral component interconnect express (PCIe) hot reset required notification (which, in some instances, can correspond to the second-stage host notification step described herein) can initiate a PCIe specification required timeout, within which the memory device can be required to return to normal operation. In such instances, completing diagnostic data save steps prior to the PCIe hot reset required notification step can enable the memory device to complete the PCIe hot reset sequence within the PCIe specification required time limit.

[0021] Additionally or alternatively, the memory device can be configured to store diagnostic data associated with the internal error handler (e.g., a panic dump) to a byte-addressable non-volatile storage component associated with the memory device. In some implementations, the byte-addressable non-volatile storage component can not require endurance management, thereby eliminating the need to repair FTL after initiating a firmware panic sequence and / or the need to restart the CPU after initiating a firmware panic sequence, thereby reducing the complexity of the procedure associated with saving diagnostic data, and thus reducing the power, compute, and other resource consumption associated with saving diagnostic data, and / or resulting in a more reliable diagnostic procedure and thus improving memory device operation.

[0022] Additionally or alternatively, the memory device can be configured to classify the type of internal reset required to recover from an internal error, and / or select a particular reset level to be performed based on the type of internal reset required. For example, the memory device can be configured to select one or more of a first level reset, which can be associated with resetting certain non-host interface management components of the memory device, and / or a second level reset, which can be associated with resetting host interface management components of the memory device. In this way, when an internal error is unrelated to the host interface module and / or when the fabric manager is unavailable, the memory device can avoid resetting host interface management components of the memory device, thereby reducing instances of sudden removal conditions and / or instances of triggering a host device panic and / or firmware panic sequence to recover from, and thus reducing power, compute, and / or other resource consumption that would otherwise be unnecessarily reset host interface modules and / or recover from unnecessarily triggered host device panics and / or firmware panic sequences.

[0023] Figure 1is a diagram illustrating an example system 100 capable of implementing an internal error correction sequence for a memory device. The system 100 can include one or more devices, apparatus, and / or components for performing the operations described herein. For example, the system 100 can include a host system 105 and a memory system 110. The memory system 110 can include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 through 120-N (where N > 1). The memory devices can include a local controller 125 and one or more memory arrays 130. The host system 105 can communicate with the memory system 110 (e.g., the memory system controller 115 of the memory system 110) via a host interface 140. The memory system controller 115 and the memory devices 120 can communicate via respective memory interfaces 145, shown as memory interfaces 145-1 through 145-N (where N > 1).

[0024] The system 100 can be any electronic device configured to store data in memory. For example, the system 100 can be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., an automobile or an airplane), and / or an Internet of Things (IoT) device. The host system 105 can include a host processor 150. The host processor 150 can include one or more processors configured to execute instructions and store data in the memory system 110. For example, the host processor 150 can include a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or another type of processing component.

[0025] The memory system 110 can be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 can be a hard disk drive, a solid state drive (SSD), a flash memory system (e.g., a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (e.g., a secure digital (SD) card), a secondary storage device, a non-volatile memory express (NVMe) device, an embedded Multi-Media Card (eMMC) device, a dual in-line memory module (DIMM), a CXL memory module, and / or a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0026] The memory system controller 115 can be any device configured to control operations of the memory system 110 and / or operations of the memory devices 120. For example, the memory system controller 115 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the memory system controller 115 can be in communication with the host system 105 and can instruct one or more memory devices 120 regarding memory operations to be performed by the one or more memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 can provide instructions to the local controller 125 regarding memory operations to be performed by the corresponding memory device 120 in conjunction with the local controller 125.

[0027] The memory devices 120 can include a local controller 125 and one or more memory arrays 130. In some implementations, a memory device 120 includes a single memory array 130. In some implementations, each memory device 120 of the memory system 110 can be implemented in a separate semiconductor package or on a separate die including the respective local controller 125 and the respective memory array 130 of the memory device 120. The memory system 110 can include a plurality of memory devices 120.

[0028] The local controller 125 can be any device configured to control memory operations of the memory device 120 within which the local controller 125 is included (e.g., and not control memory operations of other memory devices 120). For example, the local controller 125 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, a compute express link (CXL) controller connected to DRAM, and / or one or more processing components. In some implementations, the local controller 125 can be in communication with the memory system controller 115 and can control operations performed on the memory array 130 coupled with the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 can be a SSD controller and the local controller 125 can be a NAND controller.

[0029] The memory array 130 can include an array of memory cells configured to store data. For example, the memory array 130 can include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some implementations, the memory system 110 can include one or more volatile memory arrays 135. The one or more volatile memory arrays 135 can include SRAM arrays and / or DRAM arrays, among other examples. The one or more volatile memory arrays 135 can be included in the memory system controller 115, included in the one or more memory devices 120, and / or included in both the memory system controller 115 and the one or more memory devices 120. In some implementations, the memory system 110 can include both non-volatile memory capable of maintaining stored data after the memory system 110 is powered down and volatile memory (e.g., the volatile memory array 135) that requires power to maintain stored data and loses stored data after the memory system 110 is powered down. For example, the volatile memory array 135 can cache data read from or to be written to non-volatile memory and / or can cache instructions to be executed by a controller of the memory system 110.

[0030] The host interface 140 enables communication between the host system 105 (e.g., a host processor 150) and the memory system 110 (e.g., the memory system controller 115). The host interface 140 can include, for example, a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA) interface, a PCIe interface, an NVMe interface, a USB interface, a universal flash storage (UFS) interface, an eMMC interface, a double data rate (DDR) interface, a DIMM interface, and / or a CXL interface (e.g., the PCIe / CXL interface described in more detail below). Figure 2

[0031] The memory interface 145 enables communication between the memory system 110 and the memory devices 120. The memory interface 145 can include a non-volatile memory interface (e.g., for communication with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 145 can include a volatile memory interface (e.g., for communication with volatile memory), such as a DDR interface.

[0032] ​While the example memory system 110 described above includes the memory system controller 115, in some implementations, the memory system 110 does not include the memory system controller 115. For example, an external controller (e.g., included in the host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 can perform operations described herein as being performed by the memory system controller 115. Moreover, as used herein, a “controller” can refer to the memory system controller 115, a local controller 125, or an external controller. In some implementations, a set of operations described herein as being performed by a controller can be performed by a single controller. For example, an entire set of operations can be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller can be performed by more than one controller. For example, a first subset of operations can be performed by the memory system controller 115 and a second subset of operations can be performed by a local controller 125. Moreover, the term “memory device” can refer to the memory system 110 or the memory device 120, depending on the context.

[0033] A controller (e.g., the memory system controller 115, a local controller 125, or an external controller) can control operations performed on a memory (e.g., the memory array 130), for example, by executing one or more instructions. For example, the memory system 110 and / or the memory device 120 can store one or more instructions as firmware in a memory, and a controller can execute the one or more instructions. Additionally or alternatively, a controller can receive one or more instructions from the host system 105 and / or from the memory system controller 115, and can execute the one or more instructions. In some implementations, a non-transitory computer- readable medium (e.g., a volatile memory and / or a non-volatile memory) can store a set of instructions (e.g., one or more instructions or code) for execution by a controller. A controller can execute the set of instructions to perform one or more operations or methods described herein. In some implementations, execution of the set of instructions by a controller causes the controller, the memory system 110, and / or the memory device 120 to perform one or more operations or methods described herein. In some implementations, hardwired circuitry can be used in place of or in combination with the one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, a controller can be configured to perform one or more operations or methods described herein. An instruction is sometimes referred to as a “command.”

[0034] For example, a controller (e.g., a memory system controller 115, a local controller 125, or an external controller) can transmit and / or receive signals to and / or from a memory (e.g., one or more memory arrays 130) based on one or more instructions in order to transfer (e.g., write or program) data to all or a portion of the memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory), transfer data from all or a portion of the memory (e.g., read), erase all or a portion of the memory, and / or refresh all or a portion of the memory. Additionally or alternatively, a controller can be configured to control access to the memory and / or provide a translation layer between the host system 105 and the memory (e.g., for mapping logical addresses of the memory array 130 to physical addresses). In some implementations, a controller can translate host interface commands (e.g., commands received from the host system 105) into memory interface commands (e.g., commands for performing operations on the memory array 130).

[0035] In some implementations, Figure 1 One or more systems, apparatuses, devices, components, and / or controllers of the same can be configured to determine that a memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; transmit, to a host device, a first stage notification indicating that the memory device has encountered the internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the memory device; perform a first stage reset of a first set of internal memory device subsystems; and transmit, to the host device after the first stage notification and based on performing the first stage reset, a second stage notification indicating that the host device is to perform a memory device reset procedure.

[0036] In some implementations, Figure 1 One or more systems, apparatuses, devices, components, and / or controllers of the same can be configured to determine that a memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; transmit, to a host device, a first stage notification indicating that the memory device has encountered the internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the memory device; perform a first stage reset of a first set of internal memory device subsystems; and transmit, to the host device after the first stage notification and based on performing the first stage reset, a second stage notification indicating that the host device is to perform a memory device reset procedure.

[0037] In some implementations, Figure 1One or more systems, apparatuses, devices, components, and / or controllers of the present disclosure can be configured to determine that a CXL memory module has encountered an internal error that requires an internal reset of at least one component of the CXL memory module; transmit, to a host system, a first stage notification indicating that the CXL memory module has encountered an internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the CXL memory module; determine a type of internal reset to be performed; select, based on the determining the type of internal reset to be performed, one or more reset levels of a plurality of potential reset levels to be used for the internal reset; and perform a first stage reset of a first set of internal memory device subsystems based on the one or more reset levels.

[0038] As an example, the number and arrangement of components shown in Figure 1 may vary from that shown in Figure 1 may exist, than those shown in Figure 1 may be implemented within a single component, or Figure 1 may be implemented as multiple distributed components. Additionally or alternatively, Figure 1 a set of components (e.g., one or more components) of Figure 2 may perform one or more operations described as being performed by another set of components.

[0039] Figure 2 is a diagram illustrating another example system 200 capable of implementing an internal error correction sequence for a memory device. System 200 can include one or more devices, apparatuses, and / or components for performing the operations described herein. In some examples, system 200 can be associated with a CXL protocol (e.g., system 200 can utilize a CXL protocol to communicate between a host device (sometimes referred to as a CXL host) and a memory device (sometimes referred to as a CXL device)) and / or can be a CXL compatible system. In this regard, system 200 can include a CXL host 202 (which can correspond to host system 105) and a CXL device 204 (e.g., a CXL compatible memory system, which can correspond to memory system 110). CXL host 202 and CXL device 204 can communicate via an interface 203 (e.g., host interface 140), which can include a system management (SM) bus 206 and / or a CXL bus 208 (e.g., a PCIe / CXL interface), among other examples.

[0040] In some examples, the CXL device 204 can be a CXL-compatible memory system (sometimes referred to herein as a CXL memory system, a CXL memory device, a CXL memory module, and / or the like). CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation performance. CXL technology maintains memory coherency between CPU memory space and memory on attached devices, which allows resource sharing to enable higher performance, reduced software stack complexity, and reduced overall system cost. CXL is designed as an industry open standard interface for high-speed communications. CXL technology builds on the PCIe infrastructure, leveraging the PCIe physical and electrical interface to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols, and coherency interfaces.

[0041] In some examples, the memory system 110 can include a PCIe / CXL interface (e.g., the CXL bus 208 can be associated with a PCIe / CXL interface), which can be a physical interface configured to connect the CXL device 204 to a CXL-compatible host device (e.g., the CXL host 202). In such examples, the PCIe / CXL interface can adhere to the CXL standard specification for physical connectivity, ensuring broad compatibility and ease of integration into existing systems using the CXL protocol. Additionally or alternatively, the CXL device 204 can be designed to effectively interface with computing systems (e.g., the CXL host 202 and / or the host system 105) by leveraging the CXL protocol. For example, the CXL device 204 can be configured to leverage the high-speed, low-latency interconnect capabilities of CXL, such as for purposes of fitting the CXL device 204 for high-performance computing, data center applications, artificial intelligence (AI) applications, and / or the like.

[0042] In some examples, CXL device 204 can include a CXL memory controller (which can correspond to memory system controller 115 and / or local controller 125) that can be configured to manage data flow between a memory array (shown as CXL-attached memory 218, which can correspond to volatile memory array 135 and / or memory array 130) and a CXL interface (e.g., CXL bus 208). In some examples, the CXL memory controller can be configured to handle one or more CXL protocol layers, such as an I / O layer (e.g., a layer associated with the CXL.io protocol, which can be used for purposes such as device discovery, configuration, initialization, I / O virtualization, direct memory access (DMA) using non-coherent load-store semantics, and / or similar purposes); a cache coherency layer (e.g., a layer associated with the CXL.cache protocol, which can be used for purposes such as cache host memory using a modified, exclusive, shared, invalid (MESI) coherency protocol, or similar purposes); or a memory protocol layer (e.g., a layer associated with the CXL.memory (sometimes referred to as CXL.mem) protocol, which can enable a CXL memory device to expose host managed device memory (HDM) to permit a host device to manage and access memory similar to native DDR connected to the host); among other examples.

[0043] CXL device 204 can further include and / or be associated with one or more high-bandwidth memory modules (HBMMs) or similar memory arrays (e.g., CXL-attached memory 218). For example, CXL device 204 can include multiple layers of DRAM (e.g., stacked and / or interconnected through advanced through-silicon via (TSV) technology) in order to maximize storage density and / or enhance the speed of data transfer between memory layers. Additionally or alternatively, CXL device 204 can include a power management unit that can be configured to regulate power consumption associated with CXL device 204 and / or that can be configured to improve the energy efficiency of CXL device 204. Additionally or alternatively, CXL device 204 can include additional components, such as one or more error-correcting code (ECC) engines, for purposes such as detecting and / or correcting data errors to ensure data integrity and / or to improve the overall reliability of CXL device 204. CXL device 204 can be implemented using a combination of hardware and firmware blocks and / or components. In such examples, firmware can be executed on one or more embedded CPUs within CXL device 204.

[0044] Additionally or alternatively, the CXL device 204 and / or a CXL controller (e.g., ASIC) of the CXL device 204 can include a CXL host interface hardware 210, an I / O path hardware logic and DMA controller 212, a host management subsystem 214, and / or a host interface (HIF) management subsystem 216, among other examples. In some examples, the CXL host interface hardware 210 can be a hardware component that enables physical connections between the CXL device 204 and one or more external devices, such as to the CXL host 202 via the SM bus 206 and / or the CXL bus 208. In some examples, the CXL host interface hardware 210 can include the necessary physical interfaces and protocol logic required to establish and / or maintain communications over a CXL link (e.g., via the CXL bus 208). In some cases, the CXL host interface hardware 210 can ensure that the CXL host 202 can effectively access and / or control the CXL device 204.

[0045] The I / O path hardware logic and DMA controller 212 can handle data transfers between the CXL device 204 and external devices (e.g., other memory modules and / or peripheral components). In some examples, the DMA controller portion of the I / O path hardware logic and DMA controller 212 can allow for efficient data transfers directly without involving the CXL device 204 CPU. In other words, the DMA controller portion of the I / O path hardware logic and DMA controller 212 can manage data movement between the CXL device 204 and other system components, which can enhance overall system performance by offloading data transfer tasks from the CPU.

[0046] The host management subsystem 214 can act as a central control and management unit within the CXL device 204. In some examples, the host management subsystem 214 can include various functionalities and tasks, such as memory access control, error detection and / or correction, power management, and / or similar system management functionalities and / or tasks. Additionally or alternatively, the host management subsystem 214 can ensure proper functionality and / or reliability of the CXL device 204 and / or can optimize performance of the CXL device 204 under various operating conditions.

[0047] The HIF management subsystem 216 can be responsible for managing and / or controlling the CXL host interface hardware 210, among other tasks. In some examples, the HIF management subsystem 216 can handle tasks related to link initialization configuration negotiation, error handling, and / or other protocol-specific functionalities with the CXL host 202. Additionally or alternatively, the HIF management subsystem 216 can ensure smooth communications between the CXL device 204 and / or the CXL host 202, such as by maintaining compatibility and / or reliability of the CXL link, among other examples.

[0048] In some examples, CXL device 204 can be classified as a CXL Type 1 device, a CXL Type 2 device, or a CXL Type 3 device. A CXL Type 1 device can be a device that implements coherent caches using the CXL.cache protocol. A CXL Type 2 device can be a device that implements both coherent caches using the CXL.cache protocol and host-managed device memory using the CXL.mem protocol. For example, a CXL Type 2 device can be a hardware accelerator device. A CXL Type 3 device can be a device that implements host-managed device memory using the CXL.mem protocol. For example, a CXL Type 3 device can be a memory expansion device.

[0049] As an example, the number and arrangement of components shown in Figure 2 may be different than the number and arrangement of components shown in Figure 2 may be implemented in a single component, or multiple components, Figure 2 may be implemented, e.g., one or more components shown in Figure 2 may be implemented as multiple, distributed components. Additionally, or Figure 2 one or more operations described as being performed by one group of components Figures 3A to 3C may be performed by another group of components; or a combination thereof.

[0050] Figure 2 is an example diagram associated with an internal error correction sequence for a memory device. The operations described in connection with FIG. 3 can be performed by memory system 110 and / or one or more components of memory system 110 (e.g., memory system controller 115, one or more memory devices 120, and / or one or more local controllers 125), and / or by CXL device 204 and / or one or more components of CXL device 204 (e.g., I / O path hardware logic and DMA controller 212, host management subsystem 214, and / or HIF management subsystem 216).

[0051] In some implementations, a CXL device, such as described above in connection with Figure 3AThe described CXL device 204 can be configured to implement internal error correction sequences, such as firmware emergency sequences or similar error correction sequences. As described above, a "firmware emergency sequence" can refer to a sequence initiated by the firmware when the internal device firmware (e.g., firmware running on the embedded CPU of the CXL device 204) detects firmware and / or hardware errors that cannot be handled by the normal firmware process. In such cases, the firmware may collect diagnostic data (e.g., an emergency dump) and save the diagnostic data to non-volatile storage, and / or the firmware may trigger an internal reset to recover from the firmware and / or hardware errors, thus continuing the normal firmware execution sequence. For example, errors that may cause the firmware of the CXL device 204 to initiate a firmware emergency sequence may include CPU memory bus transaction errors (e.g., errors caused by the CXL device 204 CPU attempting to load and / or store to an invalid memory address and / or perform an invalid memory address alignment), CPU stack overflows, CPU instruction memory multi-bit ECC errors, firmware assertion condition failures, watchdog timeouts due to hardware or firmware state machine suspension conditions, and / or similar errors.

[0052] Figure 3A Example 300 demonstrates the association of two notifications transmitted to the host device and other features of the firmware emergency sequence procedure. For ease of discussion, [further details are provided]. Figure 3A The operations demonstrated and described involve operations and / or communications performed by the CXL device 204 and the CXL host 202. However, in some other embodiments, other memory devices and / or host devices may perform operations as described below. Figure 3A The operations described are essentially similar. For example, combining... Figure 1 The demonstration and description can be combined with the above text. Figure 3C The described memory system 110 and / or host system 105, as well as other instances, are executed.

[0053] In some embodiments, any data sent by the CXL device 204 to the CXL host 202 after a firmware emergency has occurred and before an appropriate error recovery sequence has occurred can be invalid, depending on the error condition that caused the CXL device 204 to initiate the firmware emergency. However, an internal error that caused the CXL device 204 to initiate the firmware emergency sequence and / or the firmware emergency sequence itself can have corrupted the current normal host execution sequence, and thus can need to be fixed in a future firmware version and / or handled more slowly to prevent the normal host execution sequence from being corrupted. Thus, the CXL device 204 can collect and / or save internal device diagnostic data at the time of the firmware emergency, such that the diagnostic data can be retrieved by the CXL host 202 (e.g., for offline analysis). In this regard, the CXL device 204 can implement a two-stage host notification during the firmware emergency sequence, such as for the purpose of avoiding silent user data corruption (e.g., to prioritize clearly marking any data sent back to the CXL host 202 after an internal error has occurred as invalid), allowing the CXL host 202 to continue progressing forward and / or avoiding unrecoverable host errors that can require a host cold reset (e.g., a power cycle of the CXL host 202), avoiding error cascades (e.g., cascading host command timeouts) that can otherwise make fault analysis more difficult, allowing the CXL device 204 to collect and / or save internal diagnostic data to non-volatile media (e.g., byte-addressable non-volatile memory and other examples) for later retrieval and / or offline fault analysis, and / or allowing the CXL host 202 to take appropriate error mitigation and / or recovery steps.

[0054] More specifically, as indicated by reference number 302, the CXL device 204 can detect an internal error. That is, as part of the firmware emergency sequence, the CXL device 204 firmware can perform a device internal error detection step, in which the firmware detects an internal error that requires an internal device-level hardware or firmware reset to recover from. In such a case, the firmware can initiate the firmware emergency sequence. For example, the firmware running on the CXL device 204 can detect an internal fatal uncorrectable error (e.g., an internal error that requires an internal reset of at least one component of the CXL device 204), and thus the firmware can initiate the firmware emergency sequence.

[0055] As indicated by reference number 304, the CXL device 204 can include an internal error, such as by causing the embedded CPUs within the CXL device 204 to transition to a firmware emergency error handling routine, among other examples. That is, as part of the firmware emergency sequence, the CXL device 204 firmware can perform a device firmware internal error suppression step in which the internal device firmware notifies the firmware running on all embedded CPUs that the firmware emergency sequence has been initiated. In some implementations, the embedded CPUs can thus switch to a firmware emergency error handling routine, which can include switching to a dedicated CPU stack and / or using only limited hardware functionality in any remaining firmware emergency steps, such as for the purpose of reducing the probability of encountering additional errors during the firmware emergency sequence.

[0056] As indicated by reference number 306, the CXL device 204 can transmit a first stage notification indicating that the CXL device 204 has encountered an internal error, and the CXL host 202 can receive the first stage notification. That is, as part of the firmware emergency sequence, the CXL device 204 firmware can perform a first stage host notification step. For example, the CXL device 204 can send an initial notification to the CXL host 202 informing the CXL host 202 that an internal device error has occurred. In such implementations, the first stage host notification step can be used to indicate to the CXL host 202 that commands currently in progress within the CXL device 204 (sometimes referred to as in-flight commands) and / or new commands sent to the CXL device 204 can complete with an error status and / or can return invalid data.

[0057] In some implementations, the CXL device 204 can transmit the first stage notification using one or more flits transmitted by the CXL device 204 to the CXL host 202. For example, the CXL device 204 can enter a viral mode, such as the CXL viral mode defined by the CXL 2.0 specification. In such implementations, the CXL device 204 can set a viral status bit (sometimes referred to as a Viral_Status bit) in a designated vendor specific extension capability (DVSEC) CXL status register, such as the bit at the 0E hex offset in the DVSEC CXL status register. In some implementations, the CXL device 204 can set the viral status bit in the DVSEC CXL status register based on setting a viral enable bit (sometimes referred to as a Viral_Enable bit) in a DVSEC CXL control register.

[0058] Additionally or alternatively, the CXL device 204 can transmit a first stage notification, e.g., by the device link layer on the CXL port (e.g., a port associated with the CXL bus 208) forcing a cyclic redundancy check (CRC) error on the next outgoing flit and asserting a virus bit in a subsequent retry-acknowledge flit (sometimes referred to as a RETRY.ack flit), as defined in the CXL protocol. In other words, in some embodiments, the first stage notification can be implemented by the CXL device 204 forcing a CRC check error on a flit transmitted by the CXL device 204 to the CXL host 202 (e.g., the next outgoing flit after setting the virus status bit) and / or the CXL device setting the virus bit in another flit transmitted by the CXL device 204 to the CXL host 202 (e.g., the RETRY.ack flit). This can alert the CXL host 202 that the CXL device 204 has entered the firmware emergency sequence, and thus does not trust the validity of subsequently transmitted data (e.g., flits), thereby avoiding silent data corruption, while allowing the CXL device 204 to continue sending transmissions during the diagnostic data collection phase, thereby avoiding repeated host command timeouts and thus cascading errors.

[0059] As indicated by reference number 308, the CXL device 204 can perform an internal error classification procedure. In other words, as part of the firmware emergency sequence, the CXL device 204 firmware can perform a device internal error classification step. For example, the CXL device 204 firmware can determine whether special error handling steps are required, e.g., based on whether the internal error source requires special error handling steps. In some embodiments, the CXL device 204 firmware can select one or more reset levels to be used to correct the internal device error (e.g., one or more of a first reset level associated with resetting non-host interface components of the CXL device 204, a second reset level associated with resetting host interface components of the CXL device 204, and / or the like), which will be described in more detail below in connection with FIG. 4. Figure 3B More detail is described.

[0060] As indicated by reference number 310, the CXL device 204 can perform diagnostic data collection. That is, as part of the firmware bailout sequence, the CXL device 204 firmware can perform a device internal diagnostic data collection step. For example, the CXL device 204 firmware, such as firmware running on multiple CPU cores, can coordinate to capture a snapshot of the internal device state at the time of an internal error and / or diagnostic data, such as diagnostic data associated with CPU core stack frames, CPU registers, hardware registers, internal device memory address ranges, and / or the like, to enable offline error root cause analysis. Additionally or alternatively, as indicated by reference number 312, the CXL device 204 can save diagnostic data to non-volatile memory. In other words, as part of the firmware bailout sequence, the CXL device 204 firmware can perform a device internal diagnostic data save to device internal non-volatile media step. For example, the CXL device 204 firmware can save diagnostic data to non-volatile media for later retrieval such that diagnostic data can be stored even if the CXL device 204 experiences a power removal before the diagnostic data can be retrieved. In some embodiments, the non-volatile media can be associated with a byte-addressable non-volatile memory, described in more detail below in connection with Figure 3B The byte-addressable non-volatile memory is described in more detail.

[0061] As indicated by reference number 314, the CXL device 204 can perform a first stage error recovery procedure. In other words, as part of the firmware bailout sequence, the CXL device 204 firmware can perform a first stage device internal error recovery step. For example, the CXL device 204 firmware can initiate a reset of internal device subsystems (e.g., internal device hardware subsystems) that maintain a host interface link (e.g., a CXL link via the CXL bus 208) and / or are not needed in response to any host commands. In some embodiments, this can allow certain internal device subsystems to return to normal functionality.

[0062] As indicated by reference number 316, the CXL device 204 can transmit a second stage host notification, and the CXL host 202 can receive the second stage host notification. That is, as part of the firmware emergency sequence, the CXL device 204 firmware can perform a second stage host notification step. For example, the CXL device 204 can send a notification to the CXL host 202 indicating that the host is to perform a device reset, such as for the purpose of clearing all internal device error status codes and / or returning the CXL device 204 to normal functionality. In some implementations, the second stage notification can be implemented by the CXL device 204 asserting a hot reset status in a memory device status register’s need reset field (e.g., the second stage notification can indicate that the CXL host 202 is to perform a memory device reset procedure by asserting a hot reset status using the memory device status register’s need reset field, as defined by the CXL 2.0 specification), such as for the purpose of notifying the CXL host 202 that a PCIe hot reset is needed to recover from an internal device virus error condition. Additionally or alternatively, as part of the second stage notification operation, in some implementations the CXL device 204 can create a memory module fatal error event record (e.g., the CXL device 204 can create a memory module fatal error event record, as defined by the CXL 2.0 specification), set a bit corresponding to the memory module fatal error event record in an event status register (e.g., bit 3), and / or transmit an event notification interrupt communication to the CXL host 202 indicating that the memory module fatal error event record is available for the CXL host 202 to read.

[0063] As indicated by reference number 318, in response to receiving the second stage notification, the CXL host 202 can perform a memory device reset procedure, such as a PCIe hot reset procedure. Additionally or alternatively, as indicated by reference number 320, based on the CXL host performing the PCIe hot reset procedure and / or similar memory device reset procedure, the CXL device 204 can perform a second stage error recovery procedure. For example, in some implementations, the CXL device 204 can reset internal device data path hardware blocks. Additionally or alternatively, the CXL device 204 can perform an internal device reset of any remaining device subsystems that were not previously reset, such as for the purpose of clearing all internal device error status codes and / or returning the device to normal functionality.

[0064] As described above in connection with reference number 312, in some implementations, the CXL device 204 can save diagnostic data (e.g., a panic dump) to non-volatile device memory. In some memory devices, a panic dump is typically stored in page-addressable non-volatile memory, such as NAND flash memory or similar memory. In such examples, the page-addressable non-volatile memory can be part of the memory that requires endurance management (e.g., techniques and strategies used to extend the lifetime and reliability of non-volatile memory, such as employing wear leveling and / or implementing ECC algorithms, among other endurance management techniques). In some examples, endurance management can be provided by the FTL associated with the page-addressable non-volatile memory. Thus, in order to store a panic dump in non-volatile memory, recovery of the FTL firmware can be necessary. This can include rebooting the CPU of the memory device. However, rebooting the CPU can require starting the firmware to be executed in hardware, which first causes a firmware panic, resulting in an unreliable panic dump save, as the firmware can fail when the firmware attempts to initialize the hardware in the panic state.

[0065] Thus, in some implementations, the CXL device 204 can save diagnostic data (e.g., a panic dump) to byte-addressable non-volatile memory. Using byte-addressable non-volatile memory as a storage location for a panic dump can eliminate the need to repair the FTL after a firmware panic has started. Thus, by eliminating the need to repair the FTL, the CXL device 204 can not need to reboot the embedded CPU before saving diagnostic data, reducing the complexity of the panic dump sequence. Thus, saving diagnostic data to byte-addressable non-volatile memory can result in a more reliable firmware recovery process, and thus increase memory device reliability and efficiency.

[0066] Figure 3B An example 322 of a sequence associated with saving diagnostic data to a byte- addressable non-volatile memory storage component of the CXL device 204 is shown. Again, although described below in the context of the CXL device 204 for ease of description, in some other implementations, substantially similar operations can be performed by different devices (e.g., the memory system 110 and / or components thereof) without departing from the scope of the present disclosure. Figure 3A The operations described below are described in the context of the CXL device 204 for ease of description, although in some other implementations, substantially similar operations can be performed by different devices (e.g., the memory system 110 and / or components thereof) without departing from the scope of the present disclosure.

[0067] As shown in example 322, operations associated with a firmware emergency sequence and / or diagnostic data (e.g., emergency dump) save operations can be associated with both firmware 324 of CXL device 204 and hardware 326 of CXL device 204. First, as indicated by reference number 328, certain operations can be associated with a main firmware process of CXL device 204. More specifically, as indicated by reference number 330, hardware 326 of CXL device 204 can encounter an internal error (e.g., an internal error that requires an internal reset of at least one component of CXL device 204), such as the internal error described above in connection with Figure 3A reference number 302 of example 302. Thus, as indicated by reference number 332, firmware 324 can detect the internal error and / or determine to execute a firmware emergency sequence, which can be substantially similar to one or more of the operations described above in connection with Figure 3A reference numbers 304-308 of example 302. In response, as indicated by reference number 334, firmware 324 can collect diagnostic data associated with the internal error, which can be substantially similar to the operation described above in connection with reference number 310 of example 302. Figure 3C

[0068] As indicated by reference number 336, firmware 324 can reset a quad serial peripheral interface (QSPI) component (sometimes referred to as a QSPI block) of hardware 326. The QSPI component can be a serial interface used by an embedded system (e.g., a controller, such as main management subsystem 214) of CXL device 204 to communicate with a peripheral system (e.g., a non-volatile memory (e.g., a byte-addressable non-volatile memory)) of CXL device 204. In some embodiments, the QSPI can be used by a controller of CXL device 204 to communicate with a serial NOR memory that allows individual bytes to be read and written independently (e.g., a byte-addressable non-volatile memory can be a NOR memory). In some embodiments, the QSPI component can be configured to read data from a byte-addressable non-volatile memory, write data to a byte-addressable non-volatile memory, perform byte address to appropriate memory command translations associated with a byte-addressable non-volatile memory used by CXL host 202 and / or a controller of CXL device 204, and / or implement error detection mechanisms (e.g., ECC mechanisms) associated with a byte-addressable non-volatile memory, among other examples. Thus, by resetting the QSPI block, CXL device 204 can access the non-volatile memory without needing to reboot an embedded CPU, etc., thereby simplifying the emergency dump save procedure, thus improving the reliability of diagnostic procedures associated with CXL device 204.

[0069] ​More specifically, as indicated by reference number 338, after the QSPI component is reset, the firmware 324 can save diagnostic data (e.g., a panic dump) to a byte-addressable non-volatile storage component. Further, as indicated by reference number 340, after saving the diagnostic data, the hardware 326 can restart certain components and / or the system, such as by restarting a CPU subsystem associated with the hardware 326.

[0070] In this manner, the CXL device 204 can save diagnostic data prior to executing a ROM and / or boot loader associated with an internal reset procedure, and / or prior to reinitializing a host firmware associated with the internal reset procedure. For example, as indicated by reference number 342, the CXL device 204 can execute a ROM and / or boot loader execution. Further, as indicated by reference number 344, the CXL device 204 can reinitialize the host firmware and resume normal firmware progress. More specifically, as indicated by reference number 346, the firmware 324 can initialize the host firmware associated with the CXL device 204. In instances where the panic dump is saved to a page-addressable non-volatile memory, the memory device can reinitialize the FTL in connection with the operations described with respect to reference number 346. In such instances, the panic dump can not be saved to the non-volatile memory until after the operations shown in connection with reference number 346 have been completed, resulting in an unreliable diagnostic procedure. In contrast, because in this implementation the diagnostic data is saved to a byte-addressable non-volatile storage device, the panic dump has already been saved, as described above in connection with reference number 338, resulting in an improved diagnostic procedure and thus improved memory device operation.

[0071] As indicated by reference number 348, the firmware 324 can execute any additional recovery sequences in order to return the CXL device 204 to normal operating order. Thus, once the additional recovery sequences, if any, have been executed, the firmware 324 can return to normal processing, as indicated by reference number 350.

[0072] As described above in connection with reference number 308, in some implementations, the CXL device 204 firmware 324 can select one or more reset levels to be used to correct for internal device errors (e.g., one or more of a first reset level associated with resetting non-host interface components of the CXL device 204, a second reset level associated with resetting host interface components of the CXL device 204, and / or the like). Figure 3C The example 352 shown in FIG. 3B illustrates one implementation in which the CXL device 204 firmware 324 can select one or more reset levels to be used to correct for internal device errors. In connection with the example 352, the CXL device 204 firmware 324 can select one or more reset levels to be used to correct for internal device errors, as indicated by reference number 354. For example, the CXL device 204 firmware 324 can select a first reset level associated with resetting non-host interface components of the CXL device 204, a second reset level associated with resetting host interface components of the CXL device 204, and / or the like. Figure 3B The operations shown can include some of the steps described above in connection with Figure 3C the example 352, the CXL device 204 firmware 324 can select one or more reset levels to be used to correct for internal device errors, as indicated by reference number 354. For example, the CXL device 204 firmware 324 can select a first reset level associated with resetting non-host interface components of the CXL device 204, a second reset level associated with resetting host interface components of the CXL device 204, and / or the like.Figure 3B Like numbered elements are similar throughout the figures, so that to the extent possible, like elements have been given like reference numerals, and thus will not be described in detail unless necessary.

[0073] In some instances, the CXL device 204 can be coherent with the CXL host 202, and thus can be handled by the CXL host 202 like any other processor package. Accordingly, in some instances, the CXL host 202 can desire that, prior to a managed hot removal of the CXL device 204 and / or prior to an abrupt removal of the CXL device 204, the CXL device 204 will transmit a notification to the fabric manager so that the removal of the CXL device 204 can be safely handled without causing the CXL host 202 to enter into emergency mode and / or crash. Alternatively, in some instances, a fabric manager can not be implemented to manage the CXL device 204. For example, the CXL device 204 can be associated with an SLD or dual port device that does not require a fabric manager, and thus a fabric manager can not be implemented. In such cases, it can be desirable to avoid an abrupt removal of the CXL device 204 so that the CXL host 202 does not enter into emergency mode and / or crash.

[0074] Accordingly, in some cases, the internal resets implemented by the CXL device 204 can be associated with one or more reset levels of a plurality of potential reset levels, such as for the purpose of avoiding abrupt removal conditions for certain internal reset procedures. For example, a first reset level can be associated with resetting the non-host interface components of the CXL device 204 (e.g., the first reset level can reset all ASIC blocks and / or the master management subsystem 214 except for the HIF management subsystem 216 and / or the host interface management block), and / or a second reset level can be associated with resetting the host interface components of the CXL device 204 (e.g., the second reset level can reset only the HIF management subsystem 216 and / or the host interface management block). In such instances, the firmware 324 logic can select and / or apply different levels of internal resets based on the type of internal error encountered and / or the particular architecture employed. For example, if the detected fault that caused the firmware emergency is not related to the host interface components, the CXL device 204 can use only the first level of reset. Additionally or alternatively, if the detected fault that caused the firmware emergency is due to the host interface components, and if a fabric manager is available (meaning that an unexpected link disruption (e.g., a link termination without first providing a notification to the CXL host 202) caused by an internal reset can be safely managed by the CXL host 202 and more particularly by the fabric manager associated with the CXL host 202), the CXL device 204 can use both the first level of reset and the second level of reset for emergency recovery. Additionally or alternatively, if the detected fault that caused the firmware emergency is due to the host interface components and if a fabric manager is not available, the CXL device 204 can use the first level of reset and thus wait for the CXL host 202 to take the next action, thereby avoiding an abrupt removal condition.

[0075] More specifically, as indicated by reference number 354, after the firmware 324 has saved the diagnostic data to non-volatile memory (e.g., a byte-addressable non-volatile storage component, as described above in connection with reference number 338), the firmware 324 can apply logic to determine a type of reset required for the CXL device 204. For example, the firmware 324 can determine a type of internal reset to perform, and / or can select one or more reset levels of a plurality of potential reset levels to use for the internal reset based on the determined type of internal reset to perform.

[0076] For example, as described above, a first reset level of the plurality of potential reset levels can be associated with resetting non-host interface components of the CXL device 204, and / or a second reset level of the plurality of potential reset levels can be associated with resetting host interface components of the CXL device 204. In such implementations, the logic described above in connection with reference number 354 can include determining whether the internal error is associated with a host interface component and / or determining whether the CXL device 204 and / or the CXL host 202 is associated with a CXL fabric manager. If the internal error is not associated with a host interface component, the firmware 324 can select only the first reset level, thereby reducing resource consumption associated with the internal reset procedure and / or avoiding unnecessary host errors associated with the internal reset procedure. If the internal error is associated with a host interface component and if the CXL device 204 is not associated with a CXL fabric manager, the firmware 324 can select only the first reset level, and then the CXL device 204 can wait for the CXL host 202 to take some additional action to avoid a sudden removal event. Alternatively, if the internal error is associated with a host interface component, but the CXL device 204 and / or the CXL host 202 is associated with a CXL fabric manager, the firmware 324 can select the first reset level and the second reset level, as in such cases, a host interface component reset can be safely managed by the fabric manager.

[0077] Accordingly, as indicated by reference number 356, the firmware 324 can perform an internal reset of one or more internal memory device subsystems based on the selected reset level(s). Then, operations can proceed in a similar manner as described above in connection with Figure 3B In some implementations, due to the selected internal reset level to be implemented in the firmware emergency sequence, the operations described above in connection with Figure 3Ccertain operations described. For example, as described above in connection with reference number 348, firmware 324 can perform an additional recovery sequence after initialization of the ROM and / or boot loader execution and main firmware. In some implementations, the additional recovery sequence can be associated with resetting the host interface components of CXL device 204. In such implementations, the operations described above in connection with reference number 348 (shown in Figures 3A to 3C by using dashed lines) can be avoided, for example, when the host interface components are not reset. For example, in implementations where firmware 324 determines to perform only a first level reset (e.g., resetting all ASIC blocks except the HIF management subsystem 216 and / or host interface management block and / or main management subsystem 214), the additional recovery sequence shown in connection with reference number 348 can be avoided entirely, reducing resource consumption associated with the firmware emergency sequence.

[0078] As indicated above, the provision Figures 3A to 3C is by way of example. Other examples can differ from that described with respect to Figure 4 the described examples.

[0079] Figure 4 is a flow diagram of an example method 400 associated with an internal error correction sequence for a memory device. In some implementations, a memory device and / or memory system (e.g., memory system 110, memory device 120, and / or CXL device 204) can perform or can be configured to perform method 400. In some implementations, another device or set of devices separate from the memory device and / or memory system (e.g., system 100 and / or system 200) or including the memory device and / or memory system can perform or can be configured to perform method 400. Additionally or alternatively, one or more components of the memory device and / or memory system (e.g., memory system controller 115, local controller 125, I / O path hardware logic and DMA controller 212, main management subsystem 214, and / or HIF management subsystem 216) can perform or can be configured to perform method 400. Thus, a device for performing method 400 can include a memory device and / or memory system, and / or one or more components of the memory device and / or memory system. Additionally or alternatively, a non-transitory computer- readable medium can store one or more instructions that, when executed by a memory device and / or memory system, cause the memory device and / or memory system to perform method 400.

[0080] As Figure 4As shown in FIG. 4, the method 400 can include determining that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device (block 410). For example, the CXL device 204 (e.g., the firmware 324 of the CXL device 204) can determine that the CXL device 204 has encountered an internal error requiring an internal reset (e.g., a hardware error described above in connection with reference number 330), as described above in connection with reference numbers 302 and 332. As Figure 4 As further shown in FIG. 4, the method 400 can include transmitting, to the host device, a first-stage notification indicating that the memory device has encountered the internal error (block 420). For example, the CXL device 204 can transmit the first-stage notification described above in connection with reference number 306 to the CXL host 202.

[0081] As Figure 4 As further shown in FIG. 4, the method 400 can include saving diagnostic data associated with the internal error to a non-volatile storage component of the memory device (block 430). For example, the CXL device 204 can save the panic dump to non-volatile memory, as described above in connection with reference numbers 312 and 338. As Figure 4 As further shown in FIG. 4, the method 400 can include performing a first-stage reset of a first set of internal memory device subsystems (block 440). For example, the CXL device 204 can perform the first-stage reset described above in connection with reference number 314 and / or can cause the hardware 326 CPU subsystem to reboot, as described above in connection with reference number 340. As Figure 3B As further shown in FIG. 4, the method 400 can include transmitting, to the host device after the first-stage notification and based on performing the first-stage reset, a second-stage notification indicating that the host device is to perform a memory device reset procedure (block 450). For example, the CXL device 204 can transmit the second-stage notification described above in connection with reference number 316 to the CXL host 202.

[0082] The method 400 can include additional aspects, such as any single aspect or any combination of aspects described below and / or in connection with one or more other methods described elsewhere herein.

[0083] In a first aspect, the method 400 can include setting a virus status bit in a DVSEC CXL status register, and transmitting the first-stage notification can include transmitting the first-stage notification in response to setting the virus status bit in the DVSEC CXL status register. For example, the CXL device 204 can set the virus status bit in the DVSEC CXL status register, as described above in connection with reference number 306.

[0084] In a second aspect, alone or in combination with the first aspect, transmitting the first-stage notification can include forcing a cyclic redundancy check error on a first flit transmitted by the memory device to the host device, and setting a virus bit in a second flit transmitted by the memory device to the host device. For example, the CXL device 204 can force a CRC error on the next outgoing flit in response to initiating the firmware emergency sequence, and the CXL device 204 can set a virus bit in the RETRY.ack flit, as described above in connection with reference number 306.

[0085] In a third aspect, alone or in combination with one or more of the first and second aspects, the second-stage notification indicates that the host device is to perform a memory device reset procedure using a required reset field of a memory device status register. For example, the CXL device 204 can indicate to the CXL host 202 that the CXL host 202 is to perform a memory device reset procedure using a required reset field of a memory device status register, as described above in connection with reference number 316.

[0086] In a fourth aspect, alone or in combination with one or more of the first through third aspects, transmitting the second-stage notification includes creating a memory module fatal error event record, setting a bit in an event status register corresponding to the memory module fatal error event record, and transmitting an event notification interrupt communication to the host device indicating that the memory module fatal error event record is available. For example, the CXL device 204 can create a memory module fatal error event record, can set a bit in an event status register corresponding to the memory module fatal error event record, and / or can transmit an event notification interrupt communication to the CXL host 202 indicating that the memory module fatal error event record is available, as described above in connection with reference number 306.

[0087] In a fifth aspect, alone or in combination with one or more of the first through fourth aspects, the method 400 includes performing a reset of a host interface with the host device, and performing a second-stage reset of a second set of internal memory device subsystems based on the resetting the host interface. For example, the CXL device 204 can perform the PCIe hot reset procedure described above in connection with reference number 318 with the CXL host 202, and / or the CXL device can perform the second-stage error recovery procedure described above in connection with reference numbers 320 and 348.

[0088] In a sixth aspect, alone or in combination with one or more of the first through fifth aspects, the non-volatile storage component is a byte-addressable non-volatile storage component. For example, the CXL device 204 can save the diagnostic data to a byte-addressable non-volatile memory (e.g., a NOR memory), as described above in connection with Figure 4 example 322.

[0089] In a seventh aspect, alone or in combination with one or more of the first through sixth aspects, the method 400 includes resetting a QSPI component associated with the memory device and saving diagnostic data to a byte-addressable non-volatile storage component based on resetting the QSPI component. For example, the CXL device 204 can reset the QSPI block, as described above in connection with reference number 336, and / or the CXL device 204 can save the emergency dump to a byte-addressable non-volatile (e.g., NOR memory) after resetting the QSPI block, as described above in connection with reference number 338.

[0090] In an eighth aspect, alone or in combination with one or more of the first through seventh aspects, the method 400 includes determining a type of internal reset to be performed and selecting one or more reset levels of a plurality of potential reset levels to be used for the internal reset based on determining the type of internal reset to be performed. For example, as described above in connection with reference number 354, the CXL device 204 can apply logic to determine whether to perform a first reset level (e.g., a reset level associated with resetting non-host interface components of the CXL device 204) and / or a second reset level (e.g., a reset level associated with resetting host interface components of the CXL device 204), such as by determining whether the internal error is associated with a host interface.

[0091] In a ninth aspect, alone or in combination with one or more of the first through eighth aspects, a first reset level of the plurality of potential reset levels is associated with resetting non-host interface components of the memory device and a second reset level of the plurality of potential reset levels is associated with resetting host interface components of the memory device. For example, the CXL device 204 can apply the logic described above in connection with reference number 354.

[0092] In a tenth aspect, alone or in combination with one or more of the first to ninth aspects, method 400 includes: determining whether an internal error is associated with a host interface component; determining whether a memory device is associated with a structure manager; and performing one of the following: selecting only a first reset level based on determining that the internal error is not associated with a host interface component; selecting only a first reset level based on determining that the internal error is associated with a host interface component and that the memory device is not associated with a structure manager; or selecting both a first reset level and a second reset level based on determining that the internal error is associated with a host interface component and that the memory device is associated with a structure manager. For example, CXL device 204 may select the first reset level based on determining that the internal error is not associated with a host interface component, may select only the first reset level based on determining that the internal error is associated with a host interface component and that CXL device 204 and / or CXL host 202 are not associated with a CXL structure manager, or may select both a first reset level and a second reset level based on determining that the internal error is associated with a host interface component and that CXL device 204 and / or CXL host 202 are associated with a CXL structure manager.

[0093] although Figure 4 This shows an instance box of method 400, but in some implementations, method 400 may include, compared to Figure 5 The boxes depicted herein may be additional boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively, two or more boxes of method 400 may be performed in parallel. Method 400 is an example of a method that can be performed by one or more means described herein. These one or more means may be performed based on the operations described herein or may be configured to perform one or more other methods.

[0094] Figure 5is a flow diagram of another example method 500 associated with an internal error correction sequence for a memory device. In some implementations, a memory device and / or a memory system (e.g., the memory system 110, the memory device 120, and / or the CXL device 204) can perform the method 500 or can be configured to perform the method 500. In some implementations, another device or set of devices separate from the memory device and / or the memory system (e.g., the system 100 and / or the system 200) or including the memory device and / or the memory system can perform the method 500 or can be configured to perform the method 500. Additionally or alternatively, one or more components of the memory device and / or the memory system (e.g., the memory system controller 115, the local controller 125, the I / O path hardware logic and DMA controller 212, the host management sub-system 214, and / or the HIF management sub-system 216) can perform the method 500 or can be configured to perform the method 500. Thus, a device for performing the method 500 can include a memory device and / or a memory system, and / or one or more components of the memory device and / or the memory system. Additionally or alternatively, a non-transitory computer- readable medium can store one or more instructions that, when executed by a memory device and / or a memory system, cause the memory device and / or the memory system to perform the method 500.

[0095] As shown in Figure 5 the method 500 can include determining that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device (block 510). For example, the CXL device 204 (e.g., the firmware 324 of the CXL device 204) can determine that the CXL device 204 has encountered an internal error requiring an internal reset (e.g., a hardware error described above in connection with reference number 330), as described above in connection with reference numbers 302 and 332. As further shown in Figure 5 the method 500 can include transmitting a first stage notification indicating that the memory device has encountered an internal error (block 520). For example, the CXL device 204 can transmit the first stage notification described above in connection with reference number 306 to the CXL host 202.

[0096] As further shown in Figure 3B the method 500 can include saving diagnostic data associated with the internal error to a byte-addressable non-volatile storage component of the memory device (block 530). For example, the CXL device 204 can save the diagnostic data to a byte-addressable non-volatile memory (e.g., a NOR memory), as described above in connection with the example 322. As further shown in Figure 5 the method 500 can include transmitting a second stage notification indicating that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device (block 540). For example, the CXL device 204 can transmit the second stage notification described above in connection with reference number 308 to the CXL host 202. Figure 5Further to the foregoing, the method 500 can include performing a first-stage reset of the first set of internal memory device subsystems (block 540). For example, the CXL device 204 can perform the first-stage reset described above in connection with reference number 314 and / or can cause the hardware 326 CPU subsystem to restart, as described above in connection with reference number 340. As Figure 5 Further to the foregoing, the method 500 can include transmitting, by the memory device to the host device after the first-stage notification and based on performing the first-stage reset, a second-stage notification indicating that the host device is to perform a memory device reset procedure (block 550). For example, the CXL device 204 can transmit the second-stage notification described above in connection with reference number 316 to the CXL host 202.

[0097] The method 500 can include additional aspects, such as any single aspect or any combination of aspects described below and / or in connection with one or more other methods described elsewhere herein.

[0098] In a first aspect, the method 500 includes setting, by the memory device, a virus status bit in a DVSEC CXL status register, where transmitting the first-stage notification includes transmitting the first-stage notification in response to setting the virus status bit in the DVSEC CXL status register. For example, the CXL device 204 can set the virus status bit in the DVSEC CXL status register, as described above in connection with reference number 306.

[0099] In a second aspect, alone or in combination with the first aspect, transmitting the first-stage notification includes forcing a cyclic redundancy check error on a first flit transmitted by the memory device to the host device and setting a virus bit in a second flit transmitted by the memory device to the host device. For example, the CXL device 204 can force a CRC error on the next outgoing flit in response to initiating the firmware emergency sequence, and the CXL device 204 can set the virus bit in the RETRY.ack flit, as described above in connection with reference number 306.

[0100] In a third aspect, alone or in combination with one or more of the first through second aspects, the second-stage notification indicates that the host device is to perform the memory device reset procedure using a reset required field of a memory device status register. For example, the CXL device 204 can indicate to the CXL host 202 that the CXL host 202 is to perform the memory device reset procedure using the reset required field of the memory device status register, as described above in connection with reference number 316.

[0101] In a fourth aspect alone or in combination with one or more of the first through third aspects, transmitting the second stage notification includes creating, by the memory device, a memory module fatal error event record; setting, by the memory device, a bit in an event status register corresponding to the memory module fatal error event record; and transmitting, by the memory device to the host device, an event notification interrupt communication indicating that the memory module fatal error event record is available. For example, the CXL device 204 can create a memory module fatal error event record, can set a bit in an event status register corresponding to the memory module fatal error event record, and / or can transmit an event notification interrupt communication to the CXL host 202 indicating that the memory module fatal error event record is available, as described above in connection with reference number 306.

[0102] In a fifth aspect alone or in combination with one or more of the first through fourth aspects, the method 500 includes performing, by the memory device, a reset of a host interface with the host device, and performing, by the memory device, a second stage reset of a second set of internal memory device subsystems based on resetting the host interface. For example, the CXL device 204 can perform the PCIe hot reset procedure described above in connection with reference number 318 with the CXL host 202, and / or the CXL device can perform the second stage error recovery procedure described above in connection with reference numbers 320 and 348.

[0103] In a sixth aspect alone or in combination with one or more of the first through fifth aspects, the method 500 includes resetting, by the memory device, a QSPI component associated with the memory device, and saving, by the memory device to a byte-addressable non-volatile storage component, diagnostic data based on resetting the QSPI component. For example, the CXL device 204 can reset the QSPI block as described above in connection with reference number 336, and / or the CXL device 204 can save an emergency dump to a byte-addressable non-volatile (e.g., NOR memory) after resetting the QSPI block as described above in connection with reference number 338.

[0104] In a seventh aspect alone or in combination with one or more of the first through sixth aspects, the method 500 includes determining, by the memory device, a type of internal reset to be performed, and selecting, by the memory device, one or more reset levels of a plurality of potential reset levels to be used for the internal reset based on determining the type of internal reset to be performed. For example, as described above in connection with reference number 354, the CXL device 204 can apply logic to determine whether to perform a first reset level (e.g., a reset level associated with resetting non-host interface components of the CXL device 204) and / or a second reset level (e.g., a reset level associated with resetting host interface components of the CXL device 204), for example by determining whether the internal error is associated with the host interface.

[0105] In the eighth aspect, either alone or in combination with one or more of the first to seventh aspects, a first reset level of a plurality of potential reset levels is associated with a non-host interface component of the reset memory device, and a second reset level of a plurality of potential reset levels is associated with a host interface component of the reset memory device. For example, the CXL device 204 may apply the logic described above in conjunction with reference to reference numeral 354.

[0106] In a ninth aspect, alone or in combination with one or more of the first to eighth aspects, method 500 includes determining whether an internal error is associated with a host interface component; determining whether a memory device is associated with a structure manager; and performing one of the following by the memory device: selecting only a first reset level based on determining that the internal error is not associated with a host interface component; selecting only a first reset level based on determining that the internal error is associated with a host interface component and that the memory device is not associated with a structure manager; or selecting both a first reset level and a second reset level based on determining that the internal error is associated with a host interface component and that the memory device is associated with a structure manager. For example, CXL device 204 may select the first reset level based on determining that the internal error is not associated with a host interface component, may select only the first reset level based on determining that the internal error is associated with a host interface component and that CXL device 204 and / or CXL host 202 are not associated with a CXL structure manager, or may select both a first reset level and a second reset level based on determining that the internal error is associated with a host interface component and that CXL device 204 and / or CXL host 202 are associated with a CXL structure manager.

[0107] although Figure 5 The example box for method 500 is shown, but in some implementations, method 500 may include, compared to... Figure 6 The boxes depicted herein may be additional boxes, fewer boxes, different boxes, or boxes arranged differently. Alternatively, two or more boxes of method 500 may be performed in parallel. Method 500 is an example of a method that can be performed by one or more means described herein. These one or more means may be performed based on the operations described herein or may be configured to perform one or more other methods.

[0108] Figure 6is a flowchart of another example method 600 associated with an internal error correction sequence for a memory device. In some implementations, a memory device and / or a memory system (e.g., the memory system 110, the memory device 120, and / or the CXL device 204) can perform the method 600 or can be configured to perform the method 600. In some implementations, another device or set of devices separate from or including the memory device and / or the memory system (e.g., the system 100 and / or the system 200) can perform the method 600 or can be configured to perform the method 600. Additionally or alternatively, one or more components of the memory device and / or the memory system (e.g., the memory system controller 115, the local controller 125, the I / O path hardware logic and DMA controller 212, the host management sub-system 214, and / or the HIF management sub-system 216) can perform the method 600 or can be configured to perform the method 600. Thus, a device for performing the method 600 can include a memory device and / or a memory system, and / or one or more components of a memory device and / or a memory system. Additionally or alternatively, a non-transitory computer- readable medium can store one or more instructions that, when executed by a memory device and / or a memory system, cause the memory device and / or the memory system to perform the method 600.

[0109] As shown in Figure 6 the method 600 can include determining that the CXL memory module has encountered an internal error that requires an internal reset of at least one component of the CXL memory module (block 610). For example, the CXL device 204 (e.g., the firmware 324 of the CXL device 204) can determine that the CXL device 204 has encountered an internal error that requires an internal reset (e.g., a hardware error described above in connection with reference number 330), as described above in connection with reference numbers 302 and 332. As further shown in Figure 6 the method 600 can include transmitting a first stage notification to the host system indicating that the CXL memory module has encountered an internal error (block 620). For example, the CXL device 204 can transmit the first stage notification described above in connection with reference number 306 to the CXL host 202.

[0110] As further shown in Figure 6 the method 600 can include saving diagnostic data associated with the internal error to a non-volatile storage component of the CXL memory module (block 630). For example, the CXL device 204 can save the panic dump to non-volatile memory, as described above in connection with reference numbers 312 and 338. As further shown in Figure 6Further to the foregoing, the method 600 can include determining a type of internal reset to be performed (block 640). For example, the CXL device 204 can determine whether the internal reset is associated with resetting non-host interface components of the CXL device 204 and / or is associated with resetting host interface components of the CXL device 204, as described above in connection with reference number 354. As described above in connection with reference number 354, the CXL device 204 can apply logic to determine whether to perform a first reset level (e.g., a reset level associated with resetting non-host interface components of the CXL device 204) and / or a second reset level (e.g., a reset level associated with resetting host interface components of the CXL device 204). Figure 6 Further to the foregoing, the method 600 can include selecting one or more reset levels of a plurality of potential reset levels to use for the internal reset based on determining the type of internal reset to be performed (block 650). For example, as described above in connection with reference number 354, the CXL device 204 can apply logic to determine whether to perform a first reset level (e.g., a reset level associated with resetting non-host interface components of the CXL device 204) and / or a second reset level (e.g., a reset level associated with resetting host interface components of the CXL device 204). As described above in connection with reference number 354, the CXL device 204 can apply logic to determine whether to perform a first reset level (e.g., a reset level associated with resetting non-host interface components of the CXL device 204) and / or a second reset level (e.g., a reset level associated with resetting host interface components of the CXL device 204). Figure 3B Further to the foregoing, the method 600 can include performing a first stage reset of a first set of internal memory device subsystems based on the one or more reset levels (block 660). For example, the CXL device 204 can perform the first stage reset described above in connection with reference number 314 and / or can cause the hardware 326 CPU subsystem to restart, as described above in connection with reference number 340.

[0111] The method 600 can include additional aspects, such as any single aspect or any combination of aspects described below and / or in connection with one or more other methods described elsewhere herein.

[0112] In a first aspect, the method 600 can include setting a virus status bit in a DVSEC CXL status register, where transmitting the first stage notification includes transmitting the first stage notification in response to setting the virus status bit in the DVSEC CXL status register. For example, the CXL device 204 can set the virus status bit in the DVSEC CXL status register, as described above in connection with reference number 306.

[0113] In a second aspect, alone or in combination with the first aspect, transmitting the first stage notification can include forcing a cyclic redundancy check error on a first flit transmitted by the CXL memory module to the host system and setting a virus bit in a second flit transmitted by the CXL memory module to the host system. For example, the CXL device 204 can force a CRC error on the next outgoing flit in response to initiating the firmware emergency sequence, and the CXL device 204 can set the virus bit in the RETRY.ack flit, as described above in connection with reference number 306.

[0114] In a third aspect, alone or in combination with one or more of the first and second aspects, the method 600 can include transmitting, after the first stage notification and based on performing the first stage reset, a second stage notification to the host system indicating that the host system is to perform a memory module reset procedure. For example, the CXL device 204 can transmit the second stage notification described above in connection with reference number 316 to the CXL host 202.

[0115] In a fourth aspect, alone or in combination with one or more of the first through third aspects, the second stage notification indicates that the host system is to perform the memory module reset procedure using a required reset field of a CXL memory module status register. For example, the CXL device 204 can indicate to the CXL host 202 that the CXL host 202 is to perform the memory device reset procedure using the required reset field of the memory device status register, as described above in connection with reference number 316.

[0116] In a fifth aspect, alone or in combination with one or more of the first through fourth aspects, transmitting the second stage notification includes creating a memory module fatal error event record, setting a bit in an event status register corresponding to the memory module fatal error event record, and transmitting an event notification interrupt communication to the host system indicating that the memory module fatal error event record is available. For example, the CXL device 204 can create the memory module fatal error event record, can set the bit in the event status register corresponding to the memory module fatal error event record, and / or can transmit the event notification interrupt communication to the CXL host 202 indicating that the memory module fatal error event record is available, as described above in connection with reference number 306.

[0117] In a sixth aspect, alone or in combination with one or more of the first through fifth aspects, the method 600 includes performing a reset of a host interface with the host system, and performing a second stage reset of a second set of internal memory device subsystems based on resetting the host interface. For example, the CXL device 204 can perform the PCIe hot reset procedure described above in connection with reference number 318 with the CXL host 202, and / or the CXL device can perform the second stage error recovery procedure described above in connection with reference numbers 320 and 348.

[0118] In a seventh aspect, alone or in combination with one or more of the first through sixth aspects, the non-volatile storage component is a byte-addressable non-volatile storage component. For example, the CXL device 204 can save the diagnostic data to a byte-addressable non-volatile memory (e.g., a NOR memory), as described above in connection with example 322. Figure 6

[0119] ​In an eighth aspect, alone or in combination with one or more of the first to seventh aspects, method 600 includes resetting the QSPI component associated with the CXL memory module and saving diagnostic data to a byte-addressable non-volatile memory component based on the reset of the QSPI component. For example, CXL device 204 may reset the QSPI block as described above in conjunction with reference numeral 336, and / or CXL device 204 may save an emergency dump to a byte-addressable non-volatile (e.g., NOR memory) memory after resetting the QSPI block, as described above in conjunction with reference numeral 338.

[0120] In the ninth aspect, either alone or in combination with one or more of the first to eighth aspects, a first reset level of a plurality of potential reset levels is associated with resetting the non-host interface component of the CXL memory module, and a second reset level of a plurality of potential reset levels is associated with resetting the host interface component of the CXL memory module. For example, the CXL device 204 may apply the logic described above in conjunction with reference to reference numeral 354.

[0121] In a tenth aspect, alone or in combination with one or more of the first to ninth aspects, method 600 includes: determining whether an internal error is associated with a host interface component; determining whether a CXL memory module is associated with a CXL structure manager; and performing one of the following: selecting only a first reset level based on determining that the internal error is not associated with a host interface component; selecting only a first reset level based on determining that the internal error is associated with a host interface component and the CXL memory module is not associated with a CXL structure manager; or selecting both a first reset level and a second reset level based on determining that the internal error is associated with a host interface component and the CXL memory module is associated with a CXL structure manager. For example, CXL device 204 may select the first reset level based on determining that the internal error is not associated with a host interface component, may select only the first reset level based on determining that the internal error is associated with a host interface component and CXL device 204 and / or CXL host 202 is not associated with a CXL structure manager, or may select both a first reset level and a second reset level based on determining that the internal error is associated with a host interface component and CXL device 204 and / or CXL host 202 is associated with a CXL structure manager.

[0122] although Figure 6 An instance box of method 600 is shown, but in some implementations, method 600 may include, compared to ​The additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted. Additionally or alternatively, two or more blocks of the method 600 can be performed in parallel. The method 600 is an example of one method that can be performed by one or more devices described herein. These one or more devices can perform or can be configured to perform one or more other methods based on the operations described herein.

[0123] In some implementations, a memory device includes one or more components configured to: determine that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; transmit, to a host device, a first stage notification indicating that the memory device has encountered the internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the memory device; perform a first stage reset of a first set of internal memory device subsystems; and transmit, to the host device and after the first stage notification and based on performing the first stage reset, a second stage notification indicating that the host device is to perform a memory device reset procedure.

[0124] In some implementations, a method includes: determining, by a memory device, that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; transmitting, by the memory device, to a host device, a first stage notification indicating that the memory device has encountered the internal error; saving, by the memory device, diagnostic data associated with the internal error to a byte-addressable non-volatile storage component of the memory device; performing a first stage reset of a first set of internal memory device subsystems; and transmitting, by the memory device, to the host device and after the first stage notification and based on performing the first stage reset, a second stage notification indicating that the host device is to perform a memory device reset procedure.

[0125] In some implementations, a compute express link (CXL) memory module includes one or more components configured to: determine that the CXL memory module has encountered an internal error requiring an internal reset of at least one component of the CXL memory module; transmit, to a host system, a first stage notification indicating that the CXL memory module has encountered the internal error; save diagnostic data associated with the internal error to a non-volatile storage component of the CXL memory module; determine a type of internal reset to be performed; select, based on determining the type of internal reset to be performed, one or more reset levels of a plurality of potential reset levels to be used for the internal reset; and perform a first stage reset of a first set of internal memory device subsystems based on the one or more reset levels.

[0126] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations can be made in light of the above disclosure or can be acquired from practice of the embodiments described herein. Other embodiments can provide from practice of the embodiments described herein. Other embodiments can provide from practice of the embodiments described herein.

[0127] As used herein the terms “substantially” and “approximately” mean “within reasonable tolerances for manufacture and measurement.”

[0128] While specific combinations of features are set forth in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of embodiments described herein. Many of these features can be combined in ways not specifically set forth in the claims and / or disclosed in the specification. For example, the disclosure includes every individual claim in combination with every other individual claim in the set of claims, as well as every combination of multiple claims in the set of claims. As used herein, a phrase referring to “at least one of’ a list of items means any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination of multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

[0129] When a “component” or “one or more components” (or another element, such as “controller” or “one or more controllers”) is described or claimed to perform a particular operation or is configured to perform a particular operation, this language is intended to encompass a single component performing the operation, a plurality of components performing the operation collectively, a single component performing the operation and another component performing the operation, or any combination of components performing the operation, unless otherwise specifically noted within the claims. For example, when a claim has the form “one or more components configured to: perform X; perform Y; and perform Z,” the claim should be interpreted as meaning “one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly also different) components configured to perform Z.”

[0130] No element, act or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items and can be used interchangeably with “one or more.” Furthermore, as used herein, the article “the” is intended to include one or more items referenced and can be used interchangeably with “the one or more.” Where the phrase “only one” or “single” or similar language is used, the phrase is intended to refer to a singular object unless specifically stated otherwise. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms that do not limit the object specified, e.g., an element “having” A can also have B. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. As used herein, the term “plurality” can be replaced with “a plurality of” and vice versa. Also, as used herein, the term “or” is intended to be inclusive, e.g., “A or B” is intended to mean “A or B or both” unless specifically stated otherwise.

Claims

1. A memory device comprising: One or more components, configured to: It is determined that the memory device has encountered an internal error requiring an internal reset of at least one component of the memory device; Transmit a first-stage notification to the host device indicating that the memory device has encountered the internal error; Diagnostic data associated with the internal error is saved to the non-volatile storage component of the memory device; Perform the first-stage reset of the first group of internal memory device subsystems; and Following the first phase notification and based on the execution of the first phase reset, a second phase notification instructing the host device to execute a memory device reset procedure is transmitted to the host device.

2. The memory device of claim 1, wherein the one or more components are further configured to set a virus status bit in a specified vendor-specific scalability DVSEC compute high-speed link CXL status register. The one or more components used to transmit the first phase notification are configured to transmit the first phase notification in response to setting the virus status bit in the DVSECCXL status register.

3. The memory device of claim 1, wherein the one or more components for transmitting the first phase notification are configured to: Forced cyclic redundancy check error on the first chip transferred from the memory device to the host device, and A virus bit is set in a second chip that is transferred from the memory device to the host device.

4. The memory device of claim 1, wherein the second-stage notification instructs the host device to execute the memory device reset procedure using a reset-required field of the memory device status register.

5. The memory device of claim 1, wherein the one or more components for transmitting the second phase notification are configured to: Create a fatal error event log for the memory module; Set the bit corresponding to the fatal error event record of the memory module in the event status register; and The host device transmits an event notification interruption communication indicating that the memory module's fatal error event log is available.

6. The memory device of claim 1, wherein the one or more components are further configured to: The host device is used to perform a host interface reset; and The second-stage reset of the second set of internal memory device subsystems is performed by resetting the host interface.

7. The memory device of claim 1, wherein the non-volatile memory component is a byte-addressable non-volatile memory component.

8. The memory device of claim 7, wherein the one or more components are further configured to: Reset the four-serial peripheral interface (QSPI) component associated with the memory device; and The diagnostic data is saved to the byte-addressable non-volatile memory component based on the reset of the QSPI component.

9. The memory device of claim 1, wherein the one or more components are further configured to: Determine the type of the internal reset to be performed; and One or more reset levels will be selected from a plurality of potential reset levels to be used for the internal reset based on the type of the internal reset to be performed.

10. The memory device of claim 9, wherein the first reset level of the plurality of potential reset levels is associated with resetting a non-host interface component of the memory device, and The second of the plurality of potential reset levels is associated with the host interface component that resets the memory device.

11. The memory device of claim 10, wherein the one or more components are further configured to: Determine whether the internal error is associated with the host interface component; Determine whether the memory device is associated with the structure manager; and Perform one of the following: The first reset level is selected only based on the determination that the internal error is not associated with the host interface component; The first reset level is selected only based on the determination that the internal error is associated with the host interface component and that the memory device is not associated with the structure manager; or The first reset level and the second reset level are selected based on the determination that the internal error is associated with the host interface component and that the memory device is associated with the structure manager.

12. A method comprising: The memory device determines that it has encountered an internal error requiring an internal reset of at least one component of the memory device. The memory device transmits a first-stage notification to the host device indicating that the memory device has encountered the internal error; The memory device saves diagnostic data associated with the internal error to the byte-addressable non-volatile memory component of the memory device; Perform the first-stage reset of the first group of internal memory device subsystems; and Following the first phase notification and based on the execution of the first phase reset, the memory device transmits a second phase notification to the host device instructing the host device to execute a memory device reset procedure.

13. The method of claim 12, further comprising setting a virus status bit in a high-speed link CXL status register calculated by the memory device in a specified vendor-specific scalability DVSEC. The transmission of the first phase notification includes transmitting the first phase notification in response to setting the virus status bit in the DVSEC CXL status register.

14. The method of claim 12, wherein transmitting the first phase notification comprises: The memory device forces a cyclic redundancy check error on the first chip transferred from the memory device to the host device, and The virus bit is set by the memory device in a second chip that is transferred from the memory device to the host device.

15. The method of claim 12, wherein the second-stage notification instructs the host device to perform the memory device reset procedure using a reset-required field of the memory device status register.

16. The method of claim 12, further comprising: The memory device resets the four serial peripheral interface (QSPI) components associated with the memory device. and The memory device saves the diagnostic data to the byte-addressable non-volatile memory component based on resetting the QSPI component.

17. A high-speed computing link CXL memory module, comprising: One or more components, configured to: It has been determined that the CXL memory module has encountered an internal error requiring an internal reset of at least one component of the CXL memory module; Transmit a first-stage notification to the host system indicating that the CXL memory module has encountered the internal error; Diagnostic data associated with the internal error is saved to the non-volatile storage component of the CXL memory module; Determine the type of the internal reset to be performed; Based on the type of the internal reset to be performed, one or more reset levels from a plurality of potential reset levels are selected to be used for the internal reset; and The first-stage reset of the first group of internal memory device subsystems is performed based on one or more reset levels.

18. The CXL memory module of claim 17, wherein the first of the plurality of potential reset levels is associated with resetting a non-host interface component of the CXL memory module, and The second of the plurality of potential reset levels is associated with resetting the host interface component of the CXL memory module.

19. The CXL memory module of claim 18, wherein one or more components are further configured to: determine whether the internal error is associated with the host interface component; Determine whether the CXL memory module is associated with the CXL structure manager; and Perform one of the following: The first reset level is selected only based on the determination that the internal error is not associated with the host interface component; The first reset level is selected only based on the determination that the internal error is associated with the host interface component and that the CXL memory module is not associated with the CXL structure manager; or The first reset level and the second reset level are selected based on the determination that the internal error is associated with the host interface component and that the CXL memory module is associated with the CXL structure manager.

20. The CXL memory module of claim 17, wherein the one or more components are further configured to transmit a second-stage notification to the host system, instructing the host system to execute a memory module reset procedure, after the first-stage notification and based on the execution of the first-stage reset.

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