Clock frequency division dynamic adjustment method and device, computer equipment and storage medium

Abstract

The invention relates to a clock frequency division dynamic adjustment method and device, computer equipment and a storage medium. The method comprises the following steps: determining a first frequency division channel and a second frequency division channel according to configuration information of clock frequency division; the first frequency division channel is a frequency division channel in a working state, and the second frequency division channel is a standby frequency division channel; under the condition that the processing requirement of clock frequency division is changed, the frequency division coefficient of the second frequency division channel is adjusted to be a target frequency division coefficient, and the second frequency division channel is controlled to carry out clock frequency division processing according to the target frequency division coefficient; generating a switching control signal under the condition that the second frequency division channel meets the preset condition; the switching control signal is used for switching the second frequency division channel into a frequency division channel in a working state. By adopting the method, the output frequency division clock can be switched without interruption, the continuity of clock output is ensured, and the continuous and stable operation of a digital integrated circuit is further ensured.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit technology, and in particular to a method, apparatus, computer device, and storage medium for dynamic adjustment of clock frequency division. Background Technology

[0002] In the field of digital integrated circuit design, clock signals are a core resource for ensuring the synchronous operation of digital logic. Because different functional modules within a chip have different clock frequency requirements, the input master clock typically needs to be divided to obtain an output clock suitable for each module, thereby meeting the clock frequency requirements of different application scenarios.

[0003] In traditional technology, programmable frequency dividers often need to stop the current clock when modifying the division coefficient, causing the clock output of digital integrated circuits to be interrupted, which affects the continuous and stable operation of digital integrated circuits. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer equipment, and storage medium for dynamic clock frequency adjustment that can switch the output frequency divider clock without interruption, ensure the continuity of clock output, and thus ensure the continuous and stable operation of digital integrated circuit systems, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for dynamic adjustment of clock frequency division, including:

[0006] Based on the clock division configuration information, the first and second division channels are determined; the first division channel is the working division channel, and the second division channel is the spare division channel.

[0007] When the clock frequency division processing requirements change, adjust the frequency division coefficient of the second frequency division channel to the target frequency division coefficient, and control the second frequency division channel to perform clock frequency division processing according to the target frequency division coefficient;

[0008] When the second frequency division channel meets the preset conditions, a switching control signal is generated; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to the frequency division channel in the working state.

[0009] In one embodiment, adjusting the division factor of the second frequency division channel to the target division factor includes:

[0010] Determine the target register value corresponding to the target frequency division coefficient;

[0011] Adjust the value of the division coefficient register of the second division channel to the target register value.

[0012] In one embodiment, the target division factor is determined based on the changed clock division processing requirements.

[0013] In one embodiment, the second frequency divider channel meets preset conditions including the second frequency divider channel performing clock frequency division for a target number of cycles; the target number is determined based on the target frequency division coefficient.

[0014] In one embodiment, determining the first frequency division channel and the second frequency division channel based on clock frequency division configuration information includes:

[0015] When the configuration information is the first value, the frequency division channel corresponding to the first value is determined as the first frequency division channel, and the frequency division channel corresponding to the second value is determined as the second frequency division channel;

[0016] When the configuration information is the second value, the frequency division channel corresponding to the second value is determined as the first frequency division channel, and the frequency division channel corresponding to the first value is determined as the second frequency division channel.

[0017] In one embodiment, the method further includes:

[0018] Configuration information is obtained by configuring the bus.

[0019] Secondly, this application also provides a clock frequency division dynamic adjustment device, comprising:

[0020] The determination module is used to determine the first frequency division channel and the second frequency division channel based on the clock frequency division configuration information; the first frequency division channel is the frequency division channel in the working state, and the second frequency division channel is the spare frequency division channel;

[0021] The frequency divider module is used to adjust the frequency division coefficient of the second frequency divider channel to the target frequency division coefficient when the clock frequency division processing requirements change, and to control the second frequency divider channel to perform clock frequency division processing according to the target frequency division coefficient.

[0022] The adjustment module is used to generate a switching control signal when the second frequency division channel meets the preset conditions; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to the frequency division channel in the working state.

[0023] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0024] Based on the clock division configuration information, the first and second division channels are determined; the first division channel is the working division channel, and the second division channel is the spare division channel.

[0025] When the clock frequency division processing requirements change, adjust the frequency division coefficient of the second frequency division channel to the target frequency division coefficient, and control the second frequency division channel to perform clock frequency division processing according to the target frequency division coefficient;

[0026] When the second frequency division channel meets the preset conditions, a switching control signal is generated; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to the frequency division channel in the working state.

[0027] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0028] Based on the clock division configuration information, the first and second division channels are determined; the first division channel is the working division channel, and the second division channel is the spare division channel.

[0029] When the clock frequency division processing requirements change, adjust the frequency division coefficient of the second frequency division channel to the target frequency division coefficient, and control the second frequency division channel to perform clock frequency division processing according to the target frequency division coefficient;

[0030] When the second frequency division channel meets the preset conditions, a switching control signal is generated; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to the frequency division channel in the working state.

[0031] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0032] Based on the clock division configuration information, the first and second division channels are determined; the first division channel is the working division channel, and the second division channel is the spare division channel.

[0033] When the clock frequency division processing requirements change, adjust the frequency division coefficient of the second frequency division channel to the target frequency division coefficient, and control the second frequency division channel to perform clock frequency division processing according to the target frequency division coefficient;

[0034] When the second frequency division channel meets the preset conditions, a switching control signal is generated; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to the frequency division channel in the working state.

[0035] The aforementioned clock frequency division dynamic adjustment method, device, computer equipment, and storage medium determine a first frequency division channel and a second frequency division channel based on the clock frequency division configuration information. The first frequency division channel is the active frequency division channel, and the second frequency division channel is a backup frequency division channel. When the clock frequency division processing requirements change, the frequency division coefficient of the second frequency division channel is adjusted to the target frequency division coefficient, and the second frequency division channel is controlled to perform clock frequency division processing according to the target frequency division coefficient. When the second frequency division channel meets preset conditions, a switching control signal is generated. The switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to the active frequency division channel. This method can switch the output frequency division clock without interruption, ensuring the continuity of clock output, and thus ensuring the continuous and stable operation of the digital integrated circuit system. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is an application environment diagram of the clock frequency division dynamic adjustment method in one embodiment;

[0038] Figure 2 This is a flowchart illustrating a clock frequency division dynamic adjustment method in one embodiment;

[0039] Figure 3 This is a schematic diagram of the clock control system in one embodiment;

[0040] Figure 4 This is a flowchart illustrating the process of adjusting the division coefficient of the second frequency division channel in one embodiment;

[0041] Figure 5 This is a flowchart illustrating the process of determining the first and second frequency division channels in one embodiment.

[0042] Figure 6 This is a structural block diagram of a clock frequency division dynamic adjustment device in one embodiment;

[0043] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] The clock division dynamic adjustment method provided in this application embodiment can be applied to, for example, Figure 1 In the application environment shown, the clock control system 102 communicates with the server 104 via a configuration bus. A data storage system can store the data that the server 104 needs to process. The data storage system can be integrated onto the server 104 or placed on a cloud or other network server. The server 104 obtains the clock division configuration information based on the clock control system 102, and determines the first and second division channels according to the clock division configuration information; the first division channel is the working division channel, and the second division channel is the backup division channel; when the clock division processing requirements change, the server 104 adjusts the division coefficient of the second division channel to the target division coefficient, and controls the second division channel to perform clock division processing according to the target division coefficient; when the second division channel meets preset conditions, the server 104 generates a switching control signal; the switching control signal is used to instruct the anti-glitch switching module to switch the second division channel to the working division channel. The clock control system 102 is a control system for controlling the input clock and output clock, and the clock control system 102 can switch the division channels based on the control of the server 104. Server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0046] In one exemplary embodiment, such as Figure 2 As shown, a method for dynamic adjustment of clock frequency division is provided, which can be applied to... Figure 1 Taking the server in the example, the explanation includes the following steps 202 to 206. Wherein:

[0047] Step 202: Based on the clock frequency division configuration information, determine the first frequency division channel and the second frequency division channel; the first frequency division channel is the frequency division channel in working state, and the second frequency division channel is the spare frequency division channel.

[0048] The configuration information refers to the control configuration signals written by the server to the clock control system. This configuration information includes register values ​​for setting the division coefficients of each frequency division channel and switching control signals for indicating frequency division channel switching. The switching control signals include channel selection information. A frequency division channel in active status refers to the frequency division channel currently selected for outputting the frequency-divided clock signal according to the channel selection information in the configuration information. A spare frequency division channel refers to a frequency division channel that is not currently selected for outputting the frequency-divided clock signal. This spare frequency division channel is used to pre-configure new division coefficients when there is a frequency division adjustment requirement in the digital integrated circuit system, and to achieve seamless switching with the frequency division channel in active status.

[0049] In one feasible implementation, the server obtains configuration information via a configuration bus. For details, please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of the clock control system. The clock control system includes a configuration control module and a frequency division channel module, which includes at least two frequency division channels. The server communicates with the configuration control module via a configuration bus. The server can read and write configuration information of the clock control system through the configuration bus. Specifically, the server reads the channel selection information of the current configuration information in the clock control system through the configuration bus, and determines the first frequency division channel and the second frequency division channel from the above-mentioned at least two frequency division channels based on the channel selection information.

[0050] Step 204: When the clock frequency division processing requirements change, adjust the frequency division coefficient of the second frequency division channel to the target frequency division coefficient, and control the second frequency division channel to perform clock frequency division processing according to the target frequency division coefficient.

[0051] The change in clock division requirements refers to situations where, during the operation of a digital integrated circuit system, changes in clock frequency requirements due to performance mode switching, communication rate adjustments, peripheral startup / shutdown, etc., necessitate reconfiguration of the division factor. The division factor controls the frequency division operation of the input clock by the division channel; specifically, it determines the proportional relationship between the output clock signal frequency and the input clock signal frequency.

[0052] In one feasible embodiment, the target division factor is determined based on the changed clock division processing requirements. The target division factor refers to the division factor set in response to the current clock frequency adjustment requirements of the digital integrated circuit system (i.e., in response to changes in clock division processing requirements). The target division factor is used to update the division factor of the backup division channel and instruct the backup division channel to perform the corresponding division operation.

[0053] Optionally, when the server detects a change in clock frequency requirements caused by switching performance modes of the digital integrated circuit system, adjusting communication rates, or starting / stopping peripherals, the server determines the target frequency division coefficient based on the current clock frequency requirements of the digital integrated circuit system; and writes the target frequency division coefficient into the configuration information of the clock control system through the configuration bus to update the frequency division coefficient register value corresponding to the backup frequency division channel (i.e., the second frequency division channel), so that the backup frequency division channel performs the corresponding frequency division operation according to the target frequency division coefficient.

[0054] Step 206: If the second frequency division channel meets the preset conditions, a switching control signal is generated; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to a frequency division channel in the working state.

[0055] The preset conditions refer to the constraints that the backup frequency divider channel (second frequency divider channel) must meet before the frequency divider channel switching is controlled. These conditions ensure that the frequency divider clock output by the backup frequency divider channel has reached a stable state, thus avoiding glitches or timing anomalies during the frequency divider channel switching process. The switching control signal is a control command generated by the server after detecting that the backup frequency divider channel meets the preset conditions. It is used to smoothly switch the current output channel from the first frequency divider channel to the second frequency divider channel, thereby achieving dynamic switching of the frequency divider clock.

[0056] Optionally, when the server determines that the second frequency division channel has met the preset conditions, the server updates the channel selection information of the clock control system through the configuration bus to switch the standby frequency division channel to the active frequency division channel, thereby realizing dynamic switching of the frequency division clock. Specifically, when the second frequency division channel meets the preset conditions, the server generates a switching control signal and controls the anti-glitch switching module to complete the dynamic adjustment of the frequency division clock, switching the second frequency division channel to the active frequency division channel, with no glitch output during the dynamic switching of the frequency division clock.

[0057] In this embodiment, the currently active frequency division channel and the backup frequency division channel are determined based on the clock frequency division configuration information. When the clock frequency division processing requirements change, a target frequency division coefficient can be configured for the backup frequency division channel without affecting the current clock output. The backup frequency division channel is then controlled to perform corresponding frequency division processing operations to determine whether it meets preset conditions, thereby ensuring the stability of the backup frequency division channel output. After determining that the backup frequency division channel meets the preset conditions, a switching control signal is generated to smoothly switch the backup frequency division channel to the active frequency division channel. Through the above-described dynamic clock frequency division adjustment method, online dynamic adjustment of the frequency division coefficient and uninterrupted switching between frequency division channels can be achieved, effectively ensuring the continuity and stability of the frequency division clock output and the reliability of system operation.

[0058] In one exemplary embodiment, such as Figure 4 As shown, adjusting the division coefficient of the second frequency division channel to the target division coefficient includes steps 402 to 404. Wherein:

[0059] Step 402: Determine the target register value corresponding to the target frequency division coefficient.

[0060] The target register value refers to the specific value that the server writes into the register of the corresponding frequency division coefficient of the spare frequency division channel in the configuration control module.

[0061] For example, after the server determines the target division factor based on the clock frequency requirements of the current digital integrated circuit system, it converts the target division factor into a numerical form that can be written into the division factor register corresponding to the division channel, i.e., the target register value. This target register value is used to drive the standby division channel to perform clock division processing according to the set target division factor. The division factor register is a register unit used to store and configure the division factor of the division channel; the division channel determines how to perform periodic division processing on the input clock signal by reading the value of its corresponding division factor register.

[0062] Step 404: Adjust the value of the frequency division coefficient register of the second frequency division channel to the target register value.

[0063] After determining the target division factor and generating the corresponding target register value, the server writes the target register value into the division factor register corresponding to the spare division channel via the configuration bus. By updating the value of the division factor register of the second division channel to the target register value, the second division channel can perform frequency division processing according to the current system's clock frequency requirements.

[0064] In this embodiment, the target division coefficient is determined according to the clock frequency requirements of the current digital integrated circuit system. After the target division coefficient is converted into a target register value, it is written into the division coefficient register of the second division channel (backup division channel). This enables online configuration of the division coefficient of the backup division channel, allowing the backup division channel to perform frequency division processing according to the current clock frequency requirements of the system. Compared with the problem of traditional technology using a fixed division ratio, which cannot meet the clock adjustment requirements of the system in various operating modes or dynamic frequency management scenarios, this embodiment supports the generation and configuration of the target division coefficient on demand, effectively improving the flexibility and adaptability of clock division. This ensures stable clock output while meeting the requirements for dynamic adjustment of clock division in multiple scenarios.

[0065] In an exemplary embodiment, the second frequency divider channel meets the preset conditions including the second frequency divider channel performing clock frequency division for a target number of cycles; the target number is determined according to the target frequency division coefficient.

[0066] The second frequency divider channel meets the preset conditions, which means that after the second frequency divider channel completes the configuration of the target frequency divider coefficient, it has performed clock frequency division on the input clock for the target number of cycles according to the target frequency divider coefficient to ensure that its output frequency divider clock signal reaches a stable state. The target number is determined according to the target frequency divider coefficient, and the target number is usually set to the value corresponding to the target frequency divider coefficient.

[0067] For example, after the server writes the target division factor into the division factor register corresponding to the backup division channel (i.e., the second division channel), the backup division channel performs clock division processing on the input clock according to the target number of cycles before it is switched to the working state. Although the backup division channel is not currently switched to the working state, it can be in the running state and can be used to perform clock division processing on the input clock for the target number of cycles to form a divided output clock of the corresponding frequency. The server can determine whether the backup division channel has reached a stable state based on the output clock frequency of the backup division channel.

[0068] Specifically, let Nnew be the target division factor for the backup frequency divider channel, and let clk_in be the input clock. When the backup frequency divider channel divides the input clock clk_in according to the target division factor Nnew, if the frequency of its divided output clock stabilizes at 1 / Nnew of the input clock clk_in frequency after Nnew consecutive clk_in cycles, then the server determines that the backup frequency divider channel has reached the stability requirement, that is, the backup frequency divider channel meets the preset conditions.

[0069] In this embodiment, by performing clock frequency division processing based on the target frequency division coefficient to complete the target number of cycles in the second frequency division channel (backup frequency division channel), the stability of the output clock of the second frequency division channel is verified, ensuring the continuity and glitches of the output clock when switching to the backup channel. This avoids the clock interruption or glitches caused by the instability of the frequency division channel during traditional single-channel frequency division switching, and realizes the continuity and reliability of the frequency division clock output of the digital integrated circuit system.

[0070] In one exemplary embodiment, such as Figure 5 As shown, determining the first and second frequency division channels based on the clock frequency division configuration information includes steps 502 to 504. Wherein:

[0071] Step 502: When the configuration information is the first value, the frequency division channel corresponding to the first value is determined as the first frequency division channel, and the frequency division channel corresponding to the second value is determined as the second frequency division channel.

[0072] The server uses the current configuration information in the clock control system to determine the frequency divider channels that are in operation and the backup frequency divider channels. Specifically, when the configuration information value is the first value, the frequency divider channel corresponding to the first value is determined as the first frequency divider channel, that is, the frequency divider channel that is currently in operation. This channel is responsible for outputting the frequency-divided clock to the digital integrated circuit system. Correspondingly, the frequency divider channel corresponding to the second value is determined as the backup frequency divider channel.

[0073] For example, the clock control system includes frequency division channel 1 and frequency division channel 2; let the first value be n and the second value be m, and set the frequency division channel corresponding to the first value n as frequency division channel 1, and set the frequency division channel corresponding to the second value as frequency division channel 2. When the server reads the channel selection information in the current configuration information of the clock control system as the first value n, it can determine that frequency division channel 1 is the frequency division channel in the working state, and frequency division channel 2 is the spare frequency division channel.

[0074] Step 504: When the configuration information is the second value, the frequency division channel corresponding to the second value is determined as the first frequency division channel, and the frequency division channel corresponding to the first value is determined as the second frequency division channel.

[0075] For example, when the server reads the channel selection information in the current configuration information of the clock control system as the second value m, it can determine that the frequency division channel 2 is the frequency division channel in the working state and the frequency division channel 1 is the spare frequency division channel.

[0076] In a feasible embodiment, the unique identifier corresponding to frequency division channel 1 can be denoted as n, and the unique identifier corresponding to frequency division channel 2 can be denoted as m. When the channel selection information read by the server is n, it can be determined that frequency division channel 1 is a frequency division channel in working state, and frequency division channel 2 is a spare frequency division channel.

[0077] Furthermore, when the server determines that the second frequency division channel has met the preset conditions, the server updates the channel selection information of the clock control system through the configuration bus. Specifically, when the frequency division channel 1 corresponding to the first value n is the working frequency division channel (first frequency division channel), and the frequency division channel 2 corresponding to the second value m is the spare frequency division channel (second frequency division channel), and it is necessary to switch the frequency division channel, the server modifies the channel selection information from the first value n to the second value m through the configuration bus, and transmits the modified channel selection information to the anti-glitch switching module. The anti-glitch switching module switches the working frequency division channel 1 to the frequency division channel 2 corresponding to the second value m according to the modified channel selection information.

[0078] In this embodiment, by dynamically determining the first and second frequency division channels based on the clock frequency division configuration information, flexible switching management of the frequency division channels is achieved. This allows for the rapid and accurate identification and allocation of active and standby frequency division channels, improving the responsiveness of the digital integrated circuit system to changes in clock frequency division requirements. Furthermore, by clearly distinguishing between active and standby frequency division channels, this embodiment ensures that the standby channel is always ready to take over, achieving seamless switching and continuous, stable clock output. This avoids delays or glitches caused by switching interruptions in traditional solutions.

[0079] In another feasible embodiment, please refer again. Figure 3 The clock control system includes a configuration control module, a synchronization module, a frequency division channel module, and an anti-glitch switching module. The frequency division channel module includes frequency division channel 1 and frequency division channel 2, which are used to divide the input clock according to the set frequency division coefficient. The frequency division channel includes a first frequency division channel and a second frequency division control channel, which are used to pre-configure the frequency division coefficient and prepare for switching when there is a clock frequency adjustment requirement in the digital integrated circuit system.

[0080] The server reads and writes configuration information to the registers of the configuration control module via the configuration bus, thereby configuring and controlling the entire clock control system. The configuration control module generates corresponding configuration control signals based on the server's configuration information read / write operations. These signals are synchronized to the clock domain of the input clock clk_in via the synchronization module. These control signals can be used to control the generation of division coefficients 1 and 2 for frequency division channels 1 and 2, respectively. Division coefficients 1 and 2 control frequency division channels 1 and 2 to generate corresponding divided output clocks clk_div0 and clk_div1 based on their respective division coefficients. The configuration control signals also include switching control signals to instruct the anti-glitch switching module to switch frequency division channels.

[0081] Among them, the frequency division coefficient 0 and frequency division coefficient 1 are both n-bit wide and are used to control frequency division channel 1 and frequency division channel 2 respectively, so as to realize the arbitrary integer frequency division of the input clock clk_in in the range of 1-(2^n-1). Moreover, frequency division channel 1 and frequency division channel 2 are arbitrary integer frequency division channels with an output duty cycle of 50%, so as to output the frequency division clock signal that matches its corresponding frequency division coefficient.

[0082] The anti-glitch switching module is used to realize the dynamic switching between the frequency division clock signals clk_div0 and clk_div1. The switching process is controlled by the switching control signal (including channel selection information) to ensure that the output clock clk_out is uninterrupted and glitch-free during the switching process, so as not to affect the normal and stable operation of the circuit.

[0083] In this clock control system, except for the configuration bus and configuration control module which operate in the clock domain of the configuration bus, all other modules operate in the clock domain of the input clock clk_in.

[0084] In one feasible embodiment, the server reads the channel selection information of the current configuration information in the clock control system through the configuration bus, and determines the first frequency division channel and the second frequency division channel from the above-mentioned at least two frequency division channels based on the channel selection information. Optionally, in this embodiment, the clock control system includes two frequency division channels, each corresponding to a unique identifier. The channel selection information can be set to the unique identifier corresponding to any one of the two frequency division channels to indicate the frequency division channel currently in operation and the corresponding backup frequency division channel. For example, the clock control system includes frequency division channel 1 and frequency division channel 2, where the unique identifier corresponding to frequency division channel 1 is n and the unique identifier corresponding to frequency division channel 2 is m. When the server reads the channel selection information as n, it can determine that frequency division channel 1 is the frequency division channel in operation and frequency division channel 2 is the backup frequency division channel.

[0085] During the operation of a digital integrated circuit system, when the server detects a change in the system's clock frequency requirement, it determines a new target output frequency based on the current operating status of the system, and then determines the corresponding target frequency division factor. The server accesses the clock control system via the configuration bus, writes configuration information to the configuration control module, and writes the target frequency division factor into the register corresponding to the determined backup frequency division channel to update the register value of the backup frequency division channel. After updating the register value of the backup frequency division channel, during the process of the backup frequency division channel dividing the input clock according to the target frequency division factor, the server uses a detection mechanism to determine whether the backup frequency division channel meets preset conditions (i.e., whether the output of the backup frequency division channel is stable). When the server determines that the backup frequency division channel meets the preset conditions, it modifies the channel selection information in the configuration information via the configuration bus to trigger channel switching control. Specifically, when frequency division channel 2 is the backup frequency division channel, the server changes the channel selection information from the unique identifier of frequency division channel 1 to the unique identifier of frequency division channel 2. The trigger channel switching control includes transmitting the modified channel selection information to the anti-glitch switching module, which then switches the working frequency division channel to the backup frequency division channel based on the modified channel selection information.

[0086] Before the server transmits the configuration information to the configuration control module and the anti-glitch switching module, the clock field of the configuration information is synchronized to the clock field where the input clock clk_in is located.

[0087] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0088] Based on the same inventive concept, this application also provides a clock frequency division dynamic adjustment device for implementing the aforementioned clock frequency division dynamic adjustment method. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more clock frequency division dynamic adjustment device embodiments provided below can be found in the limitations of the clock frequency division dynamic adjustment method described above, and will not be repeated here.

[0089] In one exemplary embodiment, such as Figure 6 As shown, a clock frequency division dynamic adjustment device is provided, including: a determining module 602, a frequency division module 604, and an adjustment module 606, wherein:

[0090] The determining module 602 is used to determine the first frequency division channel and the second frequency division channel according to the clock frequency division configuration information; the first frequency division channel is the frequency division channel in the working state, and the second frequency division channel is the spare frequency division channel;

[0091] The frequency divider module 604 is used to adjust the frequency division coefficient of the second frequency divider channel to the target frequency division coefficient when the clock frequency division processing requirements change, and to control the second frequency divider channel to perform clock frequency division processing according to the target frequency division coefficient.

[0092] The adjustment module 606 is used to generate a switching control signal when the second frequency division channel meets the preset conditions; the switching control signal is used to switch the second frequency division channel to a frequency division channel in the working state.

[0093] In an exemplary embodiment, the frequency divider module 604 is further configured to determine the target register value corresponding to the target frequency divider coefficient; and adjust the value of the frequency divider coefficient register of the second frequency divider channel to the target register value.

[0094] In one exemplary embodiment, the frequency division factor is determined based on the changed clock frequency division processing requirements.

[0095] In an exemplary embodiment, the second frequency divider channel meets the preset conditions including the second frequency divider channel performing clock frequency division for a target number of cycles; the target number is determined according to the target frequency division coefficient.

[0096] In an exemplary embodiment, the determining module 602 is further configured to, when the configuration information is a first value, determine the frequency division channel corresponding to the first value as the first frequency division channel and the frequency division channel corresponding to the second value as the second frequency division channel; and when the configuration information is a second value, determine the frequency division channel corresponding to the second value as the first frequency division channel and the frequency division channel corresponding to the first value as the second frequency division channel.

[0097] In one exemplary embodiment, the clock division dynamic adjustment device further includes:

[0098] The acquisition module is used to acquire configuration information via the configuration bus.

[0099] Each module in the aforementioned clock frequency division dynamic adjustment device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0100] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores clock division configuration information. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When executed by the processor, the computer program implements a dynamic clock division adjustment method.

[0101] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0102] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0103] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0104] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0105] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0106] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for dynamic adjustment of clock frequency division, characterized in that, The method includes: Based on the clock frequency division configuration information, the first frequency division channel and the second frequency division channel are determined; the first frequency division channel is the frequency division channel in working state, and the second frequency division channel is the spare frequency division channel; When the clock frequency division processing requirements change, the frequency division coefficient of the second frequency division channel is adjusted to the target frequency division coefficient, and the second frequency division channel is controlled to perform clock frequency division processing according to the target frequency division coefficient; When the second frequency division channel meets the preset conditions, a switching control signal is generated; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to a frequency division channel in the working state.

2. The method according to claim 1, characterized in that, Adjusting the division coefficient of the second frequency division channel to the target division coefficient includes: Determine the target register value corresponding to the target frequency division coefficient; Adjust the value of the division coefficient register of the second division channel to the target register value.

3. The method according to claim 2, characterized in that, The target frequency division coefficient is determined based on the changed clock frequency division processing requirements.

4. The method according to claim 1, characterized in that, The second frequency divider channel meets the preset conditions, including that the clock division period of the second frequency divider channel reaches a target number; the target number is determined according to the target frequency division coefficient.

5. The method according to any one of claims 1 to 4, characterized in that, The step of determining the first frequency division channel and the second frequency division channel based on the clock frequency division configuration information includes: When the configuration information is a first value, the frequency division channel corresponding to the first value is determined as the first frequency division channel, and the frequency division channel corresponding to the second value is determined as the second frequency division channel; When the configuration information is the second value, the frequency division channel corresponding to the second value is determined as the first frequency division channel, and the frequency division channel corresponding to the first value is determined as the second frequency division channel.

6. The method according to any one of claims 1 to 4, characterized in that, The method further includes: The configuration information is obtained through the configuration bus.

7. A clock frequency division dynamic adjustment device, characterized in that, The device includes: The determination module is used to determine the first frequency division channel and the second frequency division channel based on the clock frequency division configuration information; the first frequency division channel is the frequency division channel in the working state, and the second frequency division channel is the spare frequency division channel; The frequency division module is used to adjust the frequency division coefficient of the second frequency division channel to the target frequency division coefficient when the clock frequency division processing requirements change, and to control the second frequency division channel to perform clock frequency division processing according to the target frequency division coefficient; The adjustment module is used to generate a switching control signal when the second frequency division channel meets preset conditions; the switching control signal is used to instruct the anti-glitch switching module to switch the second frequency division channel to a frequency division channel in the working state.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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