Successive compensation sensitive amplifier

Abstract

The invention discloses a successive compensation sensitive amplifier. The working process of the successive compensation sensitive amplifier is divided into compensation mode determination and reading; compensation mode determination: after carrying out one-time idle swing on the sensitive amplifier, carrying out more than one-time compensation on the sensitive amplifier according to an idle swing output signal, and according to a compensation output signal obtained after each time of compensation, judging a compensation size suitable for the sensitive amplifier and recording the compensation size in a latch; and formal reading: after a specified clock period is delayed, starting sensitive amplifier reading. According to the invention, the accuracy of offset voltage compensation can be improved, so that the reading accuracy is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a successive compensation sense amplifier. BACKGROUND

[0002] A sense amplifier is an electronic circuit that can amplify a weak electrical signal. The sense amplifier is mainly based on the amplification of semiconductor devices such as transistors, etc. In the traditional circuit design, it is often assumed that the circuit structure is completely symmetrical, but this is not the case in the actual circuit produced. With the continuous improvement of technology, the threshold voltage is continuously reduced, and due to process fluctuations, the standard deviation of the threshold voltage increases, resulting in an increase in the relative deviation. Therefore, there is no perfect symmetrical sense amplifier (SA) circuit structure, and this defect will introduce a misalignment voltage, which will worsen the effective voltage difference of the sense amplifier.

[0003] The sense amplifier has been widely used in SRAM design, which is to amplify the small voltage difference formed between the bit line pairs to the full rail voltage. However, due to the misalignment voltage of the sense amplifier, this will worsen the speed of the SRAM, so it is crucial to compensate for the misalignment voltage of the sense amplifier.

[0004] Chinese patent application CN120148570A discloses a self-feedback upper cross-coupled sense amplifier circuit and a control method thereof, wherein the circuit comprises an input circuit, an upper cross-coupled circuit and a self-feedback circuit; the input circuit comprises two NMOS and two PMOS, each NMOS is connected between an output node and VSS, and the current conduction of the NMOS is controlled by a PMOS; two PMOS in the upper cross-coupled circuit are cross-connected between two output nodes and VDD, and are used to control VDD to charge one of the output nodes according to the voltage between the two output nodes; each PMOS in the self-feedback circuit is connected between one PMOS of the input circuit and VSS, and the current conduction thereof is controlled by an output node, so as to cut off one NMOS in the input circuit. Although this scheme can reduce the misalignment voltage and power consumption of the sense amplifier circuit, the voltage misalignment compensation effect is not ideal, and the defect of affecting the reading accuracy still exists. SUMMARY

[0005] In the summary section, a series of simplified concepts are introduced, which are simplifications of the prior art in the field. This will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor does it attempt to determine the protection scope of the claimed technical solution.

[0006] The technical problem solved by the present application is to provide a successive compensation sensitive amplifier which can compensate the offset voltage of the sensitive amplifier successively, so that the offset voltage of the sensitive amplifier is compensated and the reading accuracy is improved.

[0007] To solve the above technical problem, the present application provides a successive compensation sensitive amplifier, whose working process is divided into compensation mode determination and reading.

[0008] The compensation mode determination is that after one idle swing of the sensitive amplifier, the sensitive amplifier is compensated more than once according to the idle swing output signal, and the compensation size suitable for the sensitive amplifier is determined according to the compensation output signal obtained after each compensation and recorded in the latch LATCH.

[0009] The formal reading is that after a specified clock period, the reading of the sensitive amplifier is started, and the data of the latch LATCH is used.

[0010] Preferably, the successive compensation sensitive amplifier is further improved, and in each reading process, the sensitive amplifier is compensated according to the data of the latch LATCH.

[0011] Preferably, the successive compensation sensitive amplifier is further improved, and the compensation is performed twice with different sizes.

[0012] Preferably, the successive compensation sensitive amplifier is further improved, and the specified clock period is at least three clocks.

[0013] Preferably, the successive compensation sensitive amplifier is further improved, and the compensation mode determination includes:

[0014] When the control signal CON is in the first state, the counter COUNTER starts counting.

[0015] When the first count COUNTER<0> of the counter is valid, one idle swing of the SA is performed to obtain the idle swing output signal Q<0> for determining the compensation direction, and all compensation mode latch signals ENB_LATCH<0:2> are cleared.

[0016] When the second count COUNTER<1> of the counter is valid, the first compensation mode MODE<1> is used to compensate the SA to obtain the first compensation output signal Q<1>, and the idle swing output signal Q<0> and the first compensation output signal Q<1> are compared. If they are different, the first compensation mode latch signal ENB<0> is set to 1, and the second compensation mode latch signal ENB<1> and the third compensation mode latch signal ENB<2> are both set to 0.

[0017] When the third counter COUNTER<2> is effective, the second compensation mode MODE<2> is used to compensate the second compensation output signal Q<2>, and the first compensation output signal Q<1> and the second compensation output signal Q<2> are compared. If the first compensation output signal Q<1> and the second compensation output signal Q<2> are different, the third compensation mode latch signal ENB<2> is set to 0, and the second compensation mode latch signal ENB<1> is set to 1. If the first compensation output signal Q<1> and the second compensation output signal Q<2> are the same and the first compensation mode latch signal ENB<0> is not 1, the third compensation mode latch signal ENB<2> is set to 1.

[0018] Preferably, the successive compensation sensitive amplifier is further improved, and the formal reading comprises:

[0019] When the control signal CON is in the first state and the counter COUNTER stops counting, the SA reads the auxiliary according to the data in all compensation mode latch signals ENB_LATCH<0:2> in the latch and all compensation output signals Q_LATCH<0:2> in the latch.

[0020] Preferably, the successive compensation sensitive amplifier is further improved, and when the compensation is performed, the compensation circuit is controlled to discharge to ground by performing different compensation modes to achieve different compensation forces.

[0021] Preferably, the successive compensation sensitive amplifier is further improved, and two compensation circuits with the same structure are provided and connected to the first data sampling port SD and the second data sampling port SD_ of the sensitive amplifier respectively.

[0022] Preferably, the successive compensation sensitive amplifier is further improved, and the compensation circuit comprises:

[0023] The first PMOSP1 has its source connected to the data sampling port SD of the sensitive amplifier, its gate forms the first signal end PCOTROL, and its drain is connected to the drain of the first NMOSN1 and the drain of the second PMOSP2.

[0024] The second PMOSP2 has its source open, and its gate forms the reset end PRESA.

[0025] The first NMOSN1 has its source connected to the source of the third PMOSP3 and the source of the fourth PMOSP4, and its gate forms the second signal end NCOTROL.

[0026] The third PMOSP3 has its drain connected to ground, and its gate forms the first compensation mode selection end MODE<1>.

[0027] A fourth PMOS P4, whose drain is connected to ground, and whose gate forms a second compensation mode selection terminal MODE<2>.

[0028] The working principle of the present application is as follows:

[0029] When the first count of the counter (count: 0) is valid, the sensitive amplifier is once empty-swinged to obtain an empty-swing output signal to determine the compensation direction, and all compensation mode latched signals are cleared; that is, the start of the current period of successive compensation.

[0030] When the second count of the counter (count: 1) is valid, the sensitive amplifier is compensated by using the first compensation mode to obtain a first compensation output signal, and the first compensation output signal is compared with the empty-swing output signal; if they are different, the first compensation mode latched signal is set to 1, and the second compensation mode latched signal and the third compensation mode latched signal are both set to 0.

[0031] When the third count of the counter (count: 2) is valid, the sensitive amplifier is compensated by using the second compensation mode to obtain a second compensation output signal, and the second compensation output signal is compared with the empty-swing output signal and the first compensation output signal; if the first compensation output signal and the second compensation output signal are different, the third compensation mode latched signal is set to 0, and the second compensation mode latched signal is set to 1; if the first compensation output signal and the second compensation output signal are the same and the first compensation mode latched signal is not 1, the third compensation mode latched signal is set to 1.

[0032] Through the above successive compensation, the accuracy of the compensation of the misadjustment voltage can be improved, and the condition of opening reading is provided.

[0033] After a delay specified clock cycle, normal reading of the sensitive amplifier is started, and in each reading process, the sensitive amplifier is compensated according to the data in the latch, so as to reduce the mismatch of the sensitive amplifier.

[0034] In order to more accurately compensate the mismatch, the present application adopts a feedback mechanism. By detecting the level difference between SD and SD_, the PCONTROL, NCONTROL, PCONTROL_, and NCONTROL_ signals are dynamically adjusted, so that the levels of SD and SD_ are closer to the ideal state.

[0035] Suppose that at some point, the detected level of SD is higher than that of SD_, which may be due to mismatch. To compensate for this difference, we can: activate the NCONTROL signal, turning on the N-type transistor connected to SD to slightly discharge SD and lower its level. Simultaneously, activate the PCONTROL_ signal, turning on the P-type transistor connected to SD_ to slightly charge SD_ and increase its level. Through this successive compensation method, the levels of SD and SD_ can be dynamically adjusted, reducing the impact of mismatch and improving the performance and reliability of the sensitive amplifier. Attached Figure Description

[0036] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0037] Figure 1 This is a schematic diagram of the supplementary circuit structure of the present invention.

[0038] Figure 2 This is a schematic diagram of the priority structure of the sensitive amplifier of the present invention.

[0039] Figure 3 This is a schematic diagram of the counter priority structure of the present invention.

[0040] Figure 4 This is a schematic diagram of the latch priority structure of the present invention.

[0041] Figure 5 This is a schematic diagram of the priority structure of the compensation mode selection module of the present invention.

[0042] Figure 6 This is a schematic diagram of the priority structure of the compensation control module of the present invention.

[0043] Figure 7 This is the mode of the present invention. <0> Timing diagram of the compensation mode.

[0044] Figure 8 This is the mode of the present invention. <1> Timing diagram of the compensation mode.

[0045] Figure 9 This is the mode of the present invention. <2> Timing diagram of the compensation mode.

[0046] Figure 10is a schematic diagram of 1000 times monteCarlo effect of the present application on normal_SA and proposed_SA under tt_1.1v_25. DETAILED DESCRIPTION

[0047] The advantages and effects of the present application can be fully understood by those skilled in the art from the disclosure of the specification. The present application can also be implemented or applied in different specific embodiments, and the details in the specification can be applied based on different views, with various modifications or changes without departing from the general design idea of the application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. The exemplary embodiments of the present application can be implemented in various forms, and should not be interpreted as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application complete and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. Different is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all the drawings, the same reference signs always represent the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items.

[0048] First of all, it should be noted that the sensitive amplifier structure, compensation circuit structure and surrounding matching circuit structure provided in the following embodiments of the present application are the most optimal solutions considered by the applicant, and should not be understood as a limitation on the specific structure of each module. Correspondingly, the same functions / purposes of the preferred solutions described below can also be achieved by more complex circuits or electrical elements, but the technology is more complex or the cost is slightly higher than the solutions provided by the applicant. The transformed circuit structure or optimized circuit structure of the above-mentioned circuits based on the main design idea and principle of the present application should also be covered by the protection scope of the present application.

[0049] First embodiment;

[0050] The present application provides a successive compensation sensitive amplifier, whose working process is divided into compensation mode determination and reading;

[0051] Compensation mode determination: after one idle swing of the sensitive amplifier, the sensitive amplifier is compensated more than once according to the idle swing output signal, and the compensation output signal obtained after each compensation is used to determine the appropriate compensation size for the sensitive amplifier and record it in the latch LATCH;

[0052] More specifically, the compensation mode determination comprises:

[0053] When the control signal CON is in the first state, i.e. high level, the counter COUNTER starts counting;

[0054] When the first count of the counter COUNTER<0> is valid, the SA is once jiggled to obtain the jiggled output signal Q<0> for determining the compensation direction, and all the compensation mode latch signals ENB_LATCH<0:2> are cleared;

[0055] When the second count of the counter COUNTER<1> is valid, the first compensation mode MODE<1> is adopted to compensate the SA to obtain the first compensation output signal Q<1>, and the jiggled output signal Q<0> and the first compensation output signal Q<1> are compared, if different, the first compensation mode latch signal ENB<0> is set to 1, and the second compensation mode latch signal ENB<1> and the third compensation mode latch signal ENB<2> are both set to 0;

[0056] When the third count of the counter COUNTER<2> is valid, the second compensation mode MODE<2> is adopted to compensate to obtain the second compensation output signal Q<2>, and the jiggled output signal Q<0>, the first compensation output signal Q<1> and the second compensation output signal Q<2> are compared, if the first compensation output signal Q<1> and the second compensation output signal Q<2> are different, the third compensation mode latch signal ENB<2> is set to 0, the second compensation mode latch signal ENB<1> is set to 1, if the first compensation output signal Q<1> and the second compensation output signal Q<2> are the same and the first compensation mode latch signal ENB<0> is not 1, the third compensation mode latch signal ENB<2> is set to 1;

[0057] Formal read: after the specified clock period, the sense amplifier starts reading out;

[0058] More specifically, the formal read comprises:

[0059] When the control signal CON is in the first state and the counter COUNTER stops counting, the SA reads with the aid of all the compensation mode latch signals ENB_LATCH<0:2> in the latch and the data in all the compensation output signals Q_LATCH<0:2> in the latch.

[0060] Preferably, the above embodiment is improved, in the process of each reading, the sense amplifier is compensated according to the data in the latch LATCH.

[0061] Preferably, the above embodiment is improved, two compensations of different sizes are performed.

[0062] Optionally, the specified clock period in the above embodiment is three clocks.

[0063] Second embodiment

[0064] First of all, it needs to be pointed out that the sensitive amplifier described in the present application can be any one in the prior art, only need to be provided with two structure completely same compensation circuit is connected with the first data sampling port SD and the second data sampling port SD_ of sensitive amplifier, executes the control process of the above-mentioned first embodiment can solve the technical problems to be solved by the present application, reaches the corresponding technical effect, reference Figure 1 、 Figure 2 As shown.

[0065] The compensation circuit comprises:

[0066] The first PMOS P1, its source is connected with the data sampling port SD of sensitive amplifier, its gate forms the first signal end PCOTROL, its drain is connected with the drain of the first NMOS N1 and the drain of the second PMOS P2;

[0067] The second PMOS P2, its source is open, its gate forms the reset end PRESA;

[0068] The first NMOS N1, its source is connected with the source of the third PMOS P3 and the source of the fourth PMOS P4, its gate forms the second signal end NCOTROL;

[0069] The third PMOS P3, its drain is grounded, its gate forms the first compensation mode selection end MODE<1>;

[0070] The fourth PMOS P4, its drain is grounded, its gate forms the second compensation mode selection end MODE<2>.

[0071] The first signal end PCOTROL and the second signal end NCOTROL control the opening of compensation, the first compensation mode selection end MODE<1> and the second compensation mode selection end MODE<2> control the compensation mode.

[0072] The PCONTROL, NCONTROL, PCONTROL_, NCONTROL_ of two compensation circuits are each signal end respectively;

[0073] PCONTROL and PCONTROL: these two signal ends are used to control the switching state of P-type transistor PMOS.

[0074] NCONTROL and NCONTROL: these two signals are used to control the switching state of N-type transistor NMOS.

[0075] PCONTROL and NCONTROL: These underlined signal terminals are the inverse signals of PCONTROL and NCONTROL, used to ensure the logical control of the switching state of the transistor.

[0076] SD and SD_: These two signals are the input signal terminals of the sense amplifier, used to transmit the signals of the storage unit (such as DRAM unit). SD and SD_ are complementary signals, that is, the high level of one signal corresponds to the low level of the other signal.

[0077] By controlling the PCONTROL, NCONTROL, PCONTROL_, and NCONTROL_ signals, a small amount of discharge can be performed on SD or SD_. Specifically, by controlling these signals, the P-type or N-type transistor can be turned on, thereby performing a slight current adjustment on SD or SD_, changing its level state.

[0078] Due to the manufacturing process deviation, the characteristics of the transistor (such as threshold voltage, mobility, etc.) will have differences, which will cause the input signal (SD and SD_) of SA to be asymmetric in the ideal case, thereby generating an offset voltage. By controlling the PCONTROL, NCONTROL, PCONTROL_, and NCONTROL_ signals, a small amount of discharge can be performed on SD or SD_, which can adjust the level of SD and SD_ to be closer to the ideal state, thereby reducing the influence of the offset voltage and improving the performance and reliability of SA.

[0079] The PCONTROL, NCONTROL, PCONTROL_, and NCONTROL_ signals are generated by digital logic circuits. The logic state of these signals determines which transistors are turned on, thereby controlling the discharge of SD or SD_. In the SA circuit, P-type and N-type transistors are connected to SD and SD_, respectively, and by controlling the signals to turn on or turn off these transistors, a slight current adjustment on SD or SD_ is achieved.

[0080] The following provides a brief description of the peripheral circuit of the sense amplifier of the present application. As mentioned above, this content should not be understood as a limitation of the peripheral circuit. As long as the peripheral circuit can provide the signals required for the operation of the sense amplifier of the present application, it can be any one of the prior art.

[0081] Reference Figure 3 As shown, the counter, whose input is the control signal CON and the clock CLK, whose output is the count range COUNTER<0:2>.

[0082] Reference Figure 4The latch, whose input is the counter, the empty swing signal, the control signal and the enable signal, whose output is the compensation mode latch signal and the empty swing output signal, is shown in the figure.

[0083] The compensation mode latch signal is used to compensate the SA mismatch. According to the first two compensation, the suitable mode is determined, and then the SA is read out according to the stored ENB<0:2>.

[0084] Reference is made to Figure 5 The compensation mode selection, which determines the compensation mode according to ENB<0:2> and COUNTER<0:2>, is shown in the figure.

[0085] Reference is made to Figure 6 The compensation control, whose input is the compensation mode signal, the control signal, the bit-line pre-charge signal and the empty swing output signal, whose output signal to CONTROL, NCONTROL, PCONTROL_, NCONTROL_ is each signal terminal, is used to generate the compensation signal and control the discharge of SD or SD_, is shown in the figure.

[0086] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0087] The application has been described in detail by specific implementation and examples, but these do not constitute a limitation on the application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the application, and these should also be considered as the protection scope of the application.

Claims

1. A successive compensation sensitive amplifier, characterized in that: Its working process is divided into compensation mode determination and reading; Compensation mode determination: After the sensitive amplifier is idled once, the sensitive amplifier is compensated more than once based on the idled output signal. Based on the compensation output signal obtained after each compensation, the appropriate compensation value for the sensitive amplifier is determined and recorded in the latch. Formal reading: After a specified clock cycle delay, the sensitive amplifier begins reading.

2. The successive compensation sensitive amplifier as described in claim 1, characterized in that: Based on the data from the latch, the sensitive amplifier is compensated during each read.

3. The successive compensation sensitive amplifier as described in claim 1, characterized in that: Perform two compensations of different magnitudes.

4. The successive compensation sensitive amplifier as described in claim 1, characterized in that: The specified clock period is at least three clock cycles.

5. The successive compensation sensitive amplifier as described in claim 1, characterized in that, The determination of the compensation model includes: When the control signal (CON) is in the first state, the counter (COUNTER) starts counting; First count of the counter (COUNTER) <0> When valid, SA is oscillated once to obtain the oscillation output signal (Q). <0> ) is used to determine the compensation direction and clear all compensation mode latch signals (ENB_LATCH<0:2>); Second count of the counter (COUNTER) <1> When effective, the first compensation mode (MODE) is adopted. <1> The first compensated output signal (Q) is obtained by compensating SA. <1> ), compare the output signal (Q) of the idle pendulum <0> ) and the first compensation output signal (Q) <1> If they are different, then the first compensation mode latch signal (ENB) will be used. <0> Set to 1, second compensation mode latch signal (ENB) <1> ) and the third compensation mode latch signal (ENB) <2> Set all to 0; Counter third count (COUNTER) <2> When effective, the second compensation mode (MODE) is adopted. <2> The second compensated output signal (Q) is obtained through compensation. <2> ), compare the output signal (Q) of the idle pendulum <0> ), first compensation output signal (Q) <1> ) and second compensation output signal (Q <2> If the first compensation output signal (Q) <1> ) and second compensation output signal (Q <2> If the values ​​are different, then the third compensation mode latch signal (ENB) will be used. <2> Set to 0, second compensation mode latch signal (ENB) <1> Set to 1 if the first compensation output signal (Q) <1> ) and second compensation output signal (Q <2> The same and the first compensation mode latch signal (ENB) <0> If the value is not 1, then the third compensation mode latch signal (ENB) will be latched. <2> Set to 1.

6. The successive compensation sensitive amplifier as described in claim 1, characterized in that, Performing a formal read includes: When the control signal (CON) is in the first state and the counter (COUNTER) stops counting, SA performs reading assistance based on the data in all the compensation mode latch signals (ENB_LATCH<0:2>) and all the compensation output signals (Q_LATCH<0:2>) in the latch.

7. The successive compensation sensitive amplifier as described in claim 1, characterized in that: During compensation, different compensation modes are executed to ground the compensation circuit and control the discharge, thereby achieving different compensation levels.

8. The successive compensation sensitive amplifier as described in claim 1, characterized in that: Two identical compensation circuits are provided and connected to the first data sampling port (SD) and the second data sampling port (SD_) of the sensitive amplifier, respectively.

9. The successive compensation sensitive amplifier as described in claim 1, characterized in that, The compensation circuit includes: The first PMOS (P1) has its source connected to the data sampling port (SD) of the sensitive amplifier, its gate forming the first signal terminal (PCOTROL), and its drain connected to the drain of the first NMOS (N1) and the drain of the second PMOS (P2). The second PMOS (P2) has an open source and its gate forms a reset terminal (PRESA); The first NMOS (N1) has its source connected to the source of the third PMOS (P3) and the source of the fourth PMOS (P4), and its gate forms the second signal terminal (NCOTROL). The third PMOS (P3) has its drain grounded, and its gate forms the first compensation mode selection terminal (MODE). <1> ); The fourth PMOS (P4) has its drain grounded, and its gate forms the second compensation mode selection terminal (MODE). <2> ).

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