A data reading method of a memory and a memory

Abstract

The application provides a data reading method of a memory and the memory; the data reading method of the memory comprises the following steps: in response to a data reading instruction of a processor, based on a plurality of address intervals of a plurality of storage areas, determining a first target area in which a first address in the data reading instruction is located from the plurality of storage areas; querying a value of a first state identification bit of the first target area, the value of the first state identification bit representing whether the data checking function of the first target area is enabled; when the value of the first state identification bit represents that the data checking function of the first target area is enabled, reading data and a checking code of the data from the first address; checking the data through the checking code to obtain a checking result, and outputting the data to the processor based on the checking result. Through the application, the flexibility of data checking during data reading can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technology field, and particularly relates to a data reading method of a memory and the memory. BACKGROUND

[0002] Digital integrated circuit design, system on a chip (SoC) design, etc., all need to use a memory, for example, need to use a static random-access memory (SRAM) as a storage medium. With the increase of storage demand, the storage capacity of the memory is getting larger and larger, and some memories, for example, the SRAM, in the use process, will cause individual bit data errors due to signal interference or unstable reliability. In the related art, there is a problem of low flexibility of data checking when reading data from the memory. SUMMARY

[0003] The embodiments of the present application provide a data reading method of a memory and the memory, which can improve the flexibility of data checking when reading data.

[0004] The technical scheme of the embodiments of the present application is implemented as follows:

[0005] The embodiments of the present application provide a data reading method of a memory, the memory comprising a RAM chip, the RAM chip comprising a plurality of storage areas, and the method comprising:

[0006] In response to a data reading instruction of a processor, a first target area in which a first address in the data reading instruction is located is determined from a plurality of the storage areas based on a plurality of address intervals of the plurality of the storage areas.

[0007] The value of a first status identification bit of the first target area is queried, and the value of the first status identification bit represents whether the data checking function of the first target area is enabled.

[0008] When the value of the first status identification bit represents that the data checking function of the first target area is enabled, data and a check code of the data are read from the first address.

[0009] The data is checked through the check code to obtain a checking result, and data is output to the processor based on the checking result.

[0010] The embodiments of the present application provide a data writing method of a memory, the memory comprising a RAM chip, the RAM chip comprising a plurality of storage areas, and the method comprising:

[0011] In response to a data write instruction of a processor, a second target region in which a second address in the data write instruction is located is determined from a plurality of the storage regions based on a plurality of address intervals of the plurality of the storage regions;

[0012] A value of a second status identification bit of the second target region is queried, and the value of the second status identification bit represents whether the data check function is enabled for the second target region;

[0013] When the value of the second status identification bit represents that the data check function is enabled for the second target region, a check code is generated for data in the data write instruction;

[0014] The data and the check code are written at the second address.

[0015] Embodiments of the present application provide a memory, comprising: a region determination unit, a decoder, a RAM chip and a register, the RAM chip comprising a plurality of storage regions;

[0016] The region determination unit is configured to, in response to a data read instruction of a processor, determine a first target region in which a first address in the data read instruction is located from a plurality of the storage regions based on a plurality of address intervals of the plurality of the storage regions stored in the register, and query a value of a first status identification bit of the first target region from the register, the value of the first status identification bit representing whether a data check function is enabled for the first target region;

[0017] The decoder is configured to, when the value of the first status identification bit represents that the data check function is enabled for the first target region, read data and a check code of the data from the first address, check the data based on the check code to obtain a check result, and output the data to the processor based on the check result.

[0018] The RAM chip is configured to store the data and the check code.

[0019] The register is configured to store the plurality of address intervals of the plurality of the storage regions and the value of the first status identification bit of the first target region.

[0020] In the above scheme, the decoder is further configured to determine a companion formula based on the data and the check code, and check errors in the data based on the companion formula to obtain the check result.

[0021] In the above scheme, the register further stores a value of a first error identification bit and a value of a second error identification bit.

[0022] The decoder is further configured to perform error correction on the single-bit error in the data when the check result indicates that the data has the single-bit error, and output the data after error correction to the processor; and set values of a first error identification bit and a second error identification bit in the register to a first preset value indicating that there is an error, wherein the first error identification bit is used to indicate whether the data has an error, and the second error identification bit is used to indicate whether the data has a single-bit error.

[0023] In the above solution, the register further stores a value of the first error identification bit and a value of a third error identification bit.

[0024] The decoder is further configured to output the data to the processor when the check result indicates that the data has the double-bit error; and set values of a first error identification bit and a third error identification bit in the register to a first preset value indicating that there is an error, wherein the third error identification bit is used to indicate whether the data has a double-bit error.

[0025] In the above solution, the register further stores a value of the first error identification bit, a value of the second error identification bit, and a value of the third error identification bit.

[0026] The decoder is further configured to output the data to the processor when the check result indicates that the data has no error; and set values of a first error identification bit, a second error identification bit, and a third error identification bit in the register to a second preset value indicating that there is no error.

[0027] In the above solution, the decoder is further configured to read the data from the first address and output the data to the processor when the value of the first state identification bit indicates that the first target region does not enable the data check.

[0028] In the above solution, the plurality of storage regions are divided by the processor from the RAM chip, and the plurality of address intervals of the plurality of storage regions are generated by the processor.

[0029] The value of the first state identification bit in the register is generated by the processor.

[0030] Embodiments of the present application provide a memory, which comprises a region judging unit, an encoder, a RAM chip, and a register, wherein the RAM chip comprises a plurality of storage regions.

[0031] The region determining unit is configured to, in response to a data write instruction of the processor, determine, based on a plurality of address intervals of a plurality of storage regions stored in the register, a second target region in which a second address in the data write instruction is located from the plurality of storage regions, and query a value of a second state identification bit of the second target region from the register, the value of the second state identification bit representing whether the data check function is enabled for the second target region.

[0032] The encoder is configured to, when the value of the second state identification bit represents that the data check function is enabled for the second target region, generate a check code for data in the data write instruction, and write the data and the check code at the second address.

[0033] The RAM chip is configured to store the data and the check code.

[0034] The register is configured to store a plurality of address intervals of a plurality of storage regions and a value of a second state identification bit of a second target region.

[0035] In the above scheme, the encoder is further configured to, when the value of the second state identification bit represents that the data check function is not enabled for the second target region, write the data to the second address.

[0036] Embodiments of the present application provide an electronic device, which comprises a processor and a memory provided by embodiments of the present application.

[0037] Embodiments of the present application have the following beneficial effects: the RAM chip in the memory is divided into a plurality of storage regions, and the data check function can be independently enabled or disabled for each storage region by the value of the state identification bit corresponding to each storage region, so that in the data reading process, a first target region is determined from the plurality of storage regions according to a first address specified by a data read instruction, and then it is determined whether the data check function is enabled for the first target region by querying the value of the first state identification bit of the first target region. Only when the data check function is enabled, the data is checked by using the check code read from the first address, and then the data is output to the processor in combination with the check result, so that it is determined whether to start the data check on demand, the flexibility of data check when reading data is improved while the data reliability is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a schematic diagram of an architecture of a data reading system of a memory provided by embodiments of the present application;

[0039] Figure 2 FIG. 2 is a flowchart of a data reading method of a memory provided by embodiments of the present application; Figure One;

[0040] Figure 3 is a flowchart of a data reading method of a memory provided by an embodiment of the present application Figure Two ;

[0041] Figure 4 is a flowchart of a data reading method of a memory provided by an embodiment of the present application Figure Three ;

[0042] Figure 5 is a flowchart of a data writing method of a memory provided by an embodiment of the present application Figure One ;

[0043] Figure 6 is a flowchart of a data writing method of a memory provided by an embodiment of the present application Figure Two ;

[0044] Figure 7 is a schematic diagram of a data writing process and a data reading process provided by an embodiment of the present application

[0045] Figure 8 is a schematic diagram of a data bit during data transmission provided by an embodiment of the present application

[0046] Figure 9 is a transmission format schematic diagram of 8-bit data and 5-bit error correction code provided by an embodiment of the present application

[0047] Figure 10 is a schematic diagram of area division of an SRAM provided by an embodiment of the present application

[0048] Figure 11 is a structure schematic diagram of a memory provided by an embodiment of the present application Figure One ;

[0049] Figure 12 is a structure schematic diagram of a memory provided by an embodiment of the present application Figure Two . DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0051] In the following description, “some embodiments” are related to a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0052] In the following description, the terms "first\second\third" are merely distinguished similar objects, and do not represent the specific order of the objects. It can be understood that the "first\second\third" can be interchanged with the specific order or sequence as allowed, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein.

[0053] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined target, and can be implemented entirely or partially by using software, hardware (such as a processing circuit or a memory) or a combination thereof. Similarly, one processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of an integral module or unit that includes the functions of the module or unit.

[0054] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by one skilled in the art. The terms used in the embodiments of the present application are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0055] The relevant data collection process in the embodiments of the present application should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and within the scope of authorization of laws and regulations and the personal information subject, carry out subsequent data use and processing.

[0056] Before the embodiments of the present application are further described in detail, the terms and terms involved in the embodiments of the present application are explained, and the terms and terms involved in the embodiments of the present application are applicable to the following explanations.

[0057] 1) In response to: used to represent the conditions or states on which the operations performed depend, when the dependent conditions or states are met, one or more operations performed can be real-time or have a set delay; in the absence of special instructions, there is no restriction on the execution order of multiple operations performed.

[0058] 2) Human-computer interaction interface, an interface for providing human-computer interaction function / an interface for displaying information of business processing result. For example, a graphical user interface (GUI) display, such as an augmented reality (AR) interface, a virtual reality (VR) interface, a voice user interface (VUI), an interactive projection interface (using projection technology to display information on a plane), an eye movement control interface (an interface controlled by detecting the user's line of sight), a holographic interface (a three-dimensional holographic image formed by holographic projection technology, without wearing special glasses to see a stereoscopic image), a multi-modal interface (an interactive interface combining multiple interaction modes such as touch, vision, hearing, etc.), and the like.

[0059] 3) Memory, refers to a hardware device for saving programs and data, and its core function is to be able to store data (in binary form) in a certain location, and to accurately retrieve and operate it when needed.

[0060] 4) Check code, a redundant code bit added after the original data to detect or correct data errors. The core idea is to verify whether the data is wrong after storage by adding some extra information, or even to correct the data.

[0061] Digital integrated circuit design, system on a chip (SoC) design, etc., all need to use memory, for example, static random access memory (SRAM) is needed as a storage medium. With the increase of storage demand, the storage capacity of the memory is getting larger and larger, and some memories, such as SRAM, may cause individual bit data errors due to signal interference or unstable reliability during use. The read-out data error will cause the read-out data to be unable to be used normally, or the entire computer system to be unable to be used normally. Therefore, it is necessary to discover and correct errors in the memory in time.

[0062] In the related art, although there are check codes that can detect and correct errors in the data in the memory when reading the data, that is, error management, these schemes all check the data of the entire RAM chip of the memory through the check code, or do not check the data of the entire RAM chip, which cannot be processed finely and on demand, thereby causing the problem of low flexibility of data checking when reading data from the memory.

[0063] The embodiment of the present application provides a data reading method of a memory, a data writing method of the memory and the memory, and the flexibility of data checking during data reading can be improved. The embodiment of the present application provides an exemplary application of the memory, and the memory can be used as an independent memory IP core, which can be integrated into various system on a chip (SoC) or application specific integrated circuits as a key module, for example, as a last level cache in a central processing unit (CPU) or a graphics processing unit (GPU), or as a cache of embedded flash memory or a main static memory integrated into an industrial microcontroller unit (MCU). The memory can be applied to various electronic devices, and the electronic devices can be implemented as notebook computers, tablet computers, desktop computers, set-top boxes, smart phones, smart speakers, smart watches, smart televisions, vehicle terminals and various types of terminals, and can also be implemented as servers.

[0064] Referring to Figure 1 , Figure 1 is a schematic diagram of an architecture of a data reading system of the memory provided by the embodiment of the present application, in order to support the data reading application of one memory, in the data reading system 100 of the memory, the terminal 400 is connected to the server 200 through the network 300, the server 200 is provided with the memory, and the network 300 can be a wide area network or a local area network, or a combination of the two.

[0065] In the scene of data processing through a machine learning model, the terminal 400 is configured to send a service request to the server 200, a communication device in the server 200 receives the service request, a processor sends a data reading instruction to the memory, the memory reads corresponding data and outputs the data to the processor, the processor processes the read data to obtain a service result, and sends the result to the terminal 400. The terminal 400 receives the service result and displays it on the man-machine interaction interface 410.

[0066] Next, the data reading method of the memory provided by the embodiment of the present application will be described in combination with the exemplary application and implementation of the memory provided by the embodiment of the present application.

[0067] Referring to Figure 2 , Figure 2 is a flowchart of the data reading method of the memory provided by the embodiment of the present application Figure One , the steps shown in Figure 2 will be described.

[0068] It should be noted that the memory includes a RAM chip, i.e. a Random Access Memory chip, and the RAM chip includes a plurality of storage areas, each of which can be regarded as a part of the RAM chip, which is obtained by dividing the address interval of the RAM chip, so that the storage area can be regarded as a logical address interval. The memory can also include a register for storing some information needed in data reading.

[0069] Step 101, in response to a data reading instruction of the processor, based on a plurality of address intervals of a plurality of storage areas, determining a first target area where a first address in the data reading instruction is located from the plurality of storage areas.

[0070] When the processor processes data, it first needs to read the data needed for processing, so the processor will generate a data reading instruction and specify the address of the data to be read, i.e. the first address where the data is located, in the data reading instruction, and then send the data reading instruction to the memory. The memory parses the data reading instruction to obtain the first address. Then, the memory obtains the address interval of each storage area, and then determines the storage area where the first address is located from the plurality of storage areas according to the address interval of each storage area and the first address specified in the data reading instruction, and takes the storage area as the first target area.

[0071] It should be noted that in the embodiments of the present application, the address intervals of the plurality of storage areas can be stored in the register inside the memory, so that the memory can obtain the address interval of each storage area from the register, and then compare the first address with the start address and the end address of the address interval to determine whether the reading address falls within the address interval.

[0072] For example, assuming that the number of storage areas in the RAM chip is 3, the address intervals are [0x0000_0000, 0x0000_1FFF], [0x0000_2000, 0x0000_DFFF], and [0x0000_E000, 0x0000_FFFF], and the first address is 0x0000_1234, then the memory compares the three address intervals with the first address to determine that the first address falls within [0x0000_0000, 0x0000_1FFF], and therefore takes the storage area corresponding to [0x0000_0000, 0x0000_1FFF] as the first target area.

[0073] Step 102, querying the value of the first state identification bit of the first target area.

[0074] After determining the first target region where the first address is located, the memory obtains the value of the first status identification bit from the value of the status identification bit of all storage regions for the first target region, to determine whether the first target region enables the data check function through the value of the first status identification bit. In other words, the value of the first status identification bit represents whether the first target region enables the data check function.

[0075] It should be noted that the status identification bit is a binary bit of a register stored in the memory, and the value thereof is used to identify whether the corresponding storage region enables the data check function. Here, each storage region has a corresponding status identification bit, so that the register has multiple status identification bits corresponding to multiple storage regions, thereby respectively representing whether the multiple storage regions enable the data check function.

[0076] In other words, in the embodiment of the application, the RAM chip can be divided into multiple storage regions by the processor, and the enabling of the data check function of each storage region can be controlled individually, that is, some storage regions can enable the data check function, and some other storage regions do not enable the data check function. The change of the enabling state of the data check function can be controlled by the processor modifying the value of the corresponding status identification bit.

[0077] In some embodiments of the application, the multiple storage regions can be obtained by the processor dividing the RAM chip, and the multiple address intervals of the multiple storage regions can be generated by the processor. The processor can write the multiple address intervals of the multiple storage regions into the register, so that the memory can subsequently query the address interval of each storage region from the register. Meanwhile, the enabling of the data check function of each storage region can be controlled by the processor, so that the value of the first status identification bit of each storage region is generated by the processor. The processor can write the value of the first status identification bit into the register, so that the memory can query the value of the first status identification bit of a certain storage region from the register when data is read.

[0078] It should be noted that the data check function refers to a function of checking the stored data during data reading to detect whether the data has errors and performing corresponding processing on the errors, for example, detecting errors in the data of the RAM chip of the memory, then automatically correcting single-bit errors of the data, and reporting double-bit errors, etc.

[0079] In the embodiment of the application, the value of the first status identification bit of each storage region can be stored in the register inside the memory, so that the memory can directly query the value of the first status identification bit of the first target region from the register inside the memory to determine whether the first target region enables the data check function.

[0080] It should be noted that in the embodiments of the present application, the first preset value can represent that the data check function is enabled, that is, when the value of the first state identification bit of the first target area is the first preset value, it represents that the data check function has been enabled for the first target area; the second preset value can represent that the data check function is not enabled, that is, when the value of the first state identification bit of the first target area is the second preset value, it represents that the data check function is not enabled for the first target area. Here, the values of the first preset value and the second preset value can be set according to actual conditions, for example, the first preset value is set to 1, and the second preset value is set to 0.

[0081] In step 103, when the value of the first state identification bit represents that the first target area enables the data check function, the data and the check code of the data at the first address are read.

[0082] The memory determines that the first target area enables the data check function according to the value of the first state identification bit, and when the first target area enables the data check function, the first address not only stores the data written by the processor at the historical time, but also stores the check code generated for the data. Therefore, when the memory determines that the first target area enables the data check function by querying the value of the first state identification bit, all data at the first address will be read out, which includes the data and the check code of the data. The check code is used to check the data error, and is also used as a redundant code bit appended to the original data for error correction. Therefore, in the embodiments of the present application, some additional information, that is, the check code, can be added to check the data, that is, to detect and correct errors.

[0083] It should be noted that the memory can automatically separate the data and the check code in the first address according to a fixed mapping rule. The mapping rule defines the positions of the data bit and the check code bit in the physical storage space of the RAM chip, and the mapping rule can be determined by a design engineer in the hardware design stage of the RAM chip.

[0084] It should be further noted that since the interface bit width of some RAM chips is even, and the sum of the bit width of the data and the check code is odd, the information stored in the first address includes not only the data itself and the check code of the data, but also a redundant bit. At this time, when the memory reads the data from the first address, the data, the check code of the data and the redundancy are read out at the same time, and then the redundancy is discarded, and only the data and the check code are processed subsequently.

[0085] For example, the bit width of the data is 128 bits, the bit width of the check code is 9 bits, and the port bit width of the RAM chip is 138 bits. Therefore, the first address simultaneously stores 128 bits of data, 9 bits of check code, and 1 bit of redundancy.

[0086] Step 104, check the data by the check code to obtain a check result, and output the data to the processor based on the check result.

[0087] After obtaining the check code and the data, the memory will perform data checking on the data, i.e., retrieval or error correction, and obtain a check result of the data checking, i.e., whether there is an error in the data and the type of the error, and then perform subsequent processing on the data according to the check result, such as real-time error correction for single-bit errors or triggering an error flag for double-bit errors, and finally output the corresponding data to the processor.

[0088] Referring to Figure 3 , Figure 3 is a flowchart of a data reading method of a memory provided in an embodiment of the present application Figure Two In some embodiments of the present application, Figure 2 Step 104 in the method in the present application can be implemented by the following processing:

[0089] Step 1041, determine the syndrome based on the data and the check code.

[0090] It should be noted that the syndrome refers to a key intermediate result in the decoding process of the error correction code, and the syndrome is a binary vector composed of a group of bits, and through the syndrome, it can be determined whether there is an error in the read data and the position of the error if there is an error.

[0091] In some embodiments of the present application, the memory can generate a new check code for the data using the check equation defined when generating the check code, and then compare the generated new check code with the original check code read from the RAM chip, for example, by performing a bitwise XOR operation, and then determine the difference between the two, for example, the result of the bitwise XOR operation, as the syndrome. At this time, the obtained syndrome is a binary vector, which can be converted into a decimal value, and the value is the value of the syndrome.

[0092] For example, assuming that the bit width of the data is 8, represented as D0 to D7, and the bit width of the check code is 5, represented as P0 to P5, if the check equation used when generating the check code generates new check codes P0', P1', P2', P3', and P4' for the data, and then performs XOR operation between P0 and P0' to obtain S0, performs XOR operation between P1 and P1' to obtain S1,..., and performs XOR operation between P4 and P4' to obtain S4, then the syndrome can be represented as [S0S1S2S3S4], for example,

[00000] .

[0093] It should be noted that the check equation defined when the check code is generated can be a check equation in a commonly used encoding mode, for example, the check equation of the embodiment of the present application can be a check equation of a Hamming code, or a check equation of an extended Hamming code, and the like.

[0094] In some other embodiments of the present application, the memory can also directly calculate the syndrome by combining the data and the check code at the same time, that is, the memory performs an XOR operation on the bits participating in the check equation (including the data bits and the check code bits), and then generates a binary vector using the XOR operation result of all the bits as the syndrome, and then takes the decimal value corresponding to the binary vector as the value of the syndrome.

[0095] For example, if the check equation is P0=D0^D1^D3^D5, then the bits of the corresponding syndrome can be represented as S0=D0'^D1'^D3'^D5'^P0, and thus the syndrome [S0S1S2S3S4] such as

[00000] can also be obtained.

[0096] Step 1042, based on the syndrome, checking the error in the data to obtain a check result.

[0097] After the memory determines the syndrome, it determines whether there is an error in the data by judging whether the value of the syndrome is 0. If the value of the syndrome is 0, the memory determines that there is no error in the data, that is, the data is correct. If the value of the syndrome is not 0, the memory can also determine the number of errors, that is, the number of bits with errors in the data, according to the syndrome. In this way, the memory can complete the error checking of the data, thereby determining whether there is an error in the data and the type of error when there is an error.

[0098] When the value of the syndrome is not 0, the memory can calculate the number of 1s in the syndrome, and determine the type of error in the data according to the parity. Here, if there is an odd number of 1s in the syndrome, it is confirmed that there is a single-bit error in the data, and if there is an even number of 1s in the syndrome, it is confirmed that there is a double-bit error in the data.

[0099] When the value of the syndrome is not 0, the memory can also determine the type of error in the data, that is, whether it is a single-bit error or a double-bit error, by looking up a table, that is, from a table for recording all possible syndromes and the error type and error position corresponding thereto. All possible values of the syndromes in the table can be calculated in advance by a human expert.

[0100] For example, if the bit width of the data is 8, represented as D0 to D7, and the bit width of the check code is 5, represented as P0 to P4, in the above table, the accompanying pattern 00000 can correspond to no error, the accompanying pattern 00111 can correspond to a single-bit error of D0, the accompanying pattern 01011 can correspond to a single-bit error of D1, and so on, the accompanying pattern 10100 represents a double-bit error of D0 and D7, and the accompanying pattern 11011 represents another double-bit error. When the memory determines the accompanying pattern and the value of the accompanying pattern is not 0, the memory can determine the error type and the error position of the data by querying the data table, thereby completing the error check of the data and obtaining the check result.

[0101] It can be understood that, in the embodiments of the present application, the memory can first determine the value of the accompanying pattern based on the data and the check code, and then quickly perform error check according to the value of the accompanying pattern, so that the error check can be completed without comparing the read data with the original data written, and the efficiency of the error check can be improved.

[0102] In some embodiments of the present application, Figure 2 The step of outputting the data to the processor based on the check result in step 104 can be implemented by the following processing: when the check result represents that the data has a single-bit error, correcting the single-bit error in the data and outputting the corrected data to the processor; and setting the value of the first error identification bit and the value of the second error identification bit to a first preset value representing that there is an error, wherein the first error identification bit is used to indicate whether the data has an error, and the second error identification bit is used to indicate whether the data has a single-bit error.

[0103] After determining the check result, the memory will perform subsequent processing on the data according to the information represented by the check result. When the check result represents that the data has a single-bit error, the memory will immediately perform error correction processing on the single-bit error to obtain corrected data, and then output the corrected data to the processor. At the same time, the memory also needs to inform the processor that the read data has a single-bit error and the single-bit error has been corrected.

[0104] In the embodiments of the present application, the register of the memory is also provided with an error identification bit used to indicate the error of the data, and the memory can inform the processor whether an error occurs and the error type by setting the value of the error identification bit. In the embodiments of the present application, the register can be provided with a first error identification bit and a second error identification bit, the first error identification bit is used to indicate whether the data has an error, and the second error identification bit is used to indicate whether the data has a single-bit error. The single-bit error refers to an error in which only one bit in a binary data block is flipped from an original value to an opposite value, for example, a bit originally written with a value of 0 is flipped to 1, and a single-bit error occurs in the data.

[0105] It should be noted that in the embodiments of the present application, the first preset value can be used to represent the occurrence of an error. Therefore, the memory can set the value of the first error identification bit in the register to the first preset value and set the value of the second error identification bit in the register to the first preset value. When the processor queries the value of the first error identification bit from the register and the value of the second error identification bit is the second preset value, it is determined that the data read from the memory has a single-bit error, and the single-bit error has been automatically corrected by the memory.

[0106] It should be further noted that when the memory corrects the single-bit error, it first locates the data bit with the error from the data according to the specific decimal value of the syndrome. Then, the memory generates a flip signal for the data bit to flip the bits of the original data in the data bit, for example, to flip 1 to 0 and 0 to 1. Then, the data after the single-bit flip is taken as the data after error correction.

[0107] For example, the bit width of the data is 8, represented as D0 to D7, and the bit width of the check code is 5, represented as P0 to P4. If the original data stored at the first address is expected to be 0101_0101 and the check code is 10101, if the D0 bit is flipped, the read data becomes 0101_0100, and the check code is still 10101. The memory can calculate the syndrome 00111 (decimal value 7), which is not 0 and has an odd number of 1s in the syndrome, to determine that a single-bit error has occurred. At this time, the memory flips the value of D0, i.e., flips 0 to 1, to obtain the data after error correction 0101_0101. The data after error correction is output to the processor, and the values of the first error identification bit and the second error identification bit in the register are both set to 1, i.e., the first preset value, to realize error reporting.

[0108] It can be understood that in the embodiments of the present application, the memory will immediately correct the data when it is determined that there is a single-bit error in the data, so that the processor can avoid system crashes caused by minor errors, significantly improve the resistance of the memory to transient errors, and thus improve the reliability of the memory.

[0109] In some embodiments of the present application, Figure 2 The step 104 of outputting the data to the processor based on the check result in the method 100 can be implemented by the following processing: when the check result indicates that the data has a double-bit error, outputting the data to the processor; and setting the value of the first error identification bit and the value of the third error identification bit to the first preset value indicating the existence of an error, wherein the third error identification bit is used to indicate whether the data has a double-bit error.

[0110] Since the double-bit error can have exceeded the error correction capability of the memory, when the check result represents that there is a double-bit error in the data, the memory does not correct the error of the data, but directly outputs the data to the processor. At the same time, the memory informs the processor that there is a double-bit error in the data by modifying the value of the first error identification bit and the value of the third error identification bit in the register. The third error identification bit is used to indicate whether there is a double-bit error in the data.

[0111] It should be noted that the double-bit error refers to an error in which two different bits in binary data are flipped from their original values to opposite values at the same time. Compared with single-bit errors, double-bit errors have a lower probability of occurrence, and the hardware complexity, area, power consumption and delay required for error correction will be higher. Therefore, in the embodiments of the present application, only single-bit errors can be corrected.

[0112] For example, if the original data stored at the first address is 0101_0101, and the check code is 10101, if D0 and D1 are flipped at the same time, the read data can become 0101_0110, and the check code is still 10101. Assuming that the memory calculates the accompanying formula as 01100, which is not 0, and there are an even number of 1s, it is confirmed as a double-bit error, and the memory will not correct it. Instead, the read data, i.e., 0101_0110, is directly output to the processor. At the same time, the memory sets the values of the first error identification bit and the third error identification bit to 1, i.e., the first preset value. The processor queries the values of the two error identification bits from the register and determines that there is a double-bit error in the data output by the memory.

[0113] It can be understood that in the embodiments of the present application, when there is a more serious double-bit error in the data, the memory can detect the double-bit error in time and report it to the processor even if it does not correct it, so that the processor can process the error in time through higher-level fault tolerance techniques.

[0114] In some embodiments of the present application, Figure 2 The step 104 of outputting the data to the processor based on the check result, is further implemented by: returning the data to the processor when the check result represents that there is no error in the data; and setting the value of the first error indication bit, the value of the second error indication bit, and the value of the third error indication bit to the second preset value representing that there is no error.

[0115] If the check result represents that there is no error in the data, the memory directly outputs the data to the processor, and at the same time, sets the values of all error identification bits in the register to a second preset value representing no error, for example, to 0, so that the processor can determine that the current data has no error by querying the values of the error identification bits in the register.

[0116] It can be understood that in the embodiments of the present application, when the memory determines that there is no error in the data, it directly outputs the data and sets all error identification bits to a second preset value representing no error, to inform the processor that there is no error in the current data.

[0117] It can be understood that, compared with the related art, which either performs data checking on the entire RAM chip of the memory through the check code, or does not perform data checking on the entire RAM chip, thereby resulting in a low degree of flexibility of data checking when reading data from the memory, in the embodiments of the present application, the RAM chip is divided into a plurality of storage regions, and the data checking function can be independently enabled or disabled for each storage region through the value of the state identification bit corresponding to each storage region, so that in the data reading process, the memory can first determine a first target region from the plurality of storage regions according to a first address specified by a data reading instruction, and then determine whether the data checking function of the first target region is enabled by querying the value of the first state identification bit of the first target region. Only when the data checking function is enabled, the data is checked by using the check code read from the first address, and then the data is output to the processor in combination with the check result, so that it can be determined whether to start data checking on demand, thereby improving the degree of flexibility of data checking when reading data while ensuring data reliability.

[0118] Based on Figure 2 , referring to Figure 4 , Figure 4 is a flowchart of a data reading method of a memory provided by the embodiments of the present application Figure Three .In some embodiments of the present application, after step 102 in Figure 2 , that is, after querying the value of the first state identification bit of the first target region, the method further includes the following processing:

[0119] Step 105, when the value of the first state identification bit represents that the data checking of the first target region is not enabled, reading the data from the first address and outputting the data to the processor.

[0120] The memory queries the value of the first state identification bit from the register, and when it is determined that the value of the first state identification bit represents that the data checking of the first target region is not enabled, the memory directly reads the data from the first address and outputs the read data to the processor.

[0121] It should be noted that, in order to facilitate the uniformity of the data writing process, the memory will also synchronously write the check code in the storage area in which the data check function is not enabled, so that in the embodiment of the application, the check code of the data can be stored in the first address of the memory, and the memory will also read the check code when reading the data from the first address, but the memory will not use the check code for any processing.

[0122] It can be understood that, in the embodiment of the application, the memory will not perform any processing on the data read out from the first address when the data check function of the first target area is not enabled, and directly output the data to the processor, so that the flexibility of whether to enable the data check function for different storage areas can be realized, thereby improving the flexibility of data check when reading data.

[0123] Next, the data writing method of the memory provided by the embodiment of the application will be described in combination with an exemplary application and implementation of the memory provided by the embodiment of the application.

[0124] Referring to Figure 5 , Figure 5 is a flowchart of the data writing method of the memory provided by the embodiment of the application Figure One , the steps shown in Figure 5 will be described.

[0125] It should be noted that the memory includes a RAM chip, i.e., a Random Access Memory chip, and the RAM chip includes a plurality of storage areas, each of which can be regarded as a part of the RAM chip, which is obtained by dividing the address interval of the RAM chip, so that the storage area can be regarded as a logical address interval. The memory can also include a register, which is used to store some information needed in data writing.

[0126] In step 201, in response to a data writing instruction of a processor, a second target area in which a second address in the data writing instruction is located is determined from a plurality of storage areas based on a plurality of address intervals of the plurality of storage areas.

[0127] When the processor needs to write data into the memory, the processor will first generate a data writing instruction, specify the address of the data to be written, i.e., the second address, in the data writing instruction, and then send the data writing instruction to the memory. The memory analyzes the data writing instruction to obtain the second address, and obtains the address interval of each storage area, and then compares the second address with the address interval of each storage area to determine the storage area in which the second address is located, and takes the storage area as the second target area.

[0128] It should be noted that in the embodiments of the present application, the address interval of the plurality of storage areas can be stored in a register in the memory, so that the memory can obtain the address interval of each storage area from the register. The memory can compare the second address with the address interval and the start address and the end address to determine whether the read address falls within the address interval.

[0129] Step 202, query the value of the second state identification bit of the second target area.

[0130] After determining the second target area where the second address is located, the memory will query the value of the state identification bit for the second target area from the values of the state identification bits of all storage areas, to obtain the value of the second state identification bit, so as to determine whether the second target area has enabled the error correction function through the value of the second state identification bit. In other words, the value of the second state identification bit represents whether the second target area has enabled the data check function.

[0131] It should be noted that the state identification bit is a binary bit of a register stored in the memory, and its value is used to identify whether the corresponding storage area has enabled the data check function. Here, each storage area has its corresponding state identification bit, so that the register has a plurality of state identification bits corresponding to the plurality of storage areas, respectively, to represent whether the plurality of storage areas have enabled the data check function.

[0132] In other words, in the embodiments of the present application, the RAM chip can be divided into a plurality of storage areas by the processor, and the enabling of the data check function of each storage area can be controlled individually, that is, some storage areas can enable the data check function, while other storage areas do not enable the data check function. The change of the enabling state of the data check function can be controlled by the processor by modifying the value of the corresponding state identification bit.

[0133] Step 203, when the value of the second state identification bit represents that the second target area has enabled the data check function, generate a check code for the data in the data write instruction.

[0134] When the memory determines that the second target area has enabled the data check function, it will generate a corresponding check code for the data through a check equation defined in a commonly used encoding method. Here, the encoding method can be Hamming code or extended Hamming code.

[0135] Step 204, write the data and the check code at the second address.

[0136] The memory writes the data and the check code into the first address after obtaining the check code of the data. It should be noted that if the bit width of the input interface of the memory is even, and the sum of the bit width of the data and the bit width of the check code is odd, the memory also adds redundant bits to the data and the check code, and writes the data, the check code and the redundant bits into the second address.

[0137] It can be understood that, compared with the related art, in the embodiments of the present application, the data of the entire RAM chip of the memory is checked by the check code, or the data of the entire RAM chip is not checked, thereby causing the problem of low flexibility of data checking when reading data from the memory. In the embodiments of the present application, the RAM chip is divided into a plurality of storage areas, and the data checking function can be independently enabled or disabled for each storage area according to the value of the state identification bit corresponding to each storage area. When data is written, the second target area where the second address specified by the data write instruction is located is first determined from the plurality of storage areas. Only when the data checking function of the second target area is enabled, the check code is generated and written into the second address for the data carried in the data write instruction, so as to subsequently check the data according to the check code. In this way, it can be determined whether to start data checking on demand, thereby improving the flexibility of data checking when reading data while ensuring data reliability.

[0138] Based on Figure 5 , see Figure 6 , Figure 6 is a flowchart of a data write method of a memory provided by the embodiments of the present application Figure Two In some embodiments of the present application, after step 202 in Figure 5 , that is, after querying the value of the second state identification bit of the second target area, the scheme can further include the following processing:

[0139] Step 205, when the value of the second state identification bit represents that the data checking function of the second target area is not enabled, write the data into the second address.

[0140] The memory queries the value of the second state identification bit from the register, and determines that it represents that the data checking function of the second target area is not enabled. Then, the data in the data write instruction is directly written into the second address, thereby completing the data write.

[0141] It should be noted that when there are data bits for storing the check code in the memory (which can be determined in the design stage of the memory), the memory can generate certain redundancy for these data bits, for example, all 0, and then write these data and the generated redundancy to the second address. Of course, the memory can generate a check code for the data by default and write it to the second address, but in the subsequent data reading process, the check code can not be used.

[0142] It can be understood that in the embodiments of the present application, the memory can directly write data into the second address when it is determined that the second target area does not enable the data check function, thereby realizing the implementation of data check according to the needs of the region and improving the flexibility of data check.

[0143] In the following, an exemplary application of the embodiments of the present application in an actual application scenario will be described.

[0144] The memory in the embodiments of the present application is used to store data in the artificial intelligence operation process. The processor needs to write data to the static random access memory (SRAM) and read data from the SRAM (referred to as RAM chip) when performing artificial intelligence operation. The data reading method and data writing method of the embodiments of the present application are also applicable in other scenarios, such as industrial automation scenarios, smart home scenarios, etc.

[0145] In the related art, data is directly written into the SRAM. At this time, if individual bit data of the SRAM occurs error, it will cause the system to be unable to be normally used.

[0146] In the embodiments of the present application, the data that needs to be written into the SRAM is calculated to increase the corresponding error correction code (referred to as check code), and then the data and the error correction code are written into the SRAM. When reading, the actual data and the corresponding error correction code are read out, and through the error correction code, error correction and error detection are realized. At the same time, according to the needs, the SRAM can be divided into multiple regions (referred to as storage regions) in advance, and the regions to which the error correction technology (referred to as data check function) can be applied are specified. If there is a 1-bit error (referred to as single-bit error) in the region (referred to as the first target region and the second target region) to which the error correction technology is applied when writing and reading data, the 1-bit error can be corrected. If there is a 2-bit error (referred to as double-bit error), it can be reported to the processor; if the writing and reading data are not in the region to which the error correction technology is applied, the normal reading and writing operation is performed.

[0147] That is, first, in the embodiment of the present application, when writing data into the SRAM, the error correction code is added. Referring to Table 1, Table 1 provides the relationship between the data information width, the error correction code width and the SRAM data actual width. If 128-bit wide information is written, 9-bit error correction code can be added, and a total of 137-bit information is obtained, which is written into the SRAM together. When reading data from the SRAM, 137-bit information is read out, and if there is 1-bit error, it will be corrected directly.

[0148] Table 1

[0149]

[0150] Figure 7 is a schematic diagram of the data writing process and the data reading process provided by the embodiment of the present application. The SRAM controller (referred to as the memory) 7-1 includes the SRAM 7-11 (referred to as the RAM chip), the error correction control module 7-12 and the register 7-13, wherein the error correction control module 7-12 includes the encoder 7-121, the decoder 7-122 and the region judgment unit 7-123. If the bit width of the written data is 128 bits, represented as [127:0], in the data writing process, the encoder 7-121 first adds 9-bit error correction code to the written data, and 1-bit redundancy (since the number of SRAM ports is an even number of bits, 1-bit redundancy needs to be added), and finally 138-bit information is written into the SRAM, represented as [137:0]. In the reading process, the region judgment unit 7-123 reads the addresses of each region from the register 7-123, determines the region (referred to as the first target region) where the address (referred to as the first address) of the data to be read is located according to the address interval of each region, and then queries the enable state of the error correction technology of the region from the register 7-123. If it is enabled, the decoder 7-122 uses the 9-bit error correction code in the 138 bits read from the SRAM to correct and detect errors for the 128-bit data, and outputs to the processor.

[0151] In the embodiment of the present application, the error correction code is transmitted after the data, so that the data bit width is widened. Figure 8 is a schematic diagram of the data bit width during data transmission provided by the embodiment of the present application, referring to Figure 8 During transmission, n-bit data, i.e. D0 to Dn-1, is spliced with k-bit error correction code, i.e. P0 to Pk-1, for transmission, resulting in a wider bit width.

[0152] The generation of the error correction code is calculated according to the n-bit data. For example, 8-bit data can be calculated to obtain 5-bit error correction code, and the calculation process of each bit is shown in formula (1) to formula (5):

[0153] P0= ~(D0^D1^D3^D5)(1)

[0154] P1= ~(D0^D1^D2^D4^D6)(2)

[0155] P2= ~(D0^D2^D3^D4^D7)(3)

[0156] P3= ~(D1^D2^D5^D6^D7)(4)

[0157] P4= ~(D3^D4^D5^D6^D7)(5)

[0158] Thus, the format of the data when transmitted is as shown in Figure 9 Figure 9 The transmission format diagram of 8-bit data and 5-bit error correction code provided by the embodiment of the application can be seen that, when transmitted, the 8-bit data, i.e., D0 to D7, and the 5-bit error correction code, i.e., P0 to P4, are spliced together for transmission, resulting in a bit width of 13.

[0159] When reading the data, the decoder reads 13-bit information from the SRAM, wherein the first 8 bits are data and the last 5 bits are error correction code. The decoder generates the syndrome dec_parity[4:0] according to the 13-bit information, and the process is as shown in equations (6) to (10):

[0160] dec_parity[0]= ~(D0^D1^D3^D5^D8)(6)

[0161] dec_parity[1]= ~(D0^D1^D2^D4^D6^D9)(7)

[0162] dec_parity[2]= ~(D0^D2^D3^D4^D7^D10)(8)

[0163] dec_parity[3]= ~(D1^D2^D5^D6^D7^D11)(9)

[0164] dec_parity[4]= ~(D3^D4^D5^D6^D7^D12)(10)

[0165] Then, according to the syndrome dec_parity[4:0], the judgment of equations (11) to (13) is performed to determine whether the data has an error and the type of the error.

[0166] error = dec_parity[4:0]!=0(11)​

[0167] single_err = (dec_parity[4:0]!=0)&&(^dec_parity[4:0]) (12)

[0168] double_err = (dec_parity[4:0]!=0)&&(~^dec_parity[4:0]) (13)

[0169] Wherein, error represents error, single_err is 1-bit error, and double_err is 2-bit error.

[0170] If 1-bit error occurs, it can also be determined which bit in 8-bit data has error according to the decimal value of the accompanying formula. For example, if the decimal value of the accompanying formula is 7, it indicates that the 0th bit has error, if the decimal value of the accompanying formula is 11, it indicates that the 1st bit has error, if the decimal value of the accompanying formula is 14, it indicates that the 2nd bit has error, if the decimal value of the accompanying formula is 21, it indicates that the 3rd bit has error, if the decimal value of the accompanying formula is 22, it indicates that the 4th bit has error, if the decimal value of the accompanying formula is 25, it indicates that the 5th bit has error, if the decimal value of the accompanying formula is 26, it indicates that the 6th bit has error, and if the decimal value of the accompanying formula is 28, it indicates that the 7th bit has error.

[0171] Before data writing and data reading, the processor can divide the SRAM into multiple regions, and specify which regions use error correction technology and which regions do not use error correction technology.

[0172] For example, Figure 10 is a schematic diagram of region division of the SRAM provided by the embodiment of the application. It is assumed that the processor divides the SRAM into 8 regions, which are region 0 to region 7, and the processor specifies that region 0, region 3 and region 6 use error correction technology, and other regions do not use error correction technology.

[0173] Table 2 is a schematic of the main ports of the embodiment of the application.

[0174] Table 2

[0175]

[0176] Table 3 is an example of the register of the embodiment of the application, which is taken as an example that the SRAM is divided into 8 regions.

[0177] Table 3

[0178]

[0179] The following is an example of a specific implementation of the embodiments of the application, taking SRAM as 128 bits.

[0180] In the embodiments of the application, the SRAM with a depth of 16M ((0x0~0x00ff_ffff) is divided into 8 regions, and the addresses thereof are configured as: sec_adr0_s = 0x0000_0000, sec_adr0_p = 0x001f_ffff; sec_adr1_s = 0x0020_0000, sec_adr1_p = 0x003f_ffff; sec_adr2_s = 0x0040_0000, sec_adr2_p = 0x005f_ffff; sec_adr3_s = 0x0060_0000, sec_adr3_p = 0x007f_ffff; sec_adr4_s = 0x0080_0000, sec_adr4_p = 0x009f_ffff; sec_adr5_s = 0x00a0_0000, sec_adr5_p = 0x00bf_ffff; sec_adr6_s = 0x00c0_0000, sec_adr6_p = 0x00df_ffff; sec_adr7_s = 0x00e0_0000, sec_adr7_p = 0x00ff_ffff.

[0181] The processor plans to use error correction technology for 0#, 3# and 6#, and other regions do not use error correction technology. The configuration is as follows: sec_ctrl.sec_addr_ecc_en = 8'b0100_1001, / / bit0 / 3 / 6 enable.

[0182] The enable identification bit of the error correction technology of the SRAM is set to 1: sec_ctrl.sec_ecc_en = 1.

[0183] When writing data into the SRAM, an error correction code can be generated for each write data and written.

[0184] When reading data from the SRAM, there are three cases:

[0185] a) Normal read operation, no error, i.e. read reg sec_ctrl.sec_ecc_err = 0;

[0186] b) Normal read operation, 1-bit error, but has been corrected, i.e. read reg sec_ctrl.sec_ecc_err = 1, read reg sec_ctrl.sec_sbit_err = 1, read reg sec_ctrl.sec_dbit_err = 0.

[0187] c) Read operation is problematic, 2-bit error, i.e. read reg sec_ctrl.sec_ecc_err = 1, read reg sec_ctrl.sec_sbit_err = 0, read reg sec_ctrl.sec_dbit_err = 1.

[0188] Finally, if the read data has an error, after the error is handled, the clear flag is set, i.e. sec_ctrl.sec_ecc_err_clr = 1, sec_ctrl.sec_sbit_err_clr = 1 and sec_ctrl.sec_dbit_err_clr = 1.

[0189] In this way, not only the data error correction and error detection can be implemented, but also the area using the error correction technology can be flexibly configured, and the flexibility of data verification is improved.

[0190] Next, the storage provided by the embodiments of the present application is described by taking the storage built in the server as an example. Figure 11 is a structure diagram of the storage provided by the embodiments of the present application Figure One , referring to Figure 11 , the storage 210 includes a region judging unit 211, a decoder 212, a RAM chip 213 and a register 214, the RAM chip 213 includes a plurality of storage regions;

[0191] The region judging unit 211 is configured to determine a first target region where a first address in a data read instruction is located from the plurality of storage regions based on a plurality of address intervals of the plurality of storage regions stored in the register 214 in response to the data read instruction of the processor, and query a value of a first state identification bit of the first target region from the register 214, the value of the first state identification bit representing whether the data verification function is enabled for the first target region.

[0192] The decoder 212 is configured to read data and a verification code of the data from the first address when the value of the first state identification bit represents that the data verification function is enabled for the first target region, verify the data by using the verification code to obtain a verification result, and output the data to the processor based on the verification result.

[0193] a RAM chip 213, configured to store data and a check code;

[0194] a register 214, configured to store a plurality of address intervals of a plurality of storage areas, and a value of a first state identification bit of a first target area.

[0195] It should be noted that the area determining unit 211 in the above embodiment can be implemented by a hardware circuit structure, for example, an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) circuit. The RAM chip 213 can be implemented as an SRAM chip or a DRAM chip. The register 214 can be implemented as a latch or a D flip-flop. The decoder 212 can be implemented as an ASIC circuit or an FPGA circuit.

[0196] In some embodiments, the decoder 212 is further configured to determine a syndrome based on the data and the check code, and check an error in the data based on the syndrome to obtain the check result.

[0197] In some embodiments, the register 214 further stores a value of a first error identification bit and a value of a second error identification bit.

[0198] The decoder 212 is further configured to perform error correction on a single-bit error in the data when the check result indicates that the data has a single-bit error, and output the data after error correction to the processor; and set the value of the first error identification bit and the value of the second error identification bit in the register 214 to a first preset value indicating that there is an error, where the first error identification bit is used to indicate whether the data has an error, and the second error identification bit is used to indicate whether the data has a single-bit error.

[0199] In some embodiments, the register 214 further stores a value of a first error identification bit and a value of a third error identification bit.

[0200] The decoder 212 is further configured to output the data to the processor when the check result indicates that the data has a double-bit error, and set the value of the first error identification bit and the value of the third error identification bit in the register 214 to the first preset value indicating that there is an error, where the third error identification bit is used to indicate whether the data has a double-bit error.

[0201] In some embodiments, the register 214 further stores a value of a first error identification bit, a value of a second error identification bit, and a value of a third error identification bit.

[0202] The decoder 212 is further configured to output the data to the processor when the check result represents that there is no error in the data; and set values of the first error indication bit, the second error indication bit and the third error indication bit in the register 214 as a second preset value representing no error.

[0203] In some embodiments, the decoder 212 is further configured to read the data from the first address and output the data to the processor when the value of the first state identification bit represents that the data check is not enabled in the second target region.

[0204] In some embodiments, the plurality of storage regions are divided by the processor from the RAM chip 213, and the plurality of address intervals of the plurality of storage regions are generated by the processor; and

[0205] The value of the first state identification bit in the register 214 is generated by the processor.

[0206] Figure 12 is a structure of a memory provided by an embodiment of the present application Figure Two , see Figure 12 The memory 210 includes a region determination unit 211, an encoder 215, a RAM chip 213 and a register 214, and the RAM chip 213 includes a plurality of storage regions.

[0207] The region determination unit 211 is configured to determine, in response to a data write instruction of a processor, a second target region in which a second address in the data write instruction is located from a plurality of storage regions based on a plurality of address intervals of a plurality of storage regions stored in the register 214; and query a value of a second state identification bit of the second target region from the register 214, where the value of the second state identification bit represents whether the data check function is enabled in the second target region.

[0208] The encoder 215 is configured to generate a check code for data in the data write instruction when the value of the second state identification bit represents that the data check function is enabled in the second target region; and write the data and the check code at the second address.

[0209] The RAM chip 213 is configured to store data and check codes.

[0210] The register 214 is configured to store a plurality of address intervals of a plurality of storage regions and a value of a second state identification bit of a second target region.

[0211] It should be noted that the area judging unit 211 in the above description can be implemented by a hardware circuit structure, for example, as an Application-Specific Integrated Circuit (ASIC) or as a Field Programmable Gate Array (FPGA) circuit; the RAM chip 213 can be implemented as an SRAM chip or as a DRAM chip. The register 214 can be implemented as a latch or as a D flip-flop; and the encoder 215 can be implemented as an ASIC circuit or as an FPGA circuit.

[0212] In some embodiments, the encoder 215 is further configured to write the data to the second address when the value of the second status identification bit indicates that the data check function is not enabled for the second target area.

[0213] The above merely provides an example of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, and improvement within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reading data from a memory, characterized in that, The memory includes a RAM chip, the RAM chip includes multiple storage areas, and the method includes: In response to a data read instruction from the processor, based on multiple address ranges of the multiple storage regions, a first target region containing the first address in the data read instruction is determined from the multiple storage regions; Query the value of the first status flag bit of the first target area. The value of the first status flag bit indicates whether the data verification function is enabled in the first target area. When the value of the first status flag indicates that the data verification function is enabled in the first target area, data is read from the first address, along with the verification code of the data. The data is verified using the verification code to obtain a verification result, and the data is output to the processor based on the verification result.

2. The method according to claim 1, characterized in that, The step of verifying the data using the verification code to obtain a verification result includes: Based on the data and the checksum, determine the syndrome; Based on the aforementioned syndrome, errors in the data are verified to obtain the verification result.

3. The method according to claim 1 or 2, characterized in that, The step of outputting data to the processor based on the verification result includes: When the verification result indicates that the data has a single-bit error, the single-bit error in the data is corrected, and the corrected data is output to the processor; The values ​​of the first error flag bit and the second error flag bit are both set to a first preset value that indicates the presence of an error. The first error flag bit is used to indicate whether there is an error in the data, and the second error flag bit is used to indicate whether there is a single-bit error in the data.

4. The method according to claim 1 or 2, characterized in that, The step of outputting data to the processor based on the verification result includes: When the verification result indicates that the data has a double-bit error, the data is output to the processor; The values ​​of the first error flag bit and the third error flag bit are both set to a first preset value that indicates the presence of an error, wherein the third error flag bit is used to indicate whether there is a double-bit error in the data.

5. The method according to claim 1 or 2, characterized in that, The step of outputting data to the processor based on the verification result includes: When the verification result indicates that the data is error-free, the data is output to the processor; The values ​​of the first error indicator bit, the second error indicator bit, and the third error indicator bit are all set to a second preset value that indicates that no error exists.

6. The method according to claim 1 or 2, characterized in that, After querying the value of the first status flag bit of the first target region, the method further includes: When the value of the first status flag indicates that the data verification is not enabled in the first target area, the data is read from the first address and the data is output to the processor.

7. The method according to claim 1, characterized in that, The plurality of storage regions are obtained by the processor dividing the RAM chip, and the plurality of address ranges of the plurality of storage regions are generated by the processor; The value of the first status flag bit is generated by the processor.

8. A memory, characterized in that, The memory includes: a region determination unit, a decoder, a RAM chip, and a register, wherein the RAM chip includes multiple storage regions; The region determination unit is configured to respond to a data read instruction from the processor, and based on multiple address ranges of multiple storage regions stored in the register, determine the first target region where the first address in the data read instruction is located from the multiple storage regions; and query the value of the first status flag bit of the first target region from the register, wherein the value of the first status flag bit indicates whether the data verification function is enabled in the first target region. The decoder is configured to read data from the first address and the checksum of the data when the value of the first status flag indicates that the data verification function is enabled in the first target area; and to verify the data using the checksum to obtain a verification result, and to output data to the processor based on the verification result. The RAM chip is used to store data and checksums; The register is used to store multiple address ranges of multiple storage regions, as well as the value of the first status flag bit of the first target region.

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