Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. In one aspect, a semiconductor stack having alternating first and second semiconductor layers is formed over a substrate; patterning the semiconductor stack and the substrate to form a semiconductor fin having a semiconductor stack portion over the base portion; depositing an isolation layer over the semiconductor fins; recessing the isolation layer to form an isolation structure surrounding a base portion of the semiconductor fin; depositing a hard mask layer over the semiconductor fin and the isolation structure, the hard mask layer including a bottom portion on the isolation structure, sidewall portions on sidewalls of the semiconductor fin, and a top portion on a top surface of the semiconductor fin; performing a first etching process so that the top part of the hard mask layer is partially recessed; a second etch process is performed to planarize a bottom portion of the hard mask layer to form a hard mask structure having a planarized top surface over the isolation structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device with an isolation structure having a shield protection and a method for forming the same. Background Technology

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuous trend in the semiconductor industry towards the development of low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby increasing production efficiency and reducing associated costs. However, this size reduction increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require corresponding advancements in semiconductor manufacturing processes and technologies.

[0003] As technology nodes shrink, the risk of unwanted coupling between semiconductor active regions and / or semiconductor device components increases. This unwanted coupling leads to capacitance degradation, leakage current, and reduced electrical performance. To address this, isolation structures, such as shallow trench isolation (STI) structures, are formed between active regions (e.g., between finned active regions) to achieve proper isolation. However, STI structures can be damaged during semiconductor manufacturing, resulting in STI loss. For gate-all-around (GAA) transistor devices, STI losses can expose doped portions of the substrate sidewalls. Consequently, when a metal gate structure is formed over the active regions, it becomes electrically coupled to the exposed doped portions of the substrate. This coupling generates parasitic capacitance and / or current leakage, reducing the device's effective capacitance and causing degraded electrical performance. Furthermore, STI losses can lead to unwanted merging of source / drain epitaxial components, resulting in device defects.

[0004] Therefore, while existing methods for forming isolation structures are generally sufficient to meet their intended purposes, they are not entirely satisfactory in every respect. Summary of the Invention

[0005] Some embodiments of this disclosure provide a method for forming a semiconductor device. This method includes forming a semiconductor stack having alternating first and second semiconductor layers over a substrate; patterning the semiconductor stack and the substrate to form a semiconductor fin having a semiconductor stack portion over a base portion; depositing an isolation layer over the semiconductor fin; recessing the isolation layer to form an isolation structure surrounding the base portion of the semiconductor fin; depositing a hard mask layer over the semiconductor fin and the isolation structure, the hard mask layer including a bottom portion disposed on the isolation structure, a sidewall portion disposed on a sidewall of the semiconductor fin, and a top portion disposed on a top surface of the semiconductor fin; performing a first etching process to recess the top portion of the hard mask layer; and performing a second etching process to planarize the bottom portion of the hard mask layer, thereby forming a hard mask structure having a planarized top surface over the isolation structure.

[0006] Some embodiments of this disclosure provide another method for forming a semiconductor device. This method includes receiving a workpiece having semiconductor fins, the semiconductor fins having alternating first and second semiconductor layers, wherein the semiconductor fins are disposed above a protrusion of a substrate; forming a shallow trench isolation (STI) structure above the substrate, the shallow trench isolation structure surrounding the protrusion of the substrate; forming a hard mask structure having a planarized top surface above the shallow trench isolation structure, wherein the planarized top surface is lower than the top surface of the protrusion of the substrate, wherein the hard mask structure is thinner than the shallow trench isolation structure, and the hard mask structure and the shallow trench isolation structure comprise different dielectric materials; forming a dummy area above the channel region of the semiconductor fins and above the hard mask structure. The process involves: placing a gate; forming a source / drain trench adjacent to the aforementioned channel region to expose the side surface of the aforementioned semiconductor fin; replacing the aforementioned second semiconductor layer with an interposer layer, wherein the interposer layer includes a dielectric material identical to that of the aforementioned shallow trench isolation structure; epitaxially growing source / drain components in the aforementioned source / drain trench; forming an inter-dielectric layer (ILD) above the aforementioned source / drain components; removing the aforementioned dummy gate to expose the aforementioned semiconductor fin; selectively etching away the aforementioned interposer layer to form suspended semiconductor channels, while the aforementioned hard mask structure protects the aforementioned shallow trench isolation structure from etching; and forming a metal gate structure above the aforementioned channel region, wherein the aforementioned metal gate structure covers each of the aforementioned suspended semiconductor channels.

[0007] Some embodiments of this disclosure also provide a semiconductor device. This semiconductor device includes a semiconductor channel stack disposed over a protrusion of a substrate; an isolation structure located over the substrate and surrounding the protrusion of the substrate; and a metal gate structure located over the isolation structure, the metal gate structure surrounding each semiconductor channel in the semiconductor channel stack, wherein the isolation structure includes a shallow trench isolation layer and a hard mask layer above the shallow trench isolation layer, wherein the shallow trench isolation layer includes silicon oxide, and the hard mask layer includes silicon nitride, wherein the shallow trench isolation layer is thicker than the hard mask layer. Attached Figure Description

[0008] Figure 1 A flowchart is shown illustrating a method for forming a semiconductor device having a hard mask structure over an isolation structure, according to part or all of an embodiment of the present disclosure.

[0009] Figures 2-11 It shows that according to Figure 1 A cross-sectional schematic diagram of a semiconductor device manufactured and processed using various methods and multiple intermediate stages in the process.

[0010] Figure 10A and Figure 10B The following are cross-sectional schematic diagrams showing the hard mask adjustment considerations of a semiconductor device according to embodiments of the present disclosure when a hard mask structure is formed over an isolation structure.

[0011] Figure 12 A flowchart is shown of a method for forming a semiconductor device having a hard mask structure over part or all of an isolation structure, according to an embodiment of the present disclosure.

[0012] Figure 13 A three-dimensional schematic diagram of a semiconductor workpiece is shown. This semiconductor workpiece has a hard mask structure located above an isolation structure and has lines A-A', B-B' and C-C' that cross the semiconductor workpiece.

[0013] Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A An embodiment according to the present disclosure is shown, based on Figure 12 The method, along Figure 13 A schematic cross-sectional view of a semiconductor device cut along line A-A' at an intermediate stage of manufacturing and process.

[0014] Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B An embodiment according to the present disclosure is shown, based on Figure 12 The method, along Figure 13 A schematic cross-sectional view of a semiconductor device cut by line B-B' at an intermediate stage of manufacturing and process.

[0015] Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C An embodiment according to the present disclosure is shown, based on Figure 12 The method, along Figure 13 A schematic cross-sectional view of a semiconductor device cut with a C-C' line at an intermediate stage of manufacturing and process.

[0016] The reference numerals in the attached figures are explained as follows:

[0017] 100, 1000: Method

[0018] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016: Step 200: Semiconductor Device

[0019] 202: Base

[0020] 202a: Highlighted section

[0021] 204: Semiconductor Stacking

[0022] 204a: First semiconductor layer

[0023] 204b: Second semiconductor layer

[0024] 205: Intermediary Layer

[0025] 206: Isolation Structure

[0026] 207: Hard Mask Structure

[0027] 208: Dummy Gate Structure

[0028] 209: Dummy Gate Stack

[0029] 211: Gate spacer

[0030] 212: Source / Drain Trench

[0031] 214: Semiconductor stacking section

[0032] 215: Semiconductor fin

[0033] 216: Internal spacers

[0034] 240: Suspended Semiconductor Channel (Semiconductor Channel)

[0035] 250: Semiconductor workpiece (workpiece)

[0036] 275: Gate Trench

[0037] 303: Sacrificial Dielectric Layer

[0038] 306: Isolation layer

[0039] 307: Hard mask layer

[0040] 307a: Bottom section

[0041] 307b: Sidewall portion

[0042] 307c: Top section

[0043] 308: Metal gate structure

[0044] 800: Epitaxial source / drain device (source / drain device)

[0045] 900: Interlayer dielectric layer

[0046] h1: Height

[0047] t1, t2, t3, t4, t5, t6: Thickness

[0048] w1: Width of the slice

[0049] w2: Top width

[0050] w3: Pitch width

[0051] CR: Channel Area

[0052] SDR: Source / Drain Region

[0053] A-A', B-B', C-C': Lines Detailed Implementation

[0054] The following provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the following description refers to a first component being formed on or located on a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0055] In addition, spatial terms such as "below," "below," "lower," "above," "upper," and other similar terms may be used here to describe the relationship between one element or component and other elements or components as shown in the figure. These spatial terms include not only the orientation shown in the diagram but also the different orientations of the device in use or operation. The device can be rotated arbitrarily (e.g., rotated 90 degrees or turned to other orientations), and the spatial relative descriptions used here can also be interpreted according to the orientation after rotation.

[0056] Furthermore, when using terms such as “about,” “approximately,” “substantially,” or similar to describe a number or a range of values, unless otherwise specified, as will be apparent to a person skilled in the art, this term is used to cover values ​​within a reasonable range of the described value, such as within ±10% of the described value. For example, the term “about 5 nanometers” could cover a size range from 4.5 nanometers to 5.5 nanometers. And when comparing the size or dimensions of one component with another, terms such as “substantially identical,” “substantially the same,” or “similar in size” can be understood as components compared within + / -10%, or other values ​​within the range understood by a person skilled in the art. Moreover, the disclosed dimensions of different components may implicitly disclose the size ratio between the different components.

[0057] This disclosure relates to a semiconductor device with an isolation structure protected by a hard mask. The isolation structure may be a shallow trench isolation (STI) structure with a hard mask layer on top to suppress STI losses during semiconductor fabrication. The hard mask layer is configured to have a planar (or substantially planar) profile, which has advantages over concave and / or convex profiles (as will be explained herein). The hard mask layer is also configured to have a top surface that is exactly below the top surface of the doped substrate. Therefore, the hard mask layer improves the effective capacitance by avoiding coupling between the gate and the substrate. The hard mask layer also allows for efficient removal of the interposer layer when forming the metal gate. The hard mask layer further prevents undesirable coalescing at the epitaxial bottom of the source / drain components.

[0058] To illustrate various aspects of this disclosure, methods for forming a semiconductor device will be discussed below. The embodiments shown in this disclosure are implemented using fully wrapped gate (GAA) field-effect transistors (FETs), but this disclosure is not limited thereto. A fully wrapped gate FET refers to a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding a transistor channel, such as a vertically stacked fully wrapped gate horizontal nanowire or nanosheet MOSFET element. Those skilled in the art will understand that they can use this disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or advantages as the embodiments presented herein.

[0059] Figure 1 A flowchart of a method 100 for forming a semiconductor device having a hard mask structure over an isolation structure, according to part or all of an embodiment of the present disclosure, is shown. Note that the hard mask structure and the isolation structure may be considered as separate components, or they may be considered together as different parts of a larger isolation structure. Figures 2-11 It shows that according to Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 200 manufactured and processed using method 100, involving multiple intermediate stages. For clarity, these figures have been simplified to better understand and present the inventive concept of this disclosure. Other components may be added to the semiconductor device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device 200.

[0060] Semiconductor device 200 may be an integrated circuit (IC) wafer, a system on chip (SoC), or part of the aforementioned wafer, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), fin field-effect transistors (FinFETs), nanosheet field-effect transistors (nanosheet FETs), nanowire field-effect transistors (nanowire FETs), other types of multi-gate field-effect transistors (multi-gate FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), side-diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable devices, or combinations of the aforementioned devices. In some embodiments, the device is placed in a non-volatile memory, such as a non-volatile random access memory (NVRAM), a flash memory, an electronically erasable programmable read-only memory (EEPROM), an electronically programmable read-only memory (EPROM), other suitable memory types, or a combination of the foregoing.

[0061] Reference Figure 2 In step 102 of method 100, the semiconductor device 200 is formed first by forming a semiconductor stack 204 over a substrate 202. The substrate 202 is, for example, a silicon substrate, or a substrate having other materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 202 may be doped with, for example, a p-type dopant of boron or an n-type dopant of phosphorus. In another embodiment, the substrate 202 may be doped with nitrogen for growing a defect-free silicon crystal stack (e.g., semiconductor stack 204) or a defect-free silicon crystal source / drain component (e.g., source / drain component 800 described later). The semiconductor stack 204 is then epitaxially grown over the substrate 202. The semiconductor stack 204 includes alternating first semiconductor layers 204a and second semiconductor layers 204b. The first semiconductor layers 204a have a different material composition than the second semiconductor layers 204b. For example, each first semiconductor layer 204a is made of silicon, and each second semiconductor layer 204b is made of silicon germanium. In this embodiment, the silicon and / or silicon-germanium of the first semiconductor layer 204a and the second semiconductor layer 204b are undoped, while the substrate 202 is doped. For example, the substrate 202 is made of boron-doped silicon, while the first semiconductor layer 204a is made of pure silicon.

[0062] Reference Figure 3In step 104 of method 100, the semiconductor stack 204 and the substrate 202 are patterned to form semiconductor fins 215. Each semiconductor fin 215 includes a protruding portion 202a of the substrate 202 and a semiconductor stack portion 214 of the semiconductor stack 204. The semiconductor fins 215 can be fabricated using a patterning process that includes a lithography process and an etching process. In some embodiments, the lithography process forms a patterned mask layer for covering the area where the semiconductor fins 215 are formed, and the patterned mask layer is used as an etching mask for the etching process to etch exposed portions of the patterned mask layer. The etching process forms grooves for separating and defining the semiconductor fins 215.

[0063] Reference Figure 4 In step 106 of method 100, an isolation layer 306 is deposited over the semiconductor fins 215. The isolation layer 306 is formed on the top surface of the substrate 202, fills the grooves between the semiconductor fins 215, and covers the top surface of the semiconductor fins 215. In other words, the isolation layer 306 is overfilled so that it surrounds all exposed surfaces of the semiconductor fins 215. The isolation layer 306 can be deposited by any suitable deposition process, and the isolation layer 306 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-dielectric-constant dielectric, a combination of the foregoing, and / or other suitable materials. In this embodiment, the isolation layer 306 includes an oxide-based dielectric, such as silicon oxide.

[0064] Reference Figure 5In step 108 of method 100, the isolation layer 306 is recessed to form an isolation structure 206 surrounding the bottom portion (e.g., protrusion 202a) of the semiconductor fin 215. The isolation structure 206 can be formed by first performing chemical mechanical polishing (CMP) to remove excess portions of the isolation layer 306 above the top surface of the semiconductor fin 215. The remaining portions of the isolation layer 306 form isolation regions laterally between the semiconductor fins 215. Next, the isolation regions are recessed in an etching step such that the semiconductor stack portion 214 of the semiconductor fin 215 lies above the top surface of the isolation regions. The resulting isolation regions form the isolation structure 206. In this embodiment, the isolation structure 206 is a shallow trench isolation (STI) structure with an extended groove. As shown, the top surface of the isolation structure 206 is perpendicularly separated from the top surface of the protrusion 202a by a height h1. The height h1 is the thickness of the subsequently formed hard mask layer. In one embodiment, the height h1 is greater than approximately 5 nm. If the height h1 is too small (e.g., less than 5 nm), the subsequently formed hard mask layer risks blocking the bottommost second semiconductor layer 204b. This could result in a defective metal gate forming for the bottommost channel of the later-formed semiconductor device 200. In one embodiment, the height h1 is greater than (or equal to) the thickness of either the first semiconductor layer 204a or the second semiconductor layer 204b.

[0065] Reference Figure 6 In step 110 of method 100, a hard mask layer 307 is deposited over the isolation structure 206. The hard mask layer 307 includes a bottom portion 307a disposed on the isolation structure 206, a sidewall portion 307b disposed on the sidewall of the semiconductor fin 215, and a top portion 307c disposed on the top surface of the semiconductor fin 215. Figure 6 As shown, the thickness of the bottom portion 307a and the top portion 307c along the Z direction is greater than the thickness of the sidewall portion 307b along the Y direction. The bottom portion 307a and the top portion 307c are deposited as top surfaces with raised circular surfaces. These raised circular surfaces provide appropriate geometry for subsequent wet etching steps. As shown, the bottom portion 307a and the top portion 307c can have a thickness t1 greater than the height h1. In one embodiment, the thickness t1 ranges from about 20 nm to about 30 nm. In one embodiment, the top surface of the bottom portion 307a is located between the top surface and the bottom surface of the bottommost second semiconductor layer 204b.

[0066] Still refer to Figure 6A hard mask layer 307 is deposited using chemical vapor deposition (CVD). The hard mask layer 307 has a different material composition than the isolation structure 206 to achieve desired etch selectivity and / or different isolation effects (e.g., protecting the isolation structure 206 from etching in subsequent manufacturing steps). In this embodiment, the hard mask layer 307 comprises a nitride-based dielectric, such as silicon nitride. In some other embodiments, the hard mask layer 307 may comprise silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon carbonitride.

[0067] Reference Figure 7 In step 112 of method 100, a sacrificial dielectric layer 303 is deposited over the hard mask layer 307. The sacrificial dielectric layer 303 is used in a subsequent wet etching process to pattern and fabricate the deposited hard mask layer 307. The sacrificial dielectric layer 303 is subsequently removed. The sacrificial dielectric layer 303 may be a bottom anti-reflective coating (BARC layer). The BARC layer is formed by spin-coating, a process that is less expensive than CVD. In some cases, the BARC layer may comprise a silicon-containing polymer, a carbon-containing polymer, or spin-coated carbon (SOC). In the illustrated embodiment, the sacrificial dielectric layer 303 fills the gaps between the semiconductor fins 215, and the top surface of the sacrificial dielectric layer 303 (e.g., the BARC layer) is higher than the top surface of the top portion 307c of the hard mask layer 307.

[0068] Reference Figure 8 Figure 8 In step 114 of method 100, the top portion of the sacrificial dielectric layer 303 and the top portion 307c of the hard mask layer 307 located on the top surface of the semiconductor fin are etched. In the described embodiment, the top portions 307c of the sacrificial dielectric layer 303 and the hard mask layer 307 are simultaneously and anisotropically etched back (or recessed) to have a reduced height. Step 114 may include performing a dry etching process using nitrogen plasma, hydrogen plasma, argon (Ar), or a combination thereof. In this embodiment, step 114 includes directional plasma etching using NH3 and H2 as plasma etching gases. In this embodiment, because the composition of the sacrificial dielectric layer 303 has different etch selectivity, the sacrificial dielectric layer 303 can be etched back at a greater etch rate than the hard mask layer 307. Accordingly, after step 114, the top portion 307c of the hard mask layer 307 can still be retained, but with a reduced thickness t2.

[0069] Still refer to Figure 8It is important to emphasize that step 114 does not completely remove the top portion 307c. If the top portion 307c were completely removed, subsequent wet etching steps could damage or reduce the thickness of the topmost first semiconductor layer 204a. By retaining the top portion 307c (but with a reduced thickness t2), subsequent wet etching steps will simply remove the remaining top portion 307c without damaging or reducing the thickness of the topmost first semiconductor layer 204a. In embodiments, the thickness t2 is between about 1 nm and about 5 nm. In one embodiment, the thickness t2 is approximately equal to the thickness of the sidewall portion 307b along the y-direction.

[0070] Reference Figure 8 In an alternative embodiment, step 114 may completely remove the top portion 307c. In such an embodiment, the topmost first semiconductor layer 204a may be formed thicker than the remaining first semiconductor layers 204a, taking into account any subsequent etching that would result in a reduction in thickness. In yet another embodiment (as shown), step 114 does not completely remove the top portion 307c, but the formed topmost first semiconductor layer 204a is still thicker than the remaining first semiconductor layers 204a. This embodiment still provides additional protection if the remaining top portion 307c cannot provide sufficient protection during wet etching.

[0071] Reference Figure 9 In step 116 of method 100, the remaining portion of the sacrificial dielectric layer 303 is removed. Figure 9 As shown, the sacrificial dielectric layer 303 can be removed completely and selectively. For example, the sacrificial dielectric layer 303 can be removed by plasma ashing or wet stripping. Plasma ashing or wet stripping can completely remove the sacrificial dielectric layer 303 but does not substantially affect the hard mask layer 307. However, in some embodiments (as shown), the top of the sidewall portion 307b is slightly etched; therefore, the topmost first semiconductor layer 204a may have a slightly exposed top of the sidewall portion.

[0072] Reference Figure 10In step 118 of method 100, a hard mask layer 307 is wet-etched to form a hard mask structure 207 with a planarized surface over the isolation structure 206. In this embodiment, the wet etching includes isotropic wet etching using phosphoric acid (H3PO4) as the etchant. Phosphoric acid has high selectivity for SiN over Si / SiO2, which minimizes damage to the semiconductor stack 204 of the semiconductor fin 215. As shown, this wet etching simultaneously removes both the top portion 307c and the sidewall portion 307b of the hard mask layer 307. Furthermore, the wet etching also simultaneously adjusts the convex profile of the bottom portion 307a to a planar profile. Because the bottom portion 307a has a raised circular top surface, the isotropic wet etching etches the large contact area region (the middle portion of the raised top surface) at a higher etch rate than the small contact area region (the edge portion of the raised top surface). This geometric effect causes the bottom portion 307a to be etched until it forms a planarized top surface. Therefore, a hard mask structure 207 can be formed above the isolation structure 206. In one embodiment, the top surfaces of the hard mask structure 207 and the isolation structure 206 are parallel to each other (or substantially parallel to each other).

[0073] Note that planarizing the bottom portion 307a via wet etching is not a routine process. (See reference...) Figure 10A and Figure 10B If wet etching is not properly adjusted or controlled, the hard mask structure 207 may be formed with a convex profile. Figure 10A ) or concave contour ( Figure 10B Both of these are undesirable shapes. For example, in one example, referencing... Figure 10A If the bottom portion 307a is insufficiently etched due to time or other parameters, the resulting hard mask structure 207 will still have a convex dome surface. This convex dome surface will result in more interposer residue by blocking the bottommost second semiconductor layer 204b. This may lead to the formation of a defective metal gate for the bottommost channel of the subsequently formed semiconductor device 200. In another example, refer to... Figure 10B If the bottom portion 307a is over-etched due to time or other parameters, the resulting hard mask structure 207 will have a concave, rounded top surface. This concave top surface will reduce the isolation and protection effect, which may lead to parasitic capacitive coupling or leakage effects after the metal gate is formed.

[0074] Refer to Figure 10The resulting semiconductor device 200 includes an isolation structure 206 having a thickness t3, a hard mask structure 207 having a thickness t4, a semiconductor stack portion 214 having a thickness t5, a first semiconductor layer 204a and a second semiconductor layer 204b each having a thickness t6, a protruding portion 202a of a substrate 202 having a wafer width w1, a semiconductor fin 215 having a top width w2, and adjacent semiconductor fins 215 having a pitch width w3. In one embodiment, the thickness t3 ranges from about 30 nm to about 100 nm. In one embodiment, the thickness t4 ranges from about 1 nm to about 50 nm. In one embodiment, the thickness t5 ranges from about 5 nm to about 100 nm. In one embodiment, the thickness t6 ranges from about 1 nm to about 20 nm. In one embodiment, the wafer width w1 ranges from about 5 nm to about 200 nm. In one embodiment, the top width w2 ranges from about 2 nm to about 150 nm. Although not shown, the wafer width w1 can be greater than the top width w2 due to the gradually narrowing profile of the semiconductor fin 215. In one embodiment, the pitch width w3 ranges from about 5 nm to about 1 μm.

[0075] Refer to Figure 10 Thickness t3 is greater than thickness t4, such that isolation structure 206 provides most of the isolation between semiconductor fins 215. Thickness t4 only needs to be sufficient to prevent damage or loss to isolation structure 206. In one embodiment, the ratio of thickness t3 to thickness t4 ranges from about 2 to about 30. If the ratio of thickness t3 to thickness t4 is less than 2, the hard mask structure 207 may be too thick, increasing unnecessary manufacturing costs. If the ratio of thickness t3 to thickness t4 is greater than 30, the hard mask structure 207 may be too thin to provide adequate protection for the isolation structure. Note that thickness t4 is close to but less than height h1. In this way, there is sufficient hard mask protection to surround the top of protrusion 202a without blocking the bottommost second semiconductor layer 204b. The difference between thickness t4 and height h1 can be in the range of 1 nm to 5 nm.

[0076] Reference Figure 11 In step 120 of method 100, dummy gate stacks 209 are formed over the semiconductor fin 215 and the hard mask structure 207. As further described below, the dummy gate stacks 209 are formed over the channel region of the semiconductor fin 215. Each dummy gate stack 209 may be made of polysilicon and surrounds the semiconductor stack portion 214 of the semiconductor fin 215. Although not shown, the dummy gate stacks 209 may include various layers, such as dummy gate electrode layers, dummy gate dielectric layers, and / or dummy gate hard mask layers.

[0077] Figure 12 A flowchart of a method 1000 for forming a semiconductor device 200 having a hard mask structure 207 over part or all of an isolation structure 206, according to an embodiment of the present disclosure, is shown. In one embodiment, after method 100 is completed, the semiconductor device 200 at the end of method 100 is received, and processing of the semiconductor device 200 according to method 1000 continues. Reference is made below. Figure 13 , Figures 14A-22A , Figures 14B-22B and Figures 14C-22C Method 1000 is described. For clarity, these figures have been simplified to better understand the inventive concept of this disclosure. Other components may be added to the semiconductor device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device 200.

[0078] Figure 13 A three-dimensional schematic diagram of a semiconductor workpiece 250 is shown. This semiconductor workpiece 250 has a hard mask structure 207 located above the isolation structure 206, and has lines A-A', B-B', and C-C' that cross the semiconductor workpiece 250. The semiconductor workpiece 250 corresponds to the end of method 100 (e.g., at the end of the method). Figure 11 Semiconductor device 200 (shown in the stage). Line A-A' is cut along a semiconductor fin 215 in the X direction and passes through multiple dummy gate structures 208. Line B-B' is cut along multiple source / drain regions (SDRs) in the Y direction. Line C-C' is cut along a dummy gate stack 209 of a dummy gate structure 208 in the Y direction. Figures 14A-22A , Figures 14B-22B and Figures 14C-22C It shows that according to Figure 12 Method 1000, a cross-sectional schematic diagram of a semiconductor device 200 cut along lines A-A', B-B' and C-C' respectively at an intermediate stage of manufacturing and process. Figure 14A , Figure 14B and Figure 14C They are in the same manufacturing stage. Figure 15A , Figure 15B and Figure 15C They are in the same manufacturing stage. Figure 16A , Figure 16B and Figure 16C Those in the same manufacturing stage, and so on.

[0079] Simultaneously refer to Figure 13 and Figures 14A-14CIn step 1002 of method 1000, a workpiece 250 of semiconductor device 200 is received. Workpiece 250 includes a plurality of semiconductor fins 215 having alternating first semiconductor layers 204a and second semiconductor layers 204b, wherein the semiconductor fins 215 extend over an isolation structure assembly above substrate 202. The isolation structure assembly includes an isolation structure 206 and a hard mask structure 207 above the isolation structure 206. Workpiece 250 also includes a dummy gate structure 208 having a dummy gate stack 209 and a gate spacer 211, the gate spacer 211 being formed over the channel region CR of the semiconductor fins 215. The semiconductor fins 215 (also referred to as active regions or fin active regions) extend longitudinally in the X direction, and the dummy gate structure 208 extends longitudinally in the Y direction.

[0080] Reference Figure 14A The channel region CR is the area of ​​the semiconductor fin 215 below the dummy gate stack 209. The source / drain region SDR is the area of ​​the semiconductor fin 215 adjacent to the channel region CR and extends between the dummy gate structures 208. Each dummy gate structure 208 includes a dummy gate stack 209 and gate spacers 211 located on the sidewalls of the dummy gate stack 209. The dummy gate stack 209 may be made of polysilicon, and the gate spacers 211 may be made of silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or other suitable dielectric materials. (Refer to...) Figures 14B-14C Since the dummy gate structure 208 is only disposed above the channel region CR and not above the source / drain region SDR, therefore only Figure 14C A dummy gate stack 209 covering the semiconductor fin 215 is shown. Note that... Figure 14C It shows the corresponding Figure 11 A cross-sectional schematic diagram of the semiconductor device 200.

[0081] Simultaneously refer to Figures 15A-15CIn step 1004 of method 1000, a source / drain trench 212 is formed in the source / drain region SDR adjacent to the channel region CR. The source / drain trench 212 exposes the side surfaces of the remaining portion of the semiconductor fin 215 (i.e., the portion in the channel region CR). The source / drain trench 212 can be formed by a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may include an etchant to remove the first semiconductor layer 204a and the second semiconductor layer 204b individually and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor stack portion 214 while having minimal (or even no) etching of the dummy gate structure 208 (i.e., the dummy gate stack 209 and the gate spacer 211). In some embodiments, a photolithography process is performed to form a patterned mask layer covering the dummy gate structure 208, and this patterned mask layer is used as an etch mask for the etch process when the source / drain trench 212 is formed.

[0082] It is worth noting that, referring to Figure 15B Due to the presence of the hard mask structure 207, the etching process forming the source / drain trench 212 will not damage or destroy the isolation structure 206. In embodiments where the isolation structure 206 comprises silicon oxide and the hard mask structure 207 comprises silicon nitride, a highly selective etchant can be selected to etch either silicon or silicon oxide, but not silicon nitride. The silicon nitride hard mask structure 207 prevents the silicon oxide-containing isolation structure 206 from being etched or damaged when the source / drain region SDR is etched. With the isolation structure 206 intact, the bottoms of the protrusions 202a of adjacent semiconductor fins 215 are prevented from getting too close to each other. If they are too close, undesirable epitaxial merging may occur in subsequent steps when source / drain components are grown on the bottoms of the protrusions 202a.

[0083] Simultaneously refer to Figures 16A-16CIn step 1006 of method 1000, the second semiconductor layer 204b is replaced with an interposer 205. Step 1006 may include etching to completely remove the second semiconductor layer 204b while minimally etching (or even not etching) the first semiconductor layer 204a. The interposer 205 is then formed in the space left by the removed second semiconductor layer 204b. The interposer 205 can be formed by an interposer deposition process and an interposer etching process. For example, an interposer deposition process is performed to fill the source / drain trench 212 with dielectric material. The dielectric material penetrates into the gaps left by the removed second semiconductor layer 204b, thereby filling the gaps. Then, an interposer etching process is performed to selectively etch the dielectric material to form the interposer 205. The interposer etching process may be a dry etching process to remove excess dielectric material in the source / drain trench 212 and outside the channel region CR. In this embodiment, the dielectric material of the interposer 205 is an oxide-based dielectric, such as silicon oxide.

[0084] When the metal gate is formed, the interposer 205 will be removed in the subsequent channel release phase. Note that in other embodiments, the second semiconductor layer 204b is not replaced by the interposer 205. Instead, the second semiconductor layer 204b remains until it is removed in a later channel release phase. For this embodiment, by replacing the second semiconductor layer 204b with the interposer 205, damage to the silicon channel and source / drain components during channel release can be reduced. This is because the interposer 205 can be selectively removed with little or no semiconductor residue (e.g., no SiGe residue), as opposed to directly removing the second semiconductor layer 204b during the channel release phase.

[0085] Simultaneously refer to Figures 17A-17CIn step 1008 of method 1000, an internal spacer 216 adjacent to the interposer 205 is formed in the channel region CR. The internal spacer 216 can be formed by any suitable process. In one embodiment, a side etching process is performed to selectively etch the sidewalls of the interposer 205 without etching (or not substantially etching) the first semiconductor layer 204a. In other words, the side etching process is configured to etch the interposer 205 laterally (e.g., along the X direction), thereby reducing the length of the interposer 205 along the X direction. The side etching process can be performed after the formation of the interposer 205. Alternatively, the side etching process can be performed as part of the formation of the interposer 205. The side etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. After the side etching process, an air gap is formed under each of the first semiconductor layers 204a. The internal spacer 216 is then formed in each air gap. The internal spacers 216 are disposed directly below the gate spacers 211, and they can be substantially perpendicularly aligned with the gate spacers 211 along the Z direction.

[0086] The internal spacer 216 can be formed by a spacer deposition process and a spacer etching process. For example, a spacer deposition process is performed to form a spacer layer over the dummy gate structure 208 and over the components defining the source / drain trench 212 (e.g., the first semiconductor layer 204a, the interposer layer 205, and the substrate 202). This spacer layer partially (and in some embodiments, completely) fills the source / drain trench 212. The spacer deposition process is configured to ensure that the spacer layer can fill the air gaps between the first semiconductor layers 204a below the gate spacer 211 and between the first semiconductor layers 204a and the substrate 202. Then, a spacer etching process is performed to selectively etch the spacer layer to form the internal spacer 216, such as... Figure 17A As shown, the first semiconductor layer 204a, the dummy gate stack 209, and the gate spacer 211 are etched to a minimum (or even none) extent. The spacer layer (and thus the internal spacer 216) comprises a material different from the material of the first semiconductor layer 204a and the gate spacer 211 to achieve desired etch selectivity during the gate spacer etching process. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxynitride). In some embodiments, the spacer layer comprises a low dielectric constant dielectric material.

[0087] Simultaneously refer to Figures 18A-18CIn step 1010 of method 1000, a source / drain component 800 is epitaxially grown in the source / drain trench 212, and the source / drain component 800 is located above the protrusion 202a of the semiconductor fin 215. The source / drain component 800 may include an n-type source / drain component corresponding to an n-type GAA transistor region, or a p-type source / drain component corresponding to a p-type GAA transistor region. The source / drain component 800 may be formed by epitaxial processes using CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that react with the composition of the substrate 202 (or its protrusion 202a) and / or the semiconductor stack portion 214 (in particular, the first semiconductor layer 204a). The epitaxial source / drain component 800 is doped with n-type dopant and / or p-type dopant. In some embodiments, for an n-type GAA transistor, the epitaxial source / drain component 800 comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopant, or combinations thereof (e.g., forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for a p-type GAA transistor, the epitaxial source / drain component 800 comprises silicon-germanium or germanium and may be doped with boron, other p-type dopant, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component).

[0088] In some embodiments, the epitaxial source / drain component 800 includes a material and / or dopants that can achieve desired tensile and / or compressive stresses in the respective channel regions CR. In some embodiments, the source / drain component 800 is doped during deposition by adding dopants to the source material of the epitaxial process (i.e., in-situ doping). In some embodiments, the epitaxial source / drain component 800 is doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) may be performed to activate the dopants in the epitaxial source / drain component 800 and / or other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain regions). In some embodiments, the epitaxial source / drain components 800 are formed in a separate process sequence, which includes, for example, shielding the p-type GAA transistor region when forming the epitaxial source / drain components 800 in the n-type GAA transistor region, and shielding the n-type GAA transistor region when forming the epitaxial source / drain components 800 in the p-type GAA transistor region.

[0089] In some embodiments (not shown), the formed epitaxial source / drain components 800 include more than one epitaxial layer. For example, each source / drain component 800 includes an inner heavily doped layer and an outer lightly doped layer (or multiple layers). In one embodiment, the outer lightly doped layer is first epitaxially grown in the source / drain trench 212 from the side surfaces of the first semiconductor layer 204a and the substrate 202. Then, the inner heavily doped layer is epitaxially grown from the outer lightly doped layer to fill the source / drain trench 212. The source / drain components 800 may be grown to a height above the topmost first semiconductor layer 204a and between the gate spacers 211 of the different dummy gate structures 208. Figure 18B As shown, the source / drain component 800 is grown above the hard mask structure 207 and the isolation structure 206.

[0090] Simultaneously refer to Figures 19A-19C In step 1012 of method 1000, an interlayer dielectric (ILD) layer 900 is formed above the source / drain component 800. For example... Figure 19A As shown, the interlayer dielectric layer 900 also fills the space between adjacent dummy gate structures 208. The interlayer dielectric layer 900 can be formed by deposition processes (e.g., CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable methods, or combinations thereof). In some embodiments, the interlayer dielectric layer 900 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) on the semiconductor device 200 and converting the flowable material into a solid material by suitable techniques such as thermal annealing and / or ultraviolet radiation treatment.

[0091] The interlayer dielectric layer 900 includes a dielectric material, which may include, for example, silicon oxide, silicon nitride, silicon oxynitride, oxides formed from TEOS, PSG, BPSG, low-dielectric-constant dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-dielectric-constant dielectric materials include FSG, carbon-doped silicon oxide, and black diamond (Black) Applied Materials Inc., Santa Clara, California, USA, xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK low dielectric constant dielectric material (Dow Chemical Company, Midland, Michigan, USA), polyimide, other low dielectric constant dielectric materials, or combinations thereof. In the described embodiments, the interlayer dielectric layer 900 is a dielectric layer comprising a low dielectric constant dielectric material (commonly referred to as a low-k dielectric layer). The interlayer dielectric layer 900 may comprise a multilayer structure having a variety of dielectric materials. In some embodiments, a contact etch stop layer (CESL) (not shown) is provided between the interlayer dielectric layer 900 and the hard mask structure 207, the source / drain component 800, and the gate spacer 211. The contact etch stop layer (CESL) comprises a different material from the interlayer dielectric layer 900; for example, the contact etch stop layer (CESL) comprises a dielectric material different from the dielectric material of the interlayer dielectric layer 900. For example, when the interlayer dielectric layer 900 comprises silicon oxide or a low dielectric constant dielectric material, the contact etch stop layer (CESL) comprises silicon and nitrogen, such as silicon nitride or silicon oxynitride. After depositing the interlayer dielectric layer 900 and / or the contact etch stop layer (CESL), a CMP process and / or other planarization processes may be performed until the top portion (or top surface) of the dummy gate stack 209 is reached (exposed).

[0092] Simultaneously refer to Figures 20A-20C and Figures 21A-21C In step 1014 of method 1000, a suspended semiconductor channel 240 is formed by removing the dummy gate stack 209 from the dummy gate structure 208 and removing the interposer layer 205.

[0093] First, such as Figures 20A-20C As shown, in step 1014, the dummy gate stack 209 is removed to expose the channel region CR beneath the dummy gate stack 209. The dummy gate stack 209 can be removed by a suitable etching process, forming a gate trench 275 and exposing the semiconductor stack portion 214. The etching process is designed to use an etchant to selectively remove the dummy gate stack 209. In the embodiment described herein, the etching process completely removes the dummy gate stack 209 to expose the surfaces of the first semiconductor layer 204a and the interposer layer 205 in the YZ plane (see [link to documentation]). Figure 20CThe etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may include alternative etchants used to remove individual layers of the dummy gate stack 209, such as the dummy gate electrode layer, the dummy gate dielectric layer, and / or the dummy hard mask layer. In some embodiments, the etching process is configured to selectively etch the dummy gate stack 209 while minimally (or even not at all) etching other components of the semiconductor device 200 (e.g., the interlayer dielectric layer 900, the gate spacer 211, the first semiconductor layer 204a, and the interposer 205). In some embodiments, a lithography process is performed to form a patterned mask layer covering the interlayer dielectric layer 900 and / or the gate spacer 211, and the patterned mask layer is used as an etching mask for the etching process.

[0094] Then, as Figures 21A-21C As shown, the interposer 205 (exposed in the gate trench 275) is selectively removed from the channel region CR to form a suspended semiconductor channel 240. In other words, the remaining portion of the first semiconductor layer 204a now becomes the suspended semiconductor channel 240. This removal process is also called channel release, and this stage of the manufacturing process may be referred to as the channel release stage. In the described embodiments, the etching process selectively etches the interposer 205 while performing minimal etching (or even no etching) on ​​the first semiconductor layer 204a, and in some embodiments, minimal etching (or even no etching) is performed on the gate spacer 211 and / or the internal spacer 216. Various etching parameters, such as etchant composition, etching temperature, etchant solution concentration, etching time, etching pressure, source power, RF bias, RF bias power, etchant flow rate, other suitable etching parameters, or combinations of the aforementioned etching parameters, can be adjusted to achieve selective etching of the interposer 205. For example, an etchant is selected for the etching process to have a higher etching rate than the material of the first semiconductor layer 204a (in the described embodiment, the material of the first semiconductor layer 204a is, for example, silicon) while etching the material of the interposer 205 (in the described embodiment, the material of the interposer 205 is, for example, silicon oxide) (i.e., the etchant has high etching selectivity relative to the material of the interposer 205). The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof.

[0095] It is worth noting that, referring to Figure 21CBecause of the presence of the hard mask structure 207, the channel release process of etching away the interposer layer 205 will not damage or destroy the isolation structure 206. For example, in this embodiment, both the isolation structure 206 and the interposer layer 205 are made of silicon oxide. Without the hard mask structure 207, the isolation structure 206 would also be etched and damaged or destroyed when the interposer layer 205 is etched away to form the suspended semiconductor channel 240. The hard mask structure 207 ensures the structural integrity of the isolation structure 206, allowing it to provide adequate isolation between the active regions of the fins.

[0096] Simultaneously refer to Figures 22A-22C In step 1016 of method 1000, a metal gate structure 308 is formed above the channel region CR, and the metal gate structure 308 covers each suspended semiconductor channel 240. Although not shown, each metal gate structure 308 may include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer and a high dielectric constant dielectric layer disposed on the interface layer. The gate electrode may include one or more conductive materials, such as a capping layer, a work function metal layer, a barrier layer, a metal fill layer, and / or other suitable conductive material layers. The work function layers (if present) may be the same or different, and may be an n-type work function layer or a p-type work function layer, depending on the type of the corresponding GAA transistor. The gate dielectric layer includes a high dielectric constant dielectric material, such as a material with a dielectric constant greater than silicon oxide (k≈3.9). The gate electrode may be formed by depositing a metal fill layer to fill the remaining portion of the gate trench 275 and located above the gate dielectric layer using a CVD or PVD process. The metal filler layer comprises a suitable conductive material, such as Al, W, and / or Cu. The metal filler layer may additionally or collectively comprise other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. Alternatively, other suitable deposition processes may be used to form the metal filler layer, such as ALD, CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, electroplating, other deposition processes, or combinations thereof.

[0097] A planarization process is performed to remove excess gate material from the semiconductor device 200. For example, a CMP process is performed until the top surface of the interlayer dielectric layer 900 is exposed, such that the top surface of the metal gate structure 308 is substantially coplanar with the top surface of the interlayer dielectric layer 900 after the CMP process. Therefore, the semiconductor device 200 forms a GAA transistor having a metal gate structure 308 surrounding the respective semiconductor channels 240 (which are no longer suspended), wherein the metal gate structure 308 is disposed between the respective semiconductor channels 240 along the Z direction and between the respective epitaxial source / drain components 800 along the X direction. Furthermore, the metal gate structure 308 can be separated from the source / drain components 800 by means of gate spacers 211 and internal spacers 216.

[0098] Reference Figure 22C The metal gate structure 308 is directly disposed on the hard shield structure 207, the top surface of which is slightly lower than the top surface of the protrusion 202a of the substrate 202. The height difference between the top surface of the protrusion 202a and the top surface of the hard shield structure 207 should be small and can be defined by subtracting the previously described thickness t4 from the height h1. This small height difference can be achieved by the isolation structure 206 protected by the hard shield structure 207, so that the metal gate structure 308 can avoid penetrating into the isolation structure 206, which would otherwise lead to undesirable leakage and coupling between the metal gate structure 308 and the protrusion 202a of the substrate 202.

[0099] Method 1000 may include further steps to complete the fabrication of the semiconductor device 200. For example, method 1000 may further include forming source / drain contacts over source / drain components 800, forming gate contacts over metal gate structure 308, and forming an interconnect structure with interconnect metal lines and vias over the source / drain contacts and gate contacts. Additional steps may be provided before, during, and after method 1000. Furthermore, some of the described steps may be replaced or eliminated in other embodiments of method 1000.

[0100] While not limiting, this disclosure provides numerous advantages for semiconductor devices having isolation structures. One exemplary advantage is the formation of a hard mask layer over the isolation structure to protect it from damage. Another exemplary advantage is that the hard mask layer can be adjusted to have a planar profile.

[0101] One aspect of this disclosure relates to a method of forming a semiconductor device. This method includes forming a semiconductor stack having alternating first and second semiconductor layers over a substrate; patterning the semiconductor stack and the substrate to form a semiconductor fin having a semiconductor stack portion above a base portion; depositing an isolation layer over the semiconductor fin; recessing the isolation layer to form an isolation structure surrounding the base portion of the semiconductor fin; depositing a hard mask layer over the semiconductor fin and the isolation structure, the hard mask layer including a bottom portion disposed on the isolation structure, a sidewall portion disposed on a sidewall of the semiconductor fin, and a top portion disposed on a top surface of the semiconductor fin; performing a first etching process to recess the top portion of the hard mask layer; and performing a second etching process to planarize the bottom portion of the hard mask layer, thereby forming a hard mask structure having a planarized top surface over the isolation structure.

[0102] In one embodiment, the aforementioned first etching process includes a dry etching process, and the aforementioned second etching process includes a wet etching process. In another embodiment, the aforementioned dry etching process includes anisotropic plasma etching using ammonia and hydrogen as plasma etching gases. In another embodiment, the aforementioned wet etching process includes isotropic wet etching using phosphoric acid as an etchant.

[0103] In one embodiment, the aforementioned isolation structure includes an oxide-based dielectric, and the aforementioned hard mask layer includes a nitride-based dielectric.

[0104] In one embodiment, one top surface of the aforementioned hard mask structure is lower than the aforementioned semiconductor stack portion of the aforementioned semiconductor fin.

[0105] In one embodiment, the aforementioned first etching process further includes: depositing a sacrificial layer over the aforementioned hard mask layer; and simultaneously dry etching the top portion of the aforementioned sacrificial layer and the aforementioned top portion of the aforementioned hard mask layer, wherein the aforementioned top portion of the aforementioned sacrificial layer is etched until at least the top surface of the aforementioned semiconductor fin is above the top surface of the aforementioned sacrificial layer.

[0106] In one embodiment, the aforementioned sacrificial layer can be deposited by spin coating, and the aforementioned sacrificial layer has a bottom antireflective coating (BARC) layer of a silicon-containing polymer, a carbon-containing polymer, or spin-coated carbon (SOC).

[0107] In one embodiment, the aforementioned second etching process further includes: removing the remaining portion of the aforementioned sacrificial layer to expose the aforementioned sidewall portion and the aforementioned bottom portion of the aforementioned hard mask layer; and wet etching the aforementioned hard mask layer to simultaneously: remove the aforementioned recessed top portion and the aforementioned sidewall portion of the aforementioned hard mask layer, and planarize the aforementioned bottom portion of the aforementioned hard mask layer.

[0108] In one embodiment, removing the aforementioned remaining portion of the sacrificial layer includes performing a plasma ashing or a wet stripping process.

[0109] Another aspect of this disclosure relates to a method of forming a semiconductor device. This method includes receiving a workpiece having semiconductor fins, the semiconductor fins having alternating first and second semiconductor layers, wherein the semiconductor fins are disposed above a protrusion of a substrate; forming a shallow trench isolation (STI) structure above the substrate, the shallow trench isolation structure surrounding the protrusion of the substrate; forming a hard mask structure having a planarized top surface above the shallow trench isolation structure, wherein the planarized top surface is lower than the top surface of the protrusion of the substrate, wherein the hard mask structure is thinner than the shallow trench isolation structure, and the hard mask structure and the shallow trench isolation structure comprise different dielectric materials; forming a virtual [structure] above a channel region of the semiconductor fins and above the hard mask structure. The process involves: placing a gate; forming a source / drain trench adjacent to the aforementioned channel region to expose the side surface of the aforementioned semiconductor fin; replacing the aforementioned second semiconductor layer with an interposer layer, wherein the interposer layer includes a dielectric material identical to that of the aforementioned shallow trench isolation structure; epitaxially growing source / drain components in the aforementioned source / drain trench; forming an inter-dielectric layer (ILD) above the aforementioned source / drain components; removing the aforementioned dummy gate to expose the aforementioned semiconductor fin; selectively etching away the aforementioned interposer layer to form suspended semiconductor channels, while the aforementioned hard mask structure protects the aforementioned shallow trench isolation structure from etching; and forming a metal gate structure above the aforementioned channel region, wherein the aforementioned metal gate structure covers each of the aforementioned suspended semiconductor channels.

[0110] In one embodiment, forming the aforementioned hard mask structure includes: depositing a hard mask layer over the aforementioned semiconductor fin and the aforementioned shallow trench isolation structure, the aforementioned hard mask layer including a bottom portion disposed on the aforementioned shallow trench isolation structure, a sidewall portion disposed on the sidewall of the aforementioned semiconductor fin, and a top portion disposed on the top surface of the aforementioned semiconductor fin; performing a first etching process to recess the aforementioned top portion of the aforementioned hard mask layer; and performing a second etching process to planarize the aforementioned bottom portion of the aforementioned hard mask layer, thereby forming the aforementioned hard mask structure having the aforementioned planarized top surface over the aforementioned shallow trench isolation structure.

[0111] In another embodiment, after the first etching process and before the second etching process, the bottom portion of the hard mask layer has a greater thickness than the top portion of the hard mask layer.

[0112] In another embodiment, prior to the aforementioned second etching process, the aforementioned bottom portion of the aforementioned hard mask layer has a convex dome surface.

[0113] In one embodiment, the aforementioned shallow trench isolation structure includes silicon oxide, and the aforementioned hard mask structure includes silicon nitride, and the thickness ratio of the aforementioned shallow trench isolation structure to the aforementioned hard mask structure is in the range of 2 to 30.

[0114] In one embodiment, the aforementioned suspended semiconductor channel is made of pure silicon, and the aforementioned protruding portion of the aforementioned substrate is made of silicon doped with boron or phosphorus.

[0115] Another aspect of this disclosure relates to a semiconductor device. This semiconductor device includes a semiconductor channel stack disposed over a protrusion of a substrate; an isolation structure located over the substrate and surrounding the protrusion of the substrate; and a metal gate structure located over the isolation structure, the metal gate structure surrounding each semiconductor channel in the semiconductor channel stack, wherein the isolation structure includes a shallow trench isolation layer and a hard mask layer above the shallow trench isolation layer, wherein the shallow trench isolation layer includes silicon oxide, and the hard mask layer includes silicon nitride, wherein the shallow trench isolation layer is thicker than the hard mask layer.

[0116] In one embodiment, each semiconductor channel in the aforementioned semiconductor channel stack is made of pure silicon, and the aforementioned protruding portion of the aforementioned substrate is made of silicon doped with boron or phosphorus.

[0117] In another embodiment, the aforementioned shallow trench isolation layer has a first thickness, the aforementioned hard mask layer has a second thickness, and the ratio of the aforementioned first thickness to the aforementioned second thickness is in the range of 2 to 30.

[0118] In another embodiment, each semiconductor channel in the aforementioned semiconductor channel stack has a third thickness, and the aforementioned second thickness has the same thickness as the aforementioned third thickness.

[0119] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of this disclosure shall be defined by the appended claims.

Claims

1. A method for forming a semiconductor device, comprising: A semiconductor stack having alternating first and second semiconductor layers is formed over a substrate; The semiconductor stack and the substrate are patterned to form a semiconductor fin having a semiconductor stack portion above a base portion; An isolation layer is deposited above the semiconductor fin; The isolation layer is recessed to form an isolation structure surrounding the base portion of the semiconductor fin; A hard mask layer is deposited above the semiconductor fin and above the isolation structure. The hard mask layer includes a bottom portion disposed on the isolation structure, a sidewall portion disposed on the sidewall of the semiconductor fin, and a top portion disposed on the top surface of the semiconductor fin. A first etching process is performed to recess the top portion of the hard mask layer; as well as A second etching process is performed to planarize the bottom portion of the hard mask layer, thereby forming a hard mask structure with a planarized top surface above the isolation structure.

2. The method for forming a semiconductor device as claimed in claim 1, wherein the first etching process includes a dry etching process and the second etching process includes a wet etching process.

3. The method of forming a semiconductor device as claimed in claim 1, wherein the isolation structure comprises an oxide-based dielectric, and the hard mask layer comprises a nitride-based dielectric.

4. The method for forming a semiconductor device as claimed in claim 1, wherein the first etching process further comprises: A sacrificial layer is deposited on top of the hard masking layer; as well as Simultaneously dry-etch the top portion of the sacrificial layer and the top portion of the hard masking layer; The top portion of the sacrificial layer is etched until at least the top surface of the semiconductor fin is above the top surface of the sacrificial layer.

5. The method of forming a semiconductor device as claimed in claim 4, wherein the sacrificial layer is deposited by spin coating, and the sacrificial layer has a bottom anti-reflective coating layer containing a silicon polymer, a carbon polymer, or spin-coated carbon.

6. A method for forming a semiconductor device, comprising: A workpiece having semiconductor fins having alternating first and second semiconductor layers is received, wherein the semiconductor fins are disposed above a protruding portion of a substrate. A shallow trench isolation structure is formed above the substrate, and the shallow trench isolation structure surrounds the protruding portion of the substrate; A hard shield structure with a planarized top surface is formed above the shallow trench isolation structure, wherein the planarized top surface is the top surface of the protruding portion below the substrate, wherein the hard shield structure is thinner than the shallow trench isolation structure, and the hard shield structure and the shallow trench isolation structure comprise different dielectric materials. A dummy gate is formed above the channel region of the semiconductor fin and above the hard mask structure; A source / drain trench is formed adjacent to the channel region, thereby exposing the side surface of the semiconductor fin; The second semiconductor layer is replaced with an interposer layer, wherein the interposer layer comprises a dielectric material identical to that of the shallow trench isolation structure; Source / drain components are epitaxially grown in the source / drain trench; An inter-dielectric layer is formed above the source / drain component; Remove the dummy gate to expose the semiconductor fin; The interposer is selectively etched to form a suspended semiconductor channel, while the hard mask structure protects the shallow trench isolation structure from being etched. as well as A metal gate structure is formed above the channel region, and the metal gate structure covers each of the suspended semiconductor channels.

7. The method of forming a semiconductor device as claimed in claim 6, wherein forming the hard mask structure comprises: A hard mask layer is deposited over the semiconductor fin and the shallow trench isolation structure. The hard mask layer includes a bottom portion disposed on the shallow trench isolation structure, a sidewall portion disposed on the sidewall of the semiconductor fin, and a top portion disposed on the top surface of the semiconductor fin. A first etching process is performed to recess the top portion of the hard mask layer; as well as A second etching process is performed to planarize the bottom portion of the hard mask layer, thereby forming the hard mask structure with the planarized top surface above the shallow trench isolation structure.

8. The method of forming a semiconductor device as claimed in claim 7, wherein after the first etching process and before the second etching process, the bottom portion of the hard mask layer has a greater thickness than the top portion of the hard mask layer.

9. The method of forming a semiconductor device as claimed in claim 6, wherein the shallow trench isolation structure comprises silicon oxide, and the hard mask structure comprises silicon nitride, and the thickness ratio of the shallow trench isolation structure to the hard mask structure is in the range of 2 to 30.

10. A semiconductor device, comprising: A stack of semiconductor channels disposed above a protrusion of a substrate; An isolation structure located above the base and surrounding the protruding portion of the base; as well as A metal gate structure is located above the isolation structure, and the metal gate structure surrounds each semiconductor channel in the semiconductor channel stack. The isolation structure includes a shallow trench isolation layer and a hard masking layer above the shallow trench isolation layer, wherein the shallow trench isolation layer includes silicon oxide and the hard masking layer includes silicon nitride. The shallow trench isolation layer is thicker than the hard masking layer.

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