Stacked packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a stacked packaging structure, a preparation method thereof and electronic equipment. The stacked packaging structure comprises a first circuit carrier plate and a second circuit carrier plate which are oppositely arranged; the first chip is located between the first circuit carrier plate and the second circuit carrier plate, and the first chip is arranged on the first circuit carrier plate and electrically connected with the first circuit carrier plate; the second chip is located between the first circuit carrier plate and the second circuit carrier plate, the second chip is arranged on the second circuit carrier plate and electrically connected with the second circuit carrier plate, the second chip and the first chip are arranged in a stacked mode and connected in a heat conduction mode, and the orthographic projection area of the second chip on the second circuit carrier plate is a chip installation area; and the one or more heat sink structures penetrate through the second circuit carrier plate in the chip mounting area, and the heat sink structures are in heat conduction connection with the second chip. According to the stacked packaging structure, a heat conduction path from the first chip to the heat sink structure can be obtained, and a heat dissipation path can be shortened, so that the heat dissipation performance of the packaging structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a stacked packaging structure, its fabrication method, and electronic devices. Background Technology

[0002] With the development of integrated circuit technology, semiconductor packaging is trending towards high density, multi-functionality, low power consumption, and miniaturization. Therefore, it is necessary to integrate chips with different functions within a single packaging structure and to integrate more chips within a limited space.

[0003] Meanwhile, as chip performance improves with technological advancements, so does power consumption and heat generation. If the chip cannot be cooled in time during operation, it is prone to failure due to overheating.

[0004] Therefore, improving the heat dissipation performance of the packaging structure while integrating more chips has become an urgent problem to be solved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a stacked packaging structure and its preparation method, as well as an electronic device, to improve the heat dissipation performance of the stacked packaging structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a stacked packaging structure, comprising: a first circuit carrier and a second circuit carrier disposed opposite to each other; a first chip located between the first circuit carrier and the second circuit carrier, the first chip being disposed on and electrically connected to the first circuit carrier; a second chip located between the first circuit carrier and the second circuit carrier, the second chip being disposed on and electrically connected to the second circuit carrier, the second chip being stacked with the first chip and thermally connected, the orthogonal projection area of ​​the second chip on the second circuit carrier being a chip mounting area; and one or more heat sink structures penetrating the second circuit carrier through the chip mounting area, the heat sink structures being thermally connected to the second chip.

[0007] Accordingly, embodiments of the present invention also provide an electronic device, including the stacked packaging structure provided in any embodiment of the present invention.

[0008] Accordingly, embodiments of the present invention also provide a method for fabricating a stacked packaging structure, comprising: disposing of a first chip on a first side of a first circuit carrier, the first chip being electrically connected to the first circuit carrier; obtaining a second circuit carrier having one or more heat sink structures, the heat sink structures being located in a chip mounting area of ​​the second circuit carrier and penetrating the second circuit carrier, the chip mounting area being used to dispose of a second chip; disposing of a second chip on a second side of the second circuit carrier, the second chip being located in the chip mounting area and electrically connected to the second circuit carrier, the second chip being thermally connected to the heat sink structure; after disposing of the first chip on the first circuit carrier and the second chip on the second circuit carrier, arranging the first side and the second side opposite to each other, and stacking the first chip and the second chip to make the first chip and the second chip thermally connected.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the stacked packaging structure provided by this embodiment of the invention, a first circuit carrier board and a second circuit carrier board are disposed opposite to each other. Between the first circuit carrier board and the second circuit carrier board, a second chip is stacked with the first chip and thermally connected. A heat sink structure penetrates through the second circuit carrier board and is located in the orthogonal projection area of ​​the second chip on the second circuit carrier board. The heat sink structure is thermally connected to the second chip. Therefore, the stacked packaging structure can obtain a heat conduction path from the first chip to the heat sink structure. The heat generated by the second chip can be dissipated through the heat sink structure, and the heat generated by the first chip can be dissipated through the second chip and the heat sink structure. Moreover, the stacked arrangement of the second chip and the first chip, with the heat sink structure located in the orthogonal projection area of ​​the second chip on the second circuit carrier board, helps to shorten the heat dissipation path, thereby improving the heat dissipation performance of the packaging structure.

[0011] In the method for fabricating a stacked packaging structure provided in this embodiment of the invention, a first chip is disposed on a first side of a first circuit carrier, and a second chip is disposed on a second circuit carrier with a heat sink structure. The heat sink structure penetrates the second circuit carrier and is located in the orthogonal projection area of ​​the second chip on the second circuit carrier. The heat sink structure is thermally connected to the second chip. Then, the first and second sides are arranged opposite to each other, and the first and second chips are stacked to make the first and second chips thermally connected. Therefore, through this fabrication method, the stacked packaging structure can obtain a heat conduction path from the first chip to the heat sink structure. The heat generated by the second chip can be dissipated through the heat sink structure, and the heat generated by the first chip can be dissipated through the second chip and the heat sink structure. Moreover, the stacked arrangement of the second chip and the first chip, with the heat sink structure located in the orthogonal projection area of ​​the second chip on the second circuit carrier, helps to shorten the heat dissipation path, thereby improving the heat dissipation performance of the packaging structure.

[0012] The electronic device provided in this embodiment of the invention includes a stacked packaging structure provided in this embodiment of the invention. Since the stacked packaging structure has good heat dissipation performance, the working performance of the electronic device containing the stacked packaging structure is improved. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a packaging structure;

[0014] Figure 2 This is a schematic diagram of another packaging structure;

[0015] Figure 3 This is a schematic diagram of the stacked packaging structure according to the first embodiment of the present invention;

[0016] Figure 4 Based on Figure 3 A plan view of an embodiment of the second circuit carrier, heat sink structure, first welding bump and second welding bump along the direction from the first circuit carrier towards the second circuit carrier;

[0017] Figure 5 This is a plan view of the heat sink structure, the first welding bump, and the second welding bump in the chip mounting area of ​​the stacked packaging structure of the second embodiment of the present invention.

[0018] Figure 6 This is a partial schematic diagram of the stacked packaging structure according to the third embodiment of the present invention;

[0019] Figure 7 This is a partial schematic diagram of the stacked packaging structure according to the fourth embodiment of the present invention;

[0020] Figure 8 This is a partial schematic diagram of the stacked packaging structure according to the fifth embodiment of the present invention;

[0021] Figure 9 This is a flowchart of a method for fabricating a stacked packaging structure according to an embodiment of the present invention;

[0022] Figures 10 to 18 This is a schematic diagram of each step in the preparation method according to an embodiment of the present invention;

[0023] Figure 19 This is a partial schematic diagram of the preparation method according to another embodiment of the present invention, after the second chip is disposed on the second side of the second circuit carrier;

[0024] Figures 20 to 22 This is a schematic diagram of the steps in the preparation method of another embodiment of the present invention for obtaining a second circuit carrier board having one or more heat sink structures. Detailed Implementation

[0025] As the background technology shows, when more chips are integrated into the packaging structure, how to improve the heat dissipation performance of the packaging structure has become an urgent problem to be solved.

[0026] refer to Figure 1 , Figure 1 This is a schematic diagram of a packaging structure.

[0027] The packaging structure includes: a substrate 10, including a first surface 10A and a second surface 10B disposed opposite to each other; a plurality of chips 11 located on the first surface 10A of the substrate 10; a first conductive connection structure 12 located between the chips 11 and the first surface 10A, the first conductive connection structure 12 electrically connecting the chips 11 and the substrate 10; and a second conductive connection structure 13 located on the second surface 10B of the substrate 10, the second conductive connection structure 13 electrically connecting the substrate 10.

[0028] In the current field of advanced semiconductor packaging, to achieve interconnection of multiple flip chips, multiple flip chips are typically laid flat on the surface of a substrate 10, and the flip chips are interconnected through wiring within the substrate 10. However, as the number of chips 11 increases, the area of ​​the substrate 10 needs to be increased, thereby increasing the packaging area, which is not conducive to miniaturizing the packaging structure.

[0029] Therefore, in order to reduce the packaging area, another packaging structure has been proposed. Figure 2 This is a schematic diagram of another packaging structure.

[0030] The packaging structure includes: a substrate 20, including a first surface 20A and a second surface 20B disposed opposite to each other; a first chip 21 located on the first surface 20A of the substrate 20, wherein the first chip 21 has a conductive via structure 26 penetrating the first chip 21; a first conductive connection structure 22 located between the conductive via structure 26 and the first surface 20A, and electrically connecting the conductive via structure 26 and the substrate 20; a second chip 25 vertically stacked on the first chip 21; a second conductive connection structure 24 located between the second chip 25 and the conductive via structure 26, and electrically connecting the second chip 25 and the conductive via structure 26; and a third conductive connector 23 located on the second surface 20B of the substrate 20, and electrically connected to the substrate 20.

[0031] In this packaging structure, multiple flip chips are vertically stacked on the surface of substrate 20 and interconnected through conductive via structures 26. The vertical stacking of multiple flip chips helps reduce the packaging area; for example, the conductive via structure 26 can be a through-silicon via (TSV) structure. However, the fabrication technology for conductive via structures is costly, thus increasing the packaging cost.

[0032] To balance packaging area and packaging cost, Package On Package (POP) technology has become one of the important packaging methods for achieving high-density integration and has received increasing attention. The POP structure is conducive to achieving higher integration, smaller package size, and higher signal transmission rate.

[0033] A POP (Package-on-Package) structure typically consists of multiple vertically stacked packages. For example, with two packages, the POP structure includes a bottom package and a top package stacked together. However, stacking multiple packages can also lead to heat accumulation, resulting in poor heat dissipation performance of the package structure.

[0034] To address the technical issues, the stacked packaging structure provided in this embodiment of the invention features a first circuit board and a second circuit board arranged opposite to each other. A second chip is stacked and thermally connected to the first chip between the first and second circuit boards. A heat sink structure penetrates the second circuit board and is located in the orthogonal projection area of ​​the second chip on the second circuit board. The heat sink structure is thermally connected to the second chip. Therefore, the stacked packaging structure provides a thermal path from the first chip to the heat sink structure. The heat generated by the second chip can be dissipated through the heat sink structure, and the heat generated by the first chip can be dissipated through the second chip and the heat sink structure. Furthermore, the stacked arrangement of the second chip and the first chip, with the heat sink structure located in the orthogonal projection area of ​​the second chip on the second circuit board, helps to shorten the heat dissipation path, thereby improving the heat dissipation performance of the packaging structure.

[0035] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figure 3 and Figure 4 This is a schematic diagram of the first embodiment of the stacked packaging structure of the present invention. Wherein, Figure 3 This is a schematic diagram of the stacked packaging structure according to the first embodiment of the present invention. Figure 4 Based on Figure 3 A plan view of an embodiment of the second circuit carrier, heat sink structure, first welding bump and second welding bump, along the direction from the first circuit carrier towards the second circuit carrier.

[0037] Reference Figure 3 and Figure 4The stacked packaging structure includes: a first circuit carrier 100 and a second circuit carrier 200 disposed opposite to each other; a first chip 101 located between the first circuit carrier 100 and the second circuit carrier 200, the first chip 101 being disposed on and electrically connected to the first circuit carrier 100; and a second chip 201 located between the first circuit carrier 100 and the second circuit carrier 200, the second chip 201 being disposed on and electrically connected to the second circuit carrier 200, the second chip 201 being stacked with the first chip 101 and thermally connected, the orthogonal projection area of ​​the second chip 201 on the second circuit carrier 200 being a chip mounting area 2001 (e.g., ...). Figure 4 (As shown); one or more heat sink structures 202 penetrate the second circuit carrier 200 of the chip mounting area 2001, and the heat sink structure 202 is thermally connected to the second chip 201.

[0038] The first circuit carrier 100 is used to provide support for the first chip 101 and to provide electrical connection paths for the first chip 101, thereby realizing the packaging integration and electrical integration of the first chip 101.

[0039] In some embodiments, the first line carrier 100 has a first metal line layer, thereby providing an electrical connection path.

[0040] In some embodiments, the first circuit carrier 100 may include a package substrate, an interposer layer, or a redistribution layer (RDL). As an example, the first circuit carrier 100 is a package substrate.

[0041] The type of the first chip 101 depends on the actual functional requirements or application scenario. In some embodiments, the first chip 101 may include one or more of the following: a radio frequency chip, a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip. In other embodiments, the first chip may be other chips depending on actual process requirements.

[0042] In this embodiment, the first chip 101 is soldered to the first circuit carrier 100 using a flip-chip process. The flip-chip process facilitates efficient signal transmission, reduces signal delay and loss, and thus improves the performance of the package structure.

[0043] Correspondingly, the stacked packaging structure also includes a third welding bump 103, located between the first chip 101 and the first circuit carrier 100. The third welding bump 103 is used to weld the first chip 101 to the first circuit carrier 100 and realize the electrical connection between the first chip 101 and the first circuit carrier 100.

[0044] Specifically, the first chip 101 has a first effective solder pad (not shown) facing the first circuit carrier 100, and a third solder bump 103 is located between the first effective solder pad of the first chip 101 and the first circuit carrier 100, thereby realizing the electrical connection between the first effective solder pad and the first circuit carrier 100.

[0045] It should be noted that the first chip 101 has a first bonding surface (not shown) facing the first circuit carrier 100, and a first effective solder pad is exposed on the first bonding surface. The first bonding surface is used to realize the bonding between the first chip 101 and the first circuit carrier 100.

[0046] In some embodiments, the first effective pad is a metallic material, such as aluminum.

[0047] It should be noted that a valid pad refers to a pad that provides an electrical connection to the internal circuitry of the chip (e.g., a metal interconnect layer). Valid pads are used to establish electrical connections between the chip and other circuitry. Accordingly, the first valid pad refers to the pad that provides an electrical connection to the internal circuitry of the first chip 101.

[0048] The material of the third welding bump 103 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0049] In some embodiments, the third solder bump 103 is a conductive bump. For example, the third solder bump 103 may include a microbump (μBump) or a C2 bump. A C2 bump typically refers to a copper pillar bump with a solder cap on its top surface.

[0050] As an example, the third welding bump 103 is a microbump, and the material of the third welding bump 103 is tin.

[0051] In some embodiments, the packaging structure further includes a first bottom filler layer 104. The first bottom filler layer 104 is located between the first chip 101 and the first circuit carrier 100, and also fills the gaps between the third solder bumps 103.

[0052] The first bottom filler layer 104 can reduce the influence of the mismatch in thermal expansion coefficients between the first chip 101 and the first circuit carrier 100, and can redistribute stress and strain, reduce the probability of failure of the third welding bump 103, and help improve the reliability of welding between the first chip 101 and the first circuit carrier 100, thereby improving the reliability of the packaging structure.

[0053] As an example, the material of the first underfill layer 104 includes epoxy resin. In other embodiments, the first underfill layer material can also be other thermosetting materials.

[0054] The second circuit board 200 is used to provide support for the second chip 201 and to provide electrical connection paths for the second chip 201, thereby realizing the packaging integration and electrical integration of the second chip 201.

[0055] In some embodiments, the second circuit board 200 has a second metal circuit layer to provide electrical connection paths.

[0056] In some embodiments, the second circuit carrier 200 may include a packaging substrate, an interposer, or a redistribution layer. As an example, the second circuit carrier 200 is a packaging substrate.

[0057] The type of the second chip 201 depends on the actual functional requirements or application scenario. In some embodiments, the second chip 201 may include one or more of the following: a radio frequency chip, a memory chip, an ASIC chip, a CPU chip, a GPU chip, and an FPGA chip. In other embodiments, the second chip may be other chips depending on the actual process requirements.

[0058] In this embodiment, the second chip 201 is soldered onto the second circuit carrier 200 using flip-chip packaging technology to achieve efficient signal transmission, reduce signal delay and loss, and thus improve the performance of the packaging structure.

[0059] Specifically, the second chip 201 also has an effective solder pad 2012 facing the second circuit carrier 200.

[0060] The effective pad 2012 of the second chip 201 refers to the pad that is electrically connected to the internal circuit of the second chip 201. The effective pad 2012 of the second chip 201 is used to realize the electrical connection between the second chip 201 and other circuits.

[0061] Specifically, the second chip 201 has a second bonding surface (not shown) facing the second circuit carrier 200, and the effective solder pads 2012 of the second chip 201 are exposed on the second bonding surface. The second bonding surface is used to realize the bonding between the second chip 201 and the second circuit carrier 200.

[0062] In some embodiments, the effective pads of the second chip 201 are made of a metallic material, such as aluminum.

[0063] It should be noted that if the effective pad of the first chip 101 is the first effective pad, then the effective pad 2012 of the second chip 201 is the second effective pad.

[0064] Accordingly, the stacked package structure also includes a second solder bump 2032, located between the effective solder pad 2012 of the second chip 201 and the second circuit carrier 200. The second solder bump 2032 is used to solder the second chip 201 to the second circuit carrier 200 and realize the electrical connection between the second chip 201 and the second circuit carrier 200.

[0065] The material of the second welding bump 2032 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0066] In this embodiment, the second welding bump 2032 is a conductive bump. For example, the second welding bump 2032 may include a micro bump or a C2 bump.

[0067] As an example, the second welding bump 2032 is a microbump, and the material of the second welding bump 2032 is tin.

[0068] In some embodiments, the second chip 201 has a dummy pad 2011 facing the second circuit carrier 200.

[0069] The dummy pad 2011 is used to achieve a thermally conductive connection between the second chip 201 and the heat sink structure 202. It should be noted that the dummy pad 2011 is not electrically connected to the internal circuitry of the second chip 201.

[0070] Specifically, the dummy solder pad 2011 of the second chip 201 is exposed on the second bonding surface of the second chip 201.

[0071] In some embodiments, the dummy pad 2011 is a metallic material, such as aluminum.

[0072] It should be noted that during the manufacturing process of the second chip 201, a dummy solder pad 2011 is formed at the same time as the effective solder pad 2012 is formed.

[0073] In some embodiments, a first chip 101 is located on a first circuit carrier 100 to obtain a first package containing the first circuit carrier 100 and the first chip 101, and a second chip 201 is located on a second circuit carrier 200 to obtain a second package containing the second circuit carrier 200 and the second chip 201. The first chip 101 is located between the first circuit carrier 100 and the second circuit carrier 200, and the second chip 201 is also located between the first circuit carrier 100 and the second circuit carrier 200. The first chip 101, the second chip 201 and the second circuit carrier 200 are located on the same side of the first circuit carrier 100, thereby stacking the first package and the second package to obtain a POP structure.

[0074] It should be noted that by stacking the first chip 101 and the second chip 201, and introducing the second circuit carrier 200 as an adapter board to achieve interconnection between the first chip 101 and the second chip 201, the packaging area can be greatly reduced. Moreover, the packaging process of this stacking method is more mature, which is conducive to reducing packaging costs and has higher reliability.

[0075] In some embodiments, the first package is the lower package in the POP structure, and the second package is the upper package in the POP structure. In other embodiments, the first package is the upper package in the POP structure, and the second package is the lower package in the POP structure.

[0076] In some embodiments, the second chip 201 is stacked and thermally connected to the first chip 101, thereby enabling the first chip 101 to dissipate heat via the second chip 201.

[0077] In some embodiments, the stacked package structure further includes a first solder bump 2031 located between the dummy solder pad 2011 and the heat sink structure 202. The first solder bump 2031 is used to solder the second chip 201 to the second circuit carrier 200 and to achieve a thermally conductive connection between the second chip 201 and the heat sink structure 202.

[0078] The first welding bump 2031 is welded to the heat sink structure 202, which helps to improve the bonding strength between the dummy pad 2011 and the heat sink structure 202.

[0079] In this embodiment, the second welding bump 2032 is staggered from the first welding bump 2011, thereby reducing the probability of affecting the function of the first welding bump 2011.

[0080] It should be noted that the second chip 201 is soldered to the second circuit carrier 200 through flip chip packaging technology. Therefore, the process of achieving thermal connection between the second chip 201 and the heat sink structure 202 through the first solder bump 2031 is compatible with the chip mounting process, thereby reducing the manufacturing complexity of the stacked packaging structure.

[0081] Furthermore, the first welding bump 2031 increases the number of welding bumps between the second chip 201 and the second circuit carrier 200, thereby improving the welding reliability between the second chip 201 and the second circuit carrier 200.

[0082] The material of the first welding bump 2031 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0083] In this embodiment, the first welding bump 2031 is a conductive bump. For example, the first welding bump 2031 may include a micro bump or a C2 bump.

[0084] As an example, the first welding bump 2031 is a microbump, and the material of the first welding bump 2031 is tin.

[0085] In some embodiments, the second welding bump 2032 is made of the same material as the first welding bump 2031, and both are the same size, so that they can be formed in the same step.

[0086] In other embodiments, the second welding bump is made of a different material than the first welding bump, or the second welding bump is made of a different size than the first welding bump. For example, the first welding bump and the second welding bump satisfy one or more of the following: the size of the first welding bump is larger than the size of the second welding bump; the thermal conductivity of the first welding bump is greater than the thermal conductivity of the second welding bump; the rigidity of the first welding bump is greater than the rigidity of the second welding bump.

[0087] It should be noted that by changing the type or material of the welding bump, at least one of the welding bump's size, thermal conductivity, and rigidity can be altered.

[0088] The heat sink structure 202 penetrates the chip mounting area 2001 (e.g.) Figure 4The second circuit carrier 200 (shown) has a chip mounting area 2001 that is the orthogonal projection area of ​​the second chip 201 on the second circuit carrier 200. The heat sink structure 202 is thermally connected to the second chip 201. This allows the stacked package structure to obtain a heat conduction path from the first chip 101 to the heat sink structure 202. The heat generated by the second chip 201 can be dissipated through the heat sink structure 202, and the heat generated by the first chip 101 can be dissipated through the second chip 201 and the heat sink structure 202. This allows the heat generated by the first chip 101 and the second chip 201 to be guided to the third surface 200B of the second circuit carrier 200 and dissipated through the third surface 200B. Moreover, the second chip 201 is stacked with the first chip 101, and the heat sink structure 202 is located in the orthogonal projection area of ​​the second chip 201 on the second circuit carrier 200, which helps to shorten the heat dissipation path and thus improve the heat dissipation performance of the package structure.

[0089] It should be noted that, in some embodiments, the heat sink structure 202 is disposed in the second circuit carrier 200 away from the second metal circuit layer, thereby reducing the impact on the second metal circuit layer in the second circuit carrier 200.

[0090] The heat sink structure 202 is made of a material with good thermal conductivity, which facilitates the rapid transfer of heat from the inside of the encapsulation structure to the outside. In some embodiments, the material of the heat sink structure 202 includes one or more of copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene.

[0091] As an example, the heat sink structure 202 is made of a metallic thermally conductive material, and metals have high thermal conductivity.

[0092] In some embodiments, the number of heat sink structures 202 is multiple, thereby improving heat dissipation efficiency.

[0093] like Figure 4 As shown, Figure 4 Based on Figure 3 The plan view of an embodiment of the second line carrier 200, heat sink structure 202, first welding bump 2031 and second welding bump 2032 along the direction from the first line carrier 100 toward the second line carrier 200. In this embodiment, multiple heat sink structures 202 are arranged in an array to improve heat dissipation uniformity.

[0094] It should be noted that, as an example, Figure 4 In the schematic array of heat sink structures 202, adjacent rows of heat sink structures 202 are staggered to improve heat dissipation uniformity.

[0095] It is understood that in some embodiments, adjacent rows of heat sink structures are aligned in the array of heat sink structures. In other embodiments, the layout of the heat sink structures and the layout of the metal wiring inside the second circuit board can also be designed as needed.

[0096] In some embodiments, a heat sink structure 202 is pre-fabricated in the second circuit carrier 200. Specifically, during the fabrication of the second circuit carrier 200, a second metal circuit layer is often formed simultaneously, resulting in a second circuit carrier 200 with a second metal circuit layer. Therefore, the heat sink structure 202 can be formed simultaneously during the process of forming the second metal circuit layer. This is beneficial for controlling the relative position between the heat sink structure 202 and other second metal circuit layers in the second circuit carrier 200, allowing the heat sink structure 202 to avoid other second metal circuit layers. Correspondingly, in some embodiments, the heat sink structure 202 can be formed by stacking multiple layers of thermally conductive metal layers.

[0097] In other embodiments, the heat sink structure may also be a solid heat sink structure embedded in the second circuit board, which is beneficial to increase the volume of the heat sink structure and thus improve the heat dissipation capacity of the heat sink structure.

[0098] In some embodiments, the packaging structure further includes a second bottom filler layer 204 located between the second chip 201 and the second circuit carrier 200, and also filling the gap between the second solder bump 2032 and the first solder bump 2031.

[0099] The second bottom filler layer 204 can reduce the impact of the mismatch in thermal expansion coefficients between the second chip 201 and the second circuit carrier 200, and can redistribute stress and strain, reducing the probability of failure of the second welding bump 2032 and the first welding bump 2031. This helps to improve the reliability of the welding between the second chip 201 and the second circuit carrier 200, and thus helps to improve the reliability of the stacked packaging structure.

[0100] The material of the second bottom filler layer 204 includes epoxy resin.

[0101] In some embodiments, the material of the second bottom filler layer 204 comprises an epoxy resin-based material with a thermal conductivity greater than 1 watt per meter Kelvin (W / mK), thereby further improving the heat dissipation capability of the stacked package structure. For example, the material of the second bottom filler layer 204 may be Namics U8449-33 or Henkel Loctite 8200HT-089.

[0102] In other embodiments, the second bottom filler layer material can also be other thermosetting materials.

[0103] It should be noted that the first circuit carrier 100 includes a first side 100A and a fourth side 100B arranged opposite to each other, and the second circuit carrier 200 includes a second side 200A and a third side 200B arranged opposite to each other. The first side 100A of the first circuit carrier 100 and the second side 200A of the second circuit carrier 200 are arranged opposite each other. The first chip 101 is located between the first circuit carrier 100 and the second circuit carrier 200, and the second chip 201 is also located between the first circuit carrier 100 and the second circuit carrier 200. This is beneficial for improving the utilization rate of the third side 200B of the second circuit carrier 200. For example, chips can be further stacked on the third side 200B of the second circuit carrier 200 to improve the integration of the package structure; or, a heat sink can be provided on the third side 200B of the second circuit carrier 200 to improve the heat dissipation performance of the package structure.

[0104] Continue to refer to Figure 3 The stacked packaging structure also includes a thermal interface material (TIM) layer 109, which is located between the first chip 101 and the second chip 201, and is in contact with both the first chip 101 and the second chip 201.

[0105] The thermal interface material layer 109 is used to achieve a thermally conductive connection between the first chip 101 and the second chip 201. Furthermore, the thermal interface material layer 109 is used to fill the gap between the first chip 101 and the second chip 201, thereby further improving the thermal conductivity between the first chip 101 and the second chip 201. In some embodiments, the material of the thermal interface material layer 109 is thermal grease.

[0106] In other embodiments, the stacked package structure may also omit the thermally conductive interface material layer, with the first chip and the second chip in direct contact.

[0107] In some embodiments, the packaging structure further includes a heat sink 206 located on the side of the second circuit carrier 200 facing away from the first circuit carrier 100 (i.e., the third side 200B of the second circuit carrier 200) and thermally connected to the heat sink structure 202.

[0108] By providing a heat sink 206 on the third side 200B of the second line carrier 200, the heat dissipation effect of the stacked package structure is further improved.

[0109] In some embodiments, when both the heat sink 206 and the heat sink structure 202 are made of metallic materials, the heat sink 206 and the heat sink structure 202 achieve eutectic bonding. Under the influence of high-temperature processes, the metallic materials of the heat sink 206 and the heat sink structure 202 diffuse between each other at the interface. Accordingly, the encapsulation structure also includes a eutectic layer (not shown) located between the heat sink 206 and the heat sink structure 202.

[0110] The heat sink 206 and the heat sink structure 202 are bonded together through a eutectic layer, which improves the bonding strength and heat conduction efficiency between the heat sink 206 and the heat sink structure 202.

[0111] In other embodiments, the encapsulation structure may also include a thermal adhesive layer located between the heat sink 206 and the heat sink structure 202, and in contact with both the heat sink 206 and the heat sink structure 202. The thermal adhesive layer is used to fix the heat sink 206 onto the second circuit board 200 and to facilitate heat conduction between the heat sink 206 and the heat sink structure 202. It should be noted that the thermal adhesive layer may also be located between the heat sink 206 and the third surface 200B of the second circuit board 200, thereby improving the stability of the heat sink 206.

[0112] In some embodiments, the heat sink 206 is a heat sink fin. Specifically, such as Figure 3 As shown, the heat sink 206 is a heat sink with heat dissipation fins, which includes a base (not shown) and fins (not shown) protruding from the base.

[0113] In other embodiments, the radiator may also include a liquid cooling channel for the passage of cooling liquid, the liquid cooling channel including an inlet and an outlet, thereby enabling the circulation of cooling liquid.

[0114] In some embodiments, the packaging structure further includes: a first conductive connection structure 105 located between the first circuit carrier 100 and the second circuit carrier 200, the first conductive connection structure 105 being located on the first circuit carrier 100 on the side of the first chip 101 and electrically connected to the first circuit carrier 100; and a second conductive connection structure 205 located between the first circuit carrier 100 and the second circuit carrier 200, the second conductive connection structure 205 being located on the second circuit carrier 200 on the side of the second chip 201 and electrically connected to the second circuit carrier 200, the second conductive connection structure 205 being connected to the first conductive connection structure 105.

[0115] Specifically, the first conductive connection structure 105 is electrically connected to the first metal circuit layer of the first circuit carrier 100, and the second conductive connection structure 205 is electrically connected to the second metal circuit layer in the second circuit carrier 200.

[0116] The second conductive connection structure 205 is connected to the first conductive connection structure 105, thereby enabling an electrical connection between the first circuit carrier 100 and the second circuit carrier 200, and further enabling an electrical connection between the second chip 201 and the first circuit carrier 100.

[0117] It should be noted that the heights of both the second conductive connection structure 205 and the first conductive connection structure 105 are less than the distance between the first circuit carrier 100 and the second circuit carrier 200. Therefore, when solder balls are used as the second conductive connection structure 205 or the first conductive connection structure 105, it is beneficial to reduce the lateral dimension of the solder balls, thereby reducing the probability of short circuits between adjacent solder balls. Alternatively, when conductive posts are used as the second conductive connection structure 205 or the first conductive connection structure 105, it is beneficial to reduce the probability of the conductive posts tilting.

[0118] The material of the first conductive connection structure 105 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin, and the material of the second conductive connection structure 205 includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0119] In some embodiments, the first conductive connection structure 105 is a conductive pillar, and the second conductive connection structure 205 is a solder ball. The conductive pillar is less prone to collapse, thus providing support for the solder ball and improving the overall stability of the second conductive connection structure 205 and the first conductive connection structure 105. Furthermore, using solder balls for the second conductive connection structure 205 helps ensure the effective connection between the second conductive connection structure 205 and the first conductive connection structure 105. As an example, the first conductive connection structure 105 may be a copper pillar, and the second conductive connection structure 205 may be a solder ball.

[0120] In other embodiments, both the second conductive connection structure and the first conductive connection structure may be solder balls.

[0121] In some embodiments, the stacked packaging structure further includes: a molding layer 106 located on a first circuit carrier 100 on the side of the first chip 201 and the first conductive connection structure 105, the molding layer 106 covering the sidewalls of the first chip 101 and the first conductive connection structure 105, and exposing the end face of the first conductive connection structure 105 facing away from the first circuit carrier 100, the surface of the first chip 201 facing away from the first circuit carrier 100, and the second conductive connection structure 205.

[0122] The molding layer 106 is used to protect the first chip 101 and the first conductive connection structure 105; the molding layer 106 is also used to improve the mechanical strength of the first package, thereby improving the stacking reliability of the second package and the first package.

[0123] The molding layer 106 is made of a molding material, such as epoxy resin. Epoxy resin has advantages such as low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, other suitable encapsulation materials can also be used for the molding layer.

[0124] In some embodiments, the stacked packaging structure further includes a third conductive connection structure 1001, which is located on the side of the first circuit carrier 100 facing away from the second circuit carrier 200 (i.e., the fourth side 100B of the first circuit carrier 100) and is electrically connected to the first circuit carrier 100.

[0125] The first circuit carrier 100 has a first metal circuit layer, thus obtaining a first circuit carrier 100 with a first metal circuit layer. The third conductive connection structure 1001 is electrically connected to the first metal circuit layer in the first circuit carrier 100, thereby realizing the electrical connection of the first circuit carrier 100 with other circuits. For example, the first circuit carrier 100 can be subsequently assembled onto a PCB (Printed Circuit Board) through the third conductive connection structure 1001.

[0126] The material of the third conductive connection structure 1001 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin. In some embodiments, the third conductive connection structure 1001 is a solder ball. As an example, the third conductive connection structure 1001 is a solder ball.

[0127] Figure 5 This is a plan view of the heat sink structure, the first welding bump, and the second welding bump in the chip mounting area of ​​the stacked packaging structure of the second embodiment of the present invention.

[0128] The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows: Figure 5 As shown, in the chip mounting area 3001, there are multiple heat sink structures 302, and the multiple heat sink structures 302 are non-closed concentric rings.

[0129] The use of multiple non-closed coaxial ring heat sink structures 302 is beneficial to increasing the heat dissipation area of ​​the heat sink structure 302, thereby improving the heat dissipation efficiency. At the same time, it can avoid the second metal circuit layer, allowing the second metal circuit layers inside and outside the non-closed coaxial ring to be connected, thereby reducing the impact on the second metal circuit layer in the second circuit carrier board.

[0130] Correspondingly, the first welding bump 3031 and the heat sink structure 302 are thermally connected, while the second welding bump 3032 avoids the heat sink structure 302.

[0131] Figure 6This is a partial schematic diagram of the stacked packaging structure according to the third embodiment of the present invention.

[0132] The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows: Figure 6 As shown, the end face of the heat sink structure 402 facing the first line carrier 400 is recessed into the second line carrier 410, and the heat sink structure 402 and the second line carrier 410 form a notch 405.

[0133] Correspondingly, the first welding bump 4031 is also located in the recess 405.

[0134] By recessing the heat sink structure 402 into the second circuit carrier 410 at the end face of the first circuit carrier 400, more space can be provided for the first welding bump 4031, which is beneficial to increase the size of the first welding bump 4031 and further improve the heat conduction of the first welding bump 4031.

[0135] Accordingly, in some embodiments, the size of the first welding bump is larger than the size of the second welding bump.

[0136] It should be noted that the first welding bump 4031 is also located in the recess 405, which further improves the stability of the first welding bump 4031.

[0137] Figure 7 This is a partial schematic diagram of the stacked packaging structure according to the fourth embodiment of the present invention.

[0138] The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows: Figure 7 As shown, the first welding bump 4631 is a second type of welding bump. The second type of welding bump includes a thermally conductive inner core 4631a and a solder layer 4631b covering the thermally conductive inner core 4631a. The thermal conductivity of the thermally conductive inner core 4631a is higher than that of the solder layer 4631b, and the melting point of the thermally conductive inner core 4631a is higher than that of the solder layer 4631b.

[0139] The thermal conductivity of the thermally conductive inner core 4631a is higher than that of the solder layer 4631b, thereby further improving the thermal conductivity of the first welding bump 4631.

[0140] The melting point of the heat-conducting inner core 4631a is higher than that of the solder layer 4631b, thereby ensuring that the first welding bump 4631 can be welded onto the heat sink structure 462 while reducing the possibility of the heat-conducting inner core 4631a melting. This improves the rigidity of the first welding bump 4631, enabling the heat-conducting inner core 4631a to play a supporting role and thus reducing the risk of the first welding bump 4631 collapsing.

[0141] In some embodiments, the second type of solder bump comprises a copper core solder ball. Copper has high rigidity and excellent thermal conductivity.

[0142] Accordingly, in some embodiments, the rigidity of the first welding bump 4631 is greater than that of the second welding bump (not shown), and the thermal conductivity of the first welding bump 4631 is greater than that of the second welding bump.

[0143] It should be noted that, as an example, the end face of the heat sink structure 462 facing the first circuit carrier 450 is recessed into the second circuit carrier 460, and the heat sink structure 462 and the second circuit carrier 460 form a notch 465. In other embodiments, the end face of the heat sink structure facing the first circuit carrier may also be flush with the second circuit carrier.

[0144] Figure 8 This is a partial schematic diagram of the packaging structure according to the fifth embodiment of the present invention.

[0145] The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows: Figure 8 As shown, the first solder bump 5031 is a first type of solder bump, which is a conductive post 5031a with a solder cap 5031b, and the solder cap 5031b is located on the end face of the conductive post 5031a facing away from the second chip 501.

[0146] By employing conductive post 5031a, the rigidity of the first welding bump 5031 is improved, thereby reducing the risk of the first welding bump 5031 collapsing.

[0147] One end of the conductive post 5031a has a solder cap 5031b, thereby achieving the welding combination of the first welding bump 5031 and the heat sink structure 502.

[0148] In some embodiments, the first type of welding bump is a copper pillar with a tin cap.

[0149] In some embodiments, the end face of the heat sink structure 502 facing the first circuit carrier (not shown) is recessed into the second circuit carrier 510, and the heat sink structure 502 and the second circuit carrier 510 form a notch (not shown). In this case, the first type of welding bump is also located in the notch, which helps to improve the stability of the first welding bump 5031.

[0150] In other embodiments, the end face of the heat sink structure facing the first circuit board may also be flush with the second circuit board.

[0151] It should be noted that in other embodiments, the first welding bump may also include two types of welding bumps, that is, the first welding bump includes a first type of welding bump and a second type of welding bump.

[0152] Accordingly, embodiments of the present invention also provide a preparation method. (Referring to the reference...) Figures 9 to 18 , Figure 9 This is a flowchart of a preparation method according to an embodiment of the present invention. Figures 10 to 18 This is a schematic diagram of each step in the preparation method according to an embodiment of the present invention.

[0153] refer to Figure 9 and in conjunction with references Figure 10 In step S1, a first chip 601 is disposed on the first surface 600A of the first circuit carrier 600, and the first chip 601 is electrically connected to the first circuit carrier 600.

[0154] The first circuit carrier board 600 is used to provide support for the first chip 601 and to provide electrical connection paths for the first chip 601, thereby realizing the packaging integration and electrical integration of the first chip 601.

[0155] In some embodiments, the first line carrier 600 has a first metal line layer, thereby providing an electrical connection path.

[0156] In some embodiments, the first circuit carrier 600 may include a packaging substrate, an interposer, or a redistribution layer. As an example, the first circuit carrier 600 is a packaging substrate.

[0157] The first line carrier board 600 includes a first side 600A and a fourth side 600B arranged opposite to each other.

[0158] The type of the first chip 601 depends on the actual functional requirements or application scenarios. For a description of the type of the first chip 601, please refer to the relevant content on the packaging structure, which will not be repeated here.

[0159] In some embodiments, the step of setting the first chip 601 on the first surface 600A of the first circuit carrier 600 includes: soldering the first chip 601 onto the first circuit carrier 600 by flip-chip bonding process.

[0160] In this embodiment, the first chip 601 has a first bonding surface (not shown), which is used to realize the bonding between the first chip 601 and the first circuit carrier 600.

[0161] Specifically, the method of soldering the first chip 601 to the first circuit carrier 600 by flip-chip bonding includes: forming a third solder bump 603 on the first bonding surface of the first chip 601, the third solder bump 603 being electrically connected to the first chip 601; using the third solder bump 603 to solder the first chip 601 to the first surface 600A of the first circuit carrier 600, and realizing the electrical connection between the first chip 601 and the first circuit carrier 600.

[0162] Specifically, the first chip 601 has a first effective solder pad (not shown) facing the first circuit carrier 600. After the first chip 601 is disposed on the first surface 600A of the first circuit carrier 600, the third solder bump 603 is located between the first effective solder pad of the first chip 601 and the first circuit carrier 600, thereby realizing the electrical connection between the first effective solder pad and the first circuit carrier 600.

[0163] It should be noted that the first effective solder pad of the first chip 601 is exposed on the first bonding surface.

[0164] In some embodiments, the first effective pad is a metallic material, such as aluminum.

[0165] In this embodiment, the third welding bump 603 is a conductive bump. For example, the third welding bump 603 may include a microbump or a C2 bump. The material of the third welding bump 603 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin.

[0166] As an example, the third welding bump 603 is a micro-bump, and the material of the third welding bump 603 is tin.

[0167] Continue to refer to Figure 10 After the first chip 601 is disposed on the first surface 600A of the first circuit carrier 600, the fabrication method further includes filling the space between the first chip 601 and the first circuit carrier 600 with a first bottom filler layer 604, and the first bottom filler layer 604 also fills the gap between the third solder bumps 603.

[0168] The first bottom filler layer 604 can reduce the influence of the mismatch in thermal expansion coefficients between the first chip 601 and the first circuit carrier 600, and can redistribute stress and strain, reduce the probability of failure of the third welding bump 603, and help improve the reliability of welding between the first chip 601 and the first circuit carrier 600, thereby improving the reliability of the stacked packaging structure.

[0169] As an example, the material of the first underfill layer 604 includes epoxy resin. In other embodiments, the first underfill layer material can also be other thermosetting materials.

[0170] Continue to refer to Figure 10 The preparation method further includes: setting a first conductive connection structure 605 on the first surface 600A of the first circuit carrier 600, wherein the first conductive connection structure 605 is electrically connected to the first circuit carrier 600.

[0171] Wherein, after the first chip 601 and the first conductive connection structure 605 are disposed on the first surface 600A of the first circuit carrier 600, the first conductive connection structure 605 is located on the side of the first chip 601.

[0172] The first conductive connection structure 605 is used to realize the electrical connection between the first circuit carrier 600 and the second circuit carrier. The material of the first conductive connection structure 605 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin.

[0173] In some embodiments, the first conductive connection structure 605 is a conductive pillar, which is less prone to collapse, thus improving the stability of both the second conductive connection structure and the first conductive connection structure 605. As an example, the first conductive connection structure 605 is a copper pillar. In other embodiments, the first conductive connection structure may also be a solder ball.

[0174] In some embodiments, the first conductive connection structure 605 can be soldered onto the first surface 600A of the first circuit carrier 600.

[0175] In other embodiments, a sacrificial layer may be formed on a first surface of the first circuit board, and a through-hole exposing the first circuit board may be formed in the sacrificial layer. Subsequently, a first conductive connection structure may be formed in the through-hole, and the sacrificial layer may be removed after the first conductive connection structure is formed.

[0176] As an example, after the first conductive connection structure 605 is disposed on the first surface 600A of the first circuit carrier 600, the first chip 601 is disposed on the first surface 600A of the first circuit carrier 600, thereby reducing the impact of the manufacturing process of the first conductive connection structure 605 on the first chip 601. In other embodiments, the assembly order of the first chip and the first conductive connection structure on the first circuit carrier can also be reversed.

[0177] refer to Figure 11 The preparation method further includes: after the first chip 601 and the first conductive connection structure 605 are disposed on the first surface 601A of the first circuit carrier 600, a molding layer 606 is formed on the first surface 600A of the first circuit carrier 600. The molding layer 606 covers the sidewalls of the first chip 601 and the first conductive connection structure 605, and exposes the end face of the first conductive connection structure 605 facing away from the first circuit carrier 600 and the surface of the first chip 601 facing away from the first circuit carrier 600.

[0178] The molding layer 606 is used to protect the first chip 601 and the first conductive connection structure 605.

[0179] After the molding layer 606 is formed, the first circuit carrier 600, the first chip 601, the first conductive connection structure 605 and the molding layer 606 constitute the first package. The molding layer 606 is also used to improve the mechanical strength of the first package, thereby improving the stacking reliability of the first package and the second package.

[0180] The molding layer 606 exposes the surface of the first chip 601 on the side facing away from the first circuit carrier 600, which facilitates heat dissipation of the first chip 601.

[0181] The molding compound 606 is made of a molding compound, such as epoxy resin. Epoxy resin has advantages such as low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, other suitable encapsulation materials may also be used for the molding compound.

[0182] In some embodiments, the step of forming the molding layer 606 includes: forming a molding material layer on a first surface 600A of the first circuit carrier 600, the molding material layer covering the first conductive connection structure 605 and the first chip 601; performing a planarization process on the molding material layer to expose the end face of the first conductive connection structure 605 facing away from the first circuit carrier 600 and the surface of the first chip 601 facing away from the first circuit carrier 600, the remaining molding material layer serving as the molding layer 606.

[0183] refer to Figure 12 Before stacking the first chip 601 and the second chip, the preparation method further includes forming a thermally conductive interface material layer 609 on the surface of the first chip 601 facing away from the first circuit carrier 600.

[0184] The thermal interface material layer 609 is used to achieve a thermally conductive connection between the first chip 601 and the second chip. Furthermore, the thermal interface material layer 609 also fills the gap between the first chip 601 and the second chip, thereby further improving the thermal conductivity between the first chip 601 and the second chip. In some embodiments, the material of the thermal interface material layer 609 is thermal grease.

[0185] It should be noted that, in other embodiments, after the second chip is disposed on the second side of the second circuit board, a thermally conductive interface material layer may be formed on the surface of the second chip facing away from the second circuit board.

[0186] In other embodiments, the step of forming a thermally conductive interface material layer may be omitted.

[0187] Continue to refer to Figure 9 and in conjunction with references Figure 13 and Figure 14, Figure 14 Based on Figure 13 A top view of an embodiment of a second circuit carrier, a heat sink structure, a first solder bump, and a second solder bump is provided. Step S2 is executed to obtain a second circuit carrier 800 provided with one or more heat sink structures 802. The heat sink structure 802 is located in the chip mounting area 8001 of the second circuit carrier and penetrates the second circuit carrier 800. The chip mounting area 8001 is used to set a second chip.

[0188] The second circuit board 800 is used to provide support for the second chip and to provide electrical connection paths for the second chip, thereby realizing the packaging integration and electrical integration of the second chip.

[0189] In some embodiments, the second circuit board 800 has a second metal circuit layer to provide an electrical connection path.

[0190] In some embodiments, the second circuit carrier 800 may include a packaging substrate, an interposer, or a redistribution layer. As an example, the second circuit carrier 800 is a packaging substrate.

[0191] In this embodiment, the second circuit carrier board 800 includes a second side 800A and a third side 800B arranged opposite to each other.

[0192] It should be noted that the heat sink structure 802 penetrates through the second circuit carrier board 800, thereby guiding the heat generated by the first chip 601 and the second chip to the third surface 800B of the second circuit carrier board 800, and dissipating the heat through the third surface 800B.

[0193] It should also be noted that the chip mounting area 8001 is used to set the second chip. Therefore, setting the heat sink structure 802 in the chip mounting area 8001 of the second circuit board 800 is beneficial to shortening the heat dissipation path.

[0194] It should be noted that, in some embodiments, the heat sink structure 802 is disposed in the second circuit carrier 800 away from the second metal circuit layer, thereby reducing the impact on the second metal circuit layer in the second circuit carrier 800.

[0195] The heat sink structure 802 is made of a material with good thermal conductivity, which facilitates the rapid transfer of heat from the inside of the encapsulation structure to the outside. In some embodiments, the material of the heat sink structure 802 includes one or more of copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene.

[0196] As an example, the heat sink structure 802 is made of a metallic thermally conductive material, and metals have high thermal conductivity.

[0197] In some embodiments, the number of heat sink structures 802 is multiple, thereby improving heat dissipation efficiency.

[0198] like Figure 14 As shown, in some embodiments, multiple heat sink structures 802 are arranged in an array to improve heat dissipation uniformity.

[0199] It should be noted that, as an example, Figure 14 In the schematic array of heat sink structures 802, adjacent rows of heat sink structures 802 are staggered to improve heat dissipation uniformity.

[0200] It is understood that in some embodiments, adjacent rows of heat sink structures are aligned in the array of heat sink structures. In other embodiments, the layout of the heat sink structures and the layout of the metal wiring inside the second circuit board can also be designed as needed.

[0201] In other embodiments, when there are multiple heat sink structures, these multiple heat sink structures can also be non-closed concentric rings. Using multiple non-closed concentric ring heat sink structures increases the heat dissipation area of ​​the heat sink structure, thereby improving heat dissipation efficiency. Simultaneously, it avoids the second metal circuit layer, allowing the second metal circuit layers inside and outside the non-closed concentric ring to be connected, thus reducing the impact on the second metal circuit layer in the second circuit carrier.

[0202] In some embodiments, the step of obtaining a second circuit carrier 800 having one or more heat sink structures 802 includes: providing a second circuit carrier 800, wherein the heat sink structure 802 is pre-prepared in the second circuit carrier 800.

[0203] Specifically, during the fabrication of the second circuit carrier 800, a second metal circuit layer is often formed simultaneously, resulting in a second circuit carrier 800 with the second metal circuit layer. Therefore, during the process of forming the second metal circuit layer, a heat sink structure 802 can be formed simultaneously. This facilitates control over the relative position of the heat sink structure 802 and other second metal circuit layers in the second circuit carrier 800, allowing the heat sink structure 802 to avoid other second metal circuit layers. Correspondingly, in some embodiments, the heat sink structure 802 may comprise multiple stacked metal thermally conductive layers, with adjacent metal thermally conductive layers connected to each other.

[0204] In other embodiments, the heat sink structure may also be a solid heat sink structure embedded in the second circuit board.

[0205] Continue to refer to Figure 9 , Figure 13 and Figure 14Execute step S3, and place a second chip 801 on the second side 800A of the second circuit carrier 800. The second chip 801 is located in the chip mounting area 8001 (e.g., Figure 14 As shown, the second chip 801 is electrically connected to the second circuit carrier 800, and is thermally connected to the heat sink structure 802.

[0206] The type of the second chip 801 depends on the actual functional requirements or application scenario. For a description of the type of the second chip 801, please refer to the relevant content on stacked package structures, which will not be repeated here.

[0207] In some embodiments, the step of setting the second chip 801 on the second side 800A of the second circuit carrier 800 includes: soldering the second chip 801 onto the second circuit carrier 800 by flip-chip bonding process.

[0208] In this embodiment, the second chip 801 also has an effective solder pad 8012 exposed on the bonding surface.

[0209] Specifically, the second chip 801 has a second bonding surface, which is used to achieve bonding between the second chip 801 and the second circuit carrier 800. Correspondingly, the effective solder pad 8012 is exposed on the second bonding surface.

[0210] The effective solder pad 8012 of the second chip 801 refers to the solder pad that is electrically connected to the internal circuit of the second chip 801. The effective solder pad 8012 of the second chip 801 is used to realize the electrical connection between the second chip 801 and other circuits.

[0211] In some embodiments, the effective pads of the second chip 801 are made of a metallic material, such as aluminum.

[0212] It should be noted that if the effective pad of the first chip 601 is the first effective pad, then the effective pad 8012 of the second chip 801 is the second effective pad.

[0213] Accordingly, the method of soldering the second chip 801 to the second circuit carrier 800 by flip-chip bonding includes: forming a second bonding bump 8032 on the second bonding surface (not shown) of the second chip 801, the second bonding bump 8032 being electrically connected to the second chip 801; and using the second bonding bump 8032 to solder the second chip 801 to the second surface 800A of the second circuit carrier 800, thereby achieving an electrical connection between the second chip 801 and the second circuit carrier 800.

[0214] Specifically, a second solder bump 8032 is formed on the effective solder pad 8012 of the second chip 801. Correspondingly, after the second chip 801 is disposed on the second surface 800A of the second circuit carrier 800, the second solder bump 8032 is located between the effective solder pad 8012 of the second chip 801 and the second circuit carrier 800.

[0215] The material of the second welding bump 8032 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin.

[0216] In this embodiment, the second welding bump 8032 is a conductive bump. For example, the second welding bump 8032 may include a micro bump or a C2 bump.

[0217] As an example, the second welding bump 8032 is a microbump, and the material of the second welding bump 8032 is tin.

[0218] In some embodiments, the second chip 8010 has a dummy pad 8011 exposed on the bonding surface (i.e., the second bonding surface).

[0219] The dummy solder pad 8011 is used to achieve a thermally conductive connection between the second chip 801 and the heat sink structure 802. It should be noted that the dummy solder pad 8011 is not electrically connected to the internal circuitry of the second chip 801.

[0220] In some embodiments, the dummy pad 8011 is a metallic material, such as aluminum.

[0221] It should be noted that, in some embodiments, during the manufacturing process of the second chip 801, a dummy pad 8011 may be formed at the same time as the effective solder pad 8012.

[0222] Accordingly, the step of setting the second chip 801 on the second surface 800A of the second circuit carrier 800 includes: forming a first solder bump 8031 ​​on the dummy solder pad 8011; making the bonding surface (i.e. the second bonding surface) of the second chip 801 face the second circuit carrier 800; and soldering the first solder bump 8031 ​​to the heat sink structure 802 to achieve a thermally conductive connection between the second chip 801 and the heat sink structure 802.

[0223] In this embodiment, the second welding bump 8032 is staggered from the first welding bump 8031, thereby reducing the probability of affecting the function of the first welding bump 8031.

[0224] In this embodiment, during the process of welding the first welding bump 8031 ​​to the heat sink structure 802, the second welding bump 8032 is welded to the second circuit carrier 800 to realize the electrical connection between the second chip 801 and the second circuit carrier 800.

[0225] It should be noted that the second chip 801 is soldered to the second circuit substrate 800 using flip-chip packaging technology. Therefore, the first solder bump 8031 ​​makes the process of achieving thermal conductivity between the second chip 801 and the heat sink structure 802 compatible with the chip mounting process, thereby reducing the fabrication complexity of the stacked package structure. Furthermore, the first solder bump 8031 ​​increases the number of solder bumps between the second chip 801 and the second circuit substrate 800, which helps to increase the soldering reliability between the second chip 801 and the second circuit substrate 800.

[0226] The material of the first welding bump 8031 ​​includes one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0227] In this embodiment, the first welding bump 8031 ​​is a conductive bump. For example, the first welding bump 8031 ​​may include a micro bump or a C2 bump.

[0228] As an example, the first solder bump 8031 ​​is a microbump, and the material of the first solder bump 8031 ​​is tin.

[0229] In some embodiments, the second welding bump 8032 is made of the same material as the first welding bump 8031, and both are the same size, so that they can be formed in the same step.

[0230] In other embodiments, the second welding bump is made of a different material than the first welding bump, or the second welding bump is made of a different size than the first welding bump. For example, the first welding bump and the second welding bump satisfy one or more of the following: the size of the first welding bump is larger than the size of the second welding bump; the thermal conductivity of the first welding bump is greater than the thermal conductivity of the second welding bump; the rigidity of the first welding bump is greater than the rigidity of the second welding bump.

[0231] It should be noted that by changing the type or material of the welding bump, at least one of the welding bump's size, thermal conductivity, and rigidity can be altered.

[0232] For example, in conjunction with reference Figure 7 and Figure 8 In other embodiments, the first welding bump includes one or more of a first type of welding bump and a second type of welding bump.

[0233] The first type of solder bump is a conductive post with a solder cap, and the solder cap is located on the end face of the conductive post facing away from the second chip; the second type of solder bump includes a thermally conductive core and a solder layer covering the thermally conductive core, the thermal conductivity of the thermally conductive core is higher than that of the solder layer, and the melting point of the thermally conductive core is higher than that of the solder layer.

[0234] In some embodiments, the first type of solder bump is a copper pillar with a tin cap, and the second type of solder bump includes a copper core and a tin ball. Accordingly, in some embodiments, the rigidity of the first solder bump is greater than that of the second solder bump, and the thermal conductivity of the first solder bump is greater than that of the second solder bump.

[0235] For a detailed description of the second type of solder bumps, please refer to the relevant content in the stacked packaging structure of the fourth embodiment mentioned above. For a detailed description of the first type of solder bumps, please refer to the relevant content in the stacked packaging structure of the fifth embodiment mentioned above. They will not be repeated here.

[0236] In this embodiment, after obtaining a second circuit carrier 800 with one or more heat sink structures 802, a second chip 801 is disposed on the second side 800A of the second circuit carrier 800, thereby reducing the process difficulty.

[0237] Continue to refer to Figure 13 After the second chip 801 is disposed on the second surface 800A of the second circuit carrier 800, the fabrication method further includes: filling the space between the second chip 801 and the second circuit carrier 800 with a second bottom filler layer 804, and the second bottom filler layer 804 also fills the gap between the second welding bump 8032 and the first welding bump 8031.

[0238] The second bottom filler layer 804 can reduce the impact of the mismatch in thermal expansion coefficients between the second chip 801 and the second circuit carrier 800, and can redistribute stress and strain, reducing the probability of failure of the second welding bump 8032 and the first welding bump 8031. This helps to improve the reliability of the welding between the second chip 801 and the second circuit carrier 800, and thus helps to improve the reliability of the packaging structure.

[0239] The material of the second bottom filler layer 804 includes epoxy resin. In some embodiments, the material of the second bottom filler layer 804 includes an epoxy resin-based material with a thermal conductivity greater than 1 watt per meter Kelvin, thereby further improving the heat dissipation capability of the stacked package structure.

[0240] In other embodiments, the second bottom filler layer material can also be other thermosetting materials.

[0241] refer to Figure 15A second conductive connection structure 805 is provided on the second surface 800A of the second circuit carrier 800, and the second conductive connection structure 805 is located in the chip mounting area 8001 (e.g., Figure 14 The second conductive connection structure 805 is electrically connected to the second circuit carrier board 800 on the side of the (shown).

[0242] The second conductive connection structure 805 is used to realize the electrical connection between the second circuit carrier 800 and the first circuit carrier 600.

[0243] The material of the second conductive connection structure 805 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin. In some embodiments, the second conductive connection structure 805 is a solder ball, thereby reducing the complexity of fabricating the second conductive connection structure 805. As an example, the second conductive connection structure 805 is a solder ball.

[0244] Continue to refer to Figure 9 and in conjunction with references Figure 16 In step S4, after setting the first chip 601 on the first circuit carrier 600 and the second chip 801 on the second circuit carrier 800, the first surface 600A and the second surface 800A are arranged opposite to each other, and the first chip 601 and the second chip 801 are stacked so that the first chip 601 and the second chip 801 are thermally connected.

[0245] By making the first chip 601 and the second chip 801 thermally connected, the stacked package structure can obtain a thermal path from the first chip 601 to the heat sink structure 802. The heat generated by the second chip 801 can be dissipated through the heat sink structure 802, and the heat generated by the first chip 601 can be dissipated through the second chip 801 and the heat sink structure 802. Moreover, the second chip 801 is stacked with the first chip 601, and the heat sink structure 802 is located in the orthogonal projection area of ​​the second chip 801 on the second circuit carrier 800, which helps to shorten the heat dissipation path and thus improve the heat dissipation performance of the package structure.

[0246] In some embodiments, in the step of stacking the first chip 601 and the second chip 801, the second conductive connection structure 805 is soldered to the corresponding first conductive connection structure 605, thereby achieving an electrical connection between the first circuit board 600 and the second circuit board 800, and further achieving an electrical connection between the second chip 601 and the first circuit board 600.

[0247] In some embodiments, during the step of stacking the first chip 601 and the second chip 801, both the first chip 601 and the second chip 801 are in contact with the thermally conductive interface material layer 609.

[0248] It should be noted that in some embodiments, the second circuit carrier 800 with heat sink structure 802, the second chip 801 and the second conductive connection structure 805 are used to form the second package. By stacking the first chip 601 and the second chip 801, the second package and the first package are stacked and packaged.

[0249] refer to Figure 17 The preparation method further includes: after stacking the first chip 601 and the second chip 801, a heat sink 806 is disposed on the third side 800B of the second circuit carrier board 800, and the heat sink 806 is thermally connected to the heat sink structure 802.

[0250] The heat dissipation effect of the stacked package structure is further improved by setting a heat sink 806 on the third side 800B of the second line carrier 800.

[0251] In some embodiments, when both the heat sink 806 and the heat sink structure 802 are made of metallic materials, the heat sink 806 and the heat sink structure 802 can be bonded together through a eutectic process. Under the influence of the high-temperature process, the metallic materials of the heat sink 806 and the heat sink structure 802 form a eutectic layer (not shown) at the interface due to inter-material diffusion.

[0252] The heat sink 806 and the heat sink structure 802 are bonded together through a eutectic layer, which improves the bonding strength and heat conduction efficiency between the heat sink 806 and the heat sink structure 802.

[0253] In other embodiments, the heat sink 806 may be disposed on the thermally conductive adhesive layer after a thermally conductive adhesive layer covering the heat sink structure 802 is formed on the third surface 800B of the second circuit carrier 800.

[0254] It should be noted that the thermally conductive adhesive layer can also cover the third side 800B of the second circuit carrier board 800, thereby improving the stability of the heat sink 806.

[0255] In some embodiments, the heat sink 806 is a heat sink fin. Specifically, such as Figure 17 As shown, the radiator 806 is a heat sink with heat dissipation fins. In other embodiments, the radiator may also include a liquid cooling channel for the passage of coolant, the liquid cooling channel including an inlet and an outlet, thereby realizing the circulation of coolant.

[0256] refer to Figure 18After stacking the first chip 601 and the second chip 801, the fabrication method further includes: forming a third conductive connection structure 6001 on the fourth surface 600B of the first circuit carrier 600, the third conductive connection structure 6001 being electrically connected to the first circuit carrier 600, and the fourth surface 600B being disposed opposite to the first surface 601A.

[0257] The first circuit carrier 600 has a first metal circuit layer, thus obtaining a first circuit carrier 600 with the first metal circuit. The third conductive connection structure 6001 is electrically connected to the first metal circuit layer in the first circuit carrier 600, thereby realizing the electrical connection of the first circuit carrier 600 with other circuits. For example, the first circuit carrier 600 can be subsequently assembled onto a PCB board through the third conductive connection structure 6001.

[0258] In some embodiments, before stacking the second chip and the second circuit substrate onto the first chip, a third conductive connection structure 6001 is formed on the fourth side 600B of the first circuit substrate 600, which helps to reduce the process difficulty of fabricating the third conductive connection structure 6001.

[0259] The material of the third conductive connection structure 6001 includes one or more of copper, aluminum, gold, nickel, silver, palladium, and tin. In some embodiments, the third conductive connection structure 6001 is a solder ball. As an example, the third conductive connection structure 6001 is a solder ball.

[0260] Figure 19 This is a partial schematic diagram of the preparation method according to another embodiment of the present invention, after the second chip is disposed on the second side of the second circuit carrier.

[0261] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that, in the step of obtaining the second circuit carrier 910 having one or more heat sink structures 912, the end face of the heat sink structure 912 located on the second surface (not shown) of the second circuit carrier 910 is recessed into the second surface, and the heat sink structure 912 and the second circuit carrier 910 form a recess 915. Correspondingly, in the step of welding the first welding bump 9131 to the heat sink structure 912, the first welding bump 9131 is also located in the recess 915.

[0262] By recessing the end face of the heat sink structure 912 on the second surface (not shown) of the second circuit carrier 910 into the second surface, more space can be provided for the first welding bump 9131, which is beneficial to increase the size of the first welding bump 9131 and further improve the heat conduction of the first welding bump 9131.

[0263] Accordingly, in some embodiments, the size of the first welding bump 9131 is larger than the size of the second welding bump.

[0264] It should be noted that the first welding bump 9131 is also located in the recess 915, which further improves the stability of the first welding bump 9131.

[0265] Figures 20 to 22 This is a schematic diagram of the steps in the preparation method of another embodiment of the present invention for obtaining a second circuit carrier board having one or more heat sink structures.

[0266] The similarities between this embodiment and the previous embodiment will not be repeated here. The difference between this embodiment and the previous embodiment is that after forming a through hole 9015 in the second circuit carrier board 901, a heat sink structure 9011 is provided in the through hole 9015.

[0267] Specifically, such as Figure 20 As shown, the step of obtaining a second circuit carrier 901 having one or more heat sink structures 9011 includes: providing a second circuit carrier 901; and providing a through hole 9015 penetrating the second circuit carrier 901 in the chip mounting area (not shown) of the second circuit carrier 901; as shown Figure 21 As shown, a heat sink structure 9011 is provided in the through hole 9015.

[0268] The through-hole 9015 is used to provide space for the formation of the heat sink structure 9011.

[0269] In some embodiments, an etching process can be used to form the via 9015. As an example, a laser etching process is used to etch the second circuit substrate 901 to form the via 9015.

[0270] refer to Figure 20 Before forming the through hole 9015 through the second circuit carrier 901, the preparation method further includes: temporarily bonding the second circuit carrier 901 to a temporary carrier 900, with the second surface 901A facing away from the temporary carrier 900.

[0271] Temporary carrier plate 900 is used to provide a process platform for the formation of through hole 9015 and heat sink structure 9011.

[0272] refer to Figure 21 In some embodiments, the step of providing a heat sink structure 9011 in the through hole 9015 includes filling the through hole 9015 with a thermally conductive material to form a heat sink structure 9011.

[0273] In some embodiments, after the through hole 9015 is filled with thermally conductive material, the thermally conductive material also covers the second surface 901A of the second circuit carrier 901. Therefore, the step of setting the heat sink structure 9011 in the through hole 9015 further includes: planarizing the thermally conductive material to expose the second surface 901A of the second circuit carrier 901, and retaining the thermally conductive material in the through hole 9015 as the heat sink structure 9011.

[0274] It should be noted that by setting the heat sink structure 9011 in the through hole 9015, the volume of the heat sink structure 9011 can be increased, thereby improving the heat dissipation capacity of the heat sink structure 9011.

[0275] refer to Figure 22 In through hole 9015 (e.g.) Figure 21 After setting the heat sink structure 9011 in the (as shown), the preparation method further includes: performing debonding to remove the temporary carrier plate 900 (as shown). Figure 21 (As shown).

[0276] It should be noted that, as needed, the temporary carrier board 900 can be removed after the second chip is installed on the second circuit carrier board 901, so that the temporary carrier board 900 can provide further support during the installation of the second chip 902. In other embodiments, the second chip 902 can also be installed after the temporary carrier board 900 is removed.

[0277] It should be noted that the stacked packaging structure of the present invention can be obtained by the preparation method of the present invention, or by other preparation methods.

[0278] Accordingly, embodiments of the present invention also provide an electronic device, which includes the stacked packaging structure of any of the foregoing embodiments. Because this stacked packaging structure has good heat dissipation performance, the operating performance of the electronic device including this stacked packaging structure is improved.

[0279] As an example, an electronic device may include any electronic product or device such as a mobile phone, tablet computer, laptop computer, camera, personal computer, in-vehicle equipment, wearable device, virtual reality device, augmented reality device, etc., or any intermediate product including the aforementioned packaging structure.

[0280] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A stacked packaging structure, characterized in that, include: The first and second line carrier boards are set relative to each other; A first chip is located between the first circuit board and the second circuit board. The first chip is disposed on the first circuit board and electrically connected to the first circuit board. The second chip is located between the first circuit board and the second circuit board. The second chip is disposed on the second circuit board and electrically connected to the second circuit board. The second chip is stacked with the first chip and thermally connected. The orthogonal projection area of ​​the second chip on the second circuit board is the chip mounting area. One or more heat sink structures penetrate the second circuit board of the chip mounting area, and the heat sink structures are thermally connected to the second chip.

2. The stacked packaging structure as described in claim 1, characterized in that, The number of heat sink structures is multiple, and the multiple heat sink structures are arranged in an array; or, the number of heat sink structures is multiple, and the multiple heat sink structures are non-closed concentric rings.

3. The stacked packaging structure as described in claim 1, characterized in that, The second chip has dummy solder pads facing the second circuit board; The stacked packaging structure further includes a first solder bump located between the dummy solder pad and the heat sink structure. The first solder bump is used to solder the second chip to the second circuit board and to achieve a thermally conductive connection between the second chip and the heat sink structure.

4. The stacked packaging structure as described in claim 3, characterized in that, The heat sink structure is recessed into the second circuit carrier on the end face facing the first circuit carrier, and the heat sink structure and the second circuit carrier form a notch. The first welding bump is also located in the recess.

5. The stacked packaging structure as described in claim 3, characterized in that, The second chip also has effective solder pads facing the second circuit carrier. The stacked package structure further includes a second solder bump located between the effective solder pads of the second chip and the second circuit carrier, and offset from the first solder bump. The second solder bump is used to solder the second chip to the second circuit carrier and realize the electrical connection between the second chip and the second circuit carrier. Wherein, the first welding bump and the second welding bump satisfy one or more of the following: The size of the first welding bump is larger than the size of the second welding bump; The thermal conductivity of the first welding bump is greater than that of the second welding bump. The rigidity of the first welding bump is greater than that of the second welding bump.

6. The stacked packaging structure as described in claim 3, characterized in that, The second chip also has effective solder pads facing the second circuit carrier. The stacked package structure further includes a second solder bump located between the effective solder pads of the second chip and the second circuit carrier, and offset from the first solder bump. The second solder bump is used to solder the second chip to the second circuit carrier and realize the electrical connection between the second chip and the second circuit carrier. The stacked packaging structure further includes a second bottom filler layer located between the second chip and the second circuit board, and also filling the gap between the second solder bump and the first solder bump. The material of the second bottom filler layer includes an epoxy resin-based material with a thermal conductivity greater than 1 watt per meter Kelvin.

7. The stacked packaging structure as described in any one of claims 3 to 6, characterized in that, The first welding bump includes one or more of a first type of welding bump and a second type of welding bump; The first type of welding bump is a conductive post with a solder cap, and the solder cap is located on the end face of the conductive post facing away from the second chip; The second type of welding bump includes a thermally conductive inner core and a solder layer covering the thermally conductive inner core. The thermal conductivity of the thermally conductive inner core is higher than that of the solder layer, and the melting point of the thermally conductive inner core is higher than that of the solder layer.

8. The stacked packaging structure as described in claim 7, characterized in that, The first type of solder bump includes a copper pillar with a tin cap, and the second type of solder bump includes a copper core tin ball.

9. The stacked packaging structure as described in claim 1, characterized in that, The heat sink structure is made of one or more of the following materials: copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene.

10. The stacked packaging structure as described in claim 1, characterized in that, The stacked packaging structure further includes a third welding bump located between the first chip and the first circuit board. The third welding bump is used to weld the first chip to the first circuit board and realize the electrical connection between the first chip and the first circuit board.

11. The stacked packaging structure as described in claim 1, characterized in that, The stacked packaging structure further includes a thermally conductive interface material layer, located between the first chip and the second chip, and in contact with both the first chip and the second chip.

12. The stacked packaging structure as described in claim 1, characterized in that, The packaging structure further includes a heat sink, located on the side of the second circuit board facing away from the first circuit board, and thermally connected to the heat sink structure.

13. The stacked packaging structure as described in claim 1, characterized in that, The packaging structure further includes: a first conductive connection structure located between the first circuit board and the second circuit board, wherein the first conductive connection structure is located on the first circuit board on the side of the first chip and is electrically connected to the first circuit board. The second conductive connection structure is located between the first circuit board and the second circuit board. The second conductive connection structure is located on the second circuit board on the side of the second chip and is electrically connected to the second circuit board. The second conductive connection structure is connected to the first conductive connection structure.

14. The stacked packaging structure as described in claim 13, characterized in that, The stacked packaging structure further includes: a molding layer located on the first circuit board on the side of the first chip and the first conductive connection structure, the molding layer covering the sidewalls of the first chip and the first conductive connection structure, and exposing the end face of the first conductive connection structure facing away from the first circuit board, the surface of the first chip facing away from the first circuit board, and the second conductive connection structure.

15. The stacked packaging structure as described in claim 13, characterized in that, The first conductive connection structure is a conductive post, and the second conductive connection structure is a solder ball.

16. The stacked packaging structure as described in claim 1, characterized in that, The stacked packaging structure further includes a third conductive connection structure located on the surface of the first circuit board facing away from the second circuit board and electrically connected to the first circuit board.

17. An electronic device, characterized in that, Includes the packaging structure as described in any one of claims 1 to 16.

18. A method for fabricating a stacked packaging structure, characterized in that, include: A first chip is disposed on the first side of the first circuit carrier board, and the first chip is electrically connected to the first circuit carrier board. A second circuit board with one or more heat sink structures is obtained, wherein the heat sink structures are located in the chip mounting area of ​​the second circuit board and penetrate the second circuit board, and the chip mounting area is used to mount a second chip. A second chip is disposed on the second side of the second circuit board. The second chip is located in the chip mounting area and is electrically connected to the second circuit board. The second chip is thermally connected to the heat sink structure. After the first chip is disposed on the first circuit board and the second chip is disposed on the second circuit board, the first surface and the second surface are disposed opposite to each other, and the first chip and the second chip are stacked to make the first chip and the second chip thermally connected.

19. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, In the step of obtaining a second circuit carrier board having one or more heat sink structures, the number of heat sink structures is multiple, and the multiple heat sink structures are arranged in an array; or, the number of heat sink structures is multiple, and the multiple heat sink structures are non-closed concentric loops.

20. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, The second chip has dummy pads exposed on the bonding surface, which is used to bond the second chip to the second circuit carrier. The step of setting the second chip on the second circuit carrier includes: forming a first solder bump on the dummy solder pad; making the bonding surface of the second chip face the second circuit carrier; and soldering the first solder bump to the heat sink structure to achieve a thermally conductive connection between the second chip and the heat sink structure.

21. The method for fabricating the stacked packaging structure as described in claim 20, characterized in that, In the step of obtaining a second circuit carrier board with one or more heat sink structures, the end face of the heat sink structure located on one side of the second surface of the second circuit carrier board is recessed into the second surface, and the heat sink structure and the second circuit carrier board form a notch. In the step of welding the first welding bump to the heat sink structure, the first welding bump is also located in the recess.

22. The method for fabricating the stacked packaging structure as described in claim 20, characterized in that, The second chip also has effective solder pads exposed on the bonding surface; The step of setting the second chip on the second circuit board further includes: forming a second solder bump on the effective solder pad, wherein the second solder bump is offset from the first solder bump; during the process of soldering the first solder bump to the heat sink structure, the second solder bump is soldered to the second circuit board to realize the electrical connection between the second chip and the second circuit board. Wherein, the first welding bump and the second welding bump satisfy one or more of the following: The size of the first welding bump is larger than the size of the second welding bump; The thermal conductivity of the first welding bump is greater than that of the second welding bump. The rigidity of the first welding bump is greater than that of the second welding bump.

23. The method for preparing the stacked packaging structure according to any one of claims 20 to 22, characterized in that, The first welding bump includes one or more of a first type of welding bump and a second type of welding bump; The first type of welding bump is a conductive post with a solder cap, and the solder cap is located on the end face of the conductive post facing away from the second chip; The second type of welding bump includes a thermally conductive inner core and a solder layer covering the thermally conductive inner core. The thermal conductivity of the thermally conductive inner core is higher than that of the solder layer, and the melting point of the thermally conductive inner core is higher than that of the solder layer.

24. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, In the step of obtaining a second circuit board having one or more heat sink structures, the material of the heat sink structure includes one or more of copper, aluminum, iron, tungsten, molybdenum, diamond, and graphene.

25. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, The step of obtaining a second circuit carrier board having one or more heat sink structures includes: providing a second circuit carrier board in which the heat sink structure is pre-prepared; Alternatively, the step of obtaining a second circuit carrier board having one or more heat sink structures includes: providing a second circuit carrier board; forming a through-hole in the chip mounting area of ​​the second circuit carrier board; and setting a heat sink structure in the through-hole.

26. The method for fabricating the stacked packaging structure as described in claim 25, characterized in that, Before forming a through-hole penetrating the second circuit carrier, the preparation method further includes: temporarily bonding the second circuit carrier to a temporary carrier, with the second side facing away from the temporary carrier; After the heat sink structure is placed in the through hole, the preparation method further includes: performing debonding to remove the temporary carrier plate.

27. The method for fabricating the stacked packaging structure as described in claim 26, characterized in that, The step of setting the heat sink structure in the through hole includes: filling the through hole with a thermally conductive material to form a heat sink structure.

28. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, Before stacking the first chip and the second chip, the fabrication method further includes: forming a thermally conductive interface material layer on the surface of the first chip facing away from the first circuit substrate or on the surface of the second chip facing away from the second circuit substrate; In the step of stacking the first chip and the second chip, both the first chip and the second chip are in contact with the thermally conductive interface material layer.

29. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, Before stacking the first chip and the second chip, the fabrication method further includes: A first conductive connection structure is provided on a first side of the first circuit carrier board. The first conductive connection structure is electrically connected to the first circuit carrier board. After the first conductive connection structure and the first chip are provided on the first side, the first conductive connection structure is located on the side of the first chip. A second conductive connection structure is provided on the second side of the second circuit carrier, the second conductive connection structure is located on the side of the chip mounting area, and the second conductive connection structure is electrically connected to the second circuit carrier. In the step of stacking the first chip and the second chip, the second conductive connection structure is soldered to the corresponding first conductive connection structure.

30. The method for fabricating the stacked packaging structure as described in claim 29, characterized in that, After the first conductive connection structure and the first chip are disposed on the first surface, and before the first chip and the second chip are stacked, the fabrication method further includes: forming a molding compound on the first surface of the first circuit substrate, the molding compound covering the sidewalls of the first chip and the first conductive connection structure, and exposing the end face of the first conductive connection structure facing away from the first circuit substrate and the surface of the first chip facing away from the first circuit substrate.

31. The method for fabricating the stacked packaging structure as described in claim 29, characterized in that, The first conductive connection structure is a conductive post, and the second conductive connection structure is a solder ball.

32. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, The step of setting the first chip on the first side of the first circuit carrier includes: soldering the first chip onto the first circuit carrier using a flip-chip bonding process; The step of setting the second chip on the second side of the second circuit carrier includes: soldering the second chip onto the second circuit carrier using a flip-chip bonding process.

33. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, After stacking the first chip and the second chip, the fabrication method further includes: setting a heat sink on the third side of the second circuit board, wherein the heat sink is thermally connected to the heat sink structure, and the third side is disposed opposite to the second side.

34. The method for fabricating the stacked packaging structure as described in claim 18, characterized in that, After stacking the first chip and the second chip, the fabrication method further includes: forming a third conductive connection structure on the fourth side of the first circuit carrier, wherein the third conductive connection structure is electrically connected to the first circuit carrier, and the fourth side is disposed opposite to the first side.

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