Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of suppressing noise during switching. In the semiconductor device, a first end of a first transistor on a first lead frame is connected to the first lead frame, and a first end of a second transistor on a second lead frame is connected to a third lead frame. The first end and the second end of a third transistor on the third lead frame are connected to the third lead frame and the second end of the first transistor respectively, and the first end and the second end of a fourth transistor on the second lead frame are connected to the second lead frame and the second end of the second transistor respectively. The first end and the second end of the capacitor are respectively connected to the first lead frame and the second lead frame, the sealing resin seals the first transistor, the second transistor, the third transistor and the fourth transistor and the capacitor, the first transistor and the second transistor are GaN transistors, the third transistor and the fourth transistor are MOS transistors, and the first transistor, the third transistor, the second transistor and the fourth transistor are sequentially arranged.

Description

[0001] Reference to relevant applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-082659 (filed on May 21, 2024). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] Power semiconductors containing GaN transistors, which utilize gallium nitride (GaN), are known. GaN transistors enable high-speed switching and are used in power conversion devices. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device capable of suppressing noise during switching.

[0006] The semiconductor device of the embodiment includes: a first lead frame, a second lead frame, and a third lead frame; a first transistor disposed on the first lead frame and having a first end electrically connected to the first lead frame; a second transistor disposed on the second lead frame and having a first end electrically connected to the third lead frame; a third transistor disposed on the third lead frame and having a first end electrically connected to the third lead frame and a second end electrically connected to the second end of the first transistor; a fourth transistor disposed on the second lead frame and having a first end electrically connected to the second lead frame and a second end electrically connected to the second end of the second transistor; a capacitor having a first end electrically connected to the first lead frame and a second end electrically connected to the second lead frame; and a sealing resin for sealing the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor, wherein the first transistor and the second transistor are GaN transistors, and the third transistor and the fourth transistor are MOS transistors, and the first transistor, the third transistor, the second transistor, and the fourth transistor are arranged sequentially in a first direction. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a semiconductor device in an implementation.

[0008] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a semiconductor device in an embodiment.

[0009] Figure 3 This is a perspective view showing an example of the internal structure of a semiconductor device according to an embodiment.

[0010] Figure 4This is a top view showing an example of the planar layout of a semiconductor device according to an embodiment.

[0011] Figure 5 This is a diagram showing the main flow path of the high-frequency components of the current in the semiconductor device of the embodiment.

[0012] Figure 6 This is a diagram showing the main flow path of the DC component of the current in the semiconductor device of the embodiment.

[0013] Figure 7 This is a top view showing an example of the planar layout of a semiconductor device according to a first variation of the embodiment.

[0014] Figure 8 This is a top view showing an example of the planar layout of a semiconductor device according to a second variation of the embodiment. Detailed Implementation

[0015] The embodiments are described below with reference to the accompanying drawings. In the following description, constituent elements having substantially the same function and structure are labeled with the same reference numerals.

[0016] In the following description, the first element is "connected to" the second element. The first element includes being connected to the second element indirectly, either always or selectively, via an intermediate element that is conductive, or being connected to the second element directly without via an intermediate element.

[0017] Hereinafter, power semiconductors will be described as examples of semiconductor devices used in implementation. Power semiconductors are used, for example, in power conversion devices such as inverters and converters.

[0018] First, use Figure 1 The configuration of the semiconductor device in the embodiment will be described. Figure 1 This is a block diagram illustrating an example of the configuration of a semiconductor device in an implementation.

[0019] Semiconductor device 1 includes a configuration that integrates multiple semiconductor chips into a single package. For example... Figure 1 As shown, the semiconductor device 1 includes a switching unit 10 and a control unit 50. The switching unit 10 converts and outputs input signals by switching. For example, it converts input direct current (DC) into alternating current (AC) and outputs it. The control unit 50 controls the switching operation of the switching unit 10.

[0020] Next, use Figure 2 The circuit configuration of the semiconductor device in the embodiment will be described. Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a semiconductor device in an embodiment.

[0021] like Figure 2 As shown, the switching unit 10 includes terminals P, N, and OUT, a high-side transistor HTr, a low-side transistor LTr, and a capacitor 41. The control unit 50 includes control circuits 51 and 52.

[0022] Terminals P and N are input terminals. Terminal P is connected to the positive terminal of an external DC power supply (P: Positive terminal). Terminal N is connected to the negative terminal of an external DC power supply (N: Negative terminal).

[0023] Terminal OUT is the output terminal. Semiconductor device 1 outputs current to external devices through terminal OUT.

[0024] One end of the high-side transistor HTr and one end of the low-side transistor LTr are connected in series via node N1. The other end of the high-side transistor HTr is connected to terminal P. The other end of the low-side transistor LTr is connected to terminal N. Terminal OUT is also connected to node N1. Thus, the high-side transistor HTr and the low-side transistor LTr constitute a half-bridge circuit. Semiconductor device 1 is a package containing the half-bridge circuit.

[0025] The high-side transistor HTr includes GaN transistor 21 and MOS transistors 31 and 32. The low-side transistor LTr includes GaN transistor 22 and MOS transistors 33 and 34.

[0026] GaN transistors 21 and 22 are, for example, GaN-HEMTs (High Electron Mobility Transistors) using gallium nitride (GaN). GaN transistors 21 and 22 have normally-on characteristics. That is, when the potential difference between the gate and source is 0V, the drain terminal is electrically connected to the source terminal.

[0027] MOS transistors 31, 32, 33, and 34 are, for example, silicon MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). MOS transistors 31, 32, 33, and 34 include P-type MOSFETs. MOS transistors 31, 32, 33, and 34 have normally-off characteristics; that is, when the potential difference between the gate and source is 0V, the drain terminal is electrically insulated from the source terminal. The gate threshold voltages of MOS transistors 31 and 32 are approximately equal. The gate threshold voltages of MOS transistors 33 and 34 are approximately equal.

[0028] The high-side transistor HTr has a configuration of GaN transistor 21 and parallel-connected MOS transistors 31 and 32 connected in series via node N2.

[0029] The drain terminal of GaN transistor 21 is connected to terminal P. The source terminal of GaN transistor 21 is connected to node N2. The gate terminal of GaN transistor 21 is connected to control circuit 51.

[0030] The drain terminals of MOS transistors 31 and 32 are connected to node N1. The source terminals of MOS transistors 31 and 32 are connected to node N2. The gate terminals of MOS transistors 31 and 32 are connected to control circuit 51.

[0031] The low-side transistor LTr has a configuration of GaN transistor 22 and parallel-connected MOS transistors 33 and 34 connected in series via node N3.

[0032] The drain terminal of GaN transistor 22 is connected to node N1. The source terminal of GaN transistor 22 is connected to node N3. The gate terminal of GaN transistor 22 is connected to control circuit 52.

[0033] The drain terminals of MOS transistors 33 and 34 are connected to terminal N. The source terminals of MOS transistors 33 and 34 are connected to node N3. The gate terminals of MOS transistors 33 and 34 are connected to control circuit 52.

[0034] The capacitor 41 has a first terminal connected to terminal P and a second terminal connected to terminal N. That is, the capacitor 41 is connected in parallel with the high-side transistor HTr and the low-side transistor LTr, which are connected in series.

[0035] Control circuits 51 and 52 are, for example, gate driver circuits. Control circuit 51 controls the driving of the high-side transistor HTr. Control circuit 52 controls the driving of the low-side transistor LTr. Alternatively, in this embodiment, different control circuits 51 and 52 are used to control the high-side transistor HTr and the low-side transistor LTr respectively, but a common control circuit can also be used.

[0036] The control circuit 51 includes a GaN gate control terminal 51a, a MOS gate control terminal 51b, and a source control terminal 51c. The GaN gate control terminal 51a is connected to the gate of the GaN transistor 21. The GaN gate control terminal 51a controls the driving of the GaN transistor 21 according to the applied gate voltage. The MOS gate control terminal 51b is connected to the gates of MOS transistors 31 and 32. The MOS gate control terminal 51b controls the driving of MOS transistors 31 and 32 according to the applied gate voltage. Furthermore, the gate voltages applied to the gates of MOS transistors 31 and 32 are approximately the same. The source control terminal 51c is connected to node N2. The source control terminal 51c serves, for example, as a reference potential terminal that determines the voltages applied to the GaN gate control terminal 51a and the MOS gate control terminal 51b.

[0037] The control circuit 52 includes a GaN gate control terminal 52a, a MOS gate control terminal 52b, and a source control terminal 52c. The GaN gate control terminal 52a is connected to the gate of the GaN transistor 22. The GaN gate control terminal 52a controls the driving of the GaN transistor 22 according to the applied gate voltage. The MOS gate control terminal 52b is connected to the gates of MOS transistors 33 and 34. The MOS gate control terminal 52b controls the driving of MOS transistors 33 and 34 according to the applied gate voltage. Furthermore, the gate voltages applied to the gates of MOS transistors 33 and 34 are approximately the same. The source control terminal 52c is connected to node N3. The source control terminal 52c serves, for example, as a reference potential terminal that determines the voltages applied to the GaN gate control terminal 52a and the MOS gate control terminal 52b.

[0038] Next, use Figure 3 as well as Figure 4 The internal structure of the switching section in the semiconductor device of the embodiment will be described.

[0039] Figure 3 This is a perspective view showing an example of the internal structure of a semiconductor device according to an embodiment. Figure 4 This is a top view illustrating an example of the planar layout of a semiconductor device according to an embodiment. Additionally, in Figure 3 as well as Figure 4 The control section 50 is omitted in the text.

[0040] like Figure 3 as well as Figure 4 As shown, the semiconductor device 1 also includes lead frames 11, 12 and 13, wirings 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73 and 74, and electrodes 81, 82 and 83.

[0041] Lead frames 11, 12, and 13 are flat conductive bodies disposed in a substantially homogeneous plane. Each of lead frames 11 and 12 has a substantially L-shaped form. Specifically, lead frame 11 includes a first portion 11-1 and a second portion 11-2 extending in substantially orthogonal directions. Lead frame 12 includes a third portion 12-1 and a fourth portion 12-2 extending in substantially orthogonal directions. Lead frames 11 and 12 are configured in a substantially U-shaped form. Specifically, the ends of the second portion 11-2 and the fourth portion 12-2 of lead frames 11 and 12 are opposite each other and separately arranged. Lead frame 13 has a substantially rectangular shape. Lead frame 13 is separately arranged between the first portion 11-1 and the third portion 12-1.

[0042] The planes on which lead frames 11, 12, and 13 are configured are defined as the XY plane. The direction in which the first part 11-1 and the third part 12-1 extend is defined as the X direction. The direction in which the second part 11-2 and the fourth part 12-2 extend is defined as the Y direction. The direction intersecting the XY plane and in which GaN transistors 21 and 22, MOS transistors 31, 32, 33 and 34, and capacitor 41 are positioned when viewed from lead frames 11, 12, and 13 is defined as the Z direction or the upward direction. The direction opposite to the Z direction is defined as the downward direction.

[0043] Capacitor 41 is, for example, a chip-type MLCC (Multi-Layer Ceramic Capacitor). Capacitor 41 is configured to span between the second portion 11-2 and the fourth portion 12-2 in the Y direction. The first end of capacitor 41 is connected to the upper surface of the second portion 11-2. The second end of capacitor 41 is connected to the upper surface of the fourth portion 12-2. Additionally, in... Figure 3 as well as Figure 4 In the example, there are two capacitors 41, but there can be more than one capacitor 41.

[0044] The GaN transistor 21 is, for example, rectangular in shape. The GaN transistor 21 is disposed on the upper surface of the first portion 11-1 with its length direction along the X direction. The GaN transistor 21 includes, for example, a drain terminal, a source terminal, and a gate terminal on its upper surface. The source terminal of the GaN transistor 21 is disposed on the upper surface of the GaN transistor 21, for example, extending along the long side of the lead frame 13. The drain terminal of the GaN transistor 21 is disposed on the upper surface of the GaN transistor 21, for example, extending along the long side opposite to the source terminal.

[0045] GaN transistor 22, for example, has a rectangular shape. GaN transistor 22 is disposed on the upper surface of the third portion 12-1 with its length along the X direction. GaN transistor 22 includes, for example, a drain terminal, a source terminal, and a gate terminal on its upper surface. The drain terminal of GaN transistor 22 is disposed on the upper surface of GaN transistor 22, for example, extending along the long side of the lead frame 13. The source terminal of GaN transistor 22 is disposed on the upper surface of GaN transistor 22, for example, extending along the long side opposite to the drain terminal. GaN transistors 21 and 22 are configured such that the centers of their respective drain terminals in the X direction are aligned in a straight line in the Y direction.

[0046] The MOS transistor 31 is, for example, rectangular in shape. The length of the MOS transistor 31 in its longitudinal direction is, for example, shorter than the lengths of the GaN transistors 21 and 22 in their longitudinal directions. The MOS transistor 31 is disposed on the upper surface of the lead frame 13 such that its length is along the X-direction and it is sandwiched between the GaN transistors 21 and 22 in the Y-direction. The MOS transistor 31 has, for example, a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of the MOS transistor 31 is connected to the lead frame 13.

[0047] MOS transistor 32 is, for example, rectangular in shape. The length of MOS transistor 32 in the longitudinal direction is approximately equal to the length of the short side of MOS transistor 31. MOS transistor 32 is disposed on the upper surface of lead frame 13 such that its length is along the Y direction and it is sandwiched between GaN transistors 21 and 22 in the Y direction, and sandwiched between MOS transistor 31 and capacitor 41 in the X direction. MOS transistor 32 has a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of MOS transistor 32 is connected to lead frame 13.

[0048] The MOS transistor 33 is, for example, rectangular in shape. The length of the MOS transistor 33 in the longitudinal direction is, for example, shorter than the lengths of the GaN transistors 21 and 22 in the longitudinal direction. The MOS transistor 33 is disposed on the upper surface of the third portion 12-1, sandwiching the GaN transistor 22 in the Y direction along with the MOS transistor 31. That is, the GaN transistor 21, MOS transistor 31, GaN transistor 22, and MOS transistor 32 are arranged in a straight line in the Y direction. The MOS transistor 33 has, for example, a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of the MOS transistor 33 is connected to the third portion 12-1.

[0049] MOS transistor 34 is, for example, rectangular in shape. The length of MOS transistor 34 in the longitudinal direction is approximately equal to the length of the short side of MOS transistor 33. MOS transistor 34 is disposed on the upper surface of the fourth portion 12-2 such that its length is along the Y direction, it is arranged with GaN transistor 22 in the X direction, and it is also arranged with capacitor 41 in the Y direction. MOS transistor 34 has, for example, a drain terminal on its lower surface and a source terminal and a gate terminal on its upper surface. The drain terminal of MOS transistor 34 is connected to the fourth portion 12-2.

[0050] Wiring 61 includes, for example, multiple bonding lines. Each bonding line in wiring 61 extends along the Y direction and connects the first portion 11-1 at one end and the drain terminal of the GaN transistor 21 at the other end. The other ends of the bonding lines in wiring 61 are positioned near the center of the drain terminal of the GaN transistor 21 without deviating in the X direction.

[0051] Wiring 62 includes, for example, multiple bonding lines. These bonding lines extend along the Y direction and connect the GaN transistor 21 with one end connected to the source terminal of the GaN transistor 21 and the MOS transistor 31 with the other end connected to the source terminal of the MOS transistor 31. One end of each bonding line in wiring 62 is positioned near the center of the source terminal of the GaN transistor 21, with minimal deviation in the X direction.

[0052] Wiring 63 includes, for example, a bonding wire. Wiring 63 extends along the Y direction, connecting the two terminals, with one end connected to the source terminal of GaN transistor 21 and the other end connected to the source terminal of MOS transistor 32.

[0053] Wiring 64 includes, for example, a bonding wire. One end of wiring 64 is connected to the gate terminal of GaN transistor 21, and the other end is connected to the GaN gate control terminal 51a of control circuit 51, thus connecting the two.

[0054] Wiring 65 includes, for example, multiple bonding lines. One end of each bonding line in wiring 65 is connected to the source terminal of GaN transistor 21, and the other end is connected to the source control terminal 51c of control circuit 51, thus connecting the two. Alternatively, one end of each bonding line in wiring 65 may replace the source terminal of GaN transistor 21 and be connected to the source terminal of MOS transistor 31.

[0055] Wiring 66 is, for example, a bonding wire. One end of wiring 66 is connected to the gate terminal of MOS transistor 31, and the other end is connected to the MOS gate control terminal 51b of control circuit 51, thus connecting the two.

[0056] Wiring 67 includes, for example, a bonding wire. One end of wiring 67 is connected to the gate terminal of MOS transistor 32, and the other end is connected to the MOS gate control terminal 51b of control circuit 51, thus connecting the two. Alternatively, the other end of wiring 67 may replace the MOS gate control terminal 51b of control circuit 51 and be connected to the gate terminal of MOS transistor 31.

[0057] Wiring 68 includes, for example, multiple bonding lines. Each bonding line in wiring 68 extends along the Y direction, connecting one end to the lead frame 13 and the other end to the drain terminal of the GaN transistor 22. For example, one of the bonding lines in wiring 68 is positioned such that it is sandwiched between the GaN transistor 22 and the MOS transistor 32 in the Y direction. The other ends of the bonding lines in wiring 68, except for the bonding line sandwiched between the GaN transistor 22 and the MOS transistor 32 in the Y direction, are positioned near the center of the drain terminal of the GaN transistor 22, with minimal deviation in the X direction.

[0058] Wiring 69 includes, for example, multiple bonding lines. These bonding lines extend along the Y direction, connecting the GaN transistor 22 at one end and the MOS transistor 33 at the other. One end of each bonding line is positioned near the center of the source terminal of the GaN transistor 22, with minimal deviation in the X direction.

[0059] Wiring 70 is, for example, a bonding wire. Wiring 70 extends along the X direction, connecting the two with one end connected to the source terminal of GaN transistor 22 and the other end connected to the source terminal of MOS transistor 34.

[0060] Wiring 71 includes, for example, a bonding wire. One end of wiring 71 is connected to the gate terminal of GaN transistor 22, and the other end is connected to the GaN gate control terminal 52a of control circuit 52, thus connecting the two.

[0061] Wiring 72 includes, for example, multiple bonding lines. One end of each bonding line in wiring 72 is connected to the source terminal of the MOS transistor 33, and the other end is connected to the source control terminal 52c of the control circuit 52, thus connecting the two. Alternatively, one end of each bonding line in wiring 72 may replace the source terminal of the MOS transistor 33 and be connected to the source terminal of the GaN transistor 22.

[0062] Wiring 73 includes, for example, a bonding wire. One end of wiring 73 is connected to the gate terminal of MOS transistor 33, and the other end is connected to the MOS gate control terminal 52b of control circuit 52, thus connecting the two.

[0063] Wiring 74 includes, for example, a bonding wire. One end of wiring 74 is connected to the gate terminal of MOS transistor 34, and the other end is connected to the MOS gate control terminal 52b of control circuit 52, thus connecting the two. Alternatively, the other end of wiring 74 may replace the MOS gate control terminal 52b of control circuit 52 and be connected to the gate terminal of MOS transistor 33.

[0064] In addition, from the viewpoint of suppressing ringing (Japanese: リンギング) as described later, wiring 61, 62, 63, 68, 69 and 70 are preferably set to approximately the shortest distance.

[0065] Electrodes 81, 82, and 83 are plate-shaped conductors disposed on the lower surface of the semiconductor device 1. Electrodes 81, 82, and 83 function as terminals for electrically connecting external devices and internal circuitry of the semiconductor device 1.

[0066] Electrode 81 is configured to be connected to the lower surface of lead frame 11. Electrode 81 is connected to the positive terminal of an external DC power supply. That is, electrode 81 functions as terminal P.

[0067] Electrode 82 is configured to be in contact with the lower surface of lead frame 12. Electrode 82 is connected to the negative terminal of an external DC power supply. That is, electrode 82 functions as terminal N.

[0068] Electrode 83 is configured to be in contact with the lower surface of lead frame 13. Electrode 83 functions as an output terminal, through which current is output from semiconductor device 1 to external devices. That is, electrode 83 has the function of terminal OUT.

[0069] Furthermore, the semiconductor device 1 has a frame structure sealed with a sealing resin (not shown). The sealing resin seals the switch section 10 and the control section 50, insulating unconnected conductors within the semiconductor device 1. Additionally, the sealing resin protects the components of the semiconductor device 1 from physical interference.

[0070] According to the configuration of this embodiment, the half-bridge circuit and capacitor 41 can be integrated into a single package. Consequently, the path of the current flowing in a loop through the half-bridge circuit and capacitor 41 during switching can be shortened. Therefore, noise generated during switching, accompanied by ringing, can be suppressed. This will be described in detail below.

[0071] Compared to transistors using silicon (Si), power semiconductors using GaN transistors are characterized by their ability to perform high-speed switching. Therefore, the switching frequency increases, and inductors for inductor correction are not required, thus enabling miniaturization and high efficiency in packaging.

[0072] On the other hand, due to the high switching speed, ringing is easily generated during switching. This ringing becomes a noise source, and the noise may be superimposed on the output signal. Noise degrades the quality of the transmitted signal, increasing the possibility of outputting unwanted signals and the possibility of damage to peripheral components, which is therefore undesirable.

[0073] In power semiconductors using GaN transistors and MOS transistors, when the GaN transistor switches, its output capacitor is charged, thus supplying a high-frequency component of the current from the high-voltage side of the capacitor. This high-frequency current flows through the GaN transistor and MOS transistor and returns to the low-voltage side of the capacitor. If the inductance (hereinafter referred to as loop inductance) in this path is large, ringing occurs accompanying the high-speed switching of the GaN transistor, adding noise to the output signal.

[0074] One method for suppressing noise is to reduce the loop inductance. A smaller loop inductance can suppress ringing and thus reduce noise generation. Since inductance increases proportionally to the path length of the current, the loop inductance can be reduced by shortening the path through which the high-frequency components of the current flow.

[0075] On the other hand, by simply shortening the distance between each transistor and the capacitor, the DC component of the current flowing through the GaN transistor becomes uneven, potentially leading to areas of current concentration. If the current concentrates, localized heat generation can occur, potentially degrading the reliability of the chip and the circuitry.

[0076] In this embodiment, the half-bridge circuit and capacitor 41 are integrated into a single package. This configuration eliminates the need for terminals and wiring to connect individual packages, reducing current paths and thus lowering loop inductance and suppressing noise generation.

[0077] Furthermore, in this embodiment, two MOS transistors are connected in parallel for each GaN transistor. With this configuration, the main current paths for the high-frequency and DC components can be separated. For this purpose, [the following is used...] Figure 5 as well as Figure 6 Please provide an explanation.

[0078] Figure 5 This is a diagram showing the main flow path of the high-frequency components of the current in the semiconductor device of the embodiment. Figure 6 This is a diagram showing the main flow path of the DC component of the current in the semiconductor device of the embodiment. Figure 5 as well as Figure 6 In Figure 4 In the planar layout of the semiconductor device shown, arrows indicate the main current flow paths.

[0079] The high-frequency components of the current flow in a path where the loop inductance decreases. That is, the loop that becomes the shortest path becomes the path for the high-frequency components of the current. Therefore, as... Figure 5 As shown, the high-frequency component of the current mainly flows from the first end of capacitor 41 through lead frame 11, wiring 61, GaN transistor 21, wiring 63, MOS transistor 32, lead frame 13, wiring 68, GaN transistor 22, wiring 70, MOS transistor 34, and lead frame 12, to the second end of capacitor 41. Furthermore, when wiring 61 and 68 include multiple bonding lines, the current flows through the bonding line with the shortest path, i.e., the bonding line located closest to capacitor 41.

[0080] On the other hand, such as Figure 6 As shown, the DC component of the current mainly flows from the electrode 81 connected to the lower surface of the lead frame 11 through the lead frame 11, wiring 61, GaN transistor 21, wiring 62, MOS transistor 31, lead frame 13, wiring 68, GaN transistor 22, wiring 69, MOS transistor 33 and lead frame 12, and flows to the electrode 82 connected to the lower surface of the lead frame 12.

[0081] By dividing the main flow paths of the high-frequency and DC components of the current, the flow path of the high-frequency components can be shortened. This reduces loop inductance and suppresses noise. Furthermore, in the DC component flow path, GaN transistors 21 and 22, and MOS transistors 31 and 33 are arranged in a straight line, and the wiring connecting the transistors is positioned near the center of the drain or source terminals without deviation in the X-direction. Therefore, current can flow approximately uniformly through GaN transistors 21 and 22, and MOS transistors 31 and 33, suppressing reliability degradation caused by current concentration.

[0082] The semiconductor device described above can be modified in various ways.

[0083] Figure 7 This is a top view illustrating an example of the planar layout of a semiconductor device according to a first variation of the embodiment. Additionally, in Figure 7 The control unit 50 and the sealing resin are omitted in the text.

[0084] exist Figure 7 In the first variation shown, MOS transistor 32 and wiring 63 and 67 are not included. Instead of MOS transistor 31, MOS transistor 31A is included. MOS transistor 31A has a structure that is longer than MOS transistor 31 in the length direction. The configuration and connection relationship of MOS transistor 31A are the same as those of MOS transistor 31 in the embodiment.

[0085] MOS transistor 31A extends along the X direction to the region where MOS transistor 32 is disposed in the embodiment. Thus, MOS transistor 31A can complement the effect of MOS transistor 32, which forms the flow path for the high-frequency components of the current in the embodiment. Specifically, the high-frequency components of the current mainly flow from the first end of capacitor 41 sequentially through lead frame 11, wiring 61, GaN transistor 21, wiring 62, MOS transistor 31A, lead frame 13, wiring 68, GaN transistor 22, wiring 70, MOS transistor 34, and lead frame 12 to the second end of capacitor 41. Furthermore, when wirings 61, 62, and 68 include multiple bonding lines, the current flows through the bonding line with the shortest flow path, i.e., the bonding line located closest to capacitor 41.

[0086] According to the configuration of the first modified example, similar to the embodiment, the flow path of the high-frequency components of the current can be shortened. Therefore, loop inductance can be reduced and noise can be suppressed.

[0087] Figure 8 This is a top view illustrating an example of the planar layout of a semiconductor device according to a second variation of the embodiment. Additionally, in Figure 8 The control unit 50 and the sealing resin are omitted in the text.

[0088] exist Figure 8 In the second variation shown, wiring 61B is included instead of the bonding line located closest to capacitor 41 among the plurality of bonding lines contained in wiring 61. Wiring 61B includes, for example, a bonding line. One end of wiring 61B is connected to the second portion 11-2, and the other end is connected to the drain terminal of GaN transistor 21, extending from the drain terminal of GaN transistor 21 toward capacitor 41.

[0089] Wiring 61B serves as the flow path for the high-frequency component of the current primarily output from the first terminal of capacitor 41 to the drain terminal of GaN transistor 21.

[0090] According to the configuration of the second modification, the flow path of the high-frequency components of the current can be shortened. Therefore, the loop inductance can be reduced, and noise can be suppressed.

[0091] In addition to the variations shown above, various other variations can be considered. For example, it is also possible to replace part or all of the bonding wires included in wiring 61 to 74 with clip-on connectors.

[0092] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0093] Explanation of reference numerals in the attached figures

[0094] 1…Semiconductor devices,

[0095] 10… Switch section,

[0096] 11, 12, 13…leader frames,

[0097] 11-1… Part One,

[0098] 11-2… Part Two,

[0099] 12-1… Part Three,

[0100] 12-2… Part Four,

[0101] 21, 22…GaN transistors,

[0102] 31, 31A, 32, 33, 34… MOS transistors,

[0103] 41…capacitor,

[0104] 50…Control Department,

[0105] 51, 52… control circuits,

[0106] 51a, 52a…GaN gate control terminals,

[0107] 51b, 52b… MOS gate control terminals,

[0108] 51c, 52c... source control terminals,

[0109] Wiring for numbers 61, 61B, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74…

[0110] Electrodes 81, 82, 83…

[0111] P, N, OUT... terminals.

Claims

1. A semiconductor device, characterized in that, have: First lead frame, second lead frame and third lead frame; A first transistor is disposed on the first lead frame and has a first end electrically connected to the first lead frame; The second transistor is disposed on the second lead frame and has a first end electrically connected to the third lead frame; A third transistor is disposed on the third lead frame and has a first end electrically connected to the third lead frame and a second end electrically connected to the second end of the first transistor; A fourth transistor is disposed on the second lead frame and has a first end electrically connected to the second lead frame and a second end electrically connected to the second end of the second transistor; A capacitor having a first end electrically connected to the first lead frame and a second end electrically connected to the second lead frame; as well as A sealing resin is used to seal the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor. The first transistor and the second transistor are GaN transistors. The first transistor, the third transistor, the second transistor, and the fourth transistor are arranged sequentially in a first direction.

2. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor are GaN-HEMT.

3. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor have normally-on characteristics.

4. The semiconductor device according to claim 1, characterized in that, The third transistor and the fourth transistor are MOSFETs, i.e., metal-oxide-semiconductor field-effect transistors.

5. The semiconductor device according to claim 1, characterized in that, The third transistor and the fourth transistor have normally-off characteristics.

6. The semiconductor device according to claim 1, characterized in that, The first lead frame is connected to the first terminal of the first transistor via a plurality of bonding wires. The plurality of bonding lines includes a first line and a second line extending in a direction different from the first line. The second line connects the first terminal of the first transistor and the first terminal of the capacitor with a shorter distance than the first line.

7. The semiconductor device according to claim 1, characterized in that, It also includes a control circuit for controlling the driving of the first transistor, the second transistor, the third transistor, and the fourth transistor. The control circuit is sealed by the sealing resin.

8. The semiconductor device according to claim 1, characterized in that, It also includes a fifth transistor disposed on the second lead frame, having a first terminal electrically connected to the second lead frame, a second terminal electrically connected to the second terminal of the second transistor, and a gate terminal electrically connected to the gate terminal of the fourth transistor. The capacitors are arranged on the first lead frame and the second lead frame in a second direction intersecting the first direction with the third transistor. The fifth transistor is arranged in the second direction on the side of the capacitor closer to the second transistor.

9. The semiconductor device according to claim 8, characterized in that, The fifth transistor is a MOSFET, or metal-oxide-semiconductor field-effect transistor.

10. The semiconductor device according to claim 8, characterized in that, The fifth transistor has normally-off characteristics.

11. The semiconductor device according to claim 8, characterized in that, The threshold voltage of the fifth transistor is approximately the same as that of the fourth transistor.

12. The semiconductor device according to claim 8, characterized in that, The first lead frame is connected to the first terminal of the first transistor via a plurality of bonding wires. The plurality of bonding lines includes a first line and a second line extending in a direction different from the first line. The second line connects the first terminal of the first transistor and the first terminal of the capacitor with a shorter distance than the first line.

13. The semiconductor device according to claim 8, characterized in that, It also includes a control circuit that controls the driving of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor. The control circuit is sealed by the sealing resin.

14. The semiconductor device according to claim 8, characterized in that, It also includes a sixth transistor disposed on the third lead frame, having a first terminal electrically connected to the third lead frame, a second terminal electrically connected to the second terminal of the first transistor, and a gate terminal electrically connected to the gate terminal of the third transistor. The sixth transistor is arranged such that it is sandwiched between the third transistor and the capacitor in the second direction.

15. The semiconductor device according to claim 14, characterized in that, The sixth transistor is a MOSFET, or metal-oxide-semiconductor field-effect transistor.

16. The semiconductor device according to claim 14, characterized in that, The sixth transistor has normally-off characteristics.

17. The semiconductor device according to claim 14, characterized in that, The threshold voltage of the sixth transistor is approximately the same as that of the third transistor.

18. The semiconductor device according to claim 14, characterized in that, The first lead frame is connected to the first terminal of the first transistor via a plurality of bonding wires. The plurality of bonding lines includes a first line and a second line extending in a direction different from the first line. The second line connects the first terminal of the first transistor and the first terminal of the capacitor with a shorter distance than the first line.

19. The semiconductor device according to claim 14, characterized in that, It also includes a control circuit that controls the driving of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor. The control circuit is sealed by the sealing resin.

Images