Test structure and method for local mismatch skew rate in spice model

Abstract

The application discloses a test structure and method of local mismatch offset rate in a SPICE model. The test structure comprises a first transistor and a second transistor, and the first transistor and the second transistor respectively comprise four test terminals of a first source terminal, a first drain terminal, a gate terminal and a substrate terminal. The first transistor and the second transistor respectively further comprise two test terminals of a second source terminal and a second drain terminal. The test structure and method of local mismatch offset rate in the SPICE model provided by the application improve the accuracy of the test by arranging six test terminals for the two transistors in the test structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a test structure and method for local mismatch offset rate in a SPICE model. Background Technology

[0002] In the field of electronic technology, metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various integrated circuits due to their excellent electrical performance. However, in the actual manufacturing and application of transistors, the MOSFET local mismatch problem has gradually become a key factor restricting circuit performance. Local mismatch refers to the phenomenon where, due to non-ideal manufacturing processes (such as lithography precision deviations, uneven film thickness, and doping concentration fluctuations), adjacent or batch-produced MOSFET devices exhibit slight differences in key electrical parameters such as threshold voltage, transconductance, and drain-source current. These differences can lead to many serious consequences. For example, in analog circuits (such as operational amplifiers and reference voltage sources), it can severely affect circuit accuracy, causing signal processing deviations and thus reducing the overall system performance. In digital circuits (such as logic gates and memory cells), it can lead to timing disorders, increase the bit error rate of data transmission, and pose a serious threat to the stability and reliability of the system.

[0003] Currently, when using SPICE (Simulation Program with Integrated Circuit Emphasis) models to test the local mismatch effect in low-voltage transistor designs, a four-terminal (4T:D / G / S / B) transistor mismatch structure is commonly used. In this design, the key factor 1 / sqrt(W·L) (the reciprocal of the square root of the width-length product) can be minimized to within 0.1, where W is the channel width of the transistor and L is the channel length. Figure 1 and Figure 2 As shown.

[0004] In actual testing, as the channel area (W·L) of the transistor increases, the value of the critical factor 1 / sqrt(W·L) of the mismatch standard deviation gradually decreases. When the critical factor 1 / sqrt(W·L) is less than 0.1 and approaches 0, the slope of the curve showing the change of the mismatch standard deviation with the critical factor 1 / sqrt(W·L) can have two possibilities: either the slope rises sharply, or the slope flattens and approaches the origin. This trend of slope change directly determines the magnitude of the mismatch standard deviation offset, but the existing technology has not clearly defined this trend, making it impossible to accurately quantify the offset of the mismatch standard deviation. The offset of the mismatch standard deviation directly affects the accuracy of the mismatch model in the SPICE model, ultimately leading to deviations in the MOSFET electrical parameter measurement results based on the mismatch model, making it difficult to meet the testing requirements of high-precision circuit design.

[0005] Therefore, a test structure is needed to improve test accuracy, thereby providing the possibility of measuring offset for mismatched structures with a critical factor 1 / sqrt (W·L) less than 0.1. Summary of the Invention

[0006] In view of the above problems, this application provides a test structure and method for local mismatch offset rate in SPICE model. By setting 6 test terminals for each of the two transistors in the test structure, the accuracy of the test is improved.

[0007] According to a first aspect of the present invention, a test structure for local mismatch offset rate in a SPICE model is provided, comprising: a first transistor and a second transistor, wherein the first transistor and the second transistor each include four test terminals: a first source terminal, a first drain terminal, a gate terminal and a substrate terminal, wherein the first transistor and the second transistor each further include two test terminals: a second source terminal and a second drain terminal.

[0008] Optionally, in the first transistor or the second transistor, the first source terminal and the second source terminal are separated by a predetermined distance, and the first drain terminal and the second drain terminal are separated by a predetermined distance.

[0009] Optionally, the distance between the first source end and the gate end is greater than the distance between the second source end and the gate end, and the distance between the first drain end and the gate end is greater than the distance between the second drain end and the gate end.

[0010] Optionally, the gates of the first transistor and the second transistor include a plurality of interdigitated fingers.

[0011] Optionally, the proximal ends of the plurality of interdigitated fingers are connected via a first metal layer; and / or the distal ends of the plurality of interdigitated fingers are connected via a first metal layer.

[0012] Optionally, the length and width of the plurality of interdigitated fingers are the same.

[0013] Optionally, in the first transistor and the second transistor, the sum of the areas of the plurality of interdigitated fingers may be the same or different.

[0014] Optionally, at least one of the length and width of the interdigitated fingers of the first transistor is different from the interdigitated fingers of the second transistor.

[0015] Optionally, the first transistor and / or the second transistor includes: a substrate; an epitaxial layer on the substrate; a body region, a source region, and a drain region in the epitaxial layer; a gate on the epitaxial layer, wherein the source region and the drain region are located in the body region on both sides of the gate, the substrate end is electrically connected to the substrate, the gate end is electrically connected to the gate, the first drain end and the second drain end are electrically connected to the drain region, and the first source end and the second source end are electrically connected to the source region.

[0016] According to another aspect of the present invention, a method for testing the local mismatch offset rate in a SPICE model is provided, comprising: testing the local mismatch offset rate using the aforementioned test structure for the local mismatch offset rate in a SPICE model.

[0017] The unexpected technical effect of this application is:

[0018] According to the test structure and method for local mismatch offset rate in the SPICE model of this application embodiment, two transistors in a test structure are respectively provided with 6 test terminals, including gate terminal, substrate terminal, first source terminal, second source terminal, first drain terminal and second drain terminal. Compared with the four test terminals in the traditional test structure, the test structure with six test terminals provided in this application separates the test signal application loop and the test result acquisition loop, reducing the mutual influence between the two. At the same time, the terminals in the test result acquisition loop are closer to the substrate and gate terminal of the transistor, which can reduce the influence of parasitic resistance in the circuit and improve the measurement accuracy.

[0019] Furthermore, the test structure and method for local mismatch offset rate in the SPICE model of this application, for large-area transistor mismatch structures, sets the transistors as interdigitated structures, so that a large-area transistor mismatch structure includes multiple interdigitated structures. This allows for simulation testing of transistor mismatch structures with uniform area but different lengths, transistor mismatch structures with different areas but different lengths, transistor mismatch structures with the same length but different widths, and transistor mismatch structures with the same width but different lengths, etc., and can also maximize the reduction of the layout area occupied, saving photomask costs. At the same time, for small-area transistor mismatch structures, it can also more accurately simulate local mismatch model simulations under different conditions. Attached Figure Description

[0020] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 The diagram shows the measured data and model fitting line of the standard deviation of local mismatch in transistor devices in the prior art as a function of the inverse square root of the device area;

[0022] Figure 2 A schematic diagram of the test structure for local mismatch offset rate in the SPICE model of the prior art is shown;

[0023] Figure 3 A schematic diagram illustrating the variation of the standard deviation of local mismatch of a transistor device as a function of the inverse square root of the device area, according to an embodiment of the present invention, is shown.

[0024] Figure 4 A top view schematic diagram of a semiconductor test structure for local mismatch offset rate in a SPICE model according to an embodiment of the present invention is shown;

[0025] Figure 5 A schematic diagram of the circuit structure for testing the local mismatch offset rate in a SPICE model according to an embodiment of the present invention is shown.

[0026] Figure 6 A schematic diagram of the layout structure of the test structure for local mismatch offset rate in the SPICE model according to an embodiment of the present invention is shown;

[0027] Figure 7 A flowchart illustrating a method for testing the local mismatch offset rate in a SPICE model according to an embodiment of the present invention is shown. Detailed Implementation

[0028] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. The present application may be presented in various forms, some of which will be described below.

[0029] This application may be presented in various forms, some of which will be described below.

[0030] Local mismatch in transistors, taking metal-oxide-semiconductor field-effect transistors (MOSFETs) as an example, refers to the phenomenon where multiple transistors on the same chip, originally designed with identical parameters, exhibit different actual electrical performance parameters. This difference is not caused by the design intent, but rather stems from various non-ideal factors during the manufacturing process, such as manufacturing process deviations or inhomogeneous material properties.

[0031] SPICE (Simulation Program with Integrated Circuit Emphasis) is a powerful integrated circuit simulation program used for simulating and analyzing electronic circuits. Based on the physical characteristics of semiconductor devices and fundamental circuit theory, it simulates various electronic circuits by building accurate mathematical models, helping engineers predict the behavior and performance of circuits under different conditions.

[0032] Figure 3 A schematic diagram illustrating the variation of the standard deviation of local mismatch of a transistor device as a function of the inverse square root of the device area, according to an embodiment of the present invention, is shown. Figure 4 A top view schematic diagram of a semiconductor test structure for local mismatch offset rate in a SPICE model according to an embodiment of the present invention is shown; Figure 5 A schematic diagram of the circuit structure for testing the local mismatch offset rate in a SPICE model according to an embodiment of the present invention is shown. Figure 6 A schematic diagram of the layout structure of the test structure for local mismatch offset rate in the SPICE model according to an embodiment of the present invention is shown.

[0033] When using the SPICE model to measure the local mismatch offset rate of transistor devices, transistors of identical size are typically placed in pairs in a region within the test structure, and the differences in performance between adjacent devices are statistically analyzed.

[0034] Figure 3 The offset test graph shown in the figure has the following structure: the horizontal axis 1 / Sqrt(W·L·nf) represents the key factors affecting the mismatch standard deviation, and the vertical axis represents the mismatch standard deviation. In the key factor 1 / Sqrt(W·L·nf) on the horizontal axis, W represents the channel width of the transistor, L represents the channel length of the transistor, and nf represents the number of interdigits (channels).

[0035] In addition, curves L0 to L4 all refer to Figure 3 The curves are linear. Curve L0 represents the variation of the mismatch standard deviation with the key factor in the existing model; L1 to L4 all represent the variation of the mismatch standard deviation with the key factor in the new model of this application. The slopes of curves L1 to L4 are different because the number of interdigitated fingers nf in the key factor 1 / Sqrt(W·L·nf) is different. Among curves L0 to L4, the slope of curve L0 is greater than the slope of curve L4, greater than the slope of curve L3, greater than the slope of curve L2, and greater than the slope of curve L1.

[0036] Specifically, in Figure 3In the diagram, the interdigitation index nf in the critical factor 1 / Sqrt(W·L·nf) corresponding to curves L4 to L1 increases progressively. In one embodiment, for example, curve L4 corresponds to a transistor test structure with an interdigitation index nf = 2, curve L3 corresponds to a transistor test structure with an interdigitation index nf = 3, and curve L2 corresponds to a transistor test structure with an interdigitation index nf > 3. This is because when using an interdigitated structure, multiple interdigits are equivalent to multiple small transistors connected in parallel. With the same critical factor 1 / Sqrt(W·L·nf), the larger the interdigitation index nf, the more interdigitated transistors are connected in parallel in each transistor. Assuming that the process fluctuations experienced by each interdigitated transistor are random and independent, as the number of interdigits increases, these random process fluctuations will cancel each other out overall, thus making the electrical parameters of the entire interdigitated transistor structure more uniform and stable.

[0037] Therefore, when the key factor 1 / Sqrt(W·L·nf) takes the value of M, it can be seen that the mismatch value corresponding to curve L0 in the existing model is greater than the mismatch value corresponding to curve L4 in the new model, greater than the mismatch value corresponding to curve L3, greater than the mismatch value corresponding to curve L2, and greater than the mismatch value corresponding to curve L1. Thus, the test structure corresponding to curve L1 obtained by testing has the smallest error.

[0038] When the critical factor 1 / Sqrt(W·L·nf) approaches 0, it is impossible to confirm whether the mismatch standard deviation approaches zero or rises. However, in existing models, as the cross index nf increases, the mismatch standard deviation decreases. Therefore, a test structure with a cross index nf of at least 2 can be provided for testing.

[0039] Therefore, the test structure provided in this application can reduce the mismatch effect to a certain extent by increasing the number of interdigitated nf, and make it possible to measure the mismatch standard deviation when the critical factor 1 / Sqrt(W·L·nf) is less than 0.1.

[0040] Furthermore, for the test structure, other methods can be used to improve the measurement accuracy. The test structure provided in this application will be described in detail below.

[0041] refer to Figure 4In the local mismatch offset rate test structure of the SPICE model of this application, the local mismatch offset rates of the first transistor MOS_A and the second transistor MOS_B are measured. The first transistor MOS_A and the second transistor MOS_B are adjacent and located on a substrate (not shown in the figure). Each transistor includes: a substrate (not shown in the figure), an epitaxial layer (not shown in the figure) on the substrate; a body region 120, a source region, and a drain region 130 located in the epitaxial layer; a gate 110 located on the epitaxial layer, and the source and drain regions 130 located in the body regions 120 on both sides of the gate 110. The first transistor MOS_A and the second transistor MOS_B are arranged opposite to each other. In one embodiment, the first transistor MOS_A and the second transistor MOS_B are, for example, transistors manufactured in the same batch, or two adjacent transistors on the same substrate.

[0042] The gates 110 of the first transistor MOS_A and the second transistor MOS_B include multiple interdigitated fingers. Figure 4 The diagram shows a structure where each transistor's gate includes four interdigitated fingers. In this embodiment, the length L and width W of the interdigitated fingers in each transistor are, for example, the same. In other embodiments, the length L and width W of the interdigitated fingers in each transistor may also be different, i.e., the length L and width W of the interdigitated fingers may be set accordingly as needed; at least one of the length and width of the interdigitated fingers of the first transistor MOS_A is different from the length and width of the interdigitated fingers of the second transistor MOS_B; the sum of the areas of the interdigitated fingers in different transistors (W·L·nf, where nf represents the number of interdigitated fingers) may be the same or different.

[0043] In the SPICE model of this application, the test structure for local mismatch offset rate divides a large-area gate into multiple interdigitations, so that the structure can simultaneously cover the following situations: transistor mismatch structures with the same area but different lengths and widths, transistor mismatch structures with different areas but different lengths and widths, transistor mismatch structures with the same length but different widths, and transistor mismatch structures with the same width but different lengths, etc.

[0044] In this test structure, each transistor includes six leads as test terminals, such as... Figure 5 As shown. The first transistor MOS_A and the second transistor MOS_B each include a gate terminal G, a substrate terminal B, a first source terminal S1, a second source terminal S2, a first drain terminal D1, and a second drain terminal D2. The first source terminal S1 and the second source terminal S2 are both located at the source terminals of the transistor, but the distance between the second source terminal S2 and the substrate terminal B is less than the distance between the first source terminal S1 and the substrate terminal B, that is, the first source terminal S1 and the second source terminal S2 are separated by a predetermined distance; the first drain terminal D1 and the second drain terminal D2 are both located at the drain terminals of the transistor, but the distance between the second drain terminal D2 and the substrate terminal B is less than the distance between the first drain terminal D1 and the substrate terminal B, that is, the first drain terminal D1 and the second drain terminal D2 are separated by a predetermined distance.

[0045] Furthermore, such as Figure 5 As shown, the distance between the first source terminal S1 and the gate terminal G is greater than the distance between the second source terminal S2 and the gate terminal G, and the distance between the first drain terminal D1 and the gate terminal G is greater than the distance between the second drain terminal D2 and the gate terminal G. This distance can also be understood as the length of the current path. The longer the current path, the greater the equivalent resistance along the path, which will cause deviations in the test results and increase measurement errors. In addition, a longer current path may also be affected by parasitic capacitance, electromagnetic interference, etc., further increasing the test error.

[0046] In this application, the six terminals in the test structure enable Kelvin testing, completely separating the test signal application terminal from the test result terminal in the circuit. This also separates the current and voltage paths in the test structure, avoiding mutual interference and thus improving test accuracy. Specifically, the first source terminal S1 and the first drain terminal D1 in this application form, for example, a first loop used to apply the test signal; the second source terminal S2 and the second drain terminal D2 form, for example, a second loop and a test loop, serving as test terminals. Furthermore, since the distance between the second source terminal S2 and the second drain terminal D2 and the substrate terminal B and gate terminal G of the transistor is smaller, the resistance can also be reduced, thereby improving test accuracy.

[0047] In the SPICE model simulation, the first source terminal S1 and the second source terminal S2 are the sources of charge carriers. In the first transistor MOS_A and the second transistor MOS_B, the source and drain are physically symmetrical, but in practical applications, they are usually distinguished based on circuit connections and operating modes. The first drain terminal D1 and the second drain terminal D2 are the outlets of charge carriers in the first transistor MOS_A and the second transistor MOS_B. When the transistor is in the on state, depending on the operating mode (e.g., enhancement-mode or depletion-mode, N-channel or P-channel), charge carriers flow from the source to the drain. The substrate terminal B is usually connected to a fixed potential. For N-channel transistors, the substrate terminal B is generally connected to the lowest potential (e.g., ground GND), while for P-channel transistors, the substrate terminal B is usually connected to the highest potential. The gate terminal G plays a crucial role in controlling the transistor's on or off state. By applying a voltage (VGS) to the gate terminal G, the formation of the channel and the flow of charge carriers can be controlled.

[0048] In the SPICE model of this application, the test structure for local mismatch offset rate is provided with different test signals to the first transistor MOS_A and the second transistor MOS_B, such as measuring current by voltage or measuring voltage by current. By obtaining data from the test terminals such as the second source terminal S2 and the second drain terminal D2, more accurate test results can be obtained, thus making the detection of mismatch offset of large-area transistors more accurate.

[0049] Furthermore, Figure 6 The layout design shown is a top view of either the first transistor MOS_A or the second transistor MOS_B. The gate 110 of the transistor is connected to the first metal layer 160 via vias 140, meaning the beginnings and / or ends of multiple interdigitated fingers are connected to the same first metal layer 160. The source and drain regions 130 are located in the body region 120, and are connected to the second metal layer 150 via vias 140. The second metal layer 150 serves as the lead-out layer for the source and drain regions 130. To distinguish between the source and drain regions, the second metal layer 150 forms leads on both sides of the source and drain regions 130, as shown below. Figure 6 As shown; in addition, the first drain terminal D1, the second drain terminal D2, the first source terminal S1 and the second source terminal S2 in the test structure can be formed through different positions of the second metal layer 150.

[0050] Figure 6 In the layout design of the test structure, it is understood that the first metal layer 160 and the second metal layer 150 are separated by an insulating layer (not shown in the figure) and are located in different horizontal planes of the insulating layer. That is, the first metal layer 160 and the second metal layer 150 will not be connected in the same horizontal plane.

[0051] Furthermore, this application also provides a method for testing the local mismatch offset rate in a SPICE model, comprising: testing the local mismatch offset rate using the aforementioned test structure for the local mismatch offset rate in the SPICE model. Specifically, Figure 7 A flowchart of a test method for local mismatch offset rate in a SPICE model according to an embodiment of the present invention is shown. The test method is, for example, a test method for measuring current by applying voltage, and includes the following steps.

[0052] S10: Apply a test voltage to the gate and first source terminals of the first transistor and / or the second transistor.

[0053] In this step, appropriate test voltage signals are applied to the gate and first source terminals of the first transistor MOS_A and the second transistor MOS_B to set the operating point of the transistors. The operating point of the transistors includes, for example, amplification, cutoff, and saturation.

[0054] If the test method is to measure voltage by applying current, then a suitable test current signal is applied to the gate and the first source terminal of the first transistor MOS_A and the second transistor MOS_B.

[0055] S20: Obtain current data via the second source terminal and / or second drain terminal of the first transistor and / or the second transistor.

[0056] In this step, current data is obtained via the second source and / or second drain of the first transistor MOS_A and the second transistor MOS_B, and the current data includes, for example, the drain current.

[0057] If the test method uses the method of measuring voltage while applying current, then the obtained voltage data includes the voltage between the gate and source, the voltage between the drain and source, etc.

[0058] S30: Change the test voltage multiple times and obtain multiple corresponding current data.

[0059] In this step, the test voltage is changed to change the operating point of the first transistor MOS_A and the second transistor MOS_B, and then the corresponding current data at that operating point is obtained; the test voltage is changed again and the corresponding current data is obtained; the steps of changing the test voltage and obtaining the corresponding current data are repeated multiple times.

[0060] If the test method uses the method of measuring voltage by applying current, then the steps of changing the test current and obtaining the corresponding voltage data are repeated multiple times.

[0061] S40: Calculate and compare the key electrical parameters of the first and second transistors based on the collected current data.

[0062] In this step, key electrical parameters of the first transistor MOS_A and the second transistor MOS_B include, for example, threshold voltage (Vth) and transconductance (gm). For the first transistor MOS_A and the second transistor MOS_B with the same design but which may have local mismatch, the differences in their electrical parameters are obtained by comparison. These differences can intuitively reflect the degree of local mismatch of the transistors.

[0063] According to the test structure and method for local mismatch offset rate in the SPICE model of the present application, two transistors in a test structure are respectively provided with 6 test terminals, including gate terminal, substrate terminal, first source terminal, second source terminal, first drain terminal and second drain terminal. Compared with the four test terminals in the traditional test structure, the test structure with six test terminals provided in this application can reduce the influence of parasitic resistance in the circuit and improve the measurement accuracy.

[0064] Furthermore, the test structure and method for local mismatch offset rate in the SPICE model of this application, for large-area transistor mismatch structures, sets the transistors as interdigitated structures, so that a large-area transistor mismatch structure includes multiple interdigitated structures. This allows for simulation testing of transistor mismatch structures with uniform area but different lengths, transistor mismatch structures with different areas but different lengths, transistor mismatch structures with the same length but different widths, and transistor mismatch structures with the same width but different lengths, etc., and can also maximize the reduction of the layout area occupied, saving photomask costs. At the same time, for small-area transistor mismatch structures, it can also more accurately simulate local mismatch model simulations under different conditions.

[0065] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A test structure for local mismatch offset rate in a SPICE model, comprising: A first transistor and a second transistor are arranged relative to each other and are independent of each other. The first transistor and the second transistor each include four test terminals: a first source terminal, a first drain terminal, a gate terminal, and a substrate terminal. The first transistor and the second transistor also include two test terminals: a second source terminal and a second drain terminal, respectively. The gates of the first transistor and the second transistor each include a plurality of interdigitated fingers, the areas of which may be the same or different; at least one of the lengths and widths of the interdigitated fingers of the first transistor is different from the interdigitated fingers of the second transistor.

2. The test structure according to claim 1, wherein, In either the first transistor or the second transistor, the first source terminal and the second source terminal are separated by a predetermined distance, and the first drain terminal and the second drain terminal are separated by a predetermined distance.

3. The test structure according to claim 2, wherein, The distance between the first source terminal and the gate terminal is greater than the distance between the second source terminal and the gate terminal, and the distance between the first drain terminal and the gate terminal is greater than the distance between the second drain terminal and the gate terminal.

4. The test structure according to claim 1, wherein, The tips of the plurality of interdigitated fingers are connected via a first metal layer; and / or The tail ends of the plurality of interdigitated fingers are connected via a first metal layer.

5. The test structure according to claim 4, wherein, The length and width of the plurality of interdigitated fingers of any of the transistors are all the same.

6. The test structure according to claim 1, wherein, The first transistor and / or the second transistor include: Substrate; Epitaxial layer located on the substrate; The body region, source region, and drain region located in the epitaxial layer; The gate is located on the epitaxial layer, and the source and drain regions are located in the body regions on both sides of the gate. The substrate terminal is electrically connected to the substrate, the gate terminal is electrically connected to the gate, the first drain terminal and the second drain terminal are electrically connected to the drain region, and the first source terminal and the second source terminal are electrically connected to the source region.

7. A method for testing the local mismatch offset rate in a SPICE model, wherein, include: The local mismatch offset rate is tested using the test structure of the SPICE model as described in any one of claims 1-6.

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