Robust high-voltage electrostatic protection circuit

Abstract

The invention provides a robust high-voltage electrostatic protection circuit, and belongs to the technical field of electrostatic protection. The robust high-voltage electrostatic protection circuit comprises a high-voltage electrostatic protection module, a charge discharge module and a state control module, the high-voltage electrostatic protection module comprises at least one floating node, and the floating node can accumulate residual charges in the process of normal work of the circuit or electrical characteristic test characterization; the state control module is used for monitoring the potential state of the floating node in real time and generating a control signal; and the charge discharge module responds to the control signal, conducts an electrostatic discharge channel and discharges charges accumulated by the floating node. The series connection type high-voltage ESD protection circuit has the beneficial effect that accumulated charges on the floating node in the series connection type high-voltage ESD protection circuit can be effectively and timely discharged.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology, and more specifically to a robust high-voltage ESD protection circuit. Background Technology

[0002] During the use of electronic devices, static electricity can easily be generated on the human body, clothing, and device surfaces due to friction, contact separation, and other reasons. When static electricity accumulates to a certain level, it will cause electrostatic discharge, releasing high-energy charges. This electrostatic discharge can cause serious damage to sensitive components such as integrated circuits inside electronic devices, leading to decreased device performance or even complete failure.

[0003] In some electronic devices, signal swings at certain ports may exhibit both positive and negative voltages simultaneously. For these ports, bidirectional ESD protection circuitry is required: bidirectional voltage blocking capability during normal chip operation, and bidirectional electrostatic discharge capability in the event of an ESD event. In practical ESD protection engineering, bidirectional ESD protection is achieved by connecting two unidirectional ESD devices in series, either head-to-head or tail-to-tail. In this case, to provide effective ESD protection, the clamping voltage after the ESD circuit is turned on needs to be monitored; typically, it must not exceed the failure voltage of the protected circuit under a specific ESD excitation level.

[0004] Existing bidirectional stacked ESD circuits, such as Figure 1(a)-Figure 1(c) As shown, for bidirectional I / O or power ports, a common ESD protection circuit strategy is to connect Zener diodes, BJTs (bipolar junction transistors), or MOSFETs in series "head-to-head" or "tail-to-tail". In this case, the internal node Ax is floating, where x = 1, 2, 3. Resistors R1 and R2 are used to limit the base current, ensuring the transistor conducts under appropriate conditions; resistors R3 and R4 are used to limit the gate current, ensuring the MOSFET conducts under appropriate conditions.

[0005] However, for chip ports employing the aforementioned bidirectional ESD circuitry, the actual ESD protection level of the port sometimes falls far short of its design value. Research indicates that this is typically due to the charge storage behavior of the internal floating nodes within the bidirectional ESD circuitry. When an ESD event occurs, the non-zero potential caused by these stored charges has a certain probability of being superimposed on the IV characteristic curve of the ESD protection device, thus drastically deteriorating its clamping voltage characteristics and ultimately significantly reducing the port's ESD protection level.

[0006] Figure 2(a) shows the influence of the ESD circuit's IV characteristics on the floating potential of Ax. The applied bias voltage represents the port voltage or the pre-charge phenomenon during ESD testing. As shown in Figure 2(a), under certain circumstances, when the applied bias voltage disappears, the Ax potential cannot be discharged to zero. As shown in Figure 2(c), when the Ax potential is not zero, the IV curve of the ESD circuit (two red lines) will drift to the right along the X-axis, thus significantly deteriorating the electrostatic protection effect of the ESD circuit. In other words, the ESD robustness will be severely affected by the Ax potential.

[0007] Therefore, a bidirectional electrostatic discharge (ESD) protection solution is needed to address the interference of non-zero potential on the internal floating nodes on the ESD protection effect. Summary of the Invention

[0008] To address the problems in the prior art, this invention provides a robust high-voltage electrostatic protection circuit.

[0009] This invention relates to a robust high-voltage electrostatic discharge (ESD) protection circuit, comprising a high-voltage ESD protection module and a floating charge discharge module, wherein...

[0010] High voltage electrostatic protection module: includes at least one floating node, which can accumulate residual charge during normal circuit operation or electrical characteristic testing and characterization;

[0011] The floating charge discharge module includes a state control module and a charge discharge module. The state control module monitors the potential state of the floating node in real time and generates a control signal. The charge discharge module responds to the control signal and conducts to discharge the charge accumulated in the floating node.

[0012] Furthermore, the high-voltage electrostatic protection module includes a first bidirectional electrostatic discharge path and a second bidirectional electrostatic discharge path arranged in parallel. One end of the first bidirectional electrostatic discharge path and the second bidirectional electrostatic discharge path are connected to a first port, and the other end of the first bidirectional electrostatic discharge path and the second bidirectional electrostatic discharge path are connected to a second port.

[0013] The first bidirectional electrostatic discharge path includes a first electrostatic discharge unit and a second electrostatic discharge unit stacked together. The second electrostatic discharge path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit stacked together. The first and second electrostatic discharge units are arranged in opposite directions, as are the third and fourth electrostatic discharge units. The first and third electrostatic discharge units are arranged in the same direction and connected to a first port, while the second and fourth electrostatic discharge units are arranged in the same direction and connected to a second port.

[0014] The layout area of ​​the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the layout area of ​​the fourth electrostatic discharge unit is larger than that of the third electrostatic discharge unit.

[0015] A first floating node is provided between the first electrostatic discharge unit and the second electrostatic discharge unit, and a second floating node is provided between the third electrostatic discharge unit and the fourth electrostatic discharge unit.

[0016] Furthermore, the first bidirectional electrostatic discharge path is the primary discharge path, and the second bidirectional electrostatic discharge path is the secondary discharge path. The layout area of ​​the second bidirectional electrostatic discharge path is smaller than the layout area of ​​the first electrostatic discharge unit.

[0017] As another improvement of the present invention, the layout area of ​​the first bidirectional electrostatic discharge path is equal to the layout area of ​​the second bidirectional electrostatic discharge path.

[0018] Furthermore, the third and fourth electrostatic discharge units on the second electrostatic discharge path constitute a state control module.

[0019] Furthermore, the charge discharge module includes a first MOS transistor and a second MOS transistor, wherein the source of the first MOS transistor is connected to a first floating node and the gate is connected to a second floating node, the source of the second MOS transistor is connected to a second floating node and the gate is connected to a first floating node, the drains of the first MOS transistor and the second MOS transistor are respectively connected to a second port, and the first MOS transistor and the second MOS transistor are respectively provided with overcurrent protection structures.

[0020] Furthermore, the overcurrent protection structure comprises a first rectifier diode and a second rectifier diode. The drain of the first MOSFET is connected to the second port through the first rectifier diode, and the drain of the second MOSFET is connected to the second port through the second rectifier diode. The first rectifier diode and the second rectifier diode are respectively configured in the same direction as the first electrostatic discharge unit.

[0021] or,

[0022] The overcurrent protection structure is a third rectifier diode. The drains of the first MOSFET and the second MOSFET are respectively connected to one end of the third rectifier diode, and the other end of the third rectifier diode is connected to the second port. The third rectifier diode is arranged in the same direction as the first electrostatic discharge unit.

[0023] Furthermore, the overcurrent protection structure involves floating the first MOS transistor and the second MOS transistor.

[0024] Furthermore, the first bidirectional electrostatic discharge path includes several parallel first electrostatic discharge branches, which are stacked together with first electrostatic discharge units and second electrostatic discharge units, and the first floating nodes of the several first electrostatic discharge branches are connected.

[0025] The second bidirectional electrostatic discharge path includes several parallel second electrostatic discharge branches. The second electrostatic discharge branches are stacked together by the third electrostatic discharge unit and the fourth electrostatic discharge unit, and the second floating nodes of the several electrostatic discharge branches are connected.

[0026] Furthermore, the first electrostatic discharge unit, the second electrostatic discharge unit, the third electrostatic discharge unit, and the fourth electrostatic discharge unit each include one or more electrostatic protection devices. The electrostatic protection devices include one or more of diodes, MOSFETs, BJTs, and thyristors. The electrostatic protection devices can be mixed and stacked together, and the number of stacking levels is one or more.

[0027] Compared with the prior art, the beneficial effects of the present invention are: through the optimization of the circuit structure, the present invention can effectively and timely discharge the accumulated charge on the floating node inside the series-type high voltage ESD protection circuit, avoid the interference of the non-zero potential on the internal floating node on the ESD protection effect, and thus realize the intrinsic ESD protection capability of the protection circuit. Attached Figure Description

[0028] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1(a) is a circuit schematic diagram of an embodiment of an existing bidirectional stacked ESD circuit;

[0030] Figure 1(b) is a circuit schematic diagram of an existing bidirectional stacked ESD circuit embodiment two;

[0031] Figure 1(c) is a circuit schematic diagram of an existing bidirectional stacked ESD circuit embodiment three;

[0032] Figures 2(a) and 2(b) are schematic diagrams showing the influence of the floating potential of Ax on the IV characteristics of the existing bidirectional stacked ESD circuit.

[0033] Figure 2(c) is a schematic diagram of the rightward drift of the IV curve of the existing bidirectional stacked ESD circuit;

[0034] Figure 3 This is a schematic diagram of the robust high-voltage electrostatic protection circuit structure of the present invention;

[0035] Figure 4 The circuit schematics are for the first and second embodiments of the present invention.

[0036] Figure 5 These are circuit schematics for the third and fourth embodiments of the present invention;

[0037] Figure 6 These are circuit schematics for the fifth and sixth embodiments of the present invention;

[0038] Figure 7 The circuit diagrams are for the seventh and eighth embodiments of the present invention. Detailed Implementation

[0039] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0040] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment to other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0042] like Figure 3 As shown, the robust high-voltage electrostatic discharge (ESD) protection circuit of the present invention includes a high-voltage ESD protection module 1 and a floating charge discharge module 2 for discharging floating charges on floating nodes in the high-voltage ESD protection module. The floating charge discharge module 2 includes a charge discharge module and a state control module.

[0043] High voltage electrostatic protection module: includes at least one floating node, which can accumulate residual charge during normal circuit operation or electrical characteristic testing and characterization;

[0044] State control module: monitors the potential state of the floating node in real time and generates control signals;

[0045] Charge discharge module: In response to control signals, it opens the electrostatic discharge channel to discharge the charge accumulated in the floating node.

[0046] like Figures 4-7 As shown, the high-voltage electrostatic protection module of the present invention includes a first bidirectional electrostatic discharge path and a second bidirectional electrostatic discharge path arranged in parallel. One end of the first bidirectional electrostatic discharge path and the second bidirectional electrostatic discharge path are connected to a first port, and the other end of the first bidirectional electrostatic discharge path and the second bidirectional electrostatic discharge path are connected to a second port.

[0047] The first bidirectional electrostatic discharge path includes a first electrostatic discharge unit and a second electrostatic discharge unit stacked together. The second electrostatic discharge path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit stacked together. The first and second electrostatic discharge units are arranged in opposite directions, as are the third and fourth electrostatic discharge units. The first and third electrostatic discharge units are arranged in the same direction and connected to a first port, while the second and fourth electrostatic discharge units are arranged in the same direction and connected to a second port.

[0048] The layout area of ​​the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the layout area of ​​the fourth electrostatic discharge unit is larger than that of the third electrostatic discharge unit.

[0049] A first floating node is provided between the first electrostatic discharge unit and the second electrostatic discharge unit, and a second floating node is provided between the third electrostatic discharge unit and the fourth electrostatic discharge unit.

[0050] The first electrostatic discharge unit, the second electrostatic discharge unit, the third electrostatic discharge unit, and the fourth electrostatic discharge unit each include one or more electrostatic protection devices. The electrostatic protection devices include one or more of ESD diodes, Zener diodes, MOSFETs, BJTs (bipolar junction transistors), and thyristors. The electrostatic protection devices can be mixed and stacked together, and the number of stacking levels is one or more.

[0051] This invention is also applicable to rail-based protection networks based on floating ESD buses. Furthermore, this invention is not limited to ESD protection, but can also be used for surge protection and protection against other electrostatic models.

[0052] The following description is based on a specific embodiment. In this example, an ESD diode is used as the electrostatic protection device. The various reference numerals in the embodiments are explained as follows:

[0053] • 100, 200, 300, 400, 500, 600, 700, and 800 typically represent port 1;

[0054] • 101, 201, 301, 401, 501, 601, 701, and 801 typically represent port 2;

[0055] ·102, 103, 202, 203, 302, 303, 402, 403, 502, 503, 602, 603, 702, 703, 802,

[0056] 803 typically represents a bidirectional electrostatic discharge path, also known as a bidirectional ESD discharge path.

[0057] ·104-1, 104-2, 104-N, 105-1, 105-2, 105-N, 106, 107, 204-1, 204-2, 204-N,

[0058] 205-1, 205-2, 205-N, 206, 207, 304-1, 304-2, 304-N, 305-1, 305-2, 305-N,

[0059] 306, 307, 404-1, 404-2, 404-N, 405-1, 405-2, 405-N, 406, 407, 504-1, 504-2,

[0060] 504-N, 505-1, 505-2, 505-N, 506, 507, 604-1, 604-2, 604-N, 605-1, 605-2,

[0061] 605-N, 606, 607, 704-1, 704-2, 704-N, 705-1, 705-2, 705-N, 706-1, 706-2,

[0062] 706-M, 707-1, 707-2, 707-M, 804-1, 804-2, 804-N, 805-1, 805-2, 805-N, 806-1,

[0063] 806-2, 806-M, 807-1, 807-2, and 807-M typically represent ESD diodes.

[0064] ● 108, 109, 308, 309, 508, 509, 708, and 709 typically represent N-type MOS transistors, or NMOS transistors for short.

[0065] • 208, 209, 408, 409, 608, 609, 808, and 809 typically represent P-type MOS transistors, or PMOS transistors for short.

[0066] • 110, 111, 210, 211, 310, and 410 typically represent rectifier diodes;

[0067] • Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 typically represent floating nodes within a bidirectional ESD discharge path.

[0068] like Figure 4 As shown in Figure (a), as a first embodiment of the present invention, the present invention includes two bidirectional ESD discharge paths 102 and 103 connected in a "tail-to-tail" (cathode-connected) series configuration. Among them, bidirectional ESD discharge path 102 is the primary "bidirectional ESD discharge path", while bidirectional ESD discharge path 103 is the secondary bidirectional ESD discharge path, and bidirectional ESD discharge path 103 also serves as a "control path for floating charge discharge".

[0069] To achieve sufficient electrostatic discharge capability, the bidirectional ESD discharge path 102, which consists of ESD diodes 104 and 105 connected in series, has a large area (composed of N diode pairs connected in parallel). The first electrostatic discharge unit includes N first electrostatic discharge branches, where N is a positive integer. Each first electrostatic discharge branch is equipped with an ESD diode. Similarly, the second electrostatic discharge unit includes N second electrostatic discharge branches, each of which is equipped with an ESD diode. ESD diodes 104-1 and 105-1 are connected in series to form a diode pair. The bidirectional ESD discharge path 102 has a total of N diode pairs connected in parallel.

[0070] Among them, the size of ESD diode 104 is larger than that of diode 105, and the bidirectional ESD discharge path 103 serves as the control path for the floating charge discharge tube. It is composed of ESD diodes 106 and 107 forming a state control module. The layout area of ​​ESD diodes 106 and 107 has the following characteristics:

[0071] 1. Their layout areas are all much smaller than the layout area of ​​the main diode on the bidirectional ESD discharge path 102.

[0072] 2. The layout area of ​​ESD diode 107 is larger than that of ESD diode 106.

[0073] The charge discharge module of the present invention consists of two NMOS transistors: the source of NMOS transistor 108 is connected to the internal floating node Q1 and the gate is connected to the floating node Q2, and the source of NMOS transistor 109 is connected to the floating node Q2 and the gate is connected to the floating node Q1. The drains of the two transistors are connected to port 101 through reverse biased rectifier diodes 110 and 111, respectively.

[0074] The working principle of this invention is as follows:

[0075] (1) When a forward bias is applied to port 100, the potentials of floating nodes Q1 and Q2 are both diode forward voltage drops (approximately 0.7V). At this time, the gate-source voltage difference between the two NMOS transistors is zero and they remain off, which does not affect the circuit function.

[0076] (2) After the forward bias ends (i.e., the potential at port 100 returns to zero), due to the difference in the area of ​​the two path diodes, the parasitic capacitances are different. Q1 induces a larger negative potential, while Q2 induces a smaller negative potential. Since the potential of Q2 is higher than that of Q1, the gate-source voltage of NMOS transistor 108 is greater than the threshold voltage and it turns on, while NMOS transistor 109 remains off. The negative charge accumulated in Q1 is discharged to port 101 through the conducting NMOS transistor 108 and rectifier diode 110.

[0077] (3) When a negative bias voltage is applied to port 100, the potentials of Q1 and Q2 are close to the negative bias voltage of the port, and the two NMOS transistors 108 and 109 are turned off.

[0078] (4) After the negative bias ends (i.e., the potential of port 100 returns to zero), Q1 senses a small negative potential, so it does not affect the subsequent electrostatic protection capability of the bidirectional ESD discharge path 102. Q2 senses a larger negative potential. At this time, NMOS transistor 109 turns on because the gate-source voltage meets the conduction condition, and discharges the charge of Q2 to port 101 through rectifier diode 111.

[0079] (5) After the positive or negative bias is completed, due to the different negative potentials induced at nodes Q1 and Q2, one of the NMOS transistors 108 or 109 will inevitably turn on, raising the potentials at points Q1 and Q2 to near zero. This avoids the overvoltage application risk of NMOS transistors 108 or 109. Therefore, this embodiment can be applied to both low-voltage and high-voltage electrostatic discharge (ESD) and surge protection engineering applications.

[0080] In this example, rectifier diodes 110 and 111 are used to block the body diode of the NMOS transistor from turning on, preventing the NMOS transistor from burning out due to excessive current and ensuring the reliability of the circuit function.

[0081] like Figure 4As shown in Figure (b), as a second embodiment of the present invention, the difference between this example and the first embodiment is that the "tail-to-tail" ESD diode pair is changed to a "head-to-head" (anode connected) series structure, and the NMOS transistors discharging floating charge are replaced with PMOS transistors 208 and 209. During both positive and negative bias, PMOS transistors 208 and 209 remain off, without affecting the normal function of the circuit. After the positive bias ends, due to the difference in the area ratio of the diodes on the bidirectional ESD discharge paths 202 and 203 (i.e., the difference in the ratio of parasitic capacitance), node Q3 maintains a high potential, and node Q4 maintains a low potential. After the negative bias ends, the potentials of Q3 and Q4 are opposite, with Q3 maintaining a low potential and Q4 maintaining a high potential. Therefore, regardless of whether the positive or negative bias ends, one of the PMOS transistors 208 or 209 will inevitably be turned on, discharging the floating charge of the high-potential node Q3 or Q4 and pulling its potential down. This not only allows the floating charge on the Q3 or Q4 nodes to be released, but also avoids the overvoltage risk of PMOS transistors 208 and 209.

[0082] In this example, rectifier diodes 210 and 211 are used to block the body diode of the PMOS transistor from turning on, preventing the PMOS transistor from burning out due to excessive current and ensuring the reliability of the circuit.

[0083] like Figure 5 As shown in Figure (a), as a third embodiment of the present invention, compared with the first embodiment, this embodiment connects the drain terminals of NMOS transistors 308 and 309 used to discharge floating charge, and reuses rectifier diode 310 to discharge floating charge, which can reduce the chip layout area.

[0084] like Figure 5 As shown in Figure (b), this fourth embodiment of the present invention is similar to the third embodiment, except that the drain terminals of PMOS transistors 408 and 409 are connected together and rectifier diode 410 is reused. Therefore, it will not be described in detail here.

[0085] like Figure 6 As shown, the fifth and sixth embodiments of the present invention are as follows: Figure 5 Figure (a) Fifth embodiment and Figure 5 Compared to the third and fourth embodiments, the sixth embodiment of Figure (b) removes the rectifier diode in the floating charge discharge path and floats the substrates of the NMOS transistors 508 and 509 and the PMOS transistors 608 and 609 used for discharge, forming an overcurrent protection structure to prevent the body diode in the MOS transistor from overcurrent and causing the transistor to burn out.

[0086] like Figure 7As shown in Figure (a), the core improvement of the seventh embodiment of the present invention compared to the fifth embodiment lies in the structural upgrade of the control path. The bidirectional ESD discharge path 703, as the control path for the discharge tube, employs a multi-diode parallel array (composed of M bidirectional diode pairs connected in parallel), and its layout size is significantly larger than the original control path of the fifth embodiment. Since the area ratio of ESD diodes 706 and 707 in the bidirectional ESD discharge path 703 remains unchanged, the floating charge discharge function of NMOS transistors 708 and 709 is not affected. When the layout sizes of the bidirectional ESD discharge path 703 and the bidirectional ESD discharge path 702 are different, the two paths have asymmetrical bidirectional ESD protection characteristics. When the bidirectional ESD discharge path 703 and the bidirectional ESD discharge path 702 have the same layout size, the two paths can achieve symmetrical bidirectional ESD protection, which increases the design freedom.

[0087] like Figure 7 As shown in Figure (b), the core improvement of the eighth embodiment of the present invention compared with the sixth embodiment is that the layout size of the bidirectional ESD discharge path 803 is increased. The principle is similar to that of the seventh embodiment, so it will not be described again here.

[0088] As can be seen from the above, this invention has an intelligent "floating charge discharge module" through the optimization of the circuit structure. This module is composed of switching devices. By accurately monitoring the working status of the "bidirectional stacked electrostatic protection circuit", it can accurately and effectively discharge floating charges without deteriorating the protection effect against static electricity and surges.

[0089] Furthermore, this invention can effectively and promptly discharge the accumulated charge on the floating nodes inside the series-type high-voltage ESD protection circuit, avoiding interference from the non-zero potential on the internal floating nodes on the ESD protection effect, thereby realizing the intrinsic ESD protection capability of the protection circuit. Moreover, by further optimizing the device layout of the "state control module" and "charge discharge module," the protection circuit of this invention is free from overvoltage risk and can be applied to both low-voltage and high-voltage fields.

[0090] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A robust high-voltage electrostatic protection circuit, characterized in that: It includes a high-voltage electrostatic protection module and a floating charge discharge module, among which, High voltage electrostatic protection module: includes at least one floating node, which can accumulate residual charge during normal circuit operation or electrical characteristic testing and characterization; The floating charge discharge module includes a state control module and a charge discharge module. The state control module monitors the potential state of the floating node in real time and generates a control signal. The charge discharge module responds to the control signal and conducts to discharge the charge accumulated in the floating node.

2. The robust high-voltage electrostatic protection circuit according to claim 1, characterized in that: The high-voltage electrostatic protection module includes a first bidirectional electrostatic discharge path and a second bidirectional electrostatic discharge path connected in parallel. One end of the first bidirectional electrostatic discharge path and the second bidirectional electrostatic discharge path are connected to a first port, and the other end of the first bidirectional electrostatic discharge path and the second bidirectional electrostatic discharge path are connected to a second port. The first bidirectional electrostatic discharge path includes a first electrostatic discharge unit and a second electrostatic discharge unit stacked together. The second electrostatic discharge path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit stacked together. The first and second electrostatic discharge units are arranged in opposite directions, as are the third and fourth electrostatic discharge units. The first and third electrostatic discharge units are arranged in the same direction and connected to a first port, while the second and fourth electrostatic discharge units are arranged in the same direction and connected to a second port. The layout area of ​​the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the layout area of ​​the fourth electrostatic discharge unit is larger than that of the third electrostatic discharge unit. A first floating node is provided between the first electrostatic discharge unit and the second electrostatic discharge unit, and a second floating node is provided between the third electrostatic discharge unit and the fourth electrostatic discharge unit.

3. The robust high-voltage electrostatic protection circuit according to claim 2, characterized in that: The first bidirectional electrostatic discharge path is the primary discharge path, and the second bidirectional electrostatic discharge path is the secondary discharge path. The layout area of ​​the second bidirectional electrostatic discharge path is smaller than the layout area of ​​the first electrostatic discharge unit.

4. The robust high-voltage electrostatic protection circuit according to claim 2, characterized in that: The layout area of ​​the first bidirectional electrostatic discharge path is equal to the layout area of ​​the second bidirectional electrostatic discharge path.

5. The robust high-voltage electrostatic protection circuit according to any one of claims 2-4, characterized in that: The third and fourth electrostatic discharge units on the second electrostatic discharge path constitute a state control module.

6. The robust high-voltage electrostatic protection circuit according to claim 5, characterized in that: The charge discharge module includes a first MOS transistor and a second MOS transistor. The source of the first MOS transistor is connected to a first floating node, and the gate is connected to a second floating node. The source of the second MOS transistor is connected to a second floating node, and the gate is connected to a first floating node. The drains of the first MOS transistor and the second MOS transistor are respectively connected to a second port. The first MOS transistor and the second MOS transistor are respectively provided with overcurrent protection structures.

7. The robust high-voltage electrostatic protection circuit according to claim 6, characterized in that: The overcurrent protection structure comprises a first rectifier diode and a second rectifier diode. The drain of the first MOSFET is connected to the second port through the first rectifier diode, and the drain of the second MOSFET is connected to the second port through the second rectifier diode. The first and second rectifier diodes are respectively configured in the same direction as the first electrostatic discharge unit. or, The overcurrent protection structure is a third rectifier diode. The drains of the first MOSFET and the second MOSFET are respectively connected to one end of the third rectifier diode, and the other end of the third rectifier diode is connected to the second port. The third rectifier diode is arranged in the same direction as the first electrostatic discharge unit.

8. The robust high-voltage electrostatic protection circuit according to claim 6, characterized in that: The overcurrent protection structure involves floating the first MOSFET and the second MOSFET.

9. The robust high-voltage electrostatic protection circuit according to any one of claims 2-4, characterized in that: The first bidirectional electrostatic discharge path includes several parallel first electrostatic discharge branches. The first electrostatic discharge branches are stacked together with first electrostatic discharge units and second electrostatic discharge units. The first floating nodes of the several first electrostatic discharge branches are connected. The second bidirectional electrostatic discharge path includes several parallel second electrostatic discharge branches. The second electrostatic discharge branches are stacked together by the third electrostatic discharge unit and the fourth electrostatic discharge unit, and the second floating nodes of the several electrostatic discharge branches are connected.

10. The robust high-voltage electrostatic protection circuit according to any one of claims 2-4, characterized in that: The first electrostatic discharge unit, the second electrostatic discharge unit, the third electrostatic discharge unit, and the fourth electrostatic discharge unit each include one or more electrostatic protection devices. The electrostatic protection devices include one or more of diodes, MOSFETs, BJTs, and thyristors. The electrostatic protection devices can be mixed and stacked together, and the number of stacking levels is one or more.

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