Low-voltage power distribution circuit with state maintaining function

Abstract

The invention provides a low-voltage power distribution circuit with a state maintaining function, which comprises an intermediate relay and an NMOS (N-channel metal oxide semiconductor) tube, in an initial state and a power-off instruction state, the grid voltage of the NMOS tube is zero, the NMOS tube is in a cut-off state, and power distribution cannot be output; after a power-up instruction is sent, the intermediate relay switches on the instruction power, partial voltage is formed through the resistor, the partial voltage is introduced into the grid electrode of the NMOS tube after passing through the RC buffer time-delay circuit, and when the threshold voltage of the grid electrode of the NMOS tube is reached, the NMOS tube is switched on, and the power distribution output is switched on. The problem that an NMOS tube cannot be reliably conducted on a low-voltage application occasion is solved by introducing an instruction power supply, meanwhile, compared with a PMOS tube, the NMOS tube has the advantages that the conduction impedance RDS (on) is smaller, loss reduction is facilitated, safe use under a load surge large-current occasion is achieved by means of the anti-surge advantage of the MOS tube and adjustable RC buffer time delay circuit parameters, and the circuit has the advantages of being simple in structure, low in cost and the like. Relay control is introduced, so that the current power-on and power-off states can be stored, and the circuit is ensured to recover the previous power supply state after being restarted in an abnormal power-off state.

Description

Technical Field

[0001] This invention relates to the field of electrical engineering technology, and in particular to a low-voltage power distribution circuit with a status holding function. Background Technology

[0002] In missiles, launch vehicles, artificial satellites, spacecraft, space shuttles and their supporting ground tracking and control equipment, the power supply subsystem, power distribution subsystem and various control subsystems have extensive requirements for low-voltage power distribution applications.

[0003] Traditional low-voltage power distribution methods typically use direct relay connection or relay-controlled PMOS transistors for power distribution. However, direct relay connection has strict requirements on the inrush current at the load end, and large inrush currents can easily cause the relay contacts to stick together. The relay-controlled PMOS transistor method is limited by the MOS transistor's turn-on threshold voltage V. GS(th) Due to limitations, it is difficult to guarantee the effective and reliable conduction of PMOS transistors for voltages below 8V (such as +5V and +3.3V power distribution). Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a low-voltage power distribution circuit with a state-holding function, which controls the gate voltage (V) of an NMOS transistor by introducing a command power supply through a relay. GS By rationally designing circuit parameters and selecting components, reliable conduction under low voltage can be achieved, while the power-off state retention function can be realized through relays.

[0005] A low-voltage power distribution circuit with state holding function includes an intermediate relay K1 and an NMOS transistor V1;

[0006] Intermediate relay K1 includes at least one moving contact. Each moving contact corresponds to two stationary contacts, forming a normally closed contact with one of the stationary contacts and a normally open contact with the other. The normally closed stationary contact is in a floating state. The normally open stationary contact is connected to one end of resistor R6 and one end of resistor R8. The moving contact is connected to the command voltage through resistor R5. The positive and negative terminals of the de-energizing coil of intermediate relay K1 are connected through two diodes V2 and V3. The positive and negative terminals of the energizing coil of intermediate relay K1 are connected through two diodes V4 and V5. De-energizing... The negative terminal of the coil receives the power-off command, and the positive terminal of the power-off coil is connected to the command power through resistor R1. The negative terminal of the power-on coil receives the power-on command, and the positive terminal of the power-on coil is connected to the command power through resistor R2. Resistor R6 and capacitor C1 form an RC buffer delay circuit. The negative terminal of capacitor C1 is connected to the other end of resistor R8, and the positive terminal of capacitor C1 is connected to the other end of resistor R6 and then connected to the gate of NMOS transistor V1 through resistor R7. The drain of NMOS transistor V1 is the power distribution input terminal, and the source of NMOS transistor V1 is the power distribution output terminal.

[0007] Compared with the prior art, the present invention has the following beneficial effects:

[0008] The low-voltage power distribution circuit of this invention solves the problem of unreliable NMOS transistor conduction in low-voltage applications by introducing command power through a relay. Furthermore, compared to PMOS transistors, the on-resistance R of the NMOS transistor is... DS(on) Smaller size helps reduce losses, and thanks to the surge protection of the MOSFET itself and the adjustable parameters of the RC buffer delay circuit, it solves the problem of safe use in situations with high current surges. The introduction of relay control can save the current power-on / off state, ensuring that the circuit can restore the previous power supply state after an abnormal power outage and restart. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a diagram of a direct-connection circuit for a relay.

[0011] Figure 2 This is a circuit diagram of a relay-controlled PMOS transistor.

[0012] Figure 3 This is a schematic diagram of a low-voltage power distribution circuit with state maintenance function provided in an embodiment of the present invention. Detailed Implementation

[0013] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the invention. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the invention.

[0014] Figure 1 This demonstrates a traditional direct-distribution relay power supply method. The relay coil "+" terminal is connected to the command power supply through a current-limiting resistor, and the coil "-" terminal is controlled by an OC command to turn the coil on and off. When a "power-off command" is sent, contact 4-2 is closed; when a "power-on command" is sent, contact 4-3 is closed. The OC command is in the form of a negative pulse with a pulse width of 80ms ± 10ms and a pulse amplitude ≤ 1.5V. The relay's initial state is that the moving contact is located at contact 2, disconnecting the power distribution input and output. When a "power-on command" is sent, the power distribution input and output networks are connected.

[0015] The appropriate size relay is usually selected based on the load current (generally, the larger the current, the larger the relay size). However, the surge current at the load end is usually twice the rated current, so the size of the relay will be further increased. The disadvantages of this are that the mechanical resistance is significantly weakened and the printed circuit board size is increased, which is obviously not conducive to the miniaturization of equipment and the mechanical environment requirements of the load application, such as strong vibration, impact and centrifugal acceleration.

[0016] Figure 2 This demonstrates the relay-controlled PMOS transistor power distribution method. In the initial state and under the power-off command, contacts 3 and 4 of the relay are in the open state, meaning the lower end of resistor R2 is not grounded, and resistor R1 cannot form an effective voltage divider (V). GS When the PMOS transistor cannot be turned on, after the power-on command is sent, the relay contacts 3 and 4 make contact, the lower end of resistor R2 is grounded, and a voltage divider is formed across resistor R1. After reaching the gate conduction threshold voltage of MOS transistor V1, the PMOS transistor turns on, and there is power output.

[0017] The relay-controlled PMOS transistor design can mitigate the impact of load inrush current; however, for low-voltage applications, especially below 8V (such as +5V and +3.3V distribution), the voltage of the PMOS transistor cannot be guaranteed. GS When the voltage is in the fully conducting region and under high current conditions, the PMOS transistor has a large voltage drop and heat dissipation.

[0018] To address these issues, the inventors proposed a method that introduces command power to the gate of the NMOS transistor via a small relay, thereby ensuring the V of the NMOS transistor... GS The voltage is always kept in the fully conductive region, thus ensuring reliable power distribution in low-voltage fields through reasonable circuit parameter design.

[0019] Figure 3 A low-voltage power distribution circuit with state holding function provided in an embodiment of the present invention includes an intermediate relay K1 and an NMOS transistor V1;

[0020] Intermediate relay K1 is a 10-pin intermediate relay. Contacts 4 and 9 are moving contacts. Contact 4 corresponds to two stationary contacts 2 and 3. Contacts 2 and 4 form a normally closed circuit, and contact 3 and 4 form a normally open circuit. Contact 9 corresponds to two stationary contacts 8 and 7. Contacts 8 and 9 form a normally closed circuit, and contact 7 and 9 form a normally open circuit. Contacts 4 and 9 are connected and connected to a 30V command voltage via resistor R5. Contacts 5 and 6 are the terminals for the de-energizing coil. Contacts 10 and 1 are the terminals for the energizing coil. Contacts 2 and 8 are in a floating state. Contacts 5 and 6 are connected via diodes V2 and V3. The de-energizing coil receives the de-energizing command through contact 6 and is connected to resistor R5 via contact 5. 1. The other end of resistor R1 is connected to the 30V command voltage. Contacts 1 and 10 are connected through two diodes V4 and V5. The power-on coil receives the power-on command through contact 1. The power-on coil is connected to resistor R2 through contact 10. The other end of resistor R2 is connected to the 30V command voltage. Contacts 3 and 7 are connected to two branches. One branch is connected to resistor R8, and the other branch is connected to resistor R6. Resistor R6 and capacitor C1 form an RC buffer delay circuit. One end of capacitor C1 is connected to resistor R8, and the other end of capacitor C1 is connected to resistor R6 and then to the gate of NMOS transistor V1 through resistor R7. The drain of NMOS transistor V1 is the power input terminal, and the source of NMOS transistor V1 is the power output terminal.

[0021] The working principle of this low-voltage power distribution circuit with status maintenance function is as follows:

[0022] In the initial state and under the power-off command state, the 4 / 9 contact of the intermediate relay K1 is connected to the 2 / 8 contact. Since the 2 / 8 contact is in a floating state, the resistors R6 / R8 are equivalent to ground, the gate voltage of the NMOS transistor V1 is zero, the NMOS transistor V1 is in the off state, and the power distribution cannot be output. After the power-on command is sent, the 4 / 9 contact of the intermediate relay is connected to the 3 / 7 contact, and the command voltage of 30V is introduced through the resistor R5. The voltage is divided by the resistor R8, and after passing through the RC buffer delay circuit composed of the resistor R6 and the capacitor C1, the divided voltage is introduced into the gate of the NMOS transistor V1. When the gate turn-on threshold voltage of the NMOS transistor V1 is reached, the NMOS transistor V1 is turned on, and the power distribution output is turned on.

[0023] By designing the values ​​of resistors R5 and R8, V G The network voltage is:

[0024]

[0025] Before NMOS transistor V1 is turned on, its source voltage is zero. Therefore, the Vo of NMOS transistor V1 is zero. GS equals V GThe network voltage must be less than the maximum safe gate-source voltage of NMOS transistor V1. When NMOS transistor V1 is turned on, its source voltage equals the distribution voltage. At this time, the gate-source voltage V of NMOS transistor V1 is... GS for:

[0026] V GS =V G -Power distribution voltage

[0027] Under different power distribution voltages, the gate-source voltage V of NMOS transistor V1 can be adjusted by adjusting the values ​​of resistors R5 and R8. GS This voltage must be greater than the full turn-on voltage of the NMOS transistor V1 to ensure reliable conduction of V1. Since the MOS transistor itself has strong surge current resistance, the load surge current can be further suppressed by adjusting the parameters of resistor R6 and capacitor C1.

[0028] Introducing relay control can save the current power-on / off state. If the current state is power-on (intermediate relay 4 / 9 contacts connected to 3 / 7 contacts), the intermediate relay will remain power-on after a power outage and restart, without the need for an external power-on command. Conversely, if the current state is power-off (intermediate relay 4 / 9 contacts connected to 2 / 8 contacts), the intermediate relay will remain power-off after a power outage and restart, and the power distribution circuit will not output incorrectly.

[0029] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A low-voltage power distribution circuit with state retention function, characterized in that, This includes intermediate relay K1 and NMOS transistor V1; Intermediate relay K1 includes at least one moving contact. Each moving contact corresponds to two stationary contacts, forming a normally closed contact with one of the stationary contacts and a normally open contact with the other. The normally closed stationary contact is in a floating state. The normally open stationary contact is connected to one end of resistor R6 and one end of resistor R8. The moving contact is connected to the command voltage through resistor R5. The positive and negative terminals of the de-energizing coil of intermediate relay K1 are connected through two diodes V2 and V3. The positive and negative terminals of the energizing coil of intermediate relay K1 are connected through two diodes V4 and V5. De-energizing... The negative terminal of the coil receives the power-off command, and the positive terminal of the power-off coil is connected to the command power through resistor R1. The negative terminal of the power-on coil receives the power-on command, and the positive terminal of the power-on coil is connected to the command power through resistor R2. Resistor R6 and capacitor C1 form an RC buffer delay circuit. The negative terminal of capacitor C1 is connected to the other end of resistor R8, and the positive terminal of capacitor C1 is connected to the other end of resistor R6 and then connected to the gate of NMOS transistor V1 through resistor R7. The drain of NMOS transistor V1 is the power distribution input terminal, and the source of NMOS transistor V1 is the power distribution output terminal.

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