Power supply control circuit and DCDC circuit

Abstract

The embodiment of the invention discloses a power supply control circuit and a DCDC circuit, and the circuit comprises an error amplification circuit which compares a power supply feedback voltage with a power supply reference voltage to obtain an error voltage; a signal processing unit that performs compensation and current conversion on the error voltage to generate a compensation current; the current detection unit is connected with a power supply and the signal processing unit so as to convert the compensation current into a first conversion voltage and convert the output current of the power supply into a second conversion voltage; a first comparison unit which compares the first conversion voltage and the second conversion voltage and generates an on-time control signal; and the logic control unit is used for adjusting a duty ratio signal of the DCDC circuit according to the conduction time control signal. By means of the technical scheme, the conduction time control signal can be generated through simple current and voltage conversion processing under the condition that an operational amplifier circuit does not need to be arranged, so that the circuit design complexity is reduced, the signal delay is reduced, and the accuracy of the conduction time control signal is improved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and more particularly to a power control circuit and a DC-DC circuit. Background Technology

[0002] In DC-DC converter circuits, current sampling is a core component for overcurrent protection and loop regulation. Currently, a common current sampling scheme is mirror-based power transistor sampling. This method involves designing a mirror-based main power transistor and a sampling transistor, using the sampling transistor to replicate a portion of the current from the main power transistor's current based on the current mirror principle, thus providing a sampling signal.

[0003] However, because DC-DC circuits have high requirements for the current sampling accuracy and speed of the main power transistor, in practical applications, the image ratio between the main power transistor and the sampling transistor is generally large. The larger the image ratio, the more significant the error, and the higher the design requirements for the operational amplifier. Especially when the PWM frequency increases, the sampling period of the sampling transistor becomes shorter, requiring a larger bandwidth from the sampling circuit, which makes the stability design of the sampling circuit more complex. In addition, the complex structural design of the sampling circuit can also lead to a large signal delay, affecting the sampling accuracy. Summary of the Invention

[0004] In view of this, the present disclosure provides a power control circuit suitable for DC-DC circuits, which can reduce circuit design complexity, reduce signal processing delay, and improve the accuracy of the conduction time control signal.

[0005] According to a first aspect of this disclosure, a power control circuit is provided for use in a DC-DC circuit, the power control circuit comprising:

[0006] The error amplifier unit is connected to the power supply and is configured to compare the power supply feedback voltage and the power supply reference voltage to obtain the error voltage.

[0007] A signal processing unit, connected to the error amplification unit, is configured to perform compensation and current conversion on the error voltage to generate a compensation current;

[0008] A current detection unit is connected to the power supply and the signal processing unit, and provides a switching resistor and a sampling resistor, so that the compensation current is converted into a first conversion voltage through the sampling resistor, and the output current of the power supply is converted into a second conversion voltage through the switching resistor;

[0009] A first comparison unit is connected to the signal processing unit and the current detection unit, and is configured to compare the first conversion voltage and the second conversion voltage to generate a conduction time control signal;

[0010] A logic control unit, connected to the first comparison unit, is configured to adjust the duty cycle signal of the DC-DC circuit according to the on-time control signal.

[0011] According to a second aspect of this disclosure, a DC-DC circuit is provided, which includes a power control circuit as described in the first aspect to adjust the power supply voltage of the DC-DC circuit by means of a duty cycle signal output by the power control circuit.

[0012] The power control circuit provided in this disclosure generates a conduction time control signal without performing current sampling or setting up an operational amplifier circuit. This reduces the complexity of circuit design and improves the signal delay problem, thereby increasing the accuracy of the conduction time control signal (Ton signal). By converting the error voltage between the power supply feedback voltage and the power supply reference voltage into a compensation current, and by converting the compensation current into a first conversion voltage and the power supply output current into a second conversion voltage for comparison, the power control circuit provides a power control signal that can generate a conduction time control signal without performing current sampling or setting up an operational amplifier circuit. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a topology diagram of a buck-boost circuit.

[0015] Figure 2 This is a schematic diagram of a power control circuit 200 that is traditionally used in DC-DC circuits.

[0016] Figure 3 for Figure 2 The specific circuit structure of the medium current sampling unit 202.

[0017] Figure 4 and Figure 5 A simplified structural diagram of a power control circuit according to different embodiments of the present disclosure is shown.

[0018] Figure 6 for Figure 4 and Figure 5 The circuit diagram for the specific implementation of the simplified structure shown is shown.

[0019] Figure 7 for Figure 6 The signal timing diagram of the circuit shown is shown.

[0020] List of reference numerals in the attached diagram:

[0021] 100. Buck-Boost Circuit (DC-CDC Circuit) 212. Adder

[0022] 102. Pre-drive circuit; 214. Comparator

[0023] 104. First power transistor; 216. Logic unit

[0024] 106. Second power transistor 302. Main power transistor (MP)

[0025] 108. 304 Inductor, Sampling Tube (MS)

[0026] 110. Capacitor 306. Operational Amplifier (OP) Unit

[0027] 200. Current sampling control circuit (traditional) 400. Power supply control circuit

[0028] 202. Current sampling unit; 410. Error amplification unit

[0029] 204, Comparator 412, First transconductance amplifier

[0030] 206, Transconductance Amplifier 414, Compensation Network

[0031] 208, Compensation Network; 420, Signal Processing Unit

[0032] 210. Slope compensator; 422. Slope compensator

[0033] 424. Adder; 476. Second capacitor (C2)

[0034] 426. Voltage-to-current converter (M1) iL, inductor current

[0035] 428. First switching resistor (Rcs) VIN, power supply

[0036] 430. Current detection unit HS, high-level drive signal

[0037] 432, Sampling tube LS, Low-level drive signal

[0038] 434. Switching power transistor DUTY, duty cycle signal

[0039] 440, First Comparison Unit VB, Power Supply Feedback Voltage

[0040] 450, Logic Control Unit VREF, Power Supply Reference Voltage

[0041] 460. Second comparison unit Icomp, error current

[0042] 470, Clamping unit Vcomp, Error voltage

[0043] 471. Arithmetic Unit Vcomp1, Slope Compensation Voltage

[0044] 472. Sampling switch (K) Ics, compensation current

[0045] 473. First capacitor (C1), Ron, switching resistor

[0046] 474. Clamping transistor (M2), Rsen, sampling resistor

[0047] 475. Second switching resistor (Rsh)

[0048] Vset, first transition voltage CLK, clock signal

[0049] Vsw, second conversion voltage Ton, on-time control signal

[0050] Vocp, first preset voltage OCP, overcurrent protection signal

[0051] Vcs, third conversion voltage Vclamp, clamping voltage

[0052] Vsh, sampling voltage SYNC, synchronous sampling signal

[0053] Vcl, second preset voltage Detailed Implementation

[0054] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0055] Reference is made to the accompanying drawings, which form part of the detailed description and illustrate exemplary embodiments. Furthermore, it should be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that orientations and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0056] Numerous details are set forth in the following description. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the embodiments described herein. Throughout this specification, references to “embodiment,” “one embodiment,” or “some embodiments” mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment herein. Therefore, the phrases “in an embodiment,” “in one embodiment,” or “some embodiments” appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, functions, or characteristics can be combined in any suitable manner. For example, a first embodiment can be combined with a second embodiment in any way that does not mutually exclude particular features, structures, functions, or characteristics associated with two embodiments.

[0057] As used in the description and appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0058] The terms “coupling” and “connection”, along with their derivatives, are used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” can be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupling” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0059] As used herein, the terms “above,” “below,” “between,” and “on” refer to the relative position of a component or material with respect to other components or materials, where such physical relationships are noteworthy. For example, in the context of materials, a material positioned above or below another material may be in direct contact with it, or may have one or more intermediate materials. Furthermore, a material positioned between two materials may be in direct contact with both layers, or may have one or more intermediate layers. In contrast, a first material or material “on” a second material or material is in direct contact with that second material / material. Similar distinctions are made in the context of component assembly.

[0060] As described throughout this document and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0061] The terms “circuit” or “module” can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term “signal” can refer to at least one current signal, converted voltage, or magnetic signal. The terms “substantially,” “close to,” “approximately,” “near,” and “about” generally refer to within + / 10% of the target value.

[0062] In DC-DC converter circuits, current sampling is the core component for overcurrent protection and loop regulation. As an example of a DC-DC converter circuit, Figure 1 The topology of a buck-boost circuit is shown. Figure 1 As shown, the buck-boost circuit 100 mainly includes a pre-drive circuit 102, a first power transistor 104, a second power transistor 106, an inductor 108, and a capacitor 110.

[0063] The pre-drive circuit 102 outputs a high-level or low-level drive signal according to the duty cycle signal (DUTY). When the pre-drive circuit 102 outputs a high-level drive signal HS, the first power transistor 104 is turned on and the second power transistor 106 is turned off. The power supply VIN and the inductor 108 are interconnected, and the inductor current iL gradually increases. When the pre-drive circuit 102 outputs a low-level drive signal LS, the first power transistor 104 is turned off and the second power transistor 106 is turned on. The power supply VIN and the inductor 108 are disconnected. The inductor 108 releases energy to charge the capacitor 110, and the inductor current iL gradually decreases.

[0064] Figure 2 A schematic diagram of a conventional power control circuit 200 suitable for DC-DC circuits is shown. Figure 2 As shown, the current sampling control circuit 200 mainly includes a current sampling unit 202, a comparator 204, a transconductance amplifier (OTA) 206, a compensation network 208, a slope comparator 210, an adder 212, a comparator 214, and a logic operation unit 216.

[0065] The current sampling unit 202 samples the current of the inductor L and outputs the sampled current Isen. The sampled current Isen is converted into a sampled voltage Vsen through the sampling resistor Rsen and input to the comparator 204. When the comparator 204 compares the sampled voltage Vsen and finds that it exceeds the preset voltage threshold Vocp, it outputs an overcurrent protection signal OCP.

[0066] Transconductance amplifier 206 performs transconductance amplification based on power supply feedback voltage FB and power supply reference voltage VREF, generating a comparison current Icomp. Compensation network 208 compensates for the comparison current Icomp, generating a comparison voltage Vcomp. Slope compensator 210 generates a slope compensation voltage Vslope based on the slope compensation signal output by logic operation unit 216. Adder 212 superimposes the comparison voltage Vcomp compensated by compensation network 208 and the inverted signal of slope compensation voltage Vslope output by slope compensator 210 to generate a slope compensation voltage Vcomp1. Comparator 214 generates an on-time control signal Ton by comparing the sampled voltage Vsen and the slope compensation voltage Vcomp1.

[0067] The logic operation unit 216 is used to generate the duty cycle signal Duty based on the clock signal CLK, the overcurrent protection signal OCP, and the conduction time control signal Ton.

[0068] As shown in the figure above, the overcurrent protection signal OCP and the conduction time control signal Ton of the traditional power control circuit 200 both rely on the sampling current Isen output by the current sampling unit 202. A common current sampling scheme is mirror power transistor sampling. Its principle is to design a mirrored main power transistor and a sampling transistor to use the sampling transistor to copy a portion of the current from the main power transistor based on the current mirror principle as a sampling signal.

[0069] refer to Figure 3 It shows Figure 2 The specific circuit structure of the medium current sampling unit 202 mainly consists of a main power transistor 302, a sampling transistor (MS) 304, and an operational amplifier unit (OP) 306. When the upper bridge gate control voltage (HS) is high, the main power transistor 302 and the sampling transistor 304 are turned on. The operational amplifier unit 306 includes a differential pair (M1, M2) and an adjustment transistor M3. After the operational amplifier unit 306 stabilizes, the potentials of nodes A and B are equal, i.e., V(A) = V(B). The differential pair (M1, M2) detects the voltage difference between nodes A and B respectively, and the adjustment transistor M3 extracts a sampling current Isen based on the voltage difference between nodes A and B, ensuring that the potentials of nodes A and B remain equal.

[0070] The above solution requires the use of operational amplifier unit 306 to detect the current of main power transistor 302. As the PWM frequency increases, the bandwidth of operational amplifier unit 306 increases, leading to a decrease in its stability and accuracy. In addition, there is a signal delay from the output of inductor current iL to sampling current Isen, and there is also a signal delay from the output of sampling current Isen to conduction time control signal Ton.

[0071] Based on the above-mentioned technical problems, the embodiments of this disclosure provide a power control circuit for a DC-DC circuit, which can reduce the complexity of circuit design, reduce signal delay, and improve the accuracy and stability of the conduction time control signal.

[0072] The specific implementations of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings:

[0073] Power control circuit

[0074] Figure 4 and Figure 5 Simplified structural diagrams of power control circuits according to different embodiments of this disclosure are shown. Figure 4 The on-time control signal generation control scheme of the power supply control circuit is shown. Figure 5 The overcurrent protection and voltage stabilization control scheme of the power supply control circuit is shown. Figure 6 for Figure 4 and Figure 5 The circuit diagram for the specific implementation of the embodiment shown is illustrated.

[0075] like Figure 4 As shown, the power control circuit 400 in this embodiment mainly includes: an error amplifier 410, a signal processing unit 420, a current detection unit 430, a first comparison unit 440, and a logic control unit 450.

[0076] The error amplification unit 410 is connected to the power supply VIN and is configured to detect the power supply feedback voltage VB of the power supply VIN. It compares the voltage difference between the power supply feedback voltage VB and the power supply reference voltage VREF to obtain the error voltage Vcomp. The power supply reference voltage VREF is a preset value.

[0077] refer to Figure 6 In some embodiments, the error amplification unit 410 may include a first transconductance amplifier 412 and a compensation network 414.

[0078] The first transconductance amplifier 412 is configured to take the power supply feedback voltage VB as the negative feedback input and the power supply reference voltage VREF as the positive feedback input, perform voltage transconductance amplification processing, and generate an error current Icomp.

[0079] The compensation network 414 is connected to the output of the first transconductance amplifier 412 and is configured to compensate for the error current Icomp, generating an error voltage Vcomp.

[0080] The signal processing unit 420 is connected to the error amplification unit 410 and is configured to perform compensation and current conversion on the error voltage Vcomp to generate a compensation current Ics.

[0081] refer to Figure 6In some embodiments, the signal processing unit 420 includes a slope compensator 422, an adder 424, and a voltage-to-current converter 426.

[0082] The slope compensator 422 is configured to generate a slope compensation voltage Vslope.

[0083] Adder 424 is connected to compensation network 414 and slope compensator 422 and is configured to superimpose the inverted signal (-) of slope compensation voltage Vslope onto error voltage Vcomp (+) to generate error compensation voltage Vcomp1.

[0084] The voltage-to-current converter 426 is connected to the adder 424 and is configured to convert the error compensation voltage Vcomp1 into a compensation current Ics. In some embodiments, the voltage-to-current converter 426 may be designed as a MOSFET, but is not limited thereto, and other types of voltage-to-current conversion elements may also be used.

[0085] The current detection unit 430 is connected to the power supply VIN and the signal processing unit 420, and provides a switching resistor Ron and a sampling resistor Rsen, so that the compensation current Ics is converted into a first conversion voltage Vset through the sampling resistor Rsen, and the output current Iout of the power supply VIN is converted into a second conversion voltage Vsw through the switching resistor Ron.

[0086] refer to Figure 6 In some embodiments, the current detection unit 430 includes a sampling transistor 432 and a switching power transistor 434. For the basic functions and operating principles of the sampling transistor 432 and the switching power transistor 434, please refer to the foregoing. Figure 3 The relevant descriptions of the embodiments will not be repeated here. The following is a detailed description only of the improvements to the sampling transistor 432 and the switching power transistor 434.

[0087] In this embodiment, the sampling transistor 432 has a sampling resistor Rsen and is connected to the power supply VIN, the voltage-to-current converter 426, and the first comparator unit 440, so that the compensation current Ics is converted into a first conversion voltage Vset through the sampling transistor 432 and input to the first comparator unit 440. The switching power transistor 434 has a switching resistor Ron and is connected to the power supply VIN and the first comparator unit 440, so that the output current Iout of the power supply VIN is converted into a second conversion voltage Vsw through the switching power transistor 434 and input to the first comparator unit 440.

[0088] The first comparison unit 440 is connected to the voltage-to-current conversion transistor 426 and the current detection unit 430 of the signal processing unit 420, and is configured to compare the first conversion voltage Vset and the second conversion voltage Vsw to generate the on-time control signal Ton.

[0089] In this embodiment, the first conversion voltage satisfies the following formula 1:

[0090] V set =V IN -I cs ×R sen (Formula 1)

[0091] In Formula 1, V set Indicates the first conversion voltage, V IN I represents the input voltage of the power supply. cs R represents the compensation current. sen This represents the sampling resistor. Therefore, it can be seen that the larger the compensation current I... cs At that time, the first conversion voltage V set The smaller.

[0092] In this embodiment, the second conversion voltage satisfies the following formula 2:

[0093] V sw =V IN -I out ×R son (Formula 2)

[0094] In Formula 2, V sw V represents the second conversion voltage. IN I represents the input voltage of the power supply. out R represents the output current of the power supply. son This indicates the switching resistor.

[0095] In this embodiment, the first comparison unit 440 uses the first conversion voltage Vset as positive feedback input and the second conversion voltage Vsw as negative feedback input. If the first conversion voltage is not less than the second conversion voltage (Vset ≥ Vsw), it outputs a high-level on-time control signal (Ton = 1); if the first conversion voltage is less than the second conversion voltage (Vset < Vsw), it inputs a low-level on-time control signal (Ton = 0). Therefore, the toggling condition of the first comparison unit 440 is: Iout = Ics × (Rsen / Ron).

[0096] The logic control unit 450 is connected to the first comparison unit 440 and is configured to generate the duty cycle signal DUTY of the DC-DC circuit according to the on-time control signal Ton.

[0097] In this embodiment, the logic control unit 450 also receives a clock signal CLK. When the logic control unit 450 detects the rising edge of the clock signal CLK, it outputs a high-level duty cycle signal (DUTY = 1), causing the power supply voltage of the DCDC circuit to rise. When it detects a low-level on-time control signal (Ton = 0), it outputs a low-level duty cycle signal (DUTY = 0), causing the power supply voltage of the DCDC circuit to decrease. Specifically, when the slope compensation voltage Vcomp1 is larger, the first conversion voltage Vset is smaller. Therefore, when the first comparison unit 440 determines that the first conversion voltage is less than the second conversion voltage (Vset ≥ Vsw), it indicates that the power supply voltage is too high. In this case, a low-level on-time control signal (Ton = 0) can be output, causing the duty cycle signal to switch to a low level (DUTY = 0), thereby gradually reducing the power supply voltage of the DCDC circuit.

[0098] according to Figure 7 As shown in the circuit timing diagram, when the logic control unit 450 detects the rising edge of the clock signal CLK, it outputs a high-level duty cycle signal (DUTY=1), causing the power supply voltage of the DCDC circuit to rise and the power supply output current Iout to gradually increase. Since the adder 424 superimposes an inverting slope compensation voltage, the slope compensation voltage Vcomp1 gradually decreases. When a low-level on-time control signal (Ton=0) is detected, it outputs a low-level duty cycle signal (DUTY=0), causing the power supply voltage of the DCDC circuit to decrease, the power supply output current Iout to be pulled low, and the slope compensation voltage Vcomp1 to be pulled high.

[0099] refer to Figure 5 In some embodiments, the voltage-to-current converter 426 is also grounded through a first conversion resistor (Rcs) 428 to convert the compensation current Ics into a third conversion voltage Vcs = Ics × Rcs.

[0100] exist Figure 5 In the illustrated embodiment, the power control circuit 400 further includes a second comparison unit 460 and a clamping unit 470.

[0101] The second comparison unit 460 is connected to the voltage-to-current conversion transistor 426 and the first conversion resistor 428 of the signal processing unit 420 to obtain the third conversion voltage Vcs, and is configured to compare the third conversion voltage Vcs with the first preset voltage Vocp. If the first preset voltage Vocp is greater than the third conversion voltage Vcs, an overcurrent protection signal OCP is output.

[0102] When an overcurrent protection signal is detected, the logic control unit 450 outputs a low-level duty cycle signal DUTY, thereby reducing the power supply voltage of the DC-DC circuit. In other words, when the duty cycle signal DUTY is at a high level, the logic control unit 450 simultaneously detects the on-time control signal Ton and the overcurrent protection signal OCP. Upon detecting a low-level on-time control signal (Ton = 0) output by the first comparator unit 440, or upon detecting an overcurrent protection signal OCP output by the second comparator unit 460, the logic control unit 450 switches the duty cycle signal DUTY from high to low to reduce the power supply voltage. This limits the maximum output current Iout_max of the power supply VIN to: Iout_max ≤ ((V_ocp) / Rcs) × (Rsen / Ron).

[0103] The input terminal of the clamping unit 470 is connected to the signal processing unit 420 and the first conversion resistor 428 to obtain the third conversion voltage Vcs, and the output terminal of the clamping unit 470 is connected to the error amplification unit 410. The clamping unit 470 is configured to generate a clamping voltage Vclamp based on the comparison result of the third conversion voltage Vcs and the second preset voltage Vcl, so as to adjust the error voltage Vcomp output by the error amplification unit 410.

[0104] refer to Figure 6 In some embodiments, the clamping unit 470 includes an arithmetic unit 471, a sampling switch (K) 472, a first capacitor (C1) 473, and a clamping transistor (M2) 474.

[0105] The first capacitor 473 is connected to the voltage-to-current converter 426 and the first conversion resistor 428 via the sampling switch 472, and is configured to acquire the sampling voltage Vsh of the third conversion voltage Vcs when the sampling switch 472 is closed.

[0106] Reference Figure 7 In this embodiment, the logic control unit 450 is also connected to a sampling switch 472. When a high-level on-time control signal (Ton=1) is detected, a high-level synchronous sampling signal (SYNC=1) is output to control the sampling switch 472 to close. When a low-level on-time control signal (TON=0) is detected, a low-level synchronous sampling signal (SYNC=0) is output to control the sampling switch 472 to open. When the sampling switch 472 is closed, the third conversion voltage Vcs can be sampled into the first capacitor 473 to obtain the sampling voltage Vsh.

[0107] The negative feedback input terminal of the arithmetic unit 471 is connected to the first capacitor 473 to obtain the sampling voltage Vsh. The positive feedback input terminal of the arithmetic unit 471 obtains the second preset voltage Vcl. The output terminal of the arithmetic unit 471 is connected to the clamping transistor 474 to generate a clamping voltage by comparing the sampling voltage Vsh of the first capacitor 473 and the second preset voltage Vcl.

[0108] In some embodiments, the arithmetic unit 471 is a second transconductance amplifier. The output of the arithmetic unit 471 is also connected to a second capacitor (C2) 476 through a second conversion resistor (Rsh) 475 and is configured to perform transconductance amplification on the sampled voltage Vsh and the second preset voltage Vcl to generate a clamping current. The clamping current is converted into a clamping voltage Vclamp through the second conversion resistor 475.

[0109] Clamping transistor (M2) 474 connects the compensation network 414 of error amplification unit 410 and arithmetic unit 471, and is configured to turn on when the error voltage Vcomp is greater than the clamping voltage Vclamp, so as to reduce the error voltage Vcomp by the clamping voltage Vclamp, thereby keeping the error voltage Vcomp stable (see reference). Figure 7 The error voltage Vcomp in the timing diagram ensures the stability of the on-time control signal Ton.

[0110] In some embodiments, the clamping transistor 474 is a PMOS transistor, the gate of the clamping transistor 474 is connected to the arithmetic unit 471, the source of the clamping transistor 474 is connected to the compensation network 414, and the drain of the clamping transistor 474 is grounded.

[0111] In summary, the power control circuits provided in the embodiments of this disclosure convert the voltage difference between the power supply feedback voltage and the power supply reference voltage into a compensation current, and convert the compensation current into a first conversion voltage and the power supply output current into a second conversion voltage for comparison. This allows for the control output of the conduction time control signal without the need for current sampling and operational amplifier circuit design, reducing the complexity of circuit design and improving signal delay issues. It can also improve the accuracy of the conduction time control signal and enhance power management performance.

[0112] Furthermore, the power control circuits provided in the embodiments of this disclosure can achieve overcurrent protection of the power supply by converting the compensation current into a third conversion voltage and comparing it with a first preset voltage. Moreover, since the overcurrent protection signal and the conduction time control signal are two independent parallel processing threads, and are generated directly through signal comparison without current sampling, the complexity of signal processing is reduced and the signal delay problem is improved. Therefore, the reliability and safety of the entire circuit structure system can be significantly improved.

[0113] Furthermore, the power control circuits in the various embodiments of this disclosure clamp and limit the error voltage, thereby maintaining the error voltage in a stable state and improving the stability of the conduction time control signal.

[0114] DC-DC circuit

[0115] Another embodiment of this disclosure provides a DC-DC circuit, which includes a power control circuit 400 as described in the foregoing embodiments, to adjust the power supply voltage of the DC-DC circuit through a duty cycle signal generated by the power control circuit 400.

[0116] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0117] It should also be noted that improvements to a technology can be hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology), or even direct improvements to the hardware circuit structure. Therefore, it cannot be said that an improvement to a methodology cannot be implemented using hardware modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program a digital system onto a PLD themselves, without needing chip manufacturers to design and fabricate dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog are the most commonly used. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0118] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0119] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0120] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0121] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0122] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0123] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0124] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0125] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0126] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0127] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0128] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0129] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0130] This application can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific transactions or implement specific abstract data types. This application can also be practiced in distributed computing environments where transactions are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0131] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0132] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A power control circuit (400) applied to a DC-DC circuit, the power control circuit (400) comprising: An error amplification unit (410) is connected to a power supply and is configured to compare the power supply feedback voltage and the power supply reference voltage to obtain an error voltage. A signal processing unit (420), connected to the error amplification unit (410), is configured to perform compensation and current conversion on the error voltage to generate a compensation current; A current detection unit (430) is connected to the power supply and the signal processing unit (420), and provides a switching resistor and a sampling resistor, such that the compensation current is converted into a first conversion voltage through the sampling resistor, and the output current of the power supply is converted into a second conversion voltage through the switching resistor; A first comparison unit (440) is connected to the signal processing unit (420) and the current detection unit (430) and is configured to compare the first conversion voltage and the second conversion voltage to generate a conduction time control signal; A logic control unit (450), connected to the first comparison unit (440), is configured to adjust the duty cycle signal of the DC-DC circuit according to the on-time control signal.

2. The power control circuit (400) according to claim 1, wherein, The error amplification unit (410) includes: A first transconductance amplifier (412) is configured to take the power supply feedback voltage as a negative feedback input and the power supply reference voltage as a positive feedback input, perform voltage transconductance amplification processing, and generate an error current. A compensation network (414), connected to the first transconductance amplifier (412), is configured to compensate for the error current and generate an error voltage.

3. The power control circuit (400) according to claim 1 or 2, wherein, The signal processing unit (420) includes: A slope compensator (422) is configured to generate a slope compensation voltage; An adder (424), which connects the compensation network (414) and the slope compensator (422), is configured to superimpose the inverted signal of the slope compensation voltage onto the error voltage to generate the error compensation voltage; A voltage-to-current converter (426), connected to the adder (424), is configured to convert the error compensation voltage into the compensation current.

4. The power control circuit (400) according to claim 1, wherein, The current detection unit (430) includes: A sampling tube (432) having the sampling resistor and connected to the power supply, the signal processing unit (420) and the first comparison unit (440) is provided such that the compensation current is converted into the first conversion voltage through the sampling tube (432) and input to the first comparison unit (440). A switching power transistor (434) having the switching resistor and connected to the power supply and the first comparator unit (440) is provided, such that the output current of the power supply is converted into a second conversion voltage through the switching power transistor (434) and input to the second terminal of the first comparator unit (440).

5. The power control circuit (400) according to claim 4, wherein, The first conversion voltage satisfies the following formula: V set =V IN -I cs ×R sen The second conversion voltage satisfies the following formula: V sw =V IN -I out ×R son Among them, V set V represents the voltage value of the first conversion voltage. IN I represents the input voltage of the power supply. cs Represents the compensation current, the R sen Represents the sampling resistor, the V sw The I represents the voltage value of the second conversion voltage. out The R represents the output current of the power supply. son This refers to the switching resistor.

6. The power control circuit (400) according to claim 1 or 5, wherein, The first comparison unit (440) is configured to: The first conversion voltage is used as a positive feedback input, and the second conversion voltage is used as a negative feedback input. If the first conversion voltage is not less than the second conversion voltage, a high-level on-time control signal is output; if the first conversion voltage is less than the second conversion voltage, a low-level on-time control signal is input. The logic control unit (450) also receives a clock signal and is configured to: When the rising edge of the clock signal is detected, a high-level duty cycle signal is output, causing the power supply voltage of the DC-DC circuit to increase. When the low-level on-time control signal is detected, a low-level duty cycle signal is output, causing the power supply voltage of the DC-DC circuit to decrease.

7. The power control circuit (400) according to claim 3, wherein, The voltage-to-current converter (426) is also grounded through a first conversion resistor (428) to convert the compensation current into a third conversion voltage; The power control circuit (400) includes: The second comparison unit (460) is connected to the voltage-to-current converter (426) and the first conversion resistor (428) to obtain the third conversion voltage, and is configured to compare the third conversion voltage with a first preset voltage. If the first preset voltage is greater than the third conversion voltage, an overcurrent protection signal is output. The logic control unit (450) is configured to: When the overcurrent protection signal is detected, a low-potential duty cycle signal is output, causing the power supply voltage of the DC-DC circuit to decrease.

8. The power control circuit (400) according to claim 7, wherein, The power control circuit (400) includes: A clamping unit (470) is provided, the input of which is connected to the voltage-to-current converter (426) and the first conversion resistor (428) to obtain the third conversion voltage, and the output of the clamping unit (470) is connected to the error amplifier unit (410). The clamping unit (470) is configured to generate a clamping voltage based on the comparison result of the third conversion voltage and the second preset voltage, so as to adjust the error voltage output by the error amplification unit (410).

9. The power control circuit (400) according to claim 8, wherein, The clamping unit (470) includes: an arithmetic unit (471), a sampling switch (472), a first capacitor (473), and a clamping transistor (474); The first capacitor (473) is connected to the voltage-to-current converter (426) and the first conversion resistor (428) via the sampling switch (472), and is configured to acquire the sampling voltage of the third conversion voltage when the sampling switch (472) is closed; The arithmetic unit (471) is connected to the first capacitor (473) and the clamping tube (474), and is configured to compare the sampled voltage of the first capacitor (473) with the second preset voltage to generate a clamping voltage; The clamping transistor (474) is connected to the error amplification unit (410) and the arithmetic unit (471), and is configured to be turned on when the error voltage is greater than the clamping voltage, so as to reduce the error voltage by the clamping voltage.

10. The power control circuit (400) according to claim 9, wherein, The clamping transistor (474) is a PMOS transistor. The gate of the clamping transistor (474) is connected to the arithmetic unit (471), the source of the clamping transistor (474) is connected to the error amplification unit (410), and the drain of the clamping transistor (474) is grounded.

11. The power control circuit (400) according to claim 9, wherein, The logic control unit (450) is also connected to the sampling switch (472) and is configured to: When the high-potential conduction time control signal is detected, a high-potential synchronous sampling signal is output to control the sampling switch (472) to close. When the low-potential conduction time control signal is detected, a low-potential synchronous sampling signal is output to control the sampling switch (472) to open.

12. The power control circuit (400) according to claim 9, wherein, The arithmetic unit (471) is a second transconductance amplifier; The output of the second transconductance amplifier is also connected to the second capacitor (476) through the second conversion resistor (475), and is configured to perform transconductance amplification on the sampled voltage of the first capacitor (473) and the second preset voltage to generate a clamping current, and convert the clamping current into the clamping voltage through the second conversion resistor (475).

13. A DC-DC circuit comprising a power control circuit (400) as claimed in any one of claims 1 to 12, for adjusting the power supply voltage of the DC-DC circuit by means of a duty cycle signal output by the power control circuit (400).

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