SiC VDMOSFET dynamic characteristic enhancing structure with self-aligned multi-stage field plate and preparation process thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) dynamic characteristic enhancing structure with a self-aligned multi-stage field plate and a preparation process thereof, the SiC VDMOSFET dynamic characteristic enhancing structure comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a gate oxide field plate and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the gate oxide field plate is located between the gate electrode and the semiconductor epitaxial layer, and field hardening is deposited between the gate oxide field plate and the gate electrode and is composed of a plurality of silicon dioxide deposition blocks which are not in contact with one another. By adopting the self-aligned multistage field plate structure, optimal modulation of electric field distribution on the gate oxide field plate is realized, and the phenomenon of electric field concentration at the edge of the gate is effectively inhibited, so that the breakdown voltage and the dynamic stability of the device are remarkably improved, and the device shows higher reliability in the application of a high-voltage switch.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates and its fabrication process. Background Technology

[0002] Silicon carbide (SiC) VDMOSFETs, as a new generation of power semiconductor devices, have shown great potential in high-temperature, high-frequency, and high-voltage applications due to their advantages such as high breakdown field strength, high thermal conductivity, and low switching losses. However, during dynamic operation, traditional SiC VDMOSFETs are prone to current collapse, reduced switching speed, and degraded reliability due to issues such as concentrated electric field at the gate edge, uneven electric field distribution in the drift region, and interface state effects, which restricts their further application in high-performance power systems.

[0003] An existing patent discloses a method for fabricating a high-density self-aligned silicon carbide MOS device (publication number CN115188674A). This existing patent suffers from dynamic characteristic degradation due to uneven electric field distribution. Specifically, this includes reliability degradation caused by concentrated electric field at the gate edge during high-voltage switching, discrepancies between on-resistance and breakdown voltage due to insufficient electric field modulation in the drift region, and high-frequency switching losses and current collapse caused by interface state effects and poor capacitance characteristics. Summary of the Invention

[0004] This invention provides a SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates and its fabrication process to solve existing technical problems, thereby addressing the issues of limited electric field modulation effect and insignificant improvement in dynamic characteristics.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a SiC VDMOSFET dynamic characteristic enhancement structure with a self-aligned multi-level field plate, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide field plate, and a source, wherein the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P+ layer, and a P well layer, the gate oxide field plate being located between the gate and the semiconductor epitaxial layer, wherein a field plate junction is deposited between the gate oxide field plate and the gate, the field plate junction being composed of a plurality of non-contact silicon dioxide deposited blocks; The area covered by the silica deposit in the middle of the gate oxide field plate is large, while the area covered by the silica deposit on both sides of the gate oxide field plate is small.

[0006] Furthermore, the interior of the N-substrate layer is formed with several non-contacting P-type junction regions through ion implantation, and these P-type junction regions are in ohmic contact with the drain electrode.

[0007] Furthermore, the cross-sectional width of the P-type junction region in the middle of a single MOS cell is larger, while the cross-sectional width of the P-type junction region on both sides is smaller.

[0008] Furthermore, a contact capping layer is formed inside the N substrate layer and above the contact P-type junction region by ion implantation. This contact capping layer is made of N-type material with a higher doping concentration than the N substrate layer, and this contact capping layer is in ohmic contact with the drain electrode.

[0009] Furthermore, within the N-drift layer and below the gate oxide field plate, several non-contacting P-type field junctions are formed by ion implantation. Furthermore, the P-type field plate section in the middle has a greater depth, while the P-type field plate section on both sides has a smaller depth.

[0010] Furthermore, the contact P-type junction region also includes a gradient junction region, with the cross-sectional height of the gradient junction region in the middle of a single MOS cell being lower, and the cross-sectional height of the gradient junction region on both sides being higher.

[0011] Furthermore, the interior of the N drift layer is formed with several non-contact intermediate P-type junction regions through ion implantation. The cross-sectional width of the intermediate P-type junction region in the middle is large, while the cross-sectional width of the intermediate P-type junction regions on both sides is small. The bottom end of the intermediate P-type junction region is in direct contact with the N substrate layer.

[0012] Furthermore, an intermediate capping layer is formed inside the N-drift layer and in the intermediate P-type junction region through ion implantation. This intermediate capping layer is in direct contact with the N substrate layer, and the intermediate capping layer is an N-type material with a doping concentration greater than that of the N-drift layer.

[0013] Furthermore, an intermediate N-layer is formed inside the N-drift layer and above the intermediate capping layer by ion implantation. The doping concentration of the intermediate N-layer is lower than that of the N-drift layer.

[0014] The fabrication process for a SiC VDMOSFET dynamic characteristic enhancement structure with a self-aligned multi-level field plate specifically includes: S1. An N-drift layer is formed on an N-substrate layer by epitaxial growth; S2. A P-well layer, an N-well layer and a P+ layer are sequentially formed in the N-drift layer by ion implantation, and the implanted ions are activated by high-temperature annealing. S3. A gate oxide layer is grown on a semiconductor epitaxial layer, and a gate oxide field plate is formed by photolithography and etching processes. S4. A silicon dioxide layer is deposited on the gate oxide field plate, and a field plate junction is formed by self-aligned photolithography and etching processes. The field plate junction is composed of several non-contact silicon dioxide deposited blocks, and the silicon dioxide deposited blocks in the middle cover a large area on the gate oxide field plate, while the silicon dioxide deposited blocks on both sides cover a small area on the gate oxide field plate. S5. Deposit a polysilicon or metal layer on the field junction and form the gate through photolithography and etching. S6. The contact region of the source electrode is formed in the N-well layer and P+ layer by ion implantation and annealing process, and the contact region of the drain electrode is formed on the back side of the N-substrate layer. S7. Deposit a metal layer and form ohmic contacts between the source and drain electrodes through photolithography and etching to complete device fabrication.

[0015] The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates and its fabrication process provided by this invention have the following advantages compared with the prior art: 1. This invention achieves optimized modulation of the electric field distribution on the gate oxide field plate by adopting a self-aligned multi-stage field plate structure, effectively suppressing the electric field concentration phenomenon at the gate edge, thereby significantly improving the breakdown voltage and dynamic stability of the device, and making it exhibit higher reliability in high-voltage switching applications.

[0016] 2. This invention introduces a P-type junction region with a gradually varying depth below the field plate and combines it with a contact P-type junction region with a gradually varying width in the substrate to form a multi-dimensional electric field modulation mechanism. This not only optimizes the electric field distribution in the drift region but also effectively reduces the on-resistance and improves the dynamic response characteristics of the device under high-speed switching conditions.

[0017] 3. This invention improves current spreading performance and contact characteristics by introducing a highly doped N-type capping layer above the contact junction region and forming an ohmic contact with the drain, thereby reducing the conduction loss and thermal resistance of the device and improving overall energy efficiency and high-temperature operating stability.

[0018] 4. This invention achieves effective charge compensation by constructing a composite terminal structure in the drift region that combines a P-type junction region with a wide center and narrow sides with a highly doped N-type capping layer. This further enhances the device's withstand voltage capability and reduces the output capacitance, which is beneficial for improving switching speed and reducing switching losses.

[0019] 5. By introducing a low-doped intermediate N-type layer in the upper part of the drift region, the present invention forms a vertical doping gradient structure, which effectively optimizes the capacitance characteristics and electric field distribution of the device, significantly reduces energy loss during switching, and improves the overall performance of the device in high-frequency applications. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of Embodiment 4 of the present invention; Figure 5 This is a schematic diagram of Embodiment 5 of the present invention; Figure 6 This is a schematic diagram of Embodiment Six of the present invention.

[0021] In the diagram: 1. Drain; 2. Gate; 3. Gate oxide field plate; 4. Source; 5. N-substrate layer; 6. N-drift layer; 7. N-well layer; 8. P+ layer; 9. P-well layer; 10. Field plate junction; 11. Contact P-type junction region; 12. Contact capping layer; 13. P-type field plate junction; 14. Intermediate P-type junction region; 15. Intermediate capping layer; 16. Intermediate N-layer; 1101. Gradient junction region. Detailed Implementation

[0022] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 1 As shown, the fabrication process of the SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates specifically includes: Step 1: An N-drift layer 6 is formed on the N-substrate layer 5 by epitaxial growth. By epitaxially growing an N-drift layer with precise doping concentration and thickness on the N-type SiC substrate, a high-quality high-voltage bearing region is constructed for the device. The drift layer formed in this step has a uniform doping distribution and excellent crystal quality, which provides an ideal foundation for subsequent ion implantation and terminal structure fabrication, thereby ensuring that the device has the potential for low on-resistance and high breakdown voltage.

[0024] Step 2: P-well layer 9, N-well layer 7, and P+ layer 8 are sequentially formed in N-drift layer 6 by ion implantation, and the implanted ions are activated by high-temperature annealing. Through multi-step ion implantation, P-well, N-well, and P+ contact regions are precisely formed, defining the cell structure and conductive channels of the device. Combined with the high-temperature annealing process, the implanted ions are effectively activated and lattice damage is repaired. This step achieves precise control of the conductive channel and bulk region, providing the device with good threshold voltage stability and reliable conduction characteristics.

[0025] Step 3: A gate oxide layer is grown on the semiconductor epitaxial layer, and a gate oxide field plate 3 is formed by photolithography and etching processes. A high-quality gate oxide layer is grown by thermal oxidation and a gate oxide field plate is formed by photolithography. The gate oxide dielectric prepared in this step has low interface state density and high breakdown field strength characteristics. The formation of the gate oxide field plate not only provides insulation for the gate, but also lays the foundation for the subsequent fabrication of multi-level field plate structures, effectively improving the reliability and stability of the gate.

[0026] Step 4: Deposit a silicon dioxide layer on the gate oxide field plate 3, and form a field junction 10 through self-aligned photolithography and etching processes. The field junction 10 is composed of several non-contact silicon dioxide deposited blocks, with the silicon dioxide deposited block in the middle covering a larger area on the gate oxide field plate 3, and the silicon dioxide deposited blocks on both sides covering a smaller area on the gate oxide field plate 3. The silicon dioxide field junction with gradient coverage characteristics is prepared on the gate oxide field plate using self-aligned photolithography technology. This step achieves precise control of the field plate size. The design of large coverage area in the middle and small coverage area on both sides optimizes the electric field distribution, effectively alleviates the electric field concentration at the gate edge, and significantly improves the device's withstand voltage and dynamic stability.

[0027] Step 5: Deposit a polysilicon or metal layer on the field junction 10, and form the gate 2 by photolithography and etching; form the gate electrode by depositing a conductive layer and photolithography. This step achieves good contact and precise alignment with the field junction structure. The formed gate has good conductivity and interface characteristics, which not only ensures gate control capability but also avoids the introduction of additional parasitic parameters, thus ensuring the high-frequency switching performance of the device.

[0028] Step 6: Form the contact region of source 4 in N-well layer 7 and P+ layer 8 through ion implantation and annealing, and form the contact region of drain 1 on the back side of N-substrate layer 5; form source ohmic contacts in N-well and P+ regions through selective ion implantation, and simultaneously prepare drain contacts on the back side of the substrate. This step achieves the formation of low-resistance ohmic contacts, optimizes the current transport path of the device, reduces contact resistance and series resistance, and improves the conduction efficiency and current handling capability of the device.

[0029] Step 7: Deposit a metal layer and form ohmic contacts between source 4 and drain 1 through photolithography and etching to complete device fabrication. The source and drain electrodes are fabricated through metal deposition and photolithography. This step creates low-resistance, reliable metal-semiconductor ohmic contacts, optimizing the current distribution characteristics in both the lateral and longitudinal directions. This not only reduces the device's conduction losses but also improves its thermal stability and long-term operational reliability.

[0030] Example 1 like Figure 1As shown, the SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates includes several parallel MOS cells. Each MOS cell includes a drain 1, a semiconductor epitaxial layer, a gate 2, a gate oxide field plate 3, and a source 4. The semiconductor epitaxial layer includes an N substrate layer 5, an N drift layer 6, an N well layer 7, a P+ layer 8, and a P well layer 9. The gate oxide field plate 3 is located between the gate 2 and the semiconductor epitaxial layer. A field plate junction 10 is deposited between the gate oxide field plate 3 and the gate 2. The field plate junction 10 is composed of several non-contact silicon dioxide deposits. The silicon dioxide deposits in the middle cover a large area on the gate oxide field plate 3, while the silicon dioxide deposits on both sides cover a small area on the gate oxide field plate 3.

[0031] By employing a silicon dioxide deposition block structure with a large central coverage area and small side coverage areas in the field junction 10, the electric field gradient on the gate oxide field plate 3 was optimized using a self-aligned process. The principle is that by adjusting the coverage area of ​​the field junction 10 at different positions, the electric field distribution at the edge of the gate 2 is effectively modulated, thereby suppressing electric field concentration and improving the breakdown voltage and dynamic stability of the device. The advantage is a significant enhancement of the reliability of the VDMOSFET during high-voltage switching.

[0032] Example 2 like Figure 2 As shown, several non-contacting P-type junction regions 11 are formed inside the N-substrate layer 5 through ion implantation. These P-type junction regions 11 are in 1-ohm contact with the drain. The cross-sectional width of the P-type junction region 11 at the center of a single MOS cell is larger, while the cross-sectional width of the P-type junction region 11 at both sides is smaller.

[0033] A contact P-type junction region 11 with a gradually varying cross-sectional width is formed in the N-substrate layer 5. The structure design, which is wider in the middle and narrower on both sides, makes the depletion region expand more uniformly in both the longitudinal and lateral directions. The principle is to optimize the charge balance by varying the width of the contact P-type junction region 11, thereby reducing the peak electric field on the drain side. The advantage is that it effectively reduces the on-resistance, while improving the device's breakdown voltage and dynamic response speed.

[0034] Example 3 like Figure 3 As shown, a contact capping layer 12 is formed inside the N substrate layer 5 and above the contact P-type junction region 11 by ion implantation. The contact capping layer 12 is an N-type material with a doping concentration greater than that of the N substrate layer 5 (the contact capping layer 12 is in a state of semi-enclosing the contact P-type junction region 11), and the contact capping layer 12 is in 1-ohm contact with the drain electrode.

[0035] A highly doped N-type contact capping layer 12 is introduced above the P-type junction region 11 to form an ohmic contact with the drain 1. Its semi-enclosed structure enhances the contact performance between the junction region and the electrode. The principle is to reduce the contact resistance and improve current spread through high-concentration doping. The advantage is that it improves the conduction efficiency and thermal stability of the device, making it suitable for high-frequency, high-current applications.

[0036] Example 4 like Figure 4 As shown, several non-contact P-type field junctions 13 are formed inside the N-drift layer 6 and below the gate oxide field plate 3 through ion implantation; the P-type field junction 13 in the middle has a larger cross-sectional depth, while the P-type field junction 13 on both sides has a smaller cross-sectional depth. The contact P-type junction region 11 also includes a gradient junction region 1101, with the gradient junction region 1101 in the middle of a single MOS cell having a lower cross-sectional height and the gradient junction region 1101 on both sides having a higher cross-sectional height.

[0037] A depth-gradient P-type field junction 13 is disposed below the gate oxide field plate 3, and in conjunction with a height-gradient junction region 1101 in the contact P-type junction region 11, a multi-dimensional electric field modulation structure is formed. The principle is to achieve the uniform distribution of the electric field in the longitudinal and lateral directions through the synergistic gradient design of junction depth and junction height. The advantage is that it further suppresses the current collapse phenomenon during dynamic switching and improves the high-frequency dynamic characteristics of the device.

[0038] Example 5 like Figure 5 As shown, the interior of the N-drift layer 7 is formed with several non-contact intermediate P-type junction regions 14 through ion implantation. The cross-sectional width of the intermediate P-type junction region 14 in the middle is large, while the cross-sectional width of the intermediate P-type junction regions 14 on both sides is small. The bottom end of the intermediate P-type junction region 14 is in direct contact with the N substrate layer 5. The interior of the N-drift layer 6, located in the intermediate P-type junction region 14, is formed with ion implantation to form an intermediate capping layer 15. This intermediate capping layer 15 is in direct contact with the N substrate layer 5, and the intermediate capping layer 15 is an N-type material with a doping concentration greater than that of the N-drift layer 6.

[0039] A central P-type junction region 14, which is wide in the middle and narrow on both sides, is introduced into the N-type drift layer 6 and combined with a highly doped N-type intermediate capping layer 15 to form a composite termination structure. The principle is to construct a charge compensation effect through the alternating arrangement of the P-type junction region (central P-type junction region 14) and the N-type capping layer (intermediate capping layer 15). The advantage is that it effectively reduces the drift region resistance and improves the overall breakdown voltage and dynamic stability of the device.

[0040] Example 6 like Figure 6As shown, several non-contact intermediate P-type junction regions 14 are formed inside the N-drift layer 7 through ion implantation. The cross-sectional width of the intermediate P-type junction region 14 in the middle is large, while the cross-sectional width of the intermediate P-type junction regions 14 on both sides is small. The bottom end of the intermediate P-type junction region 14 is in direct contact with the N substrate layer 5. Inside the N-drift layer 6, located within the intermediate P-type junction region 14, an intermediate capping layer 15 is formed through ion implantation. This intermediate capping layer 15 is in direct contact with the N substrate layer 5, and the intermediate capping layer 15 is an N-type material with a higher doping concentration than the N-drift layer 6. Inside the N-drift layer 6, above the intermediate capping layer 15, an intermediate N-layer 16 is formed through ion implantation. The doping concentration of the intermediate N-layer 16 is lower than that of the N-drift layer 6.

[0041] A lightly doped intermediate N-layer 16 is added above the intermediate capping layer 15 to form a three-layer vertical doping gradient structure. The principle is to introduce a lightly doped layer on the upper part of the drift region 6 to slow down the rate of change of the electric field and optimize the output capacitance characteristics. The advantage is that it significantly reduces switching losses and improves the energy efficiency and reliability of the device in high-speed switching applications.

[0042] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates, comprising a plurality of parallel MOS cells, each MOS cell comprising a drain (1), a semiconductor epitaxial layer, a gate (2), a gate oxide field plate (3), and a source (4), wherein the semiconductor epitaxial layer comprises an N substrate layer (5), an N drift layer (6), an N well layer (7), a P+ layer (8), and a P well layer (9), characterized in that: The gate oxide field plate (3) is located between the gate (2) and the semiconductor epitaxial layer, wherein a field plate junction (10) is deposited between the gate oxide field plate (3) and the gate (2), and the field plate junction (10) is composed of several non-contact silicon dioxide deposited blocks; Among them, the area of ​​the silica deposit in the middle covering the gate oxide field plate (3) is large, while the area of ​​the silica deposit on both sides covering the gate oxide field plate (3) is small.

2. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-stage field plates according to claim 1, characterized in that: The interior of the N substrate layer (5) is formed by ion implantation with several non-contacting contact P-type junction regions (11), which are in ohmic contact with the drain electrode (1).

3. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-stage field plates according to claim 2, characterized in that: The cross-sectional width of the P-type junction region (11) in the middle of a single MOS cell is larger, while the cross-sectional width of the P-type junction region (11) on both sides is smaller.

4. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates according to claim 2, characterized in that: A contact capping layer (12) is formed inside the N substrate layer (5) and above the contact P-type junction region (11) by ion implantation. The contact capping layer (12) is an N-type material with a doping concentration greater than that of the N substrate layer (5), and the contact capping layer (12) is in ohmic contact with the drain electrode (1).

5. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-stage field plates according to claim 3, characterized in that: The N drift layer (6) is located inside and below the gate oxide field plate (3) and has several non-contacting P-type field junctions (13) formed by ion implantation. Furthermore, the P-type field plate (13) in the middle has a larger cross-sectional depth, while the P-type field plate (13) on both sides has a smaller cross-sectional depth.

6. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-stage field plates according to claim 5, characterized in that: The contact P-type junction region (11) also includes a gradient junction region (1101), with the gradient junction region (1101) in the middle of a single MOS cell having a lower cross-sectional height and the gradient junction regions (1101) on both sides having a higher cross-sectional height.

7. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates according to claim 1, characterized in that: The interior of the N drift layer (7) is formed by ion implantation with several non-contact intermediate P-type junction regions (14), and the cross-sectional width of the intermediate P-type junction region (14) in the middle is large, while the cross-sectional width of the intermediate P-type junction regions (14) on both sides is small. The bottom end of the intermediate P-type junction region (14) is in direct contact with the N substrate layer (5).

8. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates according to claim 7, characterized in that: The intermediate capping layer (15) is formed inside the N drift layer (6) and located in the intermediate P-type junction region (14) by ion implantation. The intermediate capping layer (15) is in direct contact with the N substrate layer (5). The intermediate capping layer (15) is an N-type material with a doping concentration greater than that of the N drift layer (6).

9. The SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates according to claim 8, characterized in that: An intermediate N-layer (16) is formed inside the N-drift layer (6) and above the intermediate capping layer (15) by ion implantation. The doping concentration of the intermediate N-layer (16) is lower than that of the N-drift layer (6).

10. A fabrication process for a SiC VDMOSFET dynamic characteristic enhancement structure with a self-aligned multi-level field plate, characterized in that, The fabrication process of the SiC VDMOSFET dynamic characteristic enhancement structure with self-aligned multi-level field plates, applied to claim 1, specifically includes: S1. An N-drift layer (6) is formed on the N substrate layer (5) by epitaxial growth. S2. P-well layer (9), N-well layer (7) and P+ layer (8) are sequentially formed in N-drift layer (6) by ion implantation, and the implanted ions are activated by high-temperature annealing. S3. A gate oxide layer is grown on the semiconductor epitaxial layer, and a gate oxide field plate is formed by photolithography and etching processes (3). S4. A silicon dioxide layer is deposited on the gate oxide field plate (3), and a field plate junction (10) is formed by self-aligned photolithography and etching process. The field plate junction (10) is composed of several non-contact silicon dioxide deposited blocks, and the silicon dioxide deposited blocks in the middle cover a large area on the gate oxide field plate (3), while the silicon dioxide deposited blocks on both sides cover a small area on the gate oxide field plate (3). S5. Deposit a polysilicon or metal layer on the field junction (10) and form a gate (2) by photolithography and etching. S6. The contact region of the source (4) is formed in the N-well layer (7) and the P+ layer (8) by ion implantation and annealing, and the contact region of the drain (1) is formed on the back side of the N-substrate layer (5). S7. Deposit a metal layer and form ohmic contacts between the source (4) and drain (1) through photolithography and etching to complete the device fabrication.

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