Method of forming electronic component having strained transistor channel

Abstract

The embodiment of the invention provides a method for manufacturing an electronic component meeting the pressure stress requirement of a PMOS (P-channel Metal Oxide Semiconductor) transistor and the tensile stress requirement of an NMOS (N-channel Metal Oxide Semiconductor) transistor. Each P-metal stack and P-metal stack is formed on a top surface of a channel between the source and drain on the semiconductor substrate, includes nanosheet channel layers and trenches between each nanosheet channel layer, and has at least one side defining a gate trench. Some embodiments include forming a work function layer in a channel and inducing a strain of the work function layer in the channel. Some embodiments include forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing gate metal fill layer strain in the channel. The gate metal filling layer covers at least one side surface of each of the P metal stack and the N metal stack and fills the gate trench.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of electronic component manufacturing, and more specifically, to transistors. More specifically, the embodiments of this disclosure relate to methods for manufacturing FinFET and GAA devices having strained transistor channels. Background Technology

[0002] Integrated circuits have evolved into complex components that can include millions of transistors, capacitors, and resistors on a single wafer. In the development of integrated circuits, functional density (i.e., the number of interconnecting elements per wafer area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased.

[0003] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, many transistors can be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Integrated circuits incorporate planar field-effect transistors (FETs), in which current flows through a semiconductor channel between the source and drain in response to a voltage applied to the control gate.

[0004] As device dimensions shrink, it becomes increasingly difficult to maintain switching speeds without failure due to variations in device geometry and materials. Emerging technologies enable chip designers to continue shortening gate lengths. Controlling the size of device structures remains a key challenge for current and future generations of technology.

[0005] For example, microelectronic field-effect transistors (such as complementary metal-oxide-semiconductor (CMOS) field-effect transistors) can be formed on a substrate and cooperate to perform various functions within a circuit. A CMOS transistor includes a gate structure disposed over a channel region formed between the source and drain of the transistor. The gate structure typically includes a gate and a gate dielectric layer. The gate, disposed above the gate dielectric layer, controls the flow of charge carriers (i.e., current) in the channel region below the gate dielectric layer during operation.

[0006] Inducing stress / strain in the transistor channel has remained a challenge throughout the transition of transistor technology from planar FETs to FinFETs and then to GAA devices such as negative metal-oxide-semiconductor (NMOS) transistors and positive metal-oxide-semiconductor (PMOS) transistors. We believe that inducing stress (or strain) can alter the arrangement of silicon atoms in the lattice of the transistor channel, thereby improving electron mobility (in NMOS transistors) and hole mobility (in PMOS transistors). For example, in PMOS transistors, holes move through bonded coupling. We believe that hole mobility can be improved and compressive stress induced in the transistor channel by reducing the longitudinal atomic spacing. For example, in NMOS transistors, electrons move through drift and diffusion. We believe that electron mobility can be improved and tensile stress induced in the transistor channel by increasing the longitudinal atomic spacing.

[0007] There are two common methods for inducing stress in transistor channels: biaxial global straining and uniaxial local straining. In a typical biaxial global straining process, the silicon lattice can be mechanically compressed and / or stretched to induce strain through various processes. For example, biaxial global strain can be achieved by epitaxially growing a thin silicon (Si) layer on a relaxor silicon germanium (SiGe) substrate. Due to the lattice mismatch between Si and SiGe, the Si lattice is subjected to biaxial tensile strain along the interface plane. Alternatively, biaxial global strain can be introduced after the wafer has been fully processed. This can be achieved, for example, by thinning the wafer to below 10 μm and then transferring it onto a polymer film. After wafer transfer, mechanical strain is applied to the Si film, allowing uniaxial and biaxial strains to be parallel to the substrate surface without inducing defects, such as vacancies, in the Si layer. As long as the strain level remains within the elastic limits, the mechanically strained wafer can be safely bonded to the final substrate.

[0008] One drawback of conventional global strain techniques is that they can only induce one type of strain: compressive stress / strain or tensile stress / strain, and cannot induce both strains simultaneously. To address this shortcoming, uniaxial local strain techniques have been developed.

[0009] In a typical uniaxial local strain process, silicon germanium (SiGe) is integrated into the source and drain regions of a PMOS transistor, and silicon carbide (SiC) is integrated into the source and drain regions of an NMOS transistor.

[0010] However, in the transistor channels of GAA devices, especially in the trenches between nanosheets, inducing and / or maintaining strain remains a challenge due to spacing constraints. Specifically, for PMOS transistors, due to the higher electron mobility and lower hole mobility, the compressive stress induced in the transistor channel by these two conventional methods is much higher than the required compressive stress (measured in GPa). For NMOS transistors, due to the lower electron mobility measured by Ron DIBL, the tensile stress induced in the transistor channel by these two conventional processes is not ideal. Ron DIBL is a graph of on-resistance versus drain-induced barrier reduction, an indicator of transistor performance. At a constant DIBL, a lower Ron indicates better performance.

[0011] Therefore, it is necessary to improve the methods of manufacturing electronic components to meet the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors. Summary of the Invention

[0012] One or more embodiments of this disclosure relate to a method of manufacturing an electronic component. The method includes forming a P-metal stack and an N-metal stack on a semiconductor substrate. Each of the P-metal stack and the N-metal stack is formed on the top surface of a channel located between a source and a drain on the semiconductor substrate. Each P-metal stack and N-metal stack includes a nanosheet channel layer and a trench between each nanosheet channel layer. The method also includes forming a work function layer in the channel between the nanosheet channel layers of each trench and inducing work function layer strain in the channel. Each of the P-metal stack and the N-metal stack independently has compressive and tensile stresses, ranging from 1 GPa to 2 GPa.

[0013] Other embodiments of this disclosure relate to a method of manufacturing an electronic component. The method includes forming a P-metal stack and an N-metal stack on a semiconductor substrate. Each of the P-metal stack and the N-metal stack is formed on the top surface of a channel located between a source and a drain on the semiconductor substrate. Each of the P-metal stack and the N-metal stack includes a nanosheet channel layer and a trench between each nanosheet channel layer. Each of the P-metal stack and the N-metal stack has at least one side surface defining a gate trench. The method also includes forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing strain in the gate metal fill layer within the channel. The gate metal fill layer covers at least one side surface of each of the P-metal stack and the N-metal stack and fills the gate trench. The compressive stress of the P-metal stack ranges from -0.1 GPa to -3.1 GPa, while the tensile stress of the N-metal stack is greater than or equal to 2 GPa.

[0014] Further embodiments of this disclosure relate to a method of manufacturing an electronic component. The method includes forming a P-metal stack and an N-metal stack on a semiconductor substrate. Each of the P-metal stack and the N-metal stack is formed on the top surface of a channel located between a source and a drain on the semiconductor substrate. Each of the P-metal stack and the N-metal stack includes a nanosheet channel layer and a trench between each nanosheet channel layer, and each of the P-metal stack and the N-metal stack has at least one side surface defining a gate trench. The method further includes forming a work function layer in the channel between the nanosheet channel layers of each trench and inducing work function layer strain in the channel, the work function layer formation including a thermal process. The method further includes forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing gate metal fill layer strain in the channel. The gate metal fill layer covers at least one side surface of each of the P-metal stack and the N-metal stack and fills the gate trench. Attached Figure Description

[0015] To gain a more detailed understanding of the features described above, reference can be made to the embodiments for a more detailed description of the present disclosure, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the present disclosure and should not be considered as limiting its scope, as other equivalent embodiments are permissible.

[0016] The embodiments described herein are illustrated in the accompanying drawings by way of example rather than limitation, in which the same element symbols denote similar elements.

[0017] Figure 1A A process flow diagram of a method for manufacturing an electronic component according to one or more embodiments of this disclosure is shown;

[0018] Figure 1B A process flow diagram of a method for manufacturing an electronic component according to one or more embodiments of this disclosure is shown;

[0019] Figure 1C A process flow diagram of a method for manufacturing an electronic component according to one or more embodiments of this disclosure is shown;

[0020] Figure 2A A cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure is shown;

[0021] Figure 2B A cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure is shown;

[0022] Figure 2C A cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure is shown;

[0023] Figure 2D A cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure is shown;

[0024] Figure 2E A cross-sectional view of a semiconductor substrate after forming a work function layer in the channel and inducing strain in the work function layer is shown.

[0025] Figure 2F Another cross-sectional view of a semiconductor substrate after forming a work function layer in the channel and inducing strain in the work function layer is shown.

[0026] Figure 2G A cross-sectional view of a semiconductor substrate is shown after forming a work function layer and a gate metal fill layer on the work function layer, inducing strain in the work function layer and the gate metal fill layer in the channel; and

[0027] Figure 3 Clustering tools according to one or more embodiments of this disclosure are shown. Detailed Implementation

[0028] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the structures or process steps set forth in the following description. There are other embodiments of this disclosure, and it can be practiced or performed in various ways.

[0029] As used herein, the term “about” means approximately or close to, and in the context of the numerical value or range, means a variation of ±15% or less in the value. For example, values ​​differing by ±14%, ±10%, ±5%, ±2%, or ±1% would meet the definition of about.

[0030] As used in this specification and the appended claims, the terms "substrate" or "wafer" refer to a surface or part thereof on which a process is performed. Those skilled in the art will understand that, unless the context clearly indicates otherwise, "substrate" may refer only to a portion of a substrate. Furthermore, "deposition on a substrate" may refer to a bare substrate or a substrate on which one or more thin films or features are deposited or formed.

[0031] As used herein, “substrate” means any substrate or any material surface formed on a substrate, on which a film treatment is performed during the manufacturing process. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate may include, but is not limited to, semiconductor wafers. The substrate may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any film treatment steps disclosed in this disclosure may also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such an underlying layer as referred to in the context. Thus, for example, where a film / layer or a portion of a film / layer has already been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0032] The term "on" indicates that there is direct contact between components. The term "directly on" indicates that there is direct contact between components without any intermediary components.

[0033] In this specification and the appended claims, the terms “precursor,” “reactant,” “reactive gas,” and similar terms are used interchangeably to refer to any type of gas that can react with the substrate surface.

[0034] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a material layer on a substrate surface. The substrate, or a portion thereof, is exposed to two or more reactive compounds in a reaction zone introduced into a processing chamber. In time-domain ALD processes, exposure to each reactive compound is time-delayed to allow each compound to adhere to and / or react on the substrate surface, subsequently being desorbed from the processing chamber. These reactive compounds are referred to as being sequentially exposed to the substrate. In spatial ALD processes, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds, such that no given point on the substrate is substantially exposed to more than one reactive compound simultaneously. As used in this specification and the appended claims, those skilled in the art will understand that the term "substantially" in this sense means that a small portion of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and that such simultaneous exposure is not intentional.

[0035] In one aspect of the time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second time delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or remove any residual reactive compounds or reaction byproducts. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are alternately pulsed until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsed compound A, purge gas, compound B, and purge gas is a cycle. The cycle may begin with compound A or compound B and continue in their respective cycle sequences until a film with a predetermined thickness is obtained.

[0036] One or more layers deposited on or on a substrate are continuous. As used herein, the term "continuous" means a layer that covers the entire exposed surface without gaps or bare spots exposing the material beneath the deposited layer. Continuous layers may have gaps or bare spots with a surface area of ​​less than about 15% or less than about 10% of the total surface area of ​​the layer.

[0037] In one embodiment of the space ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are simultaneously delivered to the reaction zone, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery equipment such that any given point on the substrate is exposed to both the first and second reactive gases.

[0038] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between source and drain regions. In one or more embodiments, the source and drain regions include doped regions of a substrate (e.g., a semiconductor substrate) and show a doping profile suitable for a particular application. The gate is disposed over the channel region and includes a gate dielectric layer disposed between the gate and the channel region of the semiconductor substrate.

[0039] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the element. A field-effect transistor is a voltage-controlled element in which its current-carrying capacity can be altered by applying an electric field. At low temperatures, field-effect transistors typically have high input impedance. The conductivity between the drain and source terminals is controlled by an electric field within the element, generated by the voltage difference between the element body and the gate. The three terminals of a field-effect transistor are the source (S), through which charge carriers enter the channel; the drain (D), through which charge carriers leave the channel; and the gate (G), the terminal that modulates the channel conductivity. The current entering the channel at the source (S) is defined as IS, and the current entering the channel at the drain (D) is defined as ID. The voltage from the drain to the source is defined as VDS. By applying a voltage to the gate (G), the current entering the drain channel (i.e., ID) can be controlled.

[0040] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate whose voltage determines the device's conductivity. This ability to change conductivity with applied voltage can be used to amplify or switch electronic signals. A MOSFET is based on modulating the charge concentration between the host electrode and the gate through a metal-oxide-semiconductor (MOS) capacitor, with the gate located above the host and insulated from all other device regions through a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated from the host region. These regions can be p-type or n-type, but they belong to the same type and are the opposite of the host region. The source and drain (different from the host) are highly doped, as indicated by a "+" symbol after the doping type.

[0041] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, while the main body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, while the main body is an n-type substrate region. The source is so named because it is the origin of charge carriers flowing through the channel (electrons for n-channels and holes for p-channels); similarly, the drain is where charge carriers leave the channel.

[0042] An nMOS FET is made of an n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to be formed between the source and drain, and electrons carry current from the source to the drain through the induced n-type channel. We consider logic gates and other digital devices implemented using NMOS to have NMOS logic. NMOS has three operating modes, called cutoff, bipolar, and saturation. Circuits using NMOS logic gates dissipate quiescent power when the circuit is idle because DC current flows through the logic gate when the output is low-order.

[0043] A pMOS FET consists of a p-type source and drain, and an n-type substrate. When a positive voltage is applied between the source and gate (or a negative voltage between the gate and source), a p-type channel of opposite polarity is formed between the source and drain. Holes carry current from the source to the drain through the induced p-type channel. A high voltage on the gate will cause the PMOS to turn off, while a low voltage on the gate will cause it to turn on. We consider logic gates and other digital devices implemented using PMOS as having PMOS logic. PMOS technology is inexpensive and offers good noise immunity.

[0044] In NMOS, the charge carriers are electrons, while in PMOS, the charge carriers are holes. When a high voltage is applied to the gate, an NMOS will conduct, while a PMOS will not. Furthermore, when a low voltage is applied to the gate, an NMOS will not conduct, and a PMOS will conduct. Because electrons move twice as fast in NMOS as holes in PMOS, NMOS is considered faster than PMOS. However, PMOS devices are more resistant to interference than NMOS devices. Additionally, NMOS integrated circuits are smaller than PMOS integrated circuits (with the same function) because the impedance provided by an NMOS is half that of a PMOS (with the same geometry and operating conditions).

[0045] As used herein, the term "FinFET" refers to a MOSFET transistor built on a substrate, wherein the gate is positioned on two, three, or four sides of the channel, or wound around the channel to form a dual-gate structure. Because the source / drain regions form "fins" on the substrate, FinFET devices are collectively referred to as FinFETs. FinFET devices have fast switching times and high current densities.

[0046] As used herein, the term "gate all-around (GAA)" refers to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires or nanoplates or nanosheets, strip channels, or other suitable channel configurations known to those skilled in the art.

[0047] In one or more embodiments, after implementing the method described herein, the channel region of the GAA transistor has stresses ranging from high tensile stress (e.g., greater than or equal to 1 gigapascal (GPa)) to compressive stress (e.g., negative GPa). In one or more specific embodiments, after implementing the method described herein, it is advantageous that the channel region of the N-metal stack has high tensile stress (e.g., greater than or equal to 1 gigapascal (GPa)) and the channel region of the P-metal stack has compressive stress (e.g., negative GPa).

[0048] In one or more embodiments, the channel region of the GAA element has a plurality of vertically spaced horizontal nanowires or horizontal strips, thereby making the GAA transistor a stacked horizontal all-around gate (hGAA) transistor.

[0049] As used herein, the term "nanowire" refers to a nanostructure with a diameter of approximately nanometers (10⁻⁹ meters). A nanowire may also be defined as having an aspect ratio greater than 1000. Alternatively, a nanowire may be defined as a structure with a thickness or diameter limited to tens of nanometers or less, but with no length limitation. Nanowires can be used in transistors and certain laser applications, and in one or more embodiments, nanowires are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) components. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness scale ranging from approximately 0.1 nanometers to 1000 nanometers, or 0.5 nanometers to 500 nanometers, or 0.5 nanometers to 100 nanometers, or 1 nanometer to 50 nanometers, or 1 nanometer to 100 nanometers, or 1 nanometer to 50 nanometers.

[0050] Embodiments of this disclosure advantageously provide methods for manufacturing electronic components that improve electron mobility (in NMOS transistors) and hole mobility (in PMOS transistors) by applying strain to the transistor channel. Some embodiments advantageously provide methods for manufacturing electronic components that meet the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors. Embodiments of this disclosure address the challenges faced by conventional biaxial global strain processes and uniaxial local strain processes due to the adoption of new integration schemes.

[0051] The inventors have advantageously developed two separate processes that can induce stress / strain in the transistor channel to meet the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors.

[0052] As described herein, the formation of the work function layer and the induction of work function layer strain can be referred to as the "first strain-induced process". As described herein, the formation of the gate metal fill layer and the induction of gate metal fill layer strain can be referred to as the "second strain-induced process". The names "first strain-induced process" and "second strain-induced process" are for illustrative purposes and are intended to describe the respective processes in the order they appear in the figures. It should be understood that the processes developed by the inventors ("first strain-induced process" and "second strain-induced process") can be implemented individually or together.

[0053] Embodiments of this disclosure are described with reference to illustrations, which depict elements (e.g., transistors) and processes for forming transistors according to one or more embodiments of this disclosure. The illustrated processes are merely illustrative potential uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications. In the one or more illustrated embodiments, unless otherwise stated, the same element symbols denote similar elements.

[0054] Figures 1A, 1B, and 1C independently illustrate process flow diagrams of methods for manufacturing electronic components according to one or more embodiments of this disclosure. Figure 1A Method 10 is shown. Figure 1B Method 50 is shown. Figure 1C Method 100 is shown.

[0055] Figures 2A-2B are cross-sectional views of an electronic component (e.g., a transistor, such as a FinFET or GAA) 200 according to one or more embodiments. Figures 2A-2C illustrate the process flow for forming P-metal stacks and N-metal stacks on a semiconductor substrate.

[0056] The electronic component 200 shown in Figure 2E-2G can be manufactured using the methods 10, 50 and 100 described herein.

[0057] Referring to Figures 2A-2G, in one or more embodiments, electronic component 200 includes a semiconductor substrate 202 having a top surface 203. Semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, semiconductor substrate 202 includes semiconductor materials such as silicon (Si), carbon (C), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon-germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Although several examples of materials that can form semiconductor substrate 202 have been described herein, any material that can serve as the basis for constructing passive and active electronic components (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic components, or any other electronic components) is within the spirit and scope of this disclosure.

[0058] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor formed during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type originates from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of wells (or holes). In contrast to an n-type semiconductor, a p-type semiconductor has a greater hole concentration than an electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0059] In one or more embodiments, source region 204a is located on the top surface 203 of semiconductor substrate 202. In one or more embodiments, source region 204a has a source electrode and a source contact (not shown). Drain region 204b is located on the top surface 203 of semiconductor substrate 202, opposite to source region 204a. In one or more embodiments, drain region 204b has a drain electrode and a drain contact (not shown).

[0060] In one or more embodiments, the source region 204a and / or the drain region 204b can be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b can have more than one layer. For example, the source region 204a and / or the drain region 204b can independently comprise three layers. In one or more embodiments, the source region 204a and the drain region 204b can independently comprise one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and drain region 204b may independently comprise a bottom layer of doped epitaxial silicon (e.g., SiGe, SiP, and the like), a second layer of silicide (which may contain nickel (Ni), titanium (Ti), aluminum (Al), and the like), and a third or top layer, which may be a metal, such as, but not limited to, cobalt, tungsten, ruthenium, and the like. In some embodiments, the source region 204a and drain region 204b may be convex source / drain regions formed through EPI growth.

[0061] In one or more embodiments, the source and / or drain contacts may be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the source and / or drain contacts are formed using any suitable process known to those skilled in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0062] In one or more embodiments, the channel 206 is located between the source 204a and the drain 204b. For example... Figure 2F and Figure 2G As shown, channel 206 comprises multiple nanosheets. As used herein, the terms "channel 206," "transistor channel 206," "multiple nanosheets 206," and "multiple nanosheet channel layer 206" are used interchangeably. Channel 206 may comprise any suitable material known to those skilled in the art. In one or more embodiments, channel 206 comprises silicon (Si).

[0063] Each of the methods described herein (e.g., methods 10, 50, and 100) includes forming a P-metal stack and an N-metal stack on a semiconductor substrate (operation 12 of method 10, operation 52 of method 50, and operation 110 of method 100).

[0064] Each of the P-metal stack and the N-metal stack is formed on the top surface 205 of a channel 206 located between a source 204a and a drain 204b on a semiconductor substrate 202. In some embodiments, forming each of the P-metal stack and the N-metal stack includes: depositing an interface layer 210 on the top surface 205 of the channel 206; depositing a high-k dielectric layer 212 on the interface layer 210; and depositing a dipole layer 214 to a predetermined thickness on the high-k dielectric layer 212.

[0065] Referring to Figures 1A-1C and 2A-2G, in some embodiments, the interface layer 210 is deposited on the top surface 205 of the channel 206 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the interface layer 210 comprises a silicon oxide (SiOx) layer formed on doped or undoped silicon. In one or more embodiments, the interface layer 210 may be formed by etching and forming oxides on the surface. In one or more embodiments, the thickness of the interface layer 210 is between 1 Å and 10 Å.

[0066] In some embodiments, a wet chemical process is performed to form the interface layer 210. The wet chemical process can be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical process includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process includes using diluted hydrofluoric acid (diluted HF) at a dilution ratio greater than 100:1, for example, diluting HF at a ratio of 130:1, to etch away the native oxide on the semiconductor substrate 202 to form a hydrophobic surface (i.e., interface layer 210).

[0067] In some embodiments, a rapid thermal process (RTP) is used to form the interface layer 210. The RTP can be any suitable process known to those skilled in the art. In some embodiments, the RTP is a thermal oxidation process in which a silicon oxide (SiOx) layer, such as the interface layer 210, is grown on a semiconductor substrate 202.

[0068] In some embodiments, the high-k dielectric layer 212 is deposited on the interface layer 210 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the high-k dielectric layer 212 is deposited via conformal ALD deposition.

[0069] The high-K dielectric layer 212 includes one or more of hafnium oxide (HfOx), zirconium oxide hafnium (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped zirconium oxide hafnium (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).

[0070] The high-k dielectric layer 212 can have any suitable thickness. In some embodiments, the thickness of the high-k dielectric layer 212 is between 10 Å and 20 Å.

[0071] In some embodiments, the dipole layer 214 is deposited on the top surface 213 of the high-k dielectric layer 212 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0072] In some embodiments, depositing the dipole layer 214 includes exposing the semiconductor substrate 202 to pulses containing a metal precursor and pulses of reactants through an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate 202 is cleaned after each pulse. In one or more specific embodiments, the dipole layer 214 is deposited through atomic layer deposition (ALD).

[0073] In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD) at a temperature ranging from about 200°C to 600°C. In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD) at a temperature less than or equal to about 450°C.

[0074] The dipole layer 214 can have any suitable thickness. In one or more embodiments, the thickness of the dipole layer 214 ranges from 1 Å to 10 Å or from 2 Å to 5 Å. In one or more specific embodiments, the thickness of the dipole layer 214 ranges from 3 Å to 4 Å. The dipole layer 214 can be deposited as a single layer or multiple layers of thin film.

[0075] In some embodiments, the dipole layer 214 includes one or more of a metal layer, a metal oxide layer, or a metal nitride layer.

[0076] In some embodiments, the metal-containing precursor used to form the dipole layer 214 includes one or more of titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).

[0077] In some embodiments, the reactant is a hydrogen-containing reactant used to form a dipole layer 214 comprising a pure metal layer. In some embodiments, the hydrogen-containing reactant used to form the dipole layer 214 includes one or more of hydrogen (H2) or deuterium (2H).

[0078] In some embodiments, the reactants are oxygen-containing reactants used to form a dipole layer 214 comprising a metal oxide layer. In some embodiments, the oxygen-containing reactants used to form the dipole layer 214 include one or more of oxygen (O2), ozone (O3), or water (H2O).

[0079] In some embodiments, the reactants are nitrogen-containing reactants used to form a dipole layer 214 comprising a metal nitride layer.

[0080] In some embodiments, the nitrogen-containing reactants used to form the dipole layer 214 include one or more of the following: nitrogen (N2), ammonia (NH3), hydrazine (N2H4), nitrogen radical (N2*) and hydrogen radical (H*), nitrogen radical (N2*) and hydrogen (H2) gas co-flow, or nitrogen radical (N2*) and deuterium (2H) gas co-flow.

[0081] In some embodiments, the nitrogen-containing reactant used to form the dipole layer 214 comprises a substituted or unsubstituted alkyl hydrazine. In some embodiments, the alkyl hydrazine comprises one to six carbon atoms. In one or more embodiments, the alkyl hydrazine is a tertiary butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0082] Figures 2B, 2C, and 2E illustrate an N-metal stack 240 and a P-metal stack 250. In one or more embodiments, the stack on the left is an N-metal stack 240, and the stack on the right is a P-metal stack 250. Those skilled in the art will recognize that the left or right side may include either an N-metal stack 240 or a P-metal stack 250, and this disclosure is not limited to the illustrated embodiments.

[0083] In one or more embodiments, the channel 206 comprises an n-type material, and the dipole layer 214 comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs).

[0084] In one or more embodiments, the channel 206 comprises a p-type material, and the dipole layer 214 comprises one or more of aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo).

[0085] The method includes annealing the P-metal stack 250 and N-metal stack 240 at a temperature less than or equal to 1000°C to drive metal atoms from the dipole layer and densify a high-k dielectric layer (not shown). In some embodiments, the method includes annealing the P-metal stack 250 and N-metal stack 240 at a temperature less than or equal to 950°C. In some embodiments, the temperature range is 500°C to 1000°C, including a range of 600°C to 1000°C, a range of 700°C to 1000°C, a range of 750°C to 950°C, or a range of 800°C to 900°C.

[0086] In one or more embodiments, the dipole layer 214 on one or more of the P-metal stack 250 or N-metal stack 240 is removed by a selective etching process. For example, in Figure 2C In this process, the dipole layer 214 is removed from each of the P metal stack 250 and the N metal stack 240 through a selective etching process.

[0087] The etching process can be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, the water (H2O) is deionized water (DI). In some embodiments, the pre-cleaning process includes using a DI:NH4OH ratio ranging from 100:1 DI:NH4OH to 5:1 DI:NH4OH.

[0088] In some embodiments, the pre-cleaning process includes using either SC-1 or SC-2 solution. In one or more embodiments, SC-1 solution comprises one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, SC-2 solution comprises one or more of hydrochloric acid or hydrogen peroxide. Advantageously, it has been found that using either SC-1 or SC-2 solution can selectively etch the deposited dipole layer 214 from one of the P-metal stacks or N-metal stacks without etching a portion of the interface layer 210.

[0089] Figure 2D It shows Figure 2C Another cross-sectional view of the semiconductor substrate 202. Figure 2D In this process, each of the multiple nanosheet channel layers 206 is encapsulated by an interface layer 210 and a high-k dielectric layer 212 on the interface layer 210. Figure 2D A trench 208 between each of the plurality of nanosheet channel layers 206 is shown. In one or more embodiments, a gate trench 255 is present on at least one side of the channel 206. For example, in Figure 2D In the middle, gate trenches 255 are present on each side of the channel 206.

[0090] Referring to Figures 1A and 2E-2F, method 10 includes, in operation 14, forming a work function layer 220 in a channel 206 (e.g., between nanosheet channel layers 206) and inducing work function layer strain in the channel 206. Figures 1A, 1C, and 2E-2G at least show a “first strain-inducing process”.

[0091] exist Figure 2F In this structure, all sides of the channel 206 are covered. Each of the plurality of nanosheet channel layers 206 comprises silicon (Si). Figure 2F In this configuration, each of the plurality of nanosheet channel layers 206 is encapsulated by an interface layer 210, a high-k dielectric layer 212 on the interface layer 210, and a work function layer 220 on the high-k dielectric layer 212. In one or more embodiments, a gate trench 255 is present on at least one side of the channel 206. Figure 2F In the illustrated embodiment, a gate trench 255 is present on each side of the channel 206.

[0092] The work function layer 220 can be formed using any suitable process known to those skilled in the art. The work function layer 220 can be formed on the N-metal stack 240 using any suitable process. In one or more embodiments, forming the work function layer 220 on the P-metal stack 250 includes a thermal process. The processing parameters of the thermal process can be optimized or modified based on a specific application.

[0093] As used herein, the term "thermal process" refers to a deposition technique that does not involve the use of plasma. As used herein, the term "plasma" refers to a composition having ionicly charged species and uncharged neutral and radical species. In one or more embodiments, the ionicly charged species in the plasma are neutralized by optimizing the pressure within a processing chamber. In embodiments where the ionicly charged species of the plasma are neutralized, the plasma comprises a larger proportion of radicals and may be referred to as "radical-based plasma" or "radical-based process." In some embodiments, the radical-based plasma is generated by a remote plasma source. Without being limited by theory, it is considered that radical-based plasma generated by a remote plasma source eliminates ionicly charged species in the plasma, resulting in a plasma comprising a larger proportion of radicals.

[0094] Radical-based plasmas can include any radical species. In some embodiments, radical-based plasmas include one or more of nitrogen radicals (N2*) or hydrogen radicals (H*). The composition of nitrogen radicals (N2*) and hydrogen radicals (H*) can include any suitable ratio of nitrogen radicals (N2*) to hydrogen radicals (H*), and this ratio can be optimized or modified based on a specific application.

[0095] In one or more embodiments, after depositing the high-k dielectric layer 212, a work function layer 220 is formed in the channel 206 (e.g., in the trench 208 between the nanosheet channel layers 206). Figures 2E and 2F illustrate the work function layer 220 formed on the high-k dielectric layer 212.

[0096] Without being bound by theory, in one or more embodiments, we believe that if the dipole satisfies the threshold voltage (Vt) required for a particular application, the work function layer 220 can be replaced by a pure intermediate bandgap metallic material with adjustable stress.

[0097] In one or more embodiments, the method further includes forming a titanium nitride (TiN) layer in one or more trenches 208 of a channel 206 (such as, for example, a channel 206 of a P-metal stack 250) prior to forming a power function layer 220 (not shown).

[0098] The work function layer 220 may include any suitable metal known to those skilled in the art. The work function layer 220 may be formed from any suitable metal-containing precursor, including but not limited to organometallic precursors and / or metal halide precursors. In one or more embodiments, the metal-containing precursor includes, but is not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), ruthenium (Ru), iridium (Ir), tantalum (Ta), niobium (Nb), vanadium (V), or rhenium (Re).

[0099] In some embodiments, the work function layer 220 comprises one or more of a P-metal or an N-metal. In one or more embodiments, the work function layer 220 comprises a P-metal. In embodiments where the work function layer 220 comprises a P-metal, the P-metal comprises, for example, any suitable highly electronegative metal nitride material. In embodiments where the work function layer 220 comprises a P-metal, the P-metal comprises one or more of molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxynitride (MoON), or molybdenum carbonitride (MoCN).

[0100] In some embodiments, the work function layer 220 comprises an N metal. In embodiments where the work function layer 220 comprises an N metal, the N metal comprises, for example, any suitable electropositive refractive metal. In some embodiments, the N metal comprises titanium aluminum nitride (TiAlN).

[0101] The work function layer 220 can have any suitable thickness. In one or more embodiments, the thickness of the work function layer ranges from 10 Å to 30 Å. In one or more embodiments, the thickness of the work function layer is less than or equal to 30 Å, or less than or equal to 20 Å.

[0102] The P-metal stack 250 and / or the N-metal stack 240 may include any suitable P-metal, such as the P-metal described herein. The P-metal stack 250 and / or the N-metal stack 240 may include any suitable N-metal, such as the N-metal described herein.

[0103] In one or more embodiments, the method further includes forming a titanium nitride (TiN) layer, a TiN layer having an amorphous silicon (a-Si) capping layer thereon, or a titanium nitride silicon (TiSiN) layer in a trench 208 of a channel 206 (e.g., a channel 206 of an N-metal stack 240) before forming the power function layer 220 (not shown).

[0104] In one or more embodiments, the work function layer 220 on the N-metal stack comprises titanium aluminum nitride (TiAlN). In one or more embodiments, the work function layer 220 on the N-metal stack comprises titanium aluminum nitride (TiAlN) formed through a thermal process.

[0105] Advantageously, it has been found that the work function material described herein induces stress in the transistor channel 206 of the electronic component 200. As described herein, the work function layer strain of the “first strain-induced process” is high tensile stress. Advantageously, when the work function layer 220 is deposited in the channel 206 (e.g., between nanosheet channel layers 206 in each of the trenches 208) and work function layer strain is induced in the channel 206, each of the P metal stack 250 and the N metal stack 240 independently has compressive and tensile stresses ranging from 1 gigapascal (GPa) to 2 gigapascal (GPa), respectively.

[0106] Referring to Figures 1B and 2F, method 50 includes, in operation 54, forming a gate metal fill layer 260 on each of the P-metal stack 250 and the N-metal stack 240, and inducing strain in the gate metal fill layer in a channel 206, the gate metal fill layer 260 covering at least one side of each of the P-metal stack and the N-metal stack and filling the gate trench 255.

[0107] Referring to Figures 1C and 2G, method 100 includes, in operation 130, forming a gate metal fill layer 260 on a channel 206 (e.g., on the channel 206 of each of the P-metal stack 250 and N-metal stack 240) and inducing strain in the gate metal fill layer within the channel 206. In one or more embodiments, the gate metal fill layer 260 covers at least one side of each of the channels 206 (e.g., the channel 206 of each of the P-metal stack 250 and N-metal stack 240). In one or more embodiments, for example in Figure 2G In this process, the gate metal fill layer 260 fills the gate trench 255 on both sides of the channel 206. In some embodiments, the process of operation 54 of method 50 and the process of operation 130 of method 100 are the same. Figures 1B, 1C, and 2G at least show a "second strain-induced process". As described herein, the strain in the gate metal fill layer of the "second strain-induced process" is compressive stress.

[0108] exist Figure 2G In the middle, covering all sides of the channel 206. Each of the plurality of nanosheet channel layers 206 comprises silicon (Si). Figure 2G In this process, each of the plurality of nanosheet channel layers 206 is encapsulated by an interface layer 210, a high-k dielectric layer 212 on the interface layer 210, a work function layer 220 on the high-k dielectric layer 212, and a gate metal filling layer 260 on the work function layer 220.

[0109] For example, in Figure 2G In the illustrated embodiment, the gate metal fill layer 260 covers all sides of the channel 206 and fills the gate trench 255 on both sides of the channel 206. In one or more embodiments, the gate metal fill layer 260 covers all sides of each of the P-metal stack 250 and the N-metal stack 240. In one or more embodiments, the gate metal fill layer 260 is a continuous layer.

[0110] In one or more embodiments, forming the gate metal fill layer 260 includes a thermal process (as described herein), followed by a post-processing process or a plasma-enhanced atomic layer deposition (PEALD) process.

[0111] In embodiments where the formation of the gate metal fill layer 260 includes a thermal process followed by a post-processing process, the post-processing process includes exposing the thermally deposited gate metal fill layer 260 to a plasma comprising one or more of argon (Ar) or hydrogen (H2), with a plasma power ranging from 150 W to 800 W, to form a treated gate metal fill layer. In some embodiments, the flow rate of the Ar plasma ranges from 0.5 standard liters per minute (slm) to 6 slm. In some embodiments, the flow rate of the H2 plasma ranges from 6 slm to 10 slm.

[0112] In one or more embodiments, the gate metal filling layer 260 is formed at a temperature ranging from 150°C to 500°C.

[0113] In one or more embodiments, forming the gate metal fill layer 260 includes exposing the semiconductor substrate 202 to one or more molybdenum-containing or tungsten-containing precursors. The molybdenum-containing and / or tungsten-containing precursors may include any suitable precursor. In one or more embodiments, the molybdenum-containing precursor includes one or more of molybdenum pentachloride (MoCl5) or molybdenum dioxide dichloride (MoO2Cl2). In one or more embodiments, the tungsten-containing precursor includes tungsten pentachloride (WCl5), tungsten hexafluoride (WF6), or tungsten oxychloride (WOxCly).

[0114] Advantageously, forming the gate metal fill layer 260 induces strain in the gate metal fill layer within the channel 206. When the gate metal fill layer 260 is formed, the P-metal stack 250 advantageously exhibits compressive stress (e.g., negative GPa).

[0115] In embodiments where the gate metal fill layer 260 is formed by the method described herein, it is advantageous that the electronic component 200 meets the compressive stress requirements of a PMOS transistor and the tensile stress requirements of an NMOS transistor. In one or more embodiments, the compressive stress of the P-metal stack 250 ranges from -0.1 GPa to -3.1 GPa, and the tensile stress of the N-metal stack 240 is greater than or equal to 2 GPa.

[0116] In one or more embodiments, the compressive stress value of the P-metal stack 250 varies based on the thickness of the gate metal fill layer 260. Without being limited by theory, it is assumed that the compressive stress of the P-metal stack 250 increases with the increase of the thickness of the gate metal fill layer 260.

[0117] The gate metal fill layer 260 can be deposited to any suitable thickness. In one or more embodiments, the gate metal fill layer 260 is deposited to a thickness greater than or equal to 30 Å, greater than or equal to 50 Å, greater than or equal to 100 Å, greater than or equal to 150 Å, or greater than or equal to 200 Å.

[0118] In some embodiments, when the gate metal fill layer 260 is deposited using a thermal process with MoO2Cl2, the compressive stress of the P metal stack 250 is -1.7 GPa at 35 Å and -0.6 GPa at 150 Å.

[0119] In some embodiments, when the gate metal fill layer 260 is deposited using a MoCl5 through-thermal process, the compressive stress of the P metal stack 250 is -0.8 GPa at 35 Å and -0.1 GPa at 150 Å.

[0120] In some embodiments, when the gate metal fill layer 260 is deposited using MoO2Cl2 via a PEALD process, the compressive stress of the P metal stack 250 is -1.8 GPa at 30 Å and -1.0 GPa at 100 Å.

[0121] In some embodiments, when the gate metal fill layer 260 is deposited using MoCl5 via a PEALD process, the compressive stress of the P metal stack 250 is -0.96 GPa at approximately 42 Å and -0.86 GPa at 90 Å.

[0122] In one or more embodiments, method 100 includes forming a work function layer 220 by heat treatment to a thickness of less than or equal to 30 Å, less than or equal to 20 Å, or less than or equal to 10 Å (“first strain-induced process”), and forming a gate metal fill layer 260 by a PEALD process to a thickness of greater than or equal to 30 Å, greater than or equal to 50 Å, greater than or equal to 100 Å, greater than or equal to 150 Å, or greater than or equal to 200 Å (“second strain-induced process”).

[0123] A further aspect of this disclosure relates to a method as part of a gap-filling composition. In some embodiments, such as method 100, a work function layer 220 is deposited on all sides of a channel 206. In one or more embodiments, the work function layer 220 acts as a pad, and a gate-filled metal layer 260 is deposited on the work function layer 220. In one or more embodiments, the work function layer 220 is deposited via a thermal process to a thickness of less than or equal to 30 Å, less than or equal to 20 Å, or less than or equal to 10 Å, and the gate-filled metal layer 260 is deposited on the work function layer via a PEALD process to a thickness of greater than or equal to 30 Å, greater than or equal to 50 Å, greater than or equal to 100 Å, greater than or equal to 150 Å, or greater than or equal to 200 Å. Advantageously, it has been found that, for example in method 100, depositing a work function layer 220 and then depositing a gate fill metal layer 260 on the work function layer 220 can advantageously induce compressive and tensile stresses that satisfy the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors, respectively.

[0124] Additional embodiments of this disclosure relate to a processing tool (i.e., a clustering tool) 900 for forming the aforementioned logic / memory elements and methods, such as Figure 3 As shown. The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are placed within the central transfer stations 921, 931 and configured to move robot blades and wafers to each of the multiple sides.

[0125] Cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, connected to central transfer stations 921 and 931. Each processing chamber provides an independent processing area isolated from adjacent processing stations. Processing chambers can be any suitable chamber, including but not limited to pre-cleaning chambers, buffer chambers, transfer spaces, wafer orientation / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, heat treatment chambers, plasma oxidation chambers, plasma nitriding chambers, atomic layer deposition (ALD) chambers, and plasma enhanced ALD (PEALD) chambers.

[0126] In one or more embodiments, the ALD chamber includes a single chamber for depositing an interface layer on the top surface of the channel; depositing a high-k dielectric layer on the interface layer; and depositing a dipole layer on the high-k dielectric layer to a predetermined thickness such that no vacuum interruption occurs between operations.

[0127] In one or more embodiments, the ALD chamber may include a single chamber for each of the following: depositing an interface layer on the top surface of the channel; depositing a high-k dielectric layer on the interface layer; and depositing a dipole layer on the high-k dielectric layer to a predetermined thickness such that no vacuum interruption occurs between at least one operation in operation.

[0128] In one or more embodiments, the heat treatment chamber is used to form the power function layer 220. In one or more embodiments, the PEALD chamber is used to form the gate metal fill layer 260. In one or more embodiments, the heat treatment chamber and the PEALD chamber are connected such that no vacuum interruption occurs between individual operations.

[0129] In one or more embodiments, the heat treatment chamber and the PEALD chamber are isolated in such a way that a vacuum interruption is created between the individual operations.

[0130] The specific arrangement of the processing chambers and components varies depending on the cluster tool and should not be considered a limitation on the scope of this disclosure.

[0131] In one or more embodiments, the swarm tool 900 includes a silica (SiO2) chamber for depositing silica (SiO2). Some embodiments of the silica (SiO2) deposition chamber include an atomic layer deposition chamber, a plasma-enhanced atomic layer deposition chamber, or a space atomic layer deposition chamber. In one or more embodiments, the swarm tool 900 includes a pre-cleaning chamber connected to a central transfer station.

[0132] exist Figure 3 In the illustrated embodiment, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 located on the front portion 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this represents only one possible configuration.

[0133] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending on the substrate or the like that being processed by the clustering tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to accommodate a wafer cassette containing multiple wafers.

[0134] Robot 952 is located within factory interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 can transfer wafers from cassettes in loading chamber 954 to loading gate chamber 960 via factory interface 950. Robot 952 can also transfer wafers from loading gate chamber 962 to cassettes in unloading chamber 956 via factory interface 950. Those skilled in the art will understand that factory interface 950 can have more than one robot 952. For example, factory interface 950 can have a first robot transferring wafers between loading chamber 954 and loading gate chamber 960, and a second robot transferring wafers between loading gate 962 and unloading chamber 956.

[0135] Figure 3The clustering tool 900 shown may have a first portion 920 and a second portion 930. The first portion 920 is connected to the factory interface 950 via loading gate chambers 960, 962. The first portion 920 includes a first transfer chamber 921 in which at least one robot 925 is housed. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the loading gate chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-armed robot capable of independently moving more than one wafer at a time. In one or more embodiments, the first transfer chamber 921 includes more than one robotic wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Each wafer is carried by a wafer transfer blade located at the distal end of the first robotic mechanism.

[0136] After the wafer is processed in the first section 920, it can be transferred to the second section 930 via a through chamber. For example, chambers 922 and 924 can be unidirectional or bidirectional through chambers. The through chambers 922 and 924 can be used to cryogenically cool the wafer before processing in the second section 930, or to allow the wafer to be cooled or post-processed before being moved back to the first section 920.

[0137] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0138] The process can typically be stored as a software routine in the memory of the system controller 990, which, when executed by the processor, causes the processing chamber to execute the process of this disclosure. The software routine can also be stored and / or executed by a second controller (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods described herein (e.g., methods 10, 50, and / or 100) can also be executed in hardware. Therefore, the process can be implemented in software and executed using a computer system, implemented in hardware (e.g., as an application-specific integrated circuit or other type of hardware implementation), or implemented as a combination of software and hardware. When the processor executes the software routine, it transforms a general-purpose computer into a special-purpose computer (controller), thereby controlling the chamber operation to execute the process.

[0139] The embodiments disclosed herein relate to non-transitory computer-readable media. In one or more embodiments, the non-transitory computer-readable media includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the operations of any of the methods described herein. In one or more embodiments, the controller causes the processing chamber to perform the operations of method 10. In one or more embodiments, the controller causes the processing chamber to perform the operations of method 50. In one or more embodiments, the controller causes the processing chamber to perform the operations of method 100.

[0140] In one or more embodiments, the processing tool 900 includes central transfer stations 921, 931, the central transfer stations 921, 931 including at least one robot 925, 935 configured to move a wafer; one or more of a rapid thermal processing (RTP) station, a decoupled plasma oxidation (DPO) station, or a decoupled plasma nitridation (DPN) station connected to the central transfer station; an atomic layer deposition (ALD) station connected to the central transfer station; a thermal processing station; a plasma enhanced ALD (PEALD) station; an optional pre-processing station connected to the central transfer station; and at least one controller connected to one or more of the central transfer station, RTP station, DPO station, DPN station, ALD station, or optional pre-cleaning station. In one or more embodiments, at least one controller has at least one configuration selected from the following: a configuration for moving wafers between stations using a robot; a configuration for performing a rapid thermal process; a configuration for performing a decoupled plasma process; a configuration for controlling the flow rate of oxidizing gas entering an RTP station or a DPO station; a configuration for controlling the flow rate of nitriding gas entering an RTP station or a DPN station; a configuration for depositing a silicon oxide film through atomic layer deposition; and a configuration for pre-cleaning wafers.

[0141] For ease of description, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature shown in the figure and another element or feature. It is understood that, in addition to the orientations described in the figure, spatially relative terms also include different orientations of the element in use or operation. For example, if the element in the figure is flipped over, an element described as “below” or “under” other elements or features would be positioned “above” other elements or features. Therefore, the exemplary term “below” can include both above and below orientations. Elements may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0142] In the context of describing the materials and methods described herein (particularly in the context of the following claims), the terms “a,” “an,” and “the,” and similar representations, shall be construed as including both singular and plural forms, unless otherwise stated herein or clearly contradicted by the context. Unless otherwise stated herein, the description of numerical ranges herein is merely a shorthand method used to individually represent each individual numerical value belonging to that range, and each individual value has been incorporated into the specification as if it were described separately herein. Unless otherwise stated herein or clearly contradicted by the context, all methods described herein may be performed in any suitable order. The use of any and all example or exemplary language provided herein (e.g., “such as”) is solely for the purpose of better elucidating the materials and methods and does not constitute a limitation on the scope, unless otherwise required. No language in the specification should be construed as indicating that any unclaimed element is essential for the practice of the disclosed materials and methods.

[0143] The terms "an embodiment," "some embodiments," "one or more embodiments," or "an embodiment" used in this specification refer to a specific feature, structure, material, or characteristic associated with an embodiment that is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" throughout this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, specific features, structures, materials, or characteristics are combined in any suitable manner.

[0144] Although this disclosure has been described with reference to specific embodiments, it should be understood that such embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and alterations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and alterations within the scope of the appended claims and their equivalents.

Claims

1. A method of fabricating an electronic component, the method comprising the steps of: forming a P-metal stack and an N-metal stack on a semiconductor substrate, each of the P-metal stack and the N-metal stack formed on a top surface of a channel between a source and a drain on the semiconductor substrate, each of the P-metal stack and the N-metal stack comprising nanosheet channel layers and trenches between each nanosheet channel layer; and forming a work function layer in the channel between the nanosheet channel layers of each of the trenches and inducing work function layer strain in the channel, each of the P-metal stack and the N-metal stack independently having compressive stress and tensile stress in a range of 1 gigapascal (GPa) to 2 GPa, respectively.

2. The method of claim 1, wherein the step of forming each of the P-metal stack and the N-metal stack comprises the steps of: depositing an interface layer on the top surface of the channel; depositing a high-K dielectric layer on the interface layer; and depositing a dipole layer on the high-K dielectric layer.

3. The method of claim 2, wherein the work function layer is formed in the channel between the nanosheet channel layers after depositing the high-K dielectric layer.

4. The method of claim 1, further comprising the step of: forming a titanium nitride (TiN) layer in one or more of the trenches of the P-metal stack prior to forming the work function layer.

5. The method of claim 1, wherein the step of forming the work function layer on the P-metal stack comprises a thermal process.

6. The method of claim 5, wherein the work function layer comprises one or more of molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxynitride (MoON), or molybdenum carbonitride (MoCN).

7. The method of claim 1, further comprising the step of: forming a titanium nitride (TiN) layer, a TiN layer with an amorphous silicon (a-Si) capping layer thereon, or a titanium silicon nitride (TiSiN) layer in the trenches of the N-metal stack prior to forming the work function layer.

8. The method of claim 1, wherein forming the work function layer on the N metal stack comprises: forming a titanium aluminum nitride (TiAlN) through a thermal process.

9. A method of fabricating an electronic component, the method comprising the steps of: forming a P-metal stack and an N-metal stack on a semiconductor substrate, each of the P-metal stack and the N-metal stack formed on a top surface of a channel between a source and a drain on the semiconductor substrate, each of the P-metal stack and the N-metal stack comprising nanosheet channel layers and trenches between each nanosheet channel layer; each of the P-metal stack and the N-metal stack having at least one side that defines a gate trench; and forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing gate metal fill layer strain in the channel, the gate metal fill layer covering the at least one side of each of the P-metal stack and the N-metal stack and filling the gate trench, the P-metal stack having compressive stress in a range of -0.1 GPa to -3.1 GPa, and the N-metal stack having tensile stress greater than or equal to 2 GPa.

10. The method of claim 9, wherein the step of forming the gate metal fill layer comprises a thermal process followed by a post-treatment process or a plasma enhanced atomic layer deposition (PEALD) process.

11. The method of claim 10, wherein the post-treatment process comprises the steps of: exposing the thermally deposited gate metal fill layer to a plasma including one or more of argon (Ar) or hydrogen (H2) at a plasma power in a range from 150 W to 800 W to form a treated gate metal fill layer.

12. The method of claim 11, comprising the step of: flowing the Ar plasma in a range from 0.5 standard liters per minute (slm) to 6 slm.

13. The method of claim 11, comprising the step of: flowing the H2 plasma in a range from 6 slm to 10 slm.

14. The method of claim 10 wherein the step of forming the gate metal fill layer comprises the steps of: exposing the semiconductor substrate to one or more of a molybdenum-containing precursor or a tungsten-containing precursor.

15. The method of claim 14, wherein the molybdenum-containing precursor includes one or more of molybdenum pentachloride (MoCl5) or molybdenum dioxide dichloride (MoO2Cl2).

16. The method of claim 14, wherein when MoO2Cl2 is used to deposit the gate metal fill layer through the thermal process, the P-metal stack has a compressive stress of -1.7 GPa at 35 Å and -0.6 GPa at 150 Å.

17. The method of claim 14, wherein when MoCl5 is used to deposit the gate metal fill layer through the thermal process, the P-metal stack has a compressive stress of -0.8 GPa at 35 Å and -0.1 GPa at 150 Å.

18. The method of claim 14, wherein when MoO2Cl2 is used to deposit the gate metal fill layer through the PEALD process, the P-metal stack has a compressive stress of -1.8 GPa at 30 Å and -1.0 GPa at 100 Å.

19. The method of claim 14, wherein when MoCl5 is used to deposit the gate metal fill layer through the PEALD process, the P-metal stack has a compressive stress of -0.96 GPa at 42 Å and -0.86 GPa at 90 Å.

20. A method of fabricating an electronic component, the method comprising: forming a P-metal stack and an N-metal stack on a semiconductor substrate, each of the P-metal stack and the N-metal stack formed on a top surface of a channel between a source and a drain on the semiconductor substrate, each of the P-metal stack and the N-metal stack including a nanosheet channel layer and a trench between each nanosheet channel layer, each of the P-metal stack and the N-metal stack having at least one side that bounds a gate trench; forming a work function layer in the channel between the nanosheet channel layers of each of the trenches and inducing work function layer strain in the channel, the step of forming the work function layer including a thermal process; and forming a gate metal fill layer on each of the P-metal stack and the N-metal stack and inducing a gate metal fill strain in the channel, the gate metal fill layer covering the at least one side of each of the P-metal stack and the N-metal stack and filling the gate trench, the step of forming the gate metal fill layer comprising a plasma enhanced atomic layer deposition (PEALD) process, the tensile stress of the N-metal stack being in a range of greater than or equal to 2 GPa, and the compressive stress of the P-metal stack being in a range of -0.1 GPa to -3.1 GPa.

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