Operational amplifier

Abstract

The invention provides an operational amplifier. The operational amplifier comprises a bias module, a chopping module, an enhanced recovery folded cascode module and an output stage module, the enhanced recovery folded cascode module comprises a first input tube group, a second input tube group and a regulation resistor, grid electrodes of the first input tube group and the second input tube group are connected with the output end of the chopping module, a source electrode of the first input tube group is connected to one end of the regulation resistor, a source electrode of the second input tube group is connected to the other end of the regulation resistor, and a source electrode of the second input tube group is connected to the other end of the regulation resistor. The first input tube group and the second input tube group generate different gate-source voltages; the three-path current recovery structure comprises at least two folded node transistors, two circulating current mirror transistors and two shunt transistors, the ratio of the width-to-length ratios of the folded node transistors, the circulating current mirror transistors and the shunt transistors is (1 + x): z (1-x): y (1-x), the value of x is larger than 0 and smaller than 1, and y + z = 1; and the grid electrodes of the matching transistors are connected to the bias voltage provided by the bias module.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuits, and more specifically, to an operational amplifier. Background Technology

[0002] Operational amplifiers (op-amps) are one of the core components of analog integrated circuits and are widely used in various industries such as mobile phones, automobiles, and medical devices. Existing op-amps typically employ a two-stage structure: the first stage uses a five-transistor OTA (active load differential pair), and the second stage uses a common-source amplifier, with Miller compensation used to ensure circuit stability. However, the simple structure of the five-transistor OTA results in relatively low gain, and the two-stage structure not only limits its bandwidth but also increases circuit noise.

[0003] Based on existing structures, the gain of common operational amplifiers is typically around 80dB. While the aforementioned open-loop gain can meet the application requirements of medium-precision operational amplifiers, it will introduce significant errors in high-precision scenarios. Furthermore, the low gain-bandwidth product of traditional op-amps limits their ability to process only low-frequency data.

[0004] Given the increasingly stringent performance requirements for operational amplifiers, there is an urgent need to develop operational amplifiers that combine low noise, high gain, and high gain-bandwidth product (GBW). Summary of the Invention

[0005] To address or improve the aforementioned problems in the prior art, this application provides an operational amplifier, including a bias module, a chopper module, an enhanced reclaimed folded cascode module, and an output stage module;

[0006] The enhanced recycling folded common-source common-gate module includes:

[0007] The first input transistor group, the second input transistor group, and the control resistor are connected to the output terminal of the chopper module. The source of the first input transistor group is connected to one end of the control resistor, and the source of the second input transistor group is connected to the other end of the control resistor, so that the first input transistor group and the second input transistor group generate different gate-source voltages.

[0008] The three-path current recovery structure includes at least two folded node transistors, two circulating current mirror transistors, and two shunt transistors. The width-to-length ratio of the folded node transistors, circulating current mirror transistors, and shunt transistors is (1+x):z(1-x):y(1-x), where x, y, and z are adjustable parameters, x takes a value greater than 0 and less than 1, and y+z=1.

[0009] Multiple matching transistors, with the gates of the matching transistors connected to the bias voltage provided by the bias module.

[0010] In the aforementioned scheme, the regulating resistor causes the first input transistor group and the second input transistor group to generate different gate-source voltages. The first input transistor group and the second input transistor group together constitute a differential signal receiving structure. The sources of the two are connected through the regulating resistor instead of being directly short-circuited, which is different from the traditional differential pair structure.

[0011] An active (circulating) current mirror composed of circulating current mirror transistors recycles current. A shunt transistor acts as a shunt path and reduces the input current of the circulating current mirror. Multiple matching transistors are used to ensure the improved matching of the aforementioned current mirror.

[0012] The unbalanced bias of the first input transistor group and the second input transistor group can change the transconductance of the folded node transistor and the circulating current mirror transistor, thereby improving the overall circuit gain and gain-bandwidth product; while the ratio of the width-to-length ratio of the folded node transistor, the circulating current mirror transistor and the shunt transistor can give the circuit a suitable quiescent operating point.

[0013] Optionally, the quiescent current of the first input transistor group is (1+x)Ib, and the quiescent current of the second input transistor group is (1-x)Ib, where Ib is the reference bias current; the resistance value of the regulating resistor is configured to adjust the value of x to increase the effective transconductance of the enhanced recycle folded cascode module and increase the gain-bandwidth product of the operational amplifier.

[0014] Optionally, the resistance value of the regulating resistor is configured such that x is greater than 0 and less than 0.5; preferably, x is not less than 0.25 and less than 0.5. In the foregoing embodiment, by setting the regulating resistor, x is made to be less than 0.5 to overcome the transconductance limitation in the prior art.

[0015] Optionally, the first input transistor group includes a first PMOS transistor and a second PMOS transistor, and the second input transistor group includes a third PMOS transistor and a fourth PMOS transistor; the folding node transistor includes a first NMOS transistor and a second NMOS transistor, the circulating current mirror transistor includes a third NMOS transistor and a fourth NMOS transistor, the shunt transistor includes a fifth NMOS transistor and a sixth NMOS transistor; the matching transistor includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; wherein, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the drains of the first PMOS transistor and the drains of the second PMOS transistor respectively serve as enhancement-mode recycling folding transistors. The output node of the common source common gate module; the drain of the third PMOS transistor is connected to the drain of the ninth and tenth NMOS transistors and the gate of the second and fourth NMOS transistors; the drain of the fourth PMOS transistor is connected to the drain of the seventh and eighth NMOS transistors and the gate of the first and third NMOS transistors; the sources of the seventh, eighth, ninth, and tenth NMOS transistors are connected to the drains of the third, fifth, sixth, and fourth NMOS transistors, respectively; the sources of the folded node transistor, the circulating current mirror transistor, and the shunt transistor are all grounded; the gates of the fifth and sixth NMOS transistors are connected to the bias voltage from the bias module.

[0016] Optional, enhanced recovery of the effective transconductance G of the folded cascode module m,ERFC for:

[0017]

[0018] Among them, g mpa This represents the effective transconductance of the transistors in the first input transistor group.

[0019] Optionally, the gain-bandwidth product (GBW) of the operational amplifier is:

[0020]

[0021] Among them, g mpa C is the effective transconductance of the transistor in the first input transistor group. L This is the load capacitor.

[0022] Optional, the chopper module includes:

[0023] The input stage chopper module has its input terminal connected to the input terminal of the operational amplifier and its output terminal connected to the gates of the first input transistor group and the second input transistor group. It is used to modulate the input signal to the chopping frequency.

[0024] The output stage chopper module has its input terminal connected to the output node of the enhanced retractable folded cascode module and its output terminal connected to the input node of the output stage module. It is used to demodulate the amplified signal back to the original frequency and modulate low-frequency noise to the chopper frequency.

[0025] The chopper module is controlled by a complementary clock signal.

[0026] Optional, the output stage modules include:

[0027] Two push-pull output tubes;

[0028] A transconducting linear loop composed of multiple PMOS and NMOS transistors;

[0029] Multiple resistors and capacitors are positioned between the output of the operational amplifier and the input node of the output stage module.

[0030] Optionally, the output level module is a Class-AB output level module.

[0031] Optionally, the bias module is configured to provide four stable bias voltages for the enhanced recycle folded cascode module and the output stage module.

[0032] Optionally, the operational amplifier, under a 10pF load, has a low-frequency gain greater than 120dB, a gain-bandwidth product greater than 40MHz, and an equivalent input noise of less than [value missing] at 1kHz.

[0033] In summary, the operational amplifier provided in this application embodiment has a current recovery structure in its enhanced recovery folded cascode module that can convert the large current of the MOSFET at the fold into transconductance, and further increase the transconductance through the control resistor, thereby ultimately improving the gain and gain-bandwidth product of the operational amplifier. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0035] Figure 1 This is an overall circuit diagram of the operational amplifier provided in the embodiments of this application;

[0036] Figure 2 This is a circuit diagram of the bias module in the operational amplifier provided in the embodiments of this application;

[0037] Figure 3 This is a circuit diagram of the input stage chopper module in the operational amplifier provided in the embodiments of this application;

[0038] Figure 4This is a circuit diagram of the enhanced recycle folded cascode module in the operational amplifier provided in the embodiments of this application. The diagram also shows the output stage chopper module and part of the output stage module.

[0039] Figure 5 This is a circuit diagram of the output stage module in the operational amplifier provided in the embodiments of this application;

[0040] Figure 6 This is the amplitude-frequency response curve of the operational amplifier provided in the embodiments of this application;

[0041] Figure 7 This is the equivalent input noise curve of the operational amplifier provided in the embodiments of this application.

[0042] The image is labeled as follows:

[0043] 100: Bias module; 200: Chopper module; 210: Input stage chopper module; 220: Output stage chopper module; 300: Enhanced recycle folded cascode module; 400: Output stage module. Detailed Implementation

[0044] In this specification, it will also be understood that when a component / module is referred to as being "connected to" other components / modules relative to them, such as "connected to" other components / modules, the component / module may be directly connected to or directly coupled to the component / module, or there may be an intermediary third component / module; in addition, in the embodiments of this application, "connection" mainly refers to electrical connection.

[0045] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete, and to fully convey the scope of this application to those skilled in the art. The same reference numerals denote the same objects throughout the drawings.

[0046] To address the shortcomings of the aforementioned prior art, and considering the need to improve the gain and gain-bandwidth product of the operational amplifier, as well as reduce noise, the following improvement scheme is further proposed:

[0047] (1) Change the parameters of the transistor. For example, increase the size of the input pair transistors (width-to-length ratio W / L) in the five-transistor OTA, which can increase the gain. However, the side effect is that in order to maintain the same bias current, the current source needs to be increased, and the increased current leads to a significant increase in current noise. Alternatively, increase the length of the cascode transistor, but the side effect is that the gain-bandwidth product is reduced, and an additional cascaded structure is needed to maintain the bandwidth, which increases the circuit complexity and indirectly leads to increased power consumption.

[0048] (2) A stable current and bias are generated using a bias circuit, allowing the circuit to operate at a suitable quiescent operating point. The first stage of this scheme uses a folded cascode amplifier to provide a large input swing, while the second stage uses a common-source amplifier to provide a large output swing. Therefore, this scheme can provide a larger operational amplifier gain while ensuring a wide input and output swing, typically reaching 100–110 dB. Although this scheme ensures a wide operational amplifier swing and large gain, the MOS transistors at the folded points have a large current that is only used as a current source, failing to effectively improve the circuit gain. This not only wastes current and reduces current utilization but also increases circuit noise and introduces additional poles, limiting the improvement of the operational amplifier bandwidth.

[0049] Therefore, improving circuit gain and GBW while maintaining low power consumption and large input / output swing remains a technical challenge for the industry. In view of this, the embodiments of this application aim to provide an operational amplifier that combines high gain, high gain-bandwidth product, and low noise.

[0050] like Figure 1 As shown, the operational amplifier provided in this application specifically includes the following structure: a bias module 100, a chopper module 200, an enhanced recycle folded cascode module 300, and an output stage module 400. Each module is configured according to... Figure 1 The connection is made in the manner shown in the diagram.

[0051] Typically, each of the aforementioned modules includes the following components:

[0052] Bias module 100: includes PMOS transistors PM1 to PM4, NMOS transistors NM1 to NM6, and resistor R1;

[0053] Chopper module 200: includes PMOS transistors PM20 to PM23 and NMOS transistors NM22 to NM29;

[0054] Enhanced Recycling Folded Cascode (ERFC) 300: includes PMOS transistors PM5 to PM12, NMOS transistors NM7 to NM14 and resistor R2, wherein resistor R2 is used as a control resistor in the following description of this application;

[0055] Output stage module 400: includes PMOS transistors PM13-PM19, NMOS transistors NM15-NM21, and capacitor C. C1 C C2 resistor R Z1 R Z2 .

[0056] To facilitate full disclosure in subsequent embodiments, the functions of each module are briefly described below.

[0057] The bias module 100 is used to generate stable bias current and bias voltage, which not only provides bias for the enhanced recycle folded cascode module 300, but also for the output stage module 400.

[0058] The chopper module 200 modulates the input signal to the chopper frequency at the input of the operational amplifier and demodulates the amplified signal back to the original frequency at the output of the operational amplifier, while low-frequency noise is modulated to the chopper frequency.

[0059] The enhanced recycle folded cascode module 300 provides high gain, gain-bandwidth product (GBW), and slew rate for operational amplifiers while ensuring a wide common-mode input range.

[0060] The output stage module 400 (Class-AB output stage) can provide greater dynamic drive capability while maintaining low static power consumption.

[0061] To address the shortcomings of existing technologies, the operational amplifier provided in this application features a key structural element: an enhanced reclaimed folded cascode module 300, such as... Figure 4 As shown, it includes: the first input transistor group PM7a, PM8a, the second input transistor group PM7b, PM8b and the control resistor R2.

[0062] Combination Figure 1 The gates of the first and second input transistor groups are connected to the output of the chopper module 200. The source of the first input transistor group is connected to one end of the regulating resistor R2, and the source of the second input transistor group is connected to the other end of the regulating resistor R2, so that the first and second input transistor groups generate different gate-source voltages. The first and second input transistor groups together constitute a differential signal receiving structure. Their sources are connected through the regulating resistor R2 instead of being directly short-circuited, which is different from the traditional differential pair structure.

[0063] like Figure 4 As shown, the enhanced recycling folded cascode module 300 also includes a three-path current recovery structure, including at least two folded node transistors NM9a and NM10a, two circulating current mirror transistors NM9b and NM10b, and two shunt transistors NM9c and NM10c.

[0064] The width-to-length ratio of the folded node transistor, the circulating current mirror transistor, and the shunt transistor is: (1+x):z(1-x):y(1-x), where x, y, and z are adjustable parameters, x takes a value greater than 0 and less than 1, and y+z=1.

[0065] In addition, the enhanced recycling folded cascode module 300 also includes multiple matching transistors NM11 to NM14, the gates of which are connected to a bias voltage V provided by the bias module 100. b3 .

[0066] In the aforementioned embodiments, the active (cyclic) current mirror composed of circulating current mirror transistors recycles the current, the shunt transistor acts as a shunt path and reduces the input current of the circulating current mirror, and multiple matching transistors are used to ensure the improved matching of the current mirror. Specifically, the unbalanced bias of the first input transistor group and the second input transistor group can change the transconductance of the folded node transistor and the circulating current mirror transistor, thereby improving the overall circuit gain and gain-bandwidth product; and the aspect ratio of the folded node transistor, the circulating current mirror transistor, and the shunt transistor can ensure that the circuit has a suitable quiescent operating point.

[0067] In a typical embodiment, the values ​​of x, y, and z are x = 3 / 8, z = 1 / 5, and y = 4 / 5, respectively. Therefore, the width-to-length ratio of the folded node transistor, the circulating current mirror transistor, and the shunt transistor is (1+x):z(1-x):y(1-x) = 11:1:4.

[0068] Based on the aforementioned configuration, in a 180nm CMOS process, the aspect ratio of the folded node transistors NM9a and NM10a is 11 × (2.7μm / 1.8μm), the aspect ratio of the circulating current mirror transistors NM9b and NM10b is 1 × (2.7μm / 1.8μm), and the aspect ratio of the shunt transistors NM9c and NM10c is 4 × (2.7μm / 1.8μm), where the reference bias current Ib = 32μA and the resistor R2 = 0.96kΩ. Figure 6 As shown, the simulation measured a low-frequency gain of 125.72 dB and a GBW of 42.61 MHz. Figure 7 As shown, the equivalent input noise at 1kHz

[0069] In the aforementioned embodiments, setting the transistor to a larger size enables better current mirror matching and reduces current matching problems caused by the MOS transistor channel length modulation effect.

[0070] The performance parameters of the aforementioned embodiments compared with those in comparative documents 1 and 2 are shown in Table 1 below, based on simulation results.

[0071] Table 1. Performance parameter comparison between this scheme and comparative literature 1-2 (C) L =10pF)

[0072]

[0073] It can be seen that this scheme has significantly improved the gain and GBW of the operation method circuit.

[0074] Comparison with Reference 1: A broadband low-power transconductance operational amplifier with enhanced slew rate (Patent Application Publication No.: CN116015217A);

[0075] Comparative Reference 2: Wang Jing, Guo Ting, Li Wei. Optimized Design of Input Stage of Precision Low-Noise Operational Amplifier [J]. Semiconductor Technology, 2019, 44(11): 846-851, 875.

[0076] In a typical embodiment, the values ​​of x, y, and z are x = 5 / 16, z = 3 / 11, and y = 8 / 11, respectively. Therefore, the width-to-length ratio of the folded node transistor, the circulating current mirror transistor, and the shunt transistor is (1+x):z(1-x):y(1-x) = 23:3:8. Based on the aforementioned configuration, the control resistor is set to R2 = 1.93kΩ. The measured low-frequency gain is 120.4dB, and the 1kHz equivalent input noise is... The GBW is 45.1MHz.

[0077] In a typical embodiment, the values ​​of x, y, and z are x = 7 / 16, z = 1 / 3, and y = 2 / 3, respectively. Therefore, the width-to-length ratio of the folded node transistor, the circulating current mirror transistor, and the shunt transistor is (1+x):z(1-x):y(1-x) = 23:3:6. Based on the aforementioned configuration, the control resistor is set to R2 = 0.48kΩ. The measured low-frequency gain is 120.7dB, and the 1kHz equivalent input noise is... The GBW is 42.4MHz.

[0078] like Figure 4 As shown, (1+x) represents the static current of M9a as (1+x)Ib, z(1-x) represents the static current of M9b as z(1-x)Ib, y(1-x) represents the static current of M9c as z(1-x)Ib, and y+z=1.

[0079] When x = 1 (i.e., resistance R2 is 0), no current flows through NM9b, NM9c and NM10b, NM10c. In this case, the current path of the enhancement-type recycle folded cascode module is the same as that of a traditional folded cascode amplifier. For the enhancement-type recycle folded cascode module, its effective transconductance is:

[0080]

[0081] Among them, g mp7a This is the transconductance of the PMOS transistor PM7a in the first input transistor group.

[0082] Higher transconductance can be achieved by adjusting x and z. However, to avoid mismatch, the input transistors typically use the same width-to-length ratio, resulting in x being limited to 1 / 2, thus restricting the range of transconductance variation in the amplifier. This embodiment introduces resistor R2 to achieve different xIb values, thereby enabling a wide range of transconductance increases. The output impedance of the enhanced reclaimed cascode module is: R OUT =g mn8 r on8 (r op8a ||r on10a )||g mp12 r op12 r op10 .

[0083] Among them, g mn8 g mp12 They are respectively Figure 4 The transconductance of NM8 and PM12, r on8 r op8a r on10a r op12 r op10 They are respectively Figure 4 The output impedance of NM8, PM8a, NM10a, PM12 and PM10.

[0084] PM8a and PM7a offer higher transconductance and output impedance, thus achieving increased gain. Similarly, increased transconductance also leads to an increase in the gain-bandwidth product.

[0085]

[0086] In the above formula, C L This is the load capacitor.

[0087] Therefore, in the preferred embodiment, the quiescent current of the first input transistor group is (1+x)Ib, and the quiescent current of the second input transistor group is (1-x)Ib, where Ib is the reference bias current; the resistance value of the regulating resistor is configured to adjust the value of x to increase the effective transconductance of the enhanced recycle folded cascode module 300 and increase the gain-bandwidth product of the operational amplifier.

[0088] In a preferred embodiment, the resistance value of the regulating resistor is configured such that x is greater than 0 and less than 0.5. In a more preferred embodiment, 1 / 4 ≤ x < 1 / 2, that is, x is not less than 0.25 and less than 0.5, and z is between 1 / 5 and 1 / 3 (including the two endpoints), which enables the gain to be greater than 120dB and ensures strong inversion of the current mirror.

[0089] In the preferred embodiment, simulation determined that when resistor R2 is 0.96kΩ and reference current Ib = 32μA, x = 3 / 8. At this time, the quiescent current of the first input transistor group PM7a and PM8a is (1 + 3 / 8) × 32 = 44μA, and the quiescent current of the second input transistor group PM7b and PM8b is (1 - 3 / 8) × 32 = 20μA, achieving a gain of 125.72dB and noise reduction. The optimal balance is achieved when the gain is at its optimal value while keeping the noise as low as possible.

[0090] In a typical embodiment, such as Figure 4 As shown, the first input transistor group includes a first PMOS transistor PM7a and a second PMOS transistor PM8a, and the second input transistor group includes a third PMOS transistor PM7b and a fourth PMOS transistor PM8b; the folded node transistor includes a first NMOS transistor NM9a and a second NMOS transistor NM10a, the circulating current mirror transistor includes a third NMOS transistor NM9b and a fourth NMOS transistor NM10b, the shunt transistor includes a fifth NMOS transistor NM9c and a sixth NMOS transistor NM10c; and the matching transistor includes a seventh NMOS transistor NM11, an eighth NMOS transistor NM12, a ninth NMOS transistor NM13, and a tenth NMOS transistor NM14.

[0091] In this configuration, the drain of the first PMOS transistor PM7a is connected to the drain of the first NMOS transistor NM9a, and the drain of the second PMOS transistor PM8a is connected to the drain of the second NMOS transistor NM10a. The drains of the first PMOS transistor PM7a and the second PMOS transistor PM8a serve as the output nodes of the enhancement-mode reclaimed folded cascode module 300, respectively. The drain of the third PMOS transistor PM7b is connected to the drains of the ninth NMOS transistor NM13 and the tenth NMOS transistor NM14, as well as the gates of the second NMOS transistor NM10a and the fourth NMOS transistor NM10b. The drain of the fourth PMOS transistor PM8b is connected to the gates of the seventh NMOS transistor NM11 and the tenth NMOS transistor NM14. The drain of the eighth NMOS transistor NM12 and the gates of the first NMOS transistor NM9a and the third NMOS transistor NM9b are connected; the sources of the seventh NMOS transistor NM11, the eighth NMOS transistor NM12, the ninth NMOS transistor NM13, and the tenth NMOS transistor NM14 are connected to the drains of the third NMOS transistor NM9b, the fifth NMOS transistor NM9c, the sixth NMOS transistor NM10b, and the fourth NMOS transistor NM10b, respectively; the sources of the folded node transistor, the circulating current mirror transistor, and the shunt transistor are all grounded; the gates of the fifth NMOS transistor NM9c and the sixth NMOS transistor NM10c are connected to the bias voltage V from the bias module 100. b4 .

[0092] In a more specific circuit structure embodiment, such as Figure 1 , Figure 3 and Figure 4 As shown, the component connection method in the enhanced recycling folding common source common grid module 300 is as follows:

[0093] The bias voltage V generated by the gate bias circuit of PM5 b1 The V generated by the gate bias circuit of PM6 b2 The source of PM5 is connected to the power supply VDD, and the drain of PM5 is connected to the source of PM6. The drain of PM6, the source of PM7b, and the source of PM8b are connected to one end of resistor R2. The other end of resistor R2 is connected to the source of PM7a and the source of PM8a. The gate of PM7a and the gate of PM7b are connected to NM23 (in... Figure 3 The source of PM8a and the source of NM25 are connected to each other; the gate of PM8a and the gate of PM8b are connected to the source of NM22 and the source of NM24; the drain of PM7a and the drain of NM9a are connected to the source of NM28 and the source of NM29; the drain of PM7b, the drain of NM13, and the drain of NM14 are connected to the gate of NM10a and NM10b; the drain of PM8b, the drain of NM11, and the drain of NM12 are connected to the gate of NM9a and NM9b; the gate of NM11, the gate of NM12, the gate of NM13, and the gate of NM14 are connected to the V generated by the bias circuit. b3 The source of NM11 is connected to the drain of NM9b; the source of NM12 is connected to the drain of NM9c; the source of NM13 is connected to the drain of NM10c; the source of NM14 is connected to the drain of NM10b; the gates of NM9c and NM10c are connected to V generated by a bias circuit. b4 The sources of NM9a, NM9b, NM9c, NM10a, NM10b, and NM10c are grounded respectively; the sources of PM9 and PM10 are connected to power supply VDD respectively; the gates of PM9 and PM10, the drain of PM11, and the sources of PM13 and NM15 are connected; the drain of PM9 is connected to the sources of PM20 and PM22; the drain of PM10 is connected to the sources of PM21 and PM23; the source of PM11 is connected to the drains of PM20 and PM21; the source of PM12 is connected to the drains of PM22 and PM23; the drain of PM12 is connected to the sources of PM14, NM16, the gate of PM19, and capacitor C. C1 One end of the capacitor is connected to the other end; the drain of NM7 is connected to the drain of PM13 and the source of NM15; the drain of NM8 is connected to the drain of PM14, the source of NM16, the gate of NM21, and the capacitor C. C2One end of the two terminals is connected; the gate of NM7 and the gate of NM8 are connected to the bias voltage Vb3 generated by the bias circuit; the source of NM7 is connected to the drain of NM26 and the drain of NM28; the source of NM8 is connected to the drain of NM27 and the drain of NM29.

[0094] In a preferred embodiment, the effective transconductance G of the enhanced recycled folded cascode module 300 is... m,ERFC for:

[0095]

[0096] Among them, g mpa This represents the effective transconductance of the transistors in the first input transistor group.

[0097] In a preferred embodiment, the gain-bandwidth product (GBW) of the operational amplifier is:

[0098]

[0099] Among them, g mpa C is the effective transconductance of the transistor in the first input transistor group. L This is the load capacitor.

[0100] like Figure 1 , Figure 3 and Figure 4 As shown, in a preferred embodiment, the chopper module 200 includes an input-stage chopper module 210 and an output-stage chopper module 220; the chopper module 200 is powered by a complementary clock signal. control.

[0101] like Figure 3 As shown, the input terminal of the input stage chopper module 210 is connected to the input terminal of the operational amplifier, and the output terminal of the input stage chopper module 210 is connected to the gate of the first input transistor group and the second input transistor group, which is used to modulate the input signal to the chopper frequency.

[0102] like Figure 4 As shown, the input terminal of the output stage chopper module 220 is connected to the output node of the enhanced recycle folded cascode module 300, and the output terminal of the output stage chopper module 220 is connected to the input node of the output stage module 400. This is used to demodulate the amplified signal back to the original frequency and modulate the low-frequency noise to the chopper frequency.

[0103] In this embodiment, the input voltage signal is modulated to a high frequency at the input terminal using a chopper module. Inside the amplifier, the modulated input signal and low-frequency noise in the circuit are modulated again using the chopper module. At this time, the input signal is demodulated to the fundamental frequency and amplified, while the low-frequency noise in the circuit is modulated to a high frequency, thereby eliminating the influence of noise on the signal.

[0104] In a more specific circuit structure embodiment, such as Figure 3 and Figure 4 As shown, the connection method of the components in the chopper module 200 is as follows:

[0105] The drains of NM22 and NM23 are connected to the input signal VIN-; the drains of NM24 and NM25 are connected to the input signal VIN+; the gates of NM22 and NM25 are connected to the clock signal CK; and the gates of NM23 and NM24 are connected to the clock signal CK. The source of PM20 and the source of PM22 are connected to the drain of PM9; the source of PM21 and the source of PM23 are connected to the drain of PM10; the drain of PM20 and the drain of PM21 are connected to the source of PM11; the drain of PM22 and the drain of PM23 are connected to the source of PM12; the gate of PM20 and the gate of PM23 are connected to a clock signal. The gates of PM21 and PM22 are connected to the clock signal CK; the drains of NM26 and NM28 are connected to the source of NM7; the drains of NM27 and NM29 are connected to the source of NM8; the sources of NM26 and NM27 are connected to the drains of NM10a and PM8a; the sources of NM28 and NM29 are connected to the drains of NM9a and PM7a; the gates of NM26 and NM29 are connected to the clock signal CK. The gate of NM27 and the gate of NM28 are connected to the clock signal CK.

[0106] In a preferred embodiment, the output stage module 400 includes: two push-pull output transistors; a transconductance linear loop composed of multiple PMOS transistors and NMOS transistors; and multiple resistors and capacitors disposed between the output terminal of the operational amplifier and the input node of the output stage module 400.

[0107] In a more specific circuit structure embodiment, such as Figure 5 As shown, the connection method of the components in the output stage module 400 is as follows:

[0108] The source of PM13, the drain of NM15, the drain of PM11, the gate of PM9, and the gate of PM10 are connected; the source of PM14, the drain of PM16, the drain of PM12, the gate of PM19, and capacitor C are connected. C1 One end of each terminal is connected; the gates of PM13, PM14, PM16, and NM17 are connected to the drain of NM17; the gates of NM15, NM16, NM19, and NM18 are connected to the drain of PM18; the drain of PM13 and the source of NM15 are connected to the drain of NM7; the drain of PM14, the source of NM16, the drain of NM8, and the gate of NM21 are connected to capacitor C.C2 One end of each is connected; the source of PM15, the source of PM17, and the source of PM19 are connected to the power supply VDD; the gate and drain of PM15 are connected to the source of PM16; the gate of PM17 is connected to the VDD generated by the bias circuit. b1 The gate of PM18 is connected to the bias circuit, which generates V. b2 The drain of PM17 is connected to the source of PM18; the gate of NM17 is connected to V generated by the bias circuit. b3 The gate of the NM18 is connected to the bias circuit, which generates V. b4 The source of NM17 is connected to the drain of NM18; the gate and drain of NM20 are connected to the source of NM19; the sources of NM18, NM20, and NM21 are grounded respectively; capacitor C C1 The other end is connected to resistor R Z1 Connect one end of the capacitor C to the capacitor. C2 The other end is connected to resistor R Z2 One end of the resistor is connected to the other; the drain of PM19, the drain of NM21, and resistor R. Z1 The other end, resistor R Z2 The other end is connected to VOUT.

[0109] In a preferred embodiment, the bias module 100 is configured to provide four stable bias voltages for the enhanced recycle folded cascode module 300 and the output stage module 400.

[0110] In a more specific circuit structure embodiment, such as Figure 2 As shown, the components in the bias module 100 are connected as follows:

[0111] The gate of PM1, the gate and drain of PM2, and the gate of PM4 are all connected to the drain of NM3, and a bias voltage V is generated at this connection. b2 The drain of PM1 is connected to the source of PM2; the gate of PM3 and the drain of PM4 are both connected to the drain of NM5, thereby generating a bias voltage V at the connection point. b1 The drain of PM3 is connected to the source of PM4; the sources of PM1 and PM3 are connected to the power supply VDD; the gates of NM1, NM3, and NM5 are all connected to one end of resistor R1, and a bias voltage V is generated from this connection. b3 The source of NM1 is connected to the drain of NM2; the source of NM3 is connected to the drain of NM4; the source of NM5 is connected to the drain of NM6; the gates of NM2, NM4, and NM6 are connected to the other end of resistor R1, thereby generating a bias voltage V at the connection point. b4 The sources of NM2, NM4, and NM6 are grounded respectively.

[0112] The main circuit operation is as follows: The current recovery structure in the enhanced recovery folded cascode module 300 converts the large current of the MOSFET at the fold into transconductance, and further enhances its transconductance using the regulating resistor R2, ultimately increasing its gain and gain-bandwidth product (GBW). The input voltage signal is modulated to a high frequency by the chopper module 200, and then demodulated to the fundamental frequency and amplified by the enhanced recovery folded cascode module 300 and the chopper module 200. Noise generated by the input transistor group, the folded node transistor, and PM9 and PM10 is modulated to a high frequency to eliminate the influence of noise on the signal. The Class-AB output stage further amplifies the signal and provides a larger output swing for the circuit.

[0113] In a preferred embodiment, the operational amplifier, under a 10pF load, has a low-frequency gain greater than 120dB, a gain-bandwidth product greater than 40MHz, and an equivalent input noise of less than [value missing] at 1kHz.

[0114] The problem that the foregoing embodiments or their preferred or typical embodiments are intended to solve is: how to improve the gain and GBW of the circuit while maintaining low power consumption and a large input / output swing.

[0115] The applicant argues that increasing the gain and GBW of an operational amplifier (op-amp) typically requires increasing the circuit's power consumption and area. To improve the op-amp's gain and GBW while limiting power consumption, efficient utilization of current in each part of the circuit is crucial. Existing folded cascode amplifiers have large input-output swings and moderate gain, but the MOSFETs at the folding nodes consume significant current without improving the circuit's gain, resulting in low current utilization. To achieve efficient utilization, this application's embodiment splits the input pair and the MOSFET at the folding point, assembling them into a current recovery structure, forming the aforementioned first and second input transistor groups. In this case, the large current of the MOSFET at the folding point is converted into transconductance, increasing the circuit's effective transconductance. This increases the circuit's gain and gain-bandwidth product by a factor of two. Simultaneously, by introducing a regulating resistor R2, the effective transconductance value x can be adjusted while ensuring that the four input transistors in the first and second input groups do not mismatch. The modified circuit thus forms the enhanced reclaimable folded cascode module provided in this application.

[0116] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An operational amplifier, characterized in that, It includes a bias module (100), a chopper module (200), an enhanced recycle folded cascode module (300), and an output stage module (400); The enhanced recycling folded common-source common-gate module (300) includes: The first input transistor group, the second input transistor group, and the control resistor are provided. The gates of the first input transistor group and the second input transistor group are connected to the output terminal of the chopper module (200). The source of the first input transistor group is connected to one end of the control resistor, and the source of the second input transistor group is connected to the other end of the control resistor, so that the first input transistor group and the second input transistor group generate different gate-source voltages. The three-path current recovery structure includes at least two folded node transistors, two circulating current mirror transistors, and two shunt transistors. The width-to-length ratio of the folded node transistors, circulating current mirror transistors, and shunt transistors is (1+x):z(1-x):y(1-x), where x is greater than 0 and less than 1, and y+z=1. Multiple matching transistors, the gates of which are connected to the bias voltage provided by the bias module (100).

2. The operational amplifier according to claim 1, characterized in that, The quiescent current of the first input transistor group is (1+x)Ib, and the quiescent current of the second input transistor group is (1-x)Ib, where Ib is the reference bias current; The resistance value of the regulating resistor is configured to: adjust the value of x to increase the effective transconductance of the enhanced recycle folded cascode module (300) and increase the gain-bandwidth product of the operational amplifier.

3. The operational amplifier according to claim 2, characterized in that, The resistance value of the regulating resistor is configured such that the value of x is not less than 0.25 and less than 0.

5.

4. The operational amplifier according to any one of claims 1 to 3, characterized in that, The first input transistor group includes a first PMOS transistor and a second PMOS transistor, and the second input transistor group includes a third PMOS transistor and a fourth PMOS transistor; The folded node transistor includes a first NMOS transistor and a second NMOS transistor, the circulating current mirror transistor includes a third NMOS transistor and a fourth NMOS transistor, and the shunt transistor includes a fifth NMOS transistor and a sixth NMOS transistor; The matching transistors include a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; Wherein, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the drains of the first PMOS transistor and the drains of the second PMOS transistor serve as the output nodes of the enhanced recycling folded cascode module (300). The drain of the third PMOS transistor is connected to the drain of the ninth NMOS transistor, the tenth NMOS transistor, the second NMOS transistor, and the gate of the fourth NMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the seventh NMOS transistor, the eighth NMOS transistor, and the gate of the first NMOS transistor and the third NMOS transistor. The sources of the seventh, eighth, ninth, and tenth NMOS transistors are respectively connected to the drains of the third, fifth, sixth, and fourth NMOS transistors. The sources of the folded node transistor, the circulating current mirror transistor, and the shunt transistor are all grounded. The gates of the fifth and sixth NMOS transistors are connected to the bias voltage from the bias module (100).

5. The operational amplifier according to any one of claims 1 to 3, characterized in that, The effective transconductance G of the enhanced recycled folded cascode module (300) m,ERFC for: Among them, g mpa This is the effective transconductance of the transistors in the first input transistor group.

6. The operational amplifier according to any one of claims 1 to 3, characterized in that, The gain-bandwidth product GBW of the operational amplifier is: Among them, g mpa C represents the effective transconductance of the transistors in the first input transistor group. L This is the load capacitor.

7. The operational amplifier according to claim 1, characterized in that, The chopper module (200) includes: An input-stage chopper module (210) is provided, wherein the input terminal of the input-stage chopper module (210) is connected to the input terminal of the operational amplifier, and the output terminal is connected to the gate of the first input transistor group and the second input transistor group, for modulating the input signal to the chopper frequency. The output stage chopper module (220) has its input terminal connected to the output node of the enhanced retractable folded cascode module (300) and its output terminal connected to the input node of the output stage module (400). It is used to demodulate the amplified signal back to the original frequency and modulate low-frequency noise to the chopper frequency. The chopper module (200) is controlled by a complementary clock signal.

8. The operational amplifier according to claim 1, characterized in that, The output stage module (400) includes: Two push-pull output tubes; A transconducting linear loop composed of multiple PMOS and NMOS transistors; Multiple resistors and capacitors are disposed between the output terminal of the operational amplifier and the input node of the output stage module (400).

9. The operational amplifier according to claim 1, characterized in that, The bias module (100) provides four stable bias voltages for the enhanced recycle folded common source common grid module (300) and the output stage module (400).

10. The operational amplifier according to any one of claims 1 to 9, characterized in that, The operational amplifier, under a 10pF load, has a low-frequency gain greater than 120dB, a gain-bandwidth product greater than 40MHz, and an equivalent input noise of less than [value missing] at 1kHz.

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